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| author | Koakuma <koachan@protonmail.com> | 2022-04-21 06:06:58 +0700 |
|---|---|---|
| committer | Jakub Konka <kubkon@jakubkonka.com> | 2022-05-05 19:34:05 +0200 |
| commit | ae201807f52077709b46ab7d2adfe5178ce138af (patch) | |
| tree | 6706be1d45475bf8959d508a87b854fb3483690c | |
| parent | f6bf3dd78c7bbb139e64ddfa05995f3896366d77 (diff) | |
| download | zig-ae201807f52077709b46ab7d2adfe5178ce138af.tar.gz zig-ae201807f52077709b46ab7d2adfe5178ce138af.zip | |
stage2: sparcv9: Simplify genLoad/genStore
| -rw-r--r-- | src/arch/sparcv9/CodeGen.zig | 102 |
1 files changed, 20 insertions, 82 deletions
diff --git a/src/arch/sparcv9/CodeGen.zig b/src/arch/sparcv9/CodeGen.zig index 3715c56558..b435b1885c 100644 --- a/src/arch/sparcv9/CodeGen.zig +++ b/src/arch/sparcv9/CodeGen.zig @@ -1185,48 +1185,17 @@ fn genLoad(self: *Self, value_reg: Register, addr_reg: Register, comptime off_ty const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; switch (abi_size) { - 1 => { - _ = try self.addInst(.{ - .tag = .ldub, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 2 => { - _ = try self.addInst(.{ - .tag = .lduh, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 4 => { - _ = try self.addInst(.{ - .tag = .lduw, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 8 => { + 1, 2, 4, 8 => { + const tag: Mir.Inst.Tag = switch (abi_size) { + 1 => .ldub, + 2 => .lduh, + 4 => .lduw, + 8 => .ldx, + else => unreachable, // unexpected abi size + }; + _ = try self.addInst(.{ - .tag = .ldx, + .tag = tag, .data = .{ .arithmetic_3op = .{ .is_imm = is_imm, @@ -1436,48 +1405,17 @@ fn genStore(self: *Self, value_reg: Register, addr_reg: Register, comptime off_t const rs2_or_imm = if (is_imm) .{ .imm = off } else .{ .rs2 = off }; switch (abi_size) { - 1 => { - _ = try self.addInst(.{ - .tag = .stb, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 2 => { - _ = try self.addInst(.{ - .tag = .sth, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 4 => { - _ = try self.addInst(.{ - .tag = .stw, - .data = .{ - .arithmetic_3op = .{ - .is_imm = is_imm, - .rd = value_reg, - .rs1 = addr_reg, - .rs2_or_imm = rs2_or_imm, - }, - }, - }); - }, - 8 => { + 1, 2, 4, 8 => { + const tag: Mir.Inst.Tag = switch (abi_size) { + 1 => .stb, + 2 => .sth, + 4 => .stw, + 8 => .stx, + else => unreachable, // unexpected abi size + }; + _ = try self.addInst(.{ - .tag = .stx, + .tag = tag, .data = .{ .arithmetic_3op = .{ .is_imm = is_imm, |