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authorJakub Konka <kubkon@jakubkonka.com>2022-03-24 16:38:04 +0100
committerJakub Konka <kubkon@jakubkonka.com>2022-03-24 17:02:29 +0100
commit9d2ff7ed161ff0880818002fb75391be336b44ac (patch)
tree758f51a4bc527ab90589bd6efc802fc8e0c8d1e1
parent77352c5bea7e328006394b93bc239c3e34b464c9 (diff)
downloadzig-9d2ff7ed161ff0880818002fb75391be336b44ac.tar.gz
zig-9d2ff7ed161ff0880818002fb75391be336b44ac.zip
x64: fix struct_field_val for structs fitting in register
-rw-r--r--src/arch/x86_64/CodeGen.zig6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/arch/x86_64/CodeGen.zig b/src/arch/x86_64/CodeGen.zig
index f72086b23b..fe59cd6c63 100644
--- a/src/arch/x86_64/CodeGen.zig
+++ b/src/arch/x86_64/CodeGen.zig
@@ -2884,6 +2884,8 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
break :blk dst_mcv;
}
};
+ dst_mcv.freezeIfRegister(&self.register_manager);
+ defer dst_mcv.unfreezeIfRegister(&self.register_manager);
// Shift by struct_field_offset.
const shift = @intCast(u8, struct_field_offset * @sizeOf(usize));
@@ -2893,7 +2895,9 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
const max_reg_bit_width = Register.rax.size();
const mask_shift = @intCast(u6, (max_reg_bit_width - struct_field_ty.bitSize(self.target.*)));
const mask = (~@as(u64, 0)) >> mask_shift;
- try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .immediate = mask });
+
+ const tmp_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = mask });
+ try self.genBinMathOpMir(.@"and", Type.usize, dst_mcv, .{ .register = tmp_reg });
break :result dst_mcv;
},