aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJakub Konka <kubkon@jakubkonka.com>2024-02-17 11:43:18 +0100
committerJakub Konka <kubkon@jakubkonka.com>2024-02-17 11:46:01 +0100
commit9542ee9bf87424f89b7ca182944fe825193a5702 (patch)
treebdad4881b0874730e18b9fb7e46d738f4055eb86
parentace1a69a55dd77a8189b7408b126d9d1ca0066ee (diff)
downloadzig-9542ee9bf87424f89b7ca182944fe825193a5702.tar.gz
zig-9542ee9bf87424f89b7ca182944fe825193a5702.zip
elf: create Zig specific reloc type shared across ISAs
-rw-r--r--src/arch/x86_64/Emit.zig4
-rw-r--r--src/link/Elf.zig5
-rw-r--r--src/link/Elf/Atom.zig8
-rw-r--r--src/link/Elf/relocation.zig2
4 files changed, 10 insertions, 9 deletions
diff --git a/src/arch/x86_64/Emit.zig b/src/arch/x86_64/Emit.zig
index de510fb30c..e341372f11 100644
--- a/src/arch/x86_64/Emit.zig
+++ b/src/arch/x86_64/Emit.zig
@@ -120,7 +120,7 @@ pub fn emitMir(emit: *Emit) Error!void {
}
if (emit.lower.pic) {
const r_type: u32 = if (sym.flags.needs_zig_got and !is_obj_or_static_lib)
- link.File.Elf.R_X86_64_ZIG_GOTPCREL
+ link.File.Elf.R_ZIG_GOTPCREL
else if (sym.flags.needs_got)
@intFromEnum(std.elf.R_X86_64.R_X86_64_GOTPCREL)
else
@@ -140,7 +140,7 @@ pub fn emitMir(emit: *Emit) Error!void {
});
} else {
const r_type: u32 = if (sym.flags.needs_zig_got and !is_obj_or_static_lib)
- link.File.Elf.R_X86_64_ZIG_GOT32
+ link.File.Elf.R_ZIG_GOT32
else if (sym.flags.needs_got)
@intFromEnum(std.elf.R_X86_64.R_X86_64_GOT32)
else if (sym.flags.is_tls)
diff --git a/src/link/Elf.zig b/src/link/Elf.zig
index 2ae15a3200..a6625556e6 100644
--- a/src/link/Elf.zig
+++ b/src/link/Elf.zig
@@ -6065,8 +6065,9 @@ const RelaSection = struct {
};
const RelaSectionTable = std.AutoArrayHashMapUnmanaged(u32, RelaSection);
-pub const R_X86_64_ZIG_GOT32: u32 = 0xff00;
-pub const R_X86_64_ZIG_GOTPCREL: u32 = 0xff01;
+// TODO: add comptime check we don't clobber any reloc for any ISA
+pub const R_ZIG_GOT32: u32 = 0xff00;
+pub const R_ZIG_GOTPCREL: u32 = 0xff01;
fn defaultEntrySymbolName(cpu_arch: std.Target.Cpu.Arch) []const u8 {
return switch (cpu_arch) {
diff --git a/src/link/Elf/Atom.zig b/src/link/Elf/Atom.zig
index debdb22ad8..a86d0722ff 100644
--- a/src/link/Elf/Atom.zig
+++ b/src/link/Elf/Atom.zig
@@ -968,8 +968,8 @@ const x86_64 = struct {
else => |x| switch (@intFromEnum(x)) {
// Zig custom relocations
- Elf.R_X86_64_ZIG_GOT32,
- Elf.R_X86_64_ZIG_GOTPCREL,
+ Elf.R_ZIG_GOT32,
+ Elf.R_ZIG_GOTPCREL,
=> {
assert(symbol.flags.has_zig_got);
},
@@ -1153,8 +1153,8 @@ const x86_64 = struct {
else => |x| switch (@intFromEnum(x)) {
// Zig custom relocations
- Elf.R_X86_64_ZIG_GOT32 => try cwriter.writeInt(u32, @as(u32, @intCast(ZIG_GOT + A)), .little),
- Elf.R_X86_64_ZIG_GOTPCREL => try cwriter.writeInt(i32, @as(i32, @intCast(ZIG_GOT + A - P)), .little),
+ Elf.R_ZIG_GOT32 => try cwriter.writeInt(u32, @as(u32, @intCast(ZIG_GOT + A)), .little),
+ Elf.R_ZIG_GOTPCREL => try cwriter.writeInt(i32, @as(i32, @intCast(ZIG_GOT + A - P)), .little),
else => {},
},
diff --git a/src/link/Elf/relocation.zig b/src/link/Elf/relocation.zig
index b7b0ecf2f5..b6803f9166 100644
--- a/src/link/Elf/relocation.zig
+++ b/src/link/Elf/relocation.zig
@@ -55,7 +55,7 @@ const aarch64_relocs = Table(10, elf.R_AARCH64, .{
.{ .tlsdesc, .R_AARCH64_TLSDESC },
});
-const riscv64_relocs = Table(8, elf.R_RISCV, .{
+const riscv64_relocs = Table(9, elf.R_RISCV, .{
.{ .abs, .R_RISCV_64 },
.{ .copy, .R_RISCV_COPY },
.{ .rel, .R_RISCV_RELATIVE },