stage2 sparcv9: Add placeholder files and generate() function

Add placeholder files for Codegen, Emit, and Mir stages, complete with
a placeholder implementation of generate() to make it able to be plugged in
to the frontend. At the moment the implementation just panics, it'll be
worked on incrementally later.

Also, this registers the sparcv9 backend files into CMakeLists.txt.

5 files changed, 54 insertions, 1 deletions

diff --git a/CMakeLists.txt b/CMakeLists.txt
index 457c5297cb..646893b533 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -609,6 +609,11 @@ set(ZIG_STAGE2_SOURCES
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/Mir.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/bits.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/riscv64/abi.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/CodeGen.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Emit.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/Mir.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/bits.zig"
+    "${CMAKE_SOURCE_DIR}/src/arch/sparcv9/abi.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/CodeGen.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/Emit.zig"
     "${CMAKE_SOURCE_DIR}/src/arch/wasm/Mir.zig"
diff --git a/src/arch/sparcv9/CodeGen.zig b/src/arch/sparcv9/CodeGen.zig
new file mode 100644
index 0000000000..aa594d9f54
--- /dev/null
+++ b/src/arch/sparcv9/CodeGen.zig
@@ -0,0 +1,31 @@
+//! SPARCv9 codegen.
+//! This lowers AIR into MIR.
+const std = @import("std");
+const builtin = @import("builtin");
+const link = @import("../../link.zig");
+const Module = @import("../../Module.zig");
+const Air = @import("../../Air.zig");
+const Mir = @import("Mir.zig");
+const Emit = @import("Emit.zig");
+const Liveness = @import("../../Liveness.zig");
+
+const GenerateSymbolError = @import("../../codegen.zig").GenerateSymbolError;
+const FnResult = @import("../../codegen.zig").FnResult;
+const DebugInfoOutput = @import("../../codegen.zig").DebugInfoOutput;
+
+const bits = @import("bits.zig");
+const abi = @import("abi.zig");
+
+const Self = @This();
+
+pub fn generate(
+    bin_file: *link.File,
+    src_loc: Module.SrcLoc,
+    module_fn: *Module.Fn,
+    air: Air,
+    liveness: Liveness,
+    code: *std.ArrayList(u8),
+    debug_output: DebugInfoOutput,
+) GenerateSymbolError!FnResult {
+    @panic("TODO implement SPARCv9 codegen");
+}
diff --git a/src/arch/sparcv9/Emit.zig b/src/arch/sparcv9/Emit.zig
new file mode 100644
index 0000000000..ba644ede7e
--- /dev/null
+++ b/src/arch/sparcv9/Emit.zig
@@ -0,0 +1,6 @@
+//! This file contains the functionality for lowering SPARCv9 MIR into
+//! machine code
+
+const Emit = @This();
+const Mir = @import("Mir.zig");
+const bits = @import("bits.zig");
diff --git a/src/arch/sparcv9/Mir.zig b/src/arch/sparcv9/Mir.zig
new file mode 100644
index 0000000000..f0d3b1dfbd
--- /dev/null
+++ b/src/arch/sparcv9/Mir.zig
@@ -0,0 +1,11 @@
+//! Machine Intermediate Representation.
+//! This data is produced by SPARCv9 Codegen or SPARCv9 assembly parsing
+//! These instructions have a 1:1 correspondence with machine code instructions
+//! for the target. MIR can be lowered to source-annotated textual assembly code
+//! instructions, or it can be lowered to machine code.
+//! The main purpose of MIR is to postpone the assignment of offsets until Isel,
+//! so that, for example, the smaller encodings of jump instructions can be used.
+
+const Mir = @This();
+const bits = @import("bits.zig");
+const Register = bits.Register;
diff --git a/src/codegen.zig b/src/codegen.zig
index 6d5e140dca..0558c9c4f4 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -108,7 +108,7 @@ pub fn generateFunction(
         //.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         .riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
-        //.sparcv9 => return Function(.sparcv9).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
+        .sparcv9 => return @import("arch/sparcv9/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
         //.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output),