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| author | Koakuma <koachan@protonmail.com> | 2022-06-15 23:29:19 +0700 |
|---|---|---|
| committer | Koakuma <koachan@protonmail.com> | 2022-06-24 21:19:33 +0700 |
| commit | 672cd2f02f734a58c577a00f2bef831b6f73e8ff (patch) | |
| tree | 165025f0ad3e7839b44a4070f38e3273e275dbd2 | |
| parent | 6218d70d09cf60e3c1d83cdd5b49ea9eed3d5259 (diff) | |
| download | zig-672cd2f02f734a58c577a00f2bef831b6f73e8ff.tar.gz zig-672cd2f02f734a58c577a00f2bef831b6f73e8ff.zip | |
stage2: sparc64: Implement SPARCv9 and
| -rw-r--r-- | src/arch/sparc64/Emit.zig | 4 | ||||
| -rw-r--r-- | src/arch/sparc64/bits.zig | 8 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/arch/sparc64/Emit.zig b/src/arch/sparc64/Emit.zig index e3b65d93df..18abea63ed 100644 --- a/src/arch/sparc64/Emit.zig +++ b/src/arch/sparc64/Emit.zig @@ -93,7 +93,7 @@ pub fn emitMir( .lduw => try emit.mirArithmetic3Op(inst), .ldx => try emit.mirArithmetic3Op(inst), - .@"and" => @panic("TODO implement sparc64 and"), + .@"and" => try emit.mirArithmetic3Op(inst), .@"or" => try emit.mirArithmetic3Op(inst), .xor => try emit.mirArithmetic3Op(inst), .xnor => try emit.mirArithmetic3Op(inst), @@ -227,6 +227,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void { .lduh => try emit.writeInstruction(Instruction.lduh(i13, rs1, imm, rd)), .lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)), .ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)), + .@"and" => try emit.writeInstruction(Instruction.@"and"(i13, rs1, imm, rd)), .@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)), .xor => try emit.writeInstruction(Instruction.xor(i13, rs1, imm, rd)), .xnor => try emit.writeInstruction(Instruction.xnor(i13, rs1, imm, rd)), @@ -251,6 +252,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void { .lduh => try emit.writeInstruction(Instruction.lduh(Register, rs1, rs2, rd)), .lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)), .ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)), + .@"and" => try emit.writeInstruction(Instruction.@"and"(Register, rs1, rs2, rd)), .@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)), .xor => try emit.writeInstruction(Instruction.xor(Register, rs1, rs2, rd)), .xnor => try emit.writeInstruction(Instruction.xnor(Register, rs1, rs2, rd)), diff --git a/src/arch/sparc64/bits.zig b/src/arch/sparc64/bits.zig index 4c3e000438..29ef9da1d2 100644 --- a/src/arch/sparc64/bits.zig +++ b/src/arch/sparc64/bits.zig @@ -1229,6 +1229,14 @@ pub const Instruction = union(enum) { }; } + pub fn @"and"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction { + return switch (s2) { + Register => format3a(0b10, 0b00_0001, rs1, rs2, rd), + i13 => format3b(0b10, 0b00_0001, rs1, rs2, rd), + else => unreachable, + }; + } + pub fn @"or"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction { return switch (s2) { Register => format3a(0b10, 0b00_0010, rs1, rs2, rd), |