test: re-enable a bunch of vector behavior tests on hexagon

2 files changed, 6 insertions, 6 deletions

diff --git a/test/behavior.zig b/test/behavior.zig
index 590dfa8137..d8bcc30cb0 100644
--- a/test/behavior.zig
+++ b/test/behavior.zig
@@ -102,11 +102,7 @@ test {
     _ = @import("behavior/union.zig");
     _ = @import("behavior/union_with_members.zig");
     _ = @import("behavior/var_args.zig");
-    // https://github.com/llvm/llvm-project/issues/118879
-    // https://github.com/llvm/llvm-project/issues/134659
-    if (!(builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .hexagon)) {
-        _ = @import("behavior/vector.zig");
-    }
+    _ = @import("behavior/vector.zig");
     _ = @import("behavior/void.zig");
     _ = @import("behavior/while.zig");
     _ = @import("behavior/widening.zig");
diff --git a/test/behavior/vector.zig b/test/behavior/vector.zig
index d90f48d86d..7ffc10b5bf 100644
--- a/test/behavior/vector.zig
+++ b/test/behavior/vector.zig
@@ -639,6 +639,7 @@ test "vector division operators" {
 
     try comptime S.doTheTest();
     if ((builtin.cpu.arch == .armeb or builtin.cpu.arch == .thumbeb) and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/22060
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
     try S.doTheTest();
 }
 
@@ -767,8 +768,9 @@ test "vector shift operators" {
         }
     };
 
-    try S.doTheTest();
     try comptime S.doTheTest();
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
+    try S.doTheTest();
 }
 
 test "vector reduce operation" {
@@ -1271,6 +1273,7 @@ test "byte vector initialized in inline function" {
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
     if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
 
     if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and comptime builtin.cpu.has(.x86, .avx512f)) {
         // TODO https://github.com/ziglang/zig/issues/13279
@@ -1337,6 +1340,7 @@ test "@intCast to u0" {
     if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
     if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
+    if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
 
     var zeros = @Vector(2, u32){ 0, 0 };
     _ = &zeros;