diff options
Diffstat (limited to 'SOURCES')
66 files changed, 27285 insertions, 36694 deletions
diff --git a/SOURCES/0001-add-revoke_all-ioctl-to-release-event-and-joy-nodes-.patch b/SOURCES/0001-add-revoke_all-ioctl-to-release-event-and-joy-nodes-.patch deleted file mode 100644 index 71d9c59..0000000 --- a/SOURCES/0001-add-revoke_all-ioctl-to-release-event-and-joy-nodes-.patch +++ /dev/null @@ -1,208 +0,0 @@ -From e24eba6f9ffd2338028116ddc1e14ba5b68b997a Mon Sep 17 00:00:00 2001 -From: antheas <antheas@users.noreply.github.com> -Date: Wed, 17 Jul 2024 17:14:06 +0300 -Subject: [PATCH] add revoke_all ioctl to release event and joy nodes after - hiding - ---- - drivers/input/evdev.c | 24 ++++++++++++++++ - drivers/input/joydev.c | 54 ++++++++++++++++++++++++++++++----- - include/uapi/linux/input.h | 1 + - include/uapi/linux/joystick.h | 4 +++ - 4 files changed, 76 insertions(+), 7 deletions(-) - -diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c -index 51e0c4954600..87226069d076 100644 ---- a/drivers/input/evdev.c -+++ b/drivers/input/evdev.c -@@ -951,6 +951,21 @@ static int evdev_revoke(struct evdev *evdev, struct evdev_client *client, - return 0; - } - -+static int evdev_revoke_all(struct evdev *evdev, struct file *file) -+{ -+ struct evdev_client *client; -+ input_flush_device(&evdev->handle, file); -+ -+ spin_lock(&evdev->client_lock); -+ list_for_each_entry(client, &evdev->client_list, node) { -+ client->revoked = true; -+ evdev_ungrab(evdev, client); -+ wake_up_interruptible_poll(&client->wait, EPOLLHUP | EPOLLERR); -+ } -+ spin_unlock(&evdev->client_lock); -+ return 0; -+} -+ - /* must be called with evdev-mutex held */ - static int evdev_set_mask(struct evdev_client *client, - unsigned int type, -@@ -1094,6 +1109,15 @@ static long evdev_do_ioctl(struct file *file, unsigned int cmd, - return -EINVAL; - else - return evdev_revoke(evdev, client, file); -+ -+ case EVIOCREVOKEALL: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EACCES; -+ -+ if (p) -+ return -EINVAL; -+ else -+ return evdev_revoke_all(evdev, file); - - case EVIOCGMASK: { - void __user *codes_ptr; -diff --git a/drivers/input/joydev.c b/drivers/input/joydev.c -index 5824bca02e5a..3bdf3a1971f7 100644 ---- a/drivers/input/joydev.c -+++ b/drivers/input/joydev.c -@@ -63,8 +63,29 @@ struct joydev_client { - struct fasync_struct *fasync; - struct joydev *joydev; - struct list_head node; -+ bool revoked; - }; - -+static int joydev_revoke(struct joydev *joydev, struct joydev_client *client) -+{ -+ client->revoked = true; -+ wake_up_interruptible(&joydev->wait); -+ return 0; -+} -+ -+static int joydev_revoke_all(struct joydev *joydev) -+{ -+ struct joydev_client *client; -+ -+ spin_lock(&joydev->client_lock); -+ list_for_each_entry(client, &joydev->client_list, node) { -+ client->revoked = true; -+ } -+ spin_unlock(&joydev->client_lock); -+ wake_up_interruptible(&joydev->wait); -+ return 0; -+} -+ - static int joydev_correct(int value, struct js_corr *corr) - { - switch (corr->type) { -@@ -89,6 +110,9 @@ static void joydev_pass_event(struct joydev_client *client, - struct js_event *event) - { - struct joydev *joydev = client->joydev; -+ -+ if (client->revoked) -+ return; - - /* - * IRQs already disabled, just acquire the lock -@@ -345,6 +369,9 @@ static ssize_t joydev_0x_read(struct joydev_client *client, - struct JS_DATA_TYPE data; - int i; - -+ if (client->revoked) -+ return -ENODEV; -+ - spin_lock_irq(&input->event_lock); - - /* -@@ -402,7 +429,7 @@ static ssize_t joydev_read(struct file *file, char __user *buf, - return -EAGAIN; - - retval = wait_event_interruptible(joydev->wait, -- !joydev->exist || joydev_data_pending(client)); -+ !joydev->exist || client->revoked || joydev_data_pending(client)); - if (retval) - return retval; - -@@ -438,7 +465,7 @@ static __poll_t joydev_poll(struct file *file, poll_table *wait) - - poll_wait(file, &joydev->wait, wait); - return (joydev_data_pending(client) ? (EPOLLIN | EPOLLRDNORM) : 0) | -- (joydev->exist ? 0 : (EPOLLHUP | EPOLLERR)); -+ (joydev->exist && !client->revoked ? 0 : (EPOLLHUP | EPOLLERR)); - } - - static int joydev_handle_JSIOCSAXMAP(struct joydev *joydev, -@@ -506,9 +533,8 @@ static int joydev_handle_JSIOCSBTNMAP(struct joydev *joydev, - return retval; - } - -- --static int joydev_ioctl_common(struct joydev *joydev, -- unsigned int cmd, void __user *argp) -+static int joydev_ioctl_common(struct joydev *joydev, struct joydev_client *client, -+ unsigned int cmd, void __user *argp) - { - struct input_dev *dev = joydev->handle.dev; - size_t len; -@@ -556,6 +582,20 @@ static int joydev_ioctl_common(struct joydev *joydev, - return copy_to_user(argp, joydev->corr, - sizeof(joydev->corr[0]) * joydev->nabs) ? -EFAULT : 0; - -+ case JSIOCREVOKE: -+ if (argp) -+ return -EINVAL; -+ else -+ return joydev_revoke(joydev, client); -+ -+ case JSIOCREVOKEALL: -+ if (!capable(CAP_SYS_ADMIN)) -+ return -EACCES; -+ -+ if (argp) -+ return -EINVAL; -+ else -+ return joydev_revoke_all(joydev); - } - - /* -@@ -649,7 +689,7 @@ static long joydev_compat_ioctl(struct file *file, - break; - - default: -- retval = joydev_ioctl_common(joydev, cmd, argp); -+ retval = joydev_ioctl_common(joydev, client, cmd, argp); - break; - } - -@@ -699,7 +739,7 @@ static long joydev_ioctl(struct file *file, - break; - - default: -- retval = joydev_ioctl_common(joydev, cmd, argp); -+ retval = joydev_ioctl_common(joydev, client, cmd, argp); - break; - } - out: -diff --git a/include/uapi/linux/input.h b/include/uapi/linux/input.h -index 2557eb7b0561..38bfac937add 100644 ---- a/include/uapi/linux/input.h -+++ b/include/uapi/linux/input.h -@@ -185,6 +185,7 @@ struct input_mask { - - #define EVIOCGRAB _IOW('E', 0x90, int) /* Grab/Release device */ - #define EVIOCREVOKE _IOW('E', 0x91, int) /* Revoke device access */ -+#define EVIOCREVOKEALL _IOW('E', 0x94, int) /* Revoke device access from all clients. Requires CAP_SYS_ADMIN. */ - - /** - * EVIOCGMASK - Retrieve current event mask -diff --git a/include/uapi/linux/joystick.h b/include/uapi/linux/joystick.h -index 192bf2cf182d..543b004802f3 100644 ---- a/include/uapi/linux/joystick.h -+++ b/include/uapi/linux/joystick.h -@@ -66,6 +66,10 @@ struct js_event { - #define JSIOCSBTNMAP _IOW('j', 0x33, __u16[KEY_MAX - BTN_MISC + 1]) /* set button mapping */ - #define JSIOCGBTNMAP _IOR('j', 0x34, __u16[KEY_MAX - BTN_MISC + 1]) /* get button mapping */ - -+#define JSIOCREVOKE _IOW('j', 0x91, int) /* Revoke device access */ -+#define JSIOCREVOKEALL _IOW('j', 0x94, int) /* Revoke device access from all clients. Requires CAP_SYS_ADMIN. */ -+ -+ - /* - * Types and constants for get/set correction - */ --- -2.45.2 - diff --git a/SOURCES/0001-amd-pstate.patch b/SOURCES/0001-amd-pstate.patch deleted file mode 100644 index c865d00..0000000 --- a/SOURCES/0001-amd-pstate.patch +++ /dev/null @@ -1,734 +0,0 @@ -From 06c02d91fcfeb0fde264f03f0e364161b11a678d Mon Sep 17 00:00:00 2001 -From: Peter Jung <admin@ptr1337.dev> -Date: Sat, 3 Aug 2024 09:32:45 +0200 -Subject: [PATCH 01/12] amd-pstate - -Signed-off-by: Peter Jung <admin@ptr1337.dev> ---- - Documentation/admin-guide/pm/amd-pstate.rst | 18 +- - arch/x86/include/asm/cpufeatures.h | 1 + - arch/x86/include/asm/msr-index.h | 2 + - arch/x86/kernel/cpu/scattered.c | 1 + - drivers/cpufreq/Kconfig.x86 | 1 + - drivers/cpufreq/acpi-cpufreq.c | 3 +- - drivers/cpufreq/amd-pstate.c | 307 ++++++++++++++------ - drivers/cpufreq/amd-pstate.h | 2 + - drivers/cpufreq/cpufreq.c | 11 +- - 9 files changed, 251 insertions(+), 95 deletions(-) - -diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst -index 1e0d101b020a..d0324d44f548 100644 ---- a/Documentation/admin-guide/pm/amd-pstate.rst -+++ b/Documentation/admin-guide/pm/amd-pstate.rst -@@ -281,6 +281,22 @@ integer values defined between 0 to 255 when EPP feature is enabled by platform - firmware, if EPP feature is disabled, driver will ignore the written value - This attribute is read-write. - -+``boost`` -+The `boost` sysfs attribute provides control over the CPU core -+performance boost, allowing users to manage the maximum frequency limitation -+of the CPU. This attribute can be used to enable or disable the boost feature -+on individual CPUs. -+ -+When the boost feature is enabled, the CPU can dynamically increase its frequency -+beyond the base frequency, providing enhanced performance for demanding workloads. -+On the other hand, disabling the boost feature restricts the CPU to operate at the -+base frequency, which may be desirable in certain scenarios to prioritize power -+efficiency or manage temperature. -+ -+To manipulate the `boost` attribute, users can write a value of `0` to disable the -+boost or `1` to enable it, for the respective CPU using the sysfs path -+`/sys/devices/system/cpu/cpuX/cpufreq/boost`, where `X` represents the CPU number. -+ - Other performance and frequency values can be read back from - ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. - -@@ -406,7 +422,7 @@ control its functionality at the system level. They are located in the - ``/sys/devices/system/cpu/amd_pstate/`` directory and affect all CPUs. - - ``status`` -- Operation mode of the driver: "active", "passive" or "disable". -+ Operation mode of the driver: "active", "passive", "guided" or "disable". - - "active" - The driver is functional and in the ``active mode`` -diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h -index 3c7434329661..6c128d463a14 100644 ---- a/arch/x86/include/asm/cpufeatures.h -+++ b/arch/x86/include/asm/cpufeatures.h -@@ -470,6 +470,7 @@ - #define X86_FEATURE_BHI_CTRL (21*32+ 2) /* "" BHI_DIS_S HW control available */ - #define X86_FEATURE_CLEAR_BHB_HW (21*32+ 3) /* "" BHI_DIS_S HW control enabled */ - #define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */ -+#define X86_FEATURE_FAST_CPPC (21*32 + 5) /* "" AMD Fast CPPC */ - - /* - * BUG word(s) -diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h -index e022e6eb766c..384739d592af 100644 ---- a/arch/x86/include/asm/msr-index.h -+++ b/arch/x86/include/asm/msr-index.h -@@ -781,6 +781,8 @@ - #define MSR_K7_HWCR_IRPERF_EN BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT) - #define MSR_K7_FID_VID_CTL 0xc0010041 - #define MSR_K7_FID_VID_STATUS 0xc0010042 -+#define MSR_K7_HWCR_CPB_DIS_BIT 25 -+#define MSR_K7_HWCR_CPB_DIS BIT_ULL(MSR_K7_HWCR_CPB_DIS_BIT) - - /* K6 MSRs */ - #define MSR_K6_WHCR 0xc0000082 -diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c -index af5aa2c754c2..c84c30188fdf 100644 ---- a/arch/x86/kernel/cpu/scattered.c -+++ b/arch/x86/kernel/cpu/scattered.c -@@ -45,6 +45,7 @@ static const struct cpuid_bit cpuid_bits[] = { - { X86_FEATURE_HW_PSTATE, CPUID_EDX, 7, 0x80000007, 0 }, - { X86_FEATURE_CPB, CPUID_EDX, 9, 0x80000007, 0 }, - { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, -+ { X86_FEATURE_FAST_CPPC, CPUID_EDX, 15, 0x80000007, 0 }, - { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, - { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, - { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, -diff --git a/drivers/cpufreq/Kconfig.x86 b/drivers/cpufreq/Kconfig.x86 -index 438c9e75a04d..97c2d4f15d76 100644 ---- a/drivers/cpufreq/Kconfig.x86 -+++ b/drivers/cpufreq/Kconfig.x86 -@@ -71,6 +71,7 @@ config X86_AMD_PSTATE_DEFAULT_MODE - config X86_AMD_PSTATE_UT - tristate "selftest for AMD Processor P-State driver" - depends on X86 && ACPI_PROCESSOR -+ depends on X86_AMD_PSTATE - default n - help - This kernel module is used for testing. It's safe to say M here. -diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c -index 4ac3a35dcd98..f4f8587c4ea0 100644 ---- a/drivers/cpufreq/acpi-cpufreq.c -+++ b/drivers/cpufreq/acpi-cpufreq.c -@@ -50,8 +50,6 @@ enum { - #define AMD_MSR_RANGE (0x7) - #define HYGON_MSR_RANGE (0x7) - --#define MSR_K7_HWCR_CPB_DIS (1ULL << 25) -- - struct acpi_cpufreq_data { - unsigned int resume; - unsigned int cpu_feature; -@@ -139,6 +137,7 @@ static int set_boost(struct cpufreq_policy *policy, int val) - (void *)(long)val, 1); - pr_debug("CPU %*pbl: Core Boosting %s.\n", - cpumask_pr_args(policy->cpus), str_enabled_disabled(val)); -+ policy->boost_enabled = val; - - return 0; - } -diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c -index a092b13ffbc2..804fab4ebb26 100644 ---- a/drivers/cpufreq/amd-pstate.c -+++ b/drivers/cpufreq/amd-pstate.c -@@ -51,6 +51,7 @@ - - #define AMD_PSTATE_TRANSITION_LATENCY 20000 - #define AMD_PSTATE_TRANSITION_DELAY 1000 -+#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600 - #define CPPC_HIGHEST_PERF_PERFORMANCE 196 - #define CPPC_HIGHEST_PERF_DEFAULT 166 - -@@ -85,15 +86,6 @@ struct quirk_entry { - u32 lowest_freq; - }; - --/* -- * TODO: We need more time to fine tune processors with shared memory solution -- * with community together. -- * -- * There are some performance drops on the CPU benchmarks which reports from -- * Suse. We are co-working with them to fine tune the shared memory solution. So -- * we disable it by default to go acpi-cpufreq on these processors and add a -- * module parameter to be able to enable it manually for debugging. -- */ - static struct cpufreq_driver *current_pstate_driver; - static struct cpufreq_driver amd_pstate_driver; - static struct cpufreq_driver amd_pstate_epp_driver; -@@ -157,7 +149,7 @@ static int __init dmi_matched_7k62_bios_bug(const struct dmi_system_id *dmi) - * broken BIOS lack of nominal_freq and lowest_freq capabilities - * definition in ACPI tables - */ -- if (boot_cpu_has(X86_FEATURE_ZEN2)) { -+ if (cpu_feature_enabled(X86_FEATURE_ZEN2)) { - quirks = dmi->driver_data; - pr_info("Overriding nominal and lowest frequencies for %s\n", dmi->ident); - return 1; -@@ -199,7 +191,7 @@ static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) - u64 epp; - int ret; - -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - if (!cppc_req_cached) { - epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, - &cppc_req_cached); -@@ -272,7 +264,7 @@ static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) - int ret; - struct cppc_perf_ctrls perf_ctrls; - -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - u64 value = READ_ONCE(cpudata->cppc_req_cached); - - value &= ~GENMASK_ULL(31, 24); -@@ -524,7 +514,10 @@ static inline bool amd_pstate_sample(struct amd_cpudata *cpudata) - static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, - u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) - { -+ unsigned long max_freq; -+ struct cpufreq_policy *policy = cpufreq_cpu_get(cpudata->cpu); - u64 prev = READ_ONCE(cpudata->cppc_req_cached); -+ u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); - u64 value = prev; - - min_perf = clamp_t(unsigned long, min_perf, cpudata->min_limit_perf, -@@ -533,6 +526,9 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, - cpudata->max_limit_perf); - des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); - -+ max_freq = READ_ONCE(cpudata->max_limit_freq); -+ policy->cur = div_u64(des_perf * max_freq, max_perf); -+ - if ((cppc_state == AMD_PSTATE_GUIDED) && (gov_flags & CPUFREQ_GOV_DYNAMIC_SWITCHING)) { - min_perf = des_perf; - des_perf = 0; -@@ -544,6 +540,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - -+ /* limit the max perf when core performance boost feature is disabled */ -+ if (!cpudata->boost_supported) -+ max_perf = min_t(unsigned long, nominal_perf, max_perf); -+ - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - -@@ -654,10 +654,9 @@ static void amd_pstate_adjust_perf(unsigned int cpu, - unsigned long capacity) - { - unsigned long max_perf, min_perf, des_perf, -- cap_perf, lowest_nonlinear_perf, max_freq; -+ cap_perf, lowest_nonlinear_perf; - struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); - struct amd_cpudata *cpudata = policy->driver_data; -- unsigned int target_freq; - - if (policy->min != cpudata->min_limit_freq || policy->max != cpudata->max_limit_freq) - amd_pstate_update_min_max_limit(policy); -@@ -665,7 +664,6 @@ static void amd_pstate_adjust_perf(unsigned int cpu, - - cap_perf = READ_ONCE(cpudata->highest_perf); - lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf); -- max_freq = READ_ONCE(cpudata->max_freq); - - des_perf = cap_perf; - if (target_perf < capacity) -@@ -683,51 +681,111 @@ static void amd_pstate_adjust_perf(unsigned int cpu, - max_perf = min_perf; - - des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); -- target_freq = div_u64(des_perf * max_freq, max_perf); -- policy->cur = target_freq; - - amd_pstate_update(cpudata, min_perf, des_perf, max_perf, true, - policy->governor->flags); - cpufreq_cpu_put(policy); - } - --static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) -+static int amd_pstate_cpu_boost_update(struct cpufreq_policy *policy, bool on) - { - struct amd_cpudata *cpudata = policy->driver_data; -+ struct cppc_perf_ctrls perf_ctrls; -+ u32 highest_perf, nominal_perf, nominal_freq, max_freq; - int ret; - -- if (!cpudata->boost_supported) { -- pr_err("Boost mode is not supported by this processor or SBIOS\n"); -- return -EINVAL; -+ highest_perf = READ_ONCE(cpudata->highest_perf); -+ nominal_perf = READ_ONCE(cpudata->nominal_perf); -+ nominal_freq = READ_ONCE(cpudata->nominal_freq); -+ max_freq = READ_ONCE(cpudata->max_freq); -+ -+ if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ u64 value = READ_ONCE(cpudata->cppc_req_cached); -+ -+ value &= ~GENMASK_ULL(7, 0); -+ value |= on ? highest_perf : nominal_perf; -+ WRITE_ONCE(cpudata->cppc_req_cached, value); -+ -+ wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); -+ } else { -+ perf_ctrls.max_perf = on ? highest_perf : nominal_perf; -+ ret = cppc_set_perf(cpudata->cpu, &perf_ctrls); -+ if (ret) { -+ cpufreq_cpu_release(policy); -+ pr_debug("Failed to set max perf on CPU:%d. ret:%d\n", -+ cpudata->cpu, ret); -+ return ret; -+ } - } - -- if (state) -- policy->cpuinfo.max_freq = cpudata->max_freq; -- else -- policy->cpuinfo.max_freq = cpudata->nominal_freq * 1000; -+ if (on) -+ policy->cpuinfo.max_freq = max_freq; -+ else if (policy->cpuinfo.max_freq > nominal_freq * 1000) -+ policy->cpuinfo.max_freq = nominal_freq * 1000; - - policy->max = policy->cpuinfo.max_freq; - -- ret = freq_qos_update_request(&cpudata->req[1], -- policy->cpuinfo.max_freq); -- if (ret < 0) -- return ret; -+ if (cppc_state == AMD_PSTATE_PASSIVE) { -+ ret = freq_qos_update_request(&cpudata->req[1], policy->cpuinfo.max_freq); -+ if (ret < 0) -+ pr_debug("Failed to update freq constraint: CPU%d\n", cpudata->cpu); -+ } - -- return 0; -+ return ret < 0 ? ret : 0; - } - --static void amd_pstate_boost_init(struct amd_cpudata *cpudata) -+static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) - { -- u32 highest_perf, nominal_perf; -+ struct amd_cpudata *cpudata = policy->driver_data; -+ int ret; - -- highest_perf = READ_ONCE(cpudata->highest_perf); -- nominal_perf = READ_ONCE(cpudata->nominal_perf); -+ if (!cpudata->boost_supported) { -+ pr_err("Boost mode is not supported by this processor or SBIOS\n"); -+ return -EOPNOTSUPP; -+ } -+ mutex_lock(&amd_pstate_driver_lock); -+ ret = amd_pstate_cpu_boost_update(policy, state); -+ WRITE_ONCE(cpudata->boost_state, !ret ? state : false); -+ policy->boost_enabled = !ret ? state : false; -+ refresh_frequency_limits(policy); -+ mutex_unlock(&amd_pstate_driver_lock); - -- if (highest_perf <= nominal_perf) -- return; -+ return ret; -+} - -- cpudata->boost_supported = true; -+static int amd_pstate_init_boost_support(struct amd_cpudata *cpudata) -+{ -+ u64 boost_val; -+ int ret = -1; -+ -+ /* -+ * If platform has no CPB support or disable it, initialize current driver -+ * boost_enabled state to be false, it is not an error for cpufreq core to handle. -+ */ -+ if (!cpu_feature_enabled(X86_FEATURE_CPB)) { -+ pr_debug_once("Boost CPB capabilities not present in the processor\n"); -+ ret = 0; -+ goto exit_err; -+ } -+ -+ /* at least one CPU supports CPB, even if others fail later on to set up */ - current_pstate_driver->boost_enabled = true; -+ -+ ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); -+ if (ret) { -+ pr_err_once("failed to read initial CPU boost state!\n"); -+ ret = -EIO; -+ goto exit_err; -+ } -+ -+ if (!(boost_val & MSR_K7_HWCR_CPB_DIS)) -+ cpudata->boost_supported = true; -+ -+ return 0; -+ -+exit_err: -+ cpudata->boost_supported = false; -+ return ret; - } - - static void amd_perf_ctl_reset(unsigned int cpu) -@@ -756,7 +814,7 @@ static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) - { - int ret; - -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - u64 cap1; - - ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); -@@ -852,8 +910,12 @@ static u32 amd_pstate_get_transition_delay_us(unsigned int cpu) - u32 transition_delay_ns; - - transition_delay_ns = cppc_get_transition_latency(cpu); -- if (transition_delay_ns == CPUFREQ_ETERNAL) -- return AMD_PSTATE_TRANSITION_DELAY; -+ if (transition_delay_ns == CPUFREQ_ETERNAL) { -+ if (cpu_feature_enabled(X86_FEATURE_FAST_CPPC)) -+ return AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY; -+ else -+ return AMD_PSTATE_TRANSITION_DELAY; -+ } - - return transition_delay_ns / NSEC_PER_USEC; - } -@@ -924,12 +986,30 @@ static int amd_pstate_init_freq(struct amd_cpudata *cpudata) - WRITE_ONCE(cpudata->nominal_freq, nominal_freq); - WRITE_ONCE(cpudata->max_freq, max_freq); - -+ /** -+ * Below values need to be initialized correctly, otherwise driver will fail to load -+ * max_freq is calculated according to (nominal_freq * highest_perf)/nominal_perf -+ * lowest_nonlinear_freq is a value between [min_freq, nominal_freq] -+ * Check _CPC in ACPI table objects if any values are incorrect -+ */ -+ if (min_freq <= 0 || max_freq <= 0 || nominal_freq <= 0 || min_freq > max_freq) { -+ pr_err("min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect\n", -+ min_freq, max_freq, nominal_freq * 1000); -+ return -EINVAL; -+ } -+ -+ if (lowest_nonlinear_freq <= min_freq || lowest_nonlinear_freq > nominal_freq * 1000) { -+ pr_err("lowest_nonlinear_freq(%d) value is out of range [min_freq(%d), nominal_freq(%d)]\n", -+ lowest_nonlinear_freq, min_freq, nominal_freq * 1000); -+ return -EINVAL; -+ } -+ - return 0; - } - - static int amd_pstate_cpu_init(struct cpufreq_policy *policy) - { -- int min_freq, max_freq, nominal_freq, ret; -+ int min_freq, max_freq, ret; - struct device *dev; - struct amd_cpudata *cpudata; - -@@ -958,18 +1038,12 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) - if (ret) - goto free_cpudata1; - -+ ret = amd_pstate_init_boost_support(cpudata); -+ if (ret) -+ goto free_cpudata1; -+ - min_freq = READ_ONCE(cpudata->min_freq); - max_freq = READ_ONCE(cpudata->max_freq); -- nominal_freq = READ_ONCE(cpudata->nominal_freq); -- -- if (min_freq <= 0 || max_freq <= 0 || -- nominal_freq <= 0 || min_freq > max_freq) { -- dev_err(dev, -- "min_freq(%d) or max_freq(%d) or nominal_freq (%d) value is incorrect, check _CPC in ACPI tables\n", -- min_freq, max_freq, nominal_freq); -- ret = -EINVAL; -- goto free_cpudata1; -- } - - policy->cpuinfo.transition_latency = amd_pstate_get_transition_latency(policy->cpu); - policy->transition_delay_us = amd_pstate_get_transition_delay_us(policy->cpu); -@@ -980,10 +1054,12 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) - policy->cpuinfo.min_freq = min_freq; - policy->cpuinfo.max_freq = max_freq; - -+ policy->boost_enabled = READ_ONCE(cpudata->boost_supported); -+ - /* It will be updated by governor */ - policy->cur = policy->cpuinfo.min_freq; - -- if (boot_cpu_has(X86_FEATURE_CPPC)) -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) - policy->fast_switch_possible = true; - - ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0], -@@ -1005,7 +1081,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) - - policy->driver_data = cpudata; - -- amd_pstate_boost_init(cpudata); - if (!current_pstate_driver->adjust_perf) - current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; - -@@ -1216,7 +1291,7 @@ static int amd_pstate_change_mode_without_dvr_change(int mode) - - cppc_state = mode; - -- if (boot_cpu_has(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) -+ if (cpu_feature_enabled(X86_FEATURE_CPPC) || cppc_state == AMD_PSTATE_ACTIVE) - return 0; - - for_each_present_cpu(cpu) { -@@ -1389,7 +1464,7 @@ static bool amd_pstate_acpi_pm_profile_undefined(void) - - static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) - { -- int min_freq, max_freq, nominal_freq, ret; -+ int min_freq, max_freq, ret; - struct amd_cpudata *cpudata; - struct device *dev; - u64 value; -@@ -1420,17 +1495,12 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) - if (ret) - goto free_cpudata1; - -+ ret = amd_pstate_init_boost_support(cpudata); -+ if (ret) -+ goto free_cpudata1; -+ - min_freq = READ_ONCE(cpudata->min_freq); - max_freq = READ_ONCE(cpudata->max_freq); -- nominal_freq = READ_ONCE(cpudata->nominal_freq); -- if (min_freq <= 0 || max_freq <= 0 || -- nominal_freq <= 0 || min_freq > max_freq) { -- dev_err(dev, -- "min_freq(%d) or max_freq(%d) or nominal_freq(%d) value is incorrect, check _CPC in ACPI tables\n", -- min_freq, max_freq, nominal_freq); -- ret = -EINVAL; -- goto free_cpudata1; -- } - - policy->cpuinfo.min_freq = min_freq; - policy->cpuinfo.max_freq = max_freq; -@@ -1439,11 +1509,13 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) - - policy->driver_data = cpudata; - - cpudata->epp_cached = cpudata->epp_default = amd_pstate_get_epp(cpudata, 0); - - policy->min = policy->cpuinfo.min_freq; - policy->max = policy->cpuinfo.max_freq; - -+ policy->boost_enabled = READ_ONCE(cpudata->boost_supported); -+ - /* - * Set the policy to provide a valid fallback value in case - * the default cpufreq governor is neither powersave nor performance. -@@ -1454,7 +1526,7 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) - else - policy->policy = CPUFREQ_POLICY_POWERSAVE; - -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); - if (ret) - return ret; -@@ -1465,7 +1537,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) - return ret; - WRITE_ONCE(cpudata->cppc_cap1_cached, value); - } -- amd_pstate_boost_init(cpudata); - - return 0; - -@@ -1544,7 +1615,7 @@ static void amd_pstate_epp_update_limit(struct cpufreq_policy *policy) - epp = 0; - - /* Set initial EPP value */ -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; - } -@@ -1567,6 +1638,12 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) - - amd_pstate_epp_update_limit(policy); - -+ /* -+ * policy->cur is never updated with the amd_pstate_epp driver, but it -+ * is used as a stale frequency value. So, keep it within limits. -+ */ -+ policy->cur = policy->min; -+ - return 0; - } - -@@ -1583,7 +1660,7 @@ static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) - value = READ_ONCE(cpudata->cppc_req_cached); - max_perf = READ_ONCE(cpudata->highest_perf); - -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); - } else { - perf_ctrls.max_perf = max_perf; -@@ -1617,7 +1694,7 @@ static void amd_pstate_epp_offline(struct cpufreq_policy *policy) - value = READ_ONCE(cpudata->cppc_req_cached); - - mutex_lock(&amd_pstate_limits_lock); -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; - - /* Set max perf same as min perf */ -@@ -1721,6 +1798,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { - .suspend = amd_pstate_epp_suspend, - .resume = amd_pstate_epp_resume, - .update_limits = amd_pstate_update_limits, -+ .set_boost = amd_pstate_set_boost, - .name = "amd-pstate-epp", - .attr = amd_pstate_epp_attr, - }; -@@ -1744,6 +1822,46 @@ static int __init amd_pstate_set_driver(int mode_idx) - return -EINVAL; - } - -+/** -+ * CPPC function is not supported for family ID 17H with model_ID ranging from 0x10 to 0x2F. -+ * show the debug message that helps to check if the CPU has CPPC support for loading issue. -+ */ -+static bool amd_cppc_supported(void) -+{ -+ struct cpuinfo_x86 *c = &cpu_data(0); -+ bool warn = false; -+ -+ if ((boot_cpu_data.x86 == 0x17) && (boot_cpu_data.x86_model < 0x30)) { -+ pr_debug_once("CPPC feature is not supported by the processor\n"); -+ return false; -+ } -+ -+ /* -+ * If the CPPC feature is disabled in the BIOS for processors that support MSR-based CPPC, -+ * the AMD Pstate driver may not function correctly. -+ * Check the CPPC flag and display a warning message if the platform supports CPPC. -+ * Note: below checking code will not abort the driver registeration process because of -+ * the code is added for debugging purposes. -+ */ -+ if (!cpu_feature_enabled(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_ZEN1) || cpu_feature_enabled(X86_FEATURE_ZEN2)) { -+ if (c->x86_model > 0x60 && c->x86_model < 0xaf) -+ warn = true; -+ } else if (cpu_feature_enabled(X86_FEATURE_ZEN3) || cpu_feature_enabled(X86_FEATURE_ZEN4)) { -+ if ((c->x86_model > 0x10 && c->x86_model < 0x1F) || -+ (c->x86_model > 0x40 && c->x86_model < 0xaf)) -+ warn = true; -+ } else if (cpu_feature_enabled(X86_FEATURE_ZEN5)) { -+ warn = true; -+ } -+ } -+ -+ if (warn) -+ pr_warn_once("The CPPC feature is supported but currently disabled by the BIOS.\n" -+ "Please enable it if your BIOS has the CPPC option.\n"); -+ return true; -+} -+ - static int __init amd_pstate_init(void) - { - struct device *dev_root; -@@ -1752,6 +1870,11 @@ static int __init amd_pstate_init(void) - if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) - return -ENODEV; - -+ /* show debug message only if CPPC is not supported */ -+ if (!amd_cppc_supported()) -+ return -EOPNOTSUPP; -+ -+ /* show warning message when BIOS broken or ACPI disabled */ - if (!acpi_cpc_valid()) { - pr_warn_once("the _CPC object is not present in SBIOS or ACPI disabled\n"); - return -ENODEV; -@@ -1774,11 +1899,9 @@ static int __init amd_pstate_init(void) - /* Disable on the following configs by default: - * 1. Undefined platforms - * 2. Server platforms -- * 3. Shared memory designs - */ - if (amd_pstate_acpi_pm_profile_undefined() || -- amd_pstate_acpi_pm_profile_server() || -- !boot_cpu_has(X86_FEATURE_CPPC)) { -+ amd_pstate_acpi_pm_profile_server()) { - pr_info("driver load is disabled, boot with specific mode to enable this\n"); - return -ENODEV; - } -@@ -1802,7 +1925,7 @@ static int __init amd_pstate_init(void) - } - - /* capability check */ -- if (boot_cpu_has(X86_FEATURE_CPPC)) { -+ if (cpu_feature_enabled(X86_FEATURE_CPPC)) { - pr_debug("AMD CPPC MSR based functionality is supported\n"); - if (cppc_state != AMD_PSTATE_ACTIVE) - current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; -@@ -1821,8 +1944,10 @@ static int __init amd_pstate_init(void) - } - - ret = cpufreq_register_driver(current_pstate_driver); -- if (ret) -+ if (ret) { - pr_err("failed to register with return %d\n", ret); -+ goto disable_driver; -+ } - - dev_root = bus_get_dev_root(&cpu_subsys); - if (dev_root) { -@@ -1830,6 +1963,8 @@ static int __init amd_pstate_init(void) - - global_attr_free: - cpufreq_unregister_driver(current_pstate_driver); -+disable_driver: -+ amd_pstate_enable(false); - return ret; - } - device_initcall(amd_pstate_init); -diff --git a/drivers/cpufreq/amd-pstate.h b/drivers/cpufreq/amd-pstate.h -index e6a28e7f4dbf..cc8bb2bc325a 100644 ---- a/drivers/cpufreq/amd-pstate.h -+++ b/drivers/cpufreq/amd-pstate.h -@@ -99,7 +99,8 @@ struct amd_cpudata { - u32 policy; - u64 cppc_cap1_cached; - bool suspended; - s16 epp_default; -+ bool boost_state; - }; - - #endif /* _LINUX_AMD_PSTATE_H */ -diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c -index 9e5060b27864..270ea04fb616 100644 ---- a/drivers/cpufreq/cpufreq.c -+++ b/drivers/cpufreq/cpufreq.c -@@ -614,10 +614,9 @@ static ssize_t show_boost(struct kobject *kobj, - static ssize_t store_boost(struct kobject *kobj, struct kobj_attribute *attr, - const char *buf, size_t count) - { -- int ret, enable; -+ bool enable; - -- ret = sscanf(buf, "%d", &enable); -- if (ret != 1 || enable < 0 || enable > 1) -+ if (kstrtobool(buf, &enable)) - return -EINVAL; - - if (cpufreq_boost_trigger_state(enable)) { -@@ -641,10 +640,10 @@ static ssize_t show_local_boost(struct cpufreq_policy *policy, char *buf) - static ssize_t store_local_boost(struct cpufreq_policy *policy, - const char *buf, size_t count) - { -- int ret, enable; -+ int ret; -+ bool enable; - -- ret = kstrtoint(buf, 10, &enable); -- if (ret || enable < 0 || enable > 1) -+ if (kstrtobool(buf, &enable)) - return -EINVAL; - - if (!cpufreq_driver->boost_enabled) --- -2.46.0.rc1 - diff --git a/SOURCES/0001-ntsync.patch b/SOURCES/0001-ntsync.patch deleted file mode 100644 index 4a16758..0000000 --- a/SOURCES/0001-ntsync.patch +++ /dev/null @@ -1,3089 +0,0 @@ -From 36ef0070410e229e52c9de58d6021df36a4b1707 Mon Sep 17 00:00:00 2001 -From: Peter Jung <admin@ptr1337.dev> -Date: Sat, 3 Aug 2024 09:34:15 +0200 -Subject: [PATCH 09/12] ntsync - -Signed-off-by: Peter Jung <admin@ptr1337.dev> ---- - Documentation/userspace-api/index.rst | 1 + - Documentation/userspace-api/ntsync.rst | 398 +++++ - MAINTAINERS | 9 + - drivers/misc/Kconfig | 1 - - drivers/misc/ntsync.c | 989 +++++++++++- - include/uapi/linux/ntsync.h | 39 + - tools/testing/selftests/Makefile | 1 + - .../selftests/drivers/ntsync/.gitignore | 1 + - .../testing/selftests/drivers/ntsync/Makefile | 7 + - tools/testing/selftests/drivers/ntsync/config | 1 + - .../testing/selftests/drivers/ntsync/ntsync.c | 1407 +++++++++++++++++ - 11 files changed, 2850 insertions(+), 4 deletions(-) - create mode 100644 Documentation/userspace-api/ntsync.rst - create mode 100644 tools/testing/selftests/drivers/ntsync/.gitignore - create mode 100644 tools/testing/selftests/drivers/ntsync/Makefile - create mode 100644 tools/testing/selftests/drivers/ntsync/config - create mode 100644 tools/testing/selftests/drivers/ntsync/ntsync.c - -diff --git a/Documentation/userspace-api/index.rst b/Documentation/userspace-api/index.rst -index 8a251d71fa6e..02bea81fb4bf 100644 ---- a/Documentation/userspace-api/index.rst -+++ b/Documentation/userspace-api/index.rst -@@ -64,6 +64,7 @@ Everything else - vduse - futex2 - perf_ring_buffer -+ ntsync - - .. only:: subproject and html - -diff --git a/Documentation/userspace-api/ntsync.rst b/Documentation/userspace-api/ntsync.rst -new file mode 100644 -index 000000000000..767844637a7d ---- /dev/null -+++ b/Documentation/userspace-api/ntsync.rst -@@ -0,0 +1,398 @@ -+=================================== -+NT synchronization primitive driver -+=================================== -+ -+This page documents the user-space API for the ntsync driver. -+ -+ntsync is a support driver for emulation of NT synchronization -+primitives by user-space NT emulators. It exists because implementation -+in user-space, using existing tools, cannot match Windows performance -+while offering accurate semantics. It is implemented entirely in -+software, and does not drive any hardware device. -+ -+This interface is meant as a compatibility tool only, and should not -+be used for general synchronization. Instead use generic, versatile -+interfaces such as futex(2) and poll(2). -+ -+Synchronization primitives -+========================== -+ -+The ntsync driver exposes three types of synchronization primitives: -+semaphores, mutexes, and events. -+ -+A semaphore holds a single volatile 32-bit counter, and a static 32-bit -+integer denoting the maximum value. It is considered signaled (that is, -+can be acquired without contention, or will wake up a waiting thread) -+when the counter is nonzero. The counter is decremented by one when a -+wait is satisfied. Both the initial and maximum count are established -+when the semaphore is created. -+ -+A mutex holds a volatile 32-bit recursion count, and a volatile 32-bit -+identifier denoting its owner. A mutex is considered signaled when its -+owner is zero (indicating that it is not owned). The recursion count is -+incremented when a wait is satisfied, and ownership is set to the given -+identifier. -+ -+A mutex also holds an internal flag denoting whether its previous owner -+has died; such a mutex is said to be abandoned. Owner death is not -+tracked automatically based on thread death, but rather must be -+communicated using ``NTSYNC_IOC_MUTEX_KILL``. An abandoned mutex is -+inherently considered unowned. -+ -+Except for the "unowned" semantics of zero, the actual value of the -+owner identifier is not interpreted by the ntsync driver at all. The -+intended use is to store a thread identifier; however, the ntsync -+driver does not actually validate that a calling thread provides -+consistent or unique identifiers. -+ -+An event is similar to a semaphore with a maximum count of one. It holds -+a volatile boolean state denoting whether it is signaled or not. There -+are two types of events, auto-reset and manual-reset. An auto-reset -+event is designaled when a wait is satisfied; a manual-reset event is -+not. The event type is specified when the event is created. -+ -+Unless specified otherwise, all operations on an object are atomic and -+totally ordered with respect to other operations on the same object. -+ -+Objects are represented by files. When all file descriptors to an -+object are closed, that object is deleted. -+ -+Char device -+=========== -+ -+The ntsync driver creates a single char device /dev/ntsync. Each file -+description opened on the device represents a unique instance intended -+to back an individual NT virtual machine. Objects created by one ntsync -+instance may only be used with other objects created by the same -+instance. -+ -+ioctl reference -+=============== -+ -+All operations on the device are done through ioctls. There are four -+structures used in ioctl calls:: -+ -+ struct ntsync_sem_args { -+ __u32 sem; -+ __u32 count; -+ __u32 max; -+ }; -+ -+ struct ntsync_mutex_args { -+ __u32 mutex; -+ __u32 owner; -+ __u32 count; -+ }; -+ -+ struct ntsync_event_args { -+ __u32 event; -+ __u32 signaled; -+ __u32 manual; -+ }; -+ -+ struct ntsync_wait_args { -+ __u64 timeout; -+ __u64 objs; -+ __u32 count; -+ __u32 owner; -+ __u32 index; -+ __u32 alert; -+ __u32 flags; -+ __u32 pad; -+ }; -+ -+Depending on the ioctl, members of the structure may be used as input, -+output, or not at all. All ioctls return 0 on success. -+ -+The ioctls on the device file are as follows: -+ -+.. c:macro:: NTSYNC_IOC_CREATE_SEM -+ -+ Create a semaphore object. Takes a pointer to struct -+ :c:type:`ntsync_sem_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``sem`` -+ - On output, contains a file descriptor to the created semaphore. -+ * - ``count`` -+ - Initial count of the semaphore. -+ * - ``max`` -+ - Maximum count of the semaphore. -+ -+ Fails with ``EINVAL`` if ``count`` is greater than ``max``. -+ -+.. c:macro:: NTSYNC_IOC_CREATE_MUTEX -+ -+ Create a mutex object. Takes a pointer to struct -+ :c:type:`ntsync_mutex_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``mutex`` -+ - On output, contains a file descriptor to the created mutex. -+ * - ``count`` -+ - Initial recursion count of the mutex. -+ * - ``owner`` -+ - Initial owner of the mutex. -+ -+ If ``owner`` is nonzero and ``count`` is zero, or if ``owner`` is -+ zero and ``count`` is nonzero, the function fails with ``EINVAL``. -+ -+.. c:macro:: NTSYNC_IOC_CREATE_EVENT -+ -+ Create an event object. Takes a pointer to struct -+ :c:type:`ntsync_event_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``event`` -+ - On output, contains a file descriptor to the created event. -+ * - ``signaled`` -+ - If nonzero, the event is initially signaled, otherwise -+ nonsignaled. -+ * - ``manual`` -+ - If nonzero, the event is a manual-reset event, otherwise -+ auto-reset. -+ -+The ioctls on the individual objects are as follows: -+ -+.. c:macro:: NTSYNC_IOC_SEM_POST -+ -+ Post to a semaphore object. Takes a pointer to a 32-bit integer, -+ which on input holds the count to be added to the semaphore, and on -+ output contains its previous count. -+ -+ If adding to the semaphore's current count would raise the latter -+ past the semaphore's maximum count, the ioctl fails with -+ ``EOVERFLOW`` and the semaphore is not affected. If raising the -+ semaphore's count causes it to become signaled, eligible threads -+ waiting on this semaphore will be woken and the semaphore's count -+ decremented appropriately. -+ -+.. c:macro:: NTSYNC_IOC_MUTEX_UNLOCK -+ -+ Release a mutex object. Takes a pointer to struct -+ :c:type:`ntsync_mutex_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``mutex`` -+ - Ignored. -+ * - ``owner`` -+ - Specifies the owner trying to release this mutex. -+ * - ``count`` -+ - On output, contains the previous recursion count. -+ -+ If ``owner`` is zero, the ioctl fails with ``EINVAL``. If ``owner`` -+ is not the current owner of the mutex, the ioctl fails with -+ ``EPERM``. -+ -+ The mutex's count will be decremented by one. If decrementing the -+ mutex's count causes it to become zero, the mutex is marked as -+ unowned and signaled, and eligible threads waiting on it will be -+ woken as appropriate. -+ -+.. c:macro:: NTSYNC_IOC_SET_EVENT -+ -+ Signal an event object. Takes a pointer to a 32-bit integer, which on -+ output contains the previous state of the event. -+ -+ Eligible threads will be woken, and auto-reset events will be -+ designaled appropriately. -+ -+.. c:macro:: NTSYNC_IOC_RESET_EVENT -+ -+ Designal an event object. Takes a pointer to a 32-bit integer, which -+ on output contains the previous state of the event. -+ -+.. c:macro:: NTSYNC_IOC_PULSE_EVENT -+ -+ Wake threads waiting on an event object while leaving it in an -+ unsignaled state. Takes a pointer to a 32-bit integer, which on -+ output contains the previous state of the event. -+ -+ A pulse operation can be thought of as a set followed by a reset, -+ performed as a single atomic operation. If two threads are waiting on -+ an auto-reset event which is pulsed, only one will be woken. If two -+ threads are waiting a manual-reset event which is pulsed, both will -+ be woken. However, in both cases, the event will be unsignaled -+ afterwards, and a simultaneous read operation will always report the -+ event as unsignaled. -+ -+.. c:macro:: NTSYNC_IOC_READ_SEM -+ -+ Read the current state of a semaphore object. Takes a pointer to -+ struct :c:type:`ntsync_sem_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``sem`` -+ - Ignored. -+ * - ``count`` -+ - On output, contains the current count of the semaphore. -+ * - ``max`` -+ - On output, contains the maximum count of the semaphore. -+ -+.. c:macro:: NTSYNC_IOC_READ_MUTEX -+ -+ Read the current state of a mutex object. Takes a pointer to struct -+ :c:type:`ntsync_mutex_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``mutex`` -+ - Ignored. -+ * - ``owner`` -+ - On output, contains the current owner of the mutex, or zero -+ if the mutex is not currently owned. -+ * - ``count`` -+ - On output, contains the current recursion count of the mutex. -+ -+ If the mutex is marked as abandoned, the function fails with -+ ``EOWNERDEAD``. In this case, ``count`` and ``owner`` are set to -+ zero. -+ -+.. c:macro:: NTSYNC_IOC_READ_EVENT -+ -+ Read the current state of an event object. Takes a pointer to struct -+ :c:type:`ntsync_event_args`, which is used as follows: -+ -+ .. list-table:: -+ -+ * - ``event`` -+ - Ignored. -+ * - ``signaled`` -+ - On output, contains the current state of the event. -+ * - ``manual`` -+ - On output, contains 1 if the event is a manual-reset event, -+ and 0 otherwise. -+ -+.. c:macro:: NTSYNC_IOC_KILL_OWNER -+ -+ Mark a mutex as unowned and abandoned if it is owned by the given -+ owner. Takes an input-only pointer to a 32-bit integer denoting the -+ owner. If the owner is zero, the ioctl fails with ``EINVAL``. If the -+ owner does not own the mutex, the function fails with ``EPERM``. -+ -+ Eligible threads waiting on the mutex will be woken as appropriate -+ (and such waits will fail with ``EOWNERDEAD``, as described below). -+ -+.. c:macro:: NTSYNC_IOC_WAIT_ANY -+ -+ Poll on any of a list of objects, atomically acquiring at most one. -+ Takes a pointer to struct :c:type:`ntsync_wait_args`, which is -+ used as follows: -+ -+ .. list-table:: -+ -+ * - ``timeout`` -+ - Absolute timeout in nanoseconds. If ``NTSYNC_WAIT_REALTIME`` -+ is set, the timeout is measured against the REALTIME clock; -+ otherwise it is measured against the MONOTONIC clock. If the -+ timeout is equal to or earlier than the current time, the -+ function returns immediately without sleeping. If ``timeout`` -+ is U64_MAX, the function will sleep until an object is -+ signaled, and will not fail with ``ETIMEDOUT``. -+ * - ``objs`` -+ - Pointer to an array of ``count`` file descriptors -+ (specified as an integer so that the structure has the same -+ size regardless of architecture). If any object is -+ invalid, the function fails with ``EINVAL``. -+ * - ``count`` -+ - Number of objects specified in the ``objs`` array. -+ If greater than ``NTSYNC_MAX_WAIT_COUNT``, the function fails -+ with ``EINVAL``. -+ * - ``owner`` -+ - Mutex owner identifier. If any object in ``objs`` is a mutex, -+ the ioctl will attempt to acquire that mutex on behalf of -+ ``owner``. If ``owner`` is zero, the ioctl fails with -+ ``EINVAL``. -+ * - ``index`` -+ - On success, contains the index (into ``objs``) of the object -+ which was signaled. If ``alert`` was signaled instead, -+ this contains ``count``. -+ * - ``alert`` -+ - Optional event object file descriptor. If nonzero, this -+ specifies an "alert" event object which, if signaled, will -+ terminate the wait. If nonzero, the identifier must point to a -+ valid event. -+ * - ``flags`` -+ - Zero or more flags. Currently the only flag is -+ ``NTSYNC_WAIT_REALTIME``, which causes the timeout to be -+ measured against the REALTIME clock instead of MONOTONIC. -+ * - ``pad`` -+ - Unused, must be set to zero. -+ -+ This function attempts to acquire one of the given objects. If unable -+ to do so, it sleeps until an object becomes signaled, subsequently -+ acquiring it, or the timeout expires. In the latter case the ioctl -+ fails with ``ETIMEDOUT``. The function only acquires one object, even -+ if multiple objects are signaled. -+ -+ A semaphore is considered to be signaled if its count is nonzero, and -+ is acquired by decrementing its count by one. A mutex is considered -+ to be signaled if it is unowned or if its owner matches the ``owner`` -+ argument, and is acquired by incrementing its recursion count by one -+ and setting its owner to the ``owner`` argument. An auto-reset event -+ is acquired by designaling it; a manual-reset event is not affected -+ by acquisition. -+ -+ Acquisition is atomic and totally ordered with respect to other -+ operations on the same object. If two wait operations (with different -+ ``owner`` identifiers) are queued on the same mutex, only one is -+ signaled. If two wait operations are queued on the same semaphore, -+ and a value of one is posted to it, only one is signaled. -+ -+ If an abandoned mutex is acquired, the ioctl fails with -+ ``EOWNERDEAD``. Although this is a failure return, the function may -+ otherwise be considered successful. The mutex is marked as owned by -+ the given owner (with a recursion count of 1) and as no longer -+ abandoned, and ``index`` is still set to the index of the mutex. -+ -+ The ``alert`` argument is an "extra" event which can terminate the -+ wait, independently of all other objects. -+ -+ It is valid to pass the same object more than once, including by -+ passing the same event in the ``objs`` array and in ``alert``. If a -+ wakeup occurs due to that object being signaled, ``index`` is set to -+ the lowest index corresponding to that object. -+ -+ The function may fail with ``EINTR`` if a signal is received. -+ -+.. c:macro:: NTSYNC_IOC_WAIT_ALL -+ -+ Poll on a list of objects, atomically acquiring all of them. Takes a -+ pointer to struct :c:type:`ntsync_wait_args`, which is used -+ identically to ``NTSYNC_IOC_WAIT_ANY``, except that ``index`` is -+ always filled with zero on success if not woken via alert. -+ -+ This function attempts to simultaneously acquire all of the given -+ objects. If unable to do so, it sleeps until all objects become -+ simultaneously signaled, subsequently acquiring them, or the timeout -+ expires. In the latter case the ioctl fails with ``ETIMEDOUT`` and no -+ objects are modified. -+ -+ Objects may become signaled and subsequently designaled (through -+ acquisition by other threads) while this thread is sleeping. Only -+ once all objects are simultaneously signaled does the ioctl acquire -+ them and return. The entire acquisition is atomic and totally ordered -+ with respect to other operations on any of the given objects. -+ -+ If an abandoned mutex is acquired, the ioctl fails with -+ ``EOWNERDEAD``. Similarly to ``NTSYNC_IOC_WAIT_ANY``, all objects are -+ nevertheless marked as acquired. Note that if multiple mutex objects -+ are specified, there is no way to know which were marked as -+ abandoned. -+ -+ As with "any" waits, the ``alert`` argument is an "extra" event which -+ can terminate the wait. Critically, however, an "all" wait will -+ succeed if all members in ``objs`` are signaled, *or* if ``alert`` is -+ signaled. In the latter case ``index`` will be set to ``count``. As -+ with "any" waits, if both conditions are filled, the former takes -+ priority, and objects in ``objs`` will be acquired. -+ -+ Unlike ``NTSYNC_IOC_WAIT_ANY``, it is not valid to pass the same -+ object more than once, nor is it valid to pass the same object in -+ ``objs`` and in ``alert``. If this is attempted, the function fails -+ with ``EINVAL``. -diff --git a/MAINTAINERS b/MAINTAINERS -index b27470be2e6a..4112729fc23a 100644 ---- a/MAINTAINERS -+++ b/MAINTAINERS -@@ -15983,6 +15983,15 @@ T: git https://github.com/Paragon-Software-Group/linux-ntfs3.git - F: Documentation/filesystems/ntfs3.rst - F: fs/ntfs3/ - -+NTSYNC SYNCHRONIZATION PRIMITIVE DRIVER -+M: Elizabeth Figura <zfigura@codeweavers.com> -+L: wine-devel@winehq.org -+S: Supported -+F: Documentation/userspace-api/ntsync.rst -+F: drivers/misc/ntsync.c -+F: include/uapi/linux/ntsync.h -+F: tools/testing/selftests/drivers/ntsync/ -+ - NUBUS SUBSYSTEM - M: Finn Thain <fthain@linux-m68k.org> - L: linux-m68k@lists.linux-m68k.org -diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig -index faf983680040..2907b5c23368 100644 ---- a/drivers/misc/Kconfig -+++ b/drivers/misc/Kconfig -@@ -507,7 +507,6 @@ config OPEN_DICE - - config NTSYNC - tristate "NT synchronization primitive emulation" -- depends on BROKEN - help - This module provides kernel support for emulation of Windows NT - synchronization primitives. It is not a hardware driver. -diff --git a/drivers/misc/ntsync.c b/drivers/misc/ntsync.c -index 3c2f743c58b0..87a24798a5c7 100644 ---- a/drivers/misc/ntsync.c -+++ b/drivers/misc/ntsync.c -@@ -6,11 +6,17 @@ - */ - - #include <linux/anon_inodes.h> -+#include <linux/atomic.h> - #include <linux/file.h> - #include <linux/fs.h> -+#include <linux/hrtimer.h> -+#include <linux/ktime.h> - #include <linux/miscdevice.h> - #include <linux/module.h> -+#include <linux/mutex.h> - #include <linux/overflow.h> -+#include <linux/sched.h> -+#include <linux/sched/signal.h> - #include <linux/slab.h> - #include <linux/spinlock.h> - #include <uapi/linux/ntsync.h> -@@ -19,6 +25,8 @@ - - enum ntsync_type { - NTSYNC_TYPE_SEM, -+ NTSYNC_TYPE_MUTEX, -+ NTSYNC_TYPE_EVENT, - }; - - /* -@@ -30,10 +38,13 @@ enum ntsync_type { - * - * Both rely on struct file for reference counting. Individual - * ntsync_obj objects take a reference to the device when created. -+ * Wait operations take a reference to each object being waited on for -+ * the duration of the wait. - */ - - struct ntsync_obj { - spinlock_t lock; -+ int dev_locked; - - enum ntsync_type type; - -@@ -46,13 +57,335 @@ struct ntsync_obj { - __u32 count; - __u32 max; - } sem; -+ struct { -+ __u32 count; -+ pid_t owner; -+ bool ownerdead; -+ } mutex; -+ struct { -+ bool manual; -+ bool signaled; -+ } event; - } u; -+ -+ /* -+ * any_waiters is protected by the object lock, but all_waiters is -+ * protected by the device wait_all_lock. -+ */ -+ struct list_head any_waiters; -+ struct list_head all_waiters; -+ -+ /* -+ * Hint describing how many tasks are queued on this object in a -+ * wait-all operation. -+ * -+ * Any time we do a wake, we may need to wake "all" waiters as well as -+ * "any" waiters. In order to atomically wake "all" waiters, we must -+ * lock all of the objects, and that means grabbing the wait_all_lock -+ * below (and, due to lock ordering rules, before locking this object). -+ * However, wait-all is a rare operation, and grabbing the wait-all -+ * lock for every wake would create unnecessary contention. -+ * Therefore we first check whether all_hint is zero, and, if it is, -+ * we skip trying to wake "all" waiters. -+ * -+ * Since wait requests must originate from user-space threads, we're -+ * limited here by PID_MAX_LIMIT, so there's no risk of overflow. -+ */ -+ atomic_t all_hint; -+}; -+ -+struct ntsync_q_entry { -+ struct list_head node; -+ struct ntsync_q *q; -+ struct ntsync_obj *obj; -+ __u32 index; -+}; -+ -+struct ntsync_q { -+ struct task_struct *task; -+ __u32 owner; -+ -+ /* -+ * Protected via atomic_try_cmpxchg(). Only the thread that wins the -+ * compare-and-swap may actually change object states and wake this -+ * task. -+ */ -+ atomic_t signaled; -+ -+ bool all; -+ bool ownerdead; -+ __u32 count; -+ struct ntsync_q_entry entries[]; - }; - - struct ntsync_device { -+ /* -+ * Wait-all operations must atomically grab all objects, and be totally -+ * ordered with respect to each other and wait-any operations. -+ * If one thread is trying to acquire several objects, another thread -+ * cannot touch the object at the same time. -+ * -+ * This device-wide lock is used to serialize wait-for-all -+ * operations, and operations on an object that is involved in a -+ * wait-for-all. -+ */ -+ struct mutex wait_all_lock; -+ - struct file *file; - }; - -+/* -+ * Single objects are locked using obj->lock. -+ * -+ * Multiple objects are 'locked' while holding dev->wait_all_lock. -+ * In this case however, individual objects are not locked by holding -+ * obj->lock, but by setting obj->dev_locked. -+ * -+ * This means that in order to lock a single object, the sequence is slightly -+ * more complicated than usual. Specifically it needs to check obj->dev_locked -+ * after acquiring obj->lock, if set, it needs to drop the lock and acquire -+ * dev->wait_all_lock in order to serialize against the multi-object operation. -+ */ -+ -+static void dev_lock_obj(struct ntsync_device *dev, struct ntsync_obj *obj) -+{ -+ lockdep_assert_held(&dev->wait_all_lock); -+ lockdep_assert(obj->dev == dev); -+ spin_lock(&obj->lock); -+ /* -+ * By setting obj->dev_locked inside obj->lock, it is ensured that -+ * anyone holding obj->lock must see the value. -+ */ -+ obj->dev_locked = 1; -+ spin_unlock(&obj->lock); -+} -+ -+static void dev_unlock_obj(struct ntsync_device *dev, struct ntsync_obj *obj) -+{ -+ lockdep_assert_held(&dev->wait_all_lock); -+ lockdep_assert(obj->dev == dev); -+ spin_lock(&obj->lock); -+ obj->dev_locked = 0; -+ spin_unlock(&obj->lock); -+} -+ -+static void obj_lock(struct ntsync_obj *obj) -+{ -+ struct ntsync_device *dev = obj->dev; -+ -+ for (;;) { -+ spin_lock(&obj->lock); -+ if (likely(!obj->dev_locked)) -+ break; -+ -+ spin_unlock(&obj->lock); -+ mutex_lock(&dev->wait_all_lock); -+ spin_lock(&obj->lock); -+ /* -+ * obj->dev_locked should be set and released under the same -+ * wait_all_lock section, since we now own this lock, it should -+ * be clear. -+ */ -+ lockdep_assert(!obj->dev_locked); -+ spin_unlock(&obj->lock); -+ mutex_unlock(&dev->wait_all_lock); -+ } -+} -+ -+static void obj_unlock(struct ntsync_obj *obj) -+{ -+ spin_unlock(&obj->lock); -+} -+ -+static bool ntsync_lock_obj(struct ntsync_device *dev, struct ntsync_obj *obj) -+{ -+ bool all; -+ -+ obj_lock(obj); -+ all = atomic_read(&obj->all_hint); -+ if (unlikely(all)) { -+ obj_unlock(obj); -+ mutex_lock(&dev->wait_all_lock); -+ dev_lock_obj(dev, obj); -+ } -+ -+ return all; -+} -+ -+static void ntsync_unlock_obj(struct ntsync_device *dev, struct ntsync_obj *obj, bool all) -+{ -+ if (all) { -+ dev_unlock_obj(dev, obj); -+ mutex_unlock(&dev->wait_all_lock); -+ } else { -+ obj_unlock(obj); -+ } -+} -+ -+#define ntsync_assert_held(obj) \ -+ lockdep_assert((lockdep_is_held(&(obj)->lock) != LOCK_STATE_NOT_HELD) || \ -+ ((lockdep_is_held(&(obj)->dev->wait_all_lock) != LOCK_STATE_NOT_HELD) && \ -+ (obj)->dev_locked)) -+ -+static bool is_signaled(struct ntsync_obj *obj, __u32 owner) -+{ -+ ntsync_assert_held(obj); -+ -+ switch (obj->type) { -+ case NTSYNC_TYPE_SEM: -+ return !!obj->u.sem.count; -+ case NTSYNC_TYPE_MUTEX: -+ if (obj->u.mutex.owner && obj->u.mutex.owner != owner) -+ return false; -+ return obj->u.mutex.count < UINT_MAX; -+ case NTSYNC_TYPE_EVENT: -+ return obj->u.event.signaled; -+ } -+ -+ WARN(1, "bad object type %#x\n", obj->type); -+ return false; -+} -+ -+/* -+ * "locked_obj" is an optional pointer to an object which is already locked and -+ * should not be locked again. This is necessary so that changing an object's -+ * state and waking it can be a single atomic operation. -+ */ -+static void try_wake_all(struct ntsync_device *dev, struct ntsync_q *q, -+ struct ntsync_obj *locked_obj) -+{ -+ __u32 count = q->count; -+ bool can_wake = true; -+ int signaled = -1; -+ __u32 i; -+ -+ lockdep_assert_held(&dev->wait_all_lock); -+ if (locked_obj) -+ lockdep_assert(locked_obj->dev_locked); -+ -+ for (i = 0; i < count; i++) { -+ if (q->entries[i].obj != locked_obj) -+ dev_lock_obj(dev, q->entries[i].obj); -+ } -+ -+ for (i = 0; i < count; i++) { -+ if (!is_signaled(q->entries[i].obj, q->owner)) { -+ can_wake = false; -+ break; -+ } -+ } -+ -+ if (can_wake && atomic_try_cmpxchg(&q->signaled, &signaled, 0)) { -+ for (i = 0; i < count; i++) { -+ struct ntsync_obj *obj = q->entries[i].obj; -+ -+ switch (obj->type) { -+ case NTSYNC_TYPE_SEM: -+ obj->u.sem.count--; -+ break; -+ case NTSYNC_TYPE_MUTEX: -+ if (obj->u.mutex.ownerdead) -+ q->ownerdead = true; -+ obj->u.mutex.ownerdead = false; -+ obj->u.mutex.count++; -+ obj->u.mutex.owner = q->owner; -+ break; -+ case NTSYNC_TYPE_EVENT: -+ if (!obj->u.event.manual) -+ obj->u.event.signaled = false; -+ break; -+ } -+ } -+ wake_up_process(q->task); -+ } -+ -+ for (i = 0; i < count; i++) { -+ if (q->entries[i].obj != locked_obj) -+ dev_unlock_obj(dev, q->entries[i].obj); -+ } -+} -+ -+static void try_wake_all_obj(struct ntsync_device *dev, struct ntsync_obj *obj) -+{ -+ struct ntsync_q_entry *entry; -+ -+ lockdep_assert_held(&dev->wait_all_lock); -+ lockdep_assert(obj->dev_locked); -+ -+ list_for_each_entry(entry, &obj->all_waiters, node) -+ try_wake_all(dev, entry->q, obj); -+} -+ -+static void try_wake_any_sem(struct ntsync_obj *sem) -+{ -+ struct ntsync_q_entry *entry; -+ -+ ntsync_assert_held(sem); -+ lockdep_assert(sem->type == NTSYNC_TYPE_SEM); -+ -+ list_for_each_entry(entry, &sem->any_waiters, node) { -+ struct ntsync_q *q = entry->q; -+ int signaled = -1; -+ -+ if (!sem->u.sem.count) -+ break; -+ -+ if (atomic_try_cmpxchg(&q->signaled, &signaled, entry->index)) { -+ sem->u.sem.count--; -+ wake_up_process(q->task); -+ } -+ } -+} -+ -+static void try_wake_any_mutex(struct ntsync_obj *mutex) -+{ -+ struct ntsync_q_entry *entry; -+ -+ ntsync_assert_held(mutex); -+ lockdep_assert(mutex->type == NTSYNC_TYPE_MUTEX); -+ -+ list_for_each_entry(entry, &mutex->any_waiters, node) { -+ struct ntsync_q *q = entry->q; -+ int signaled = -1; -+ -+ if (mutex->u.mutex.count == UINT_MAX) -+ break; -+ if (mutex->u.mutex.owner && mutex->u.mutex.owner != q->owner) -+ continue; -+ -+ if (atomic_try_cmpxchg(&q->signaled, &signaled, entry->index)) { -+ if (mutex->u.mutex.ownerdead) -+ q->ownerdead = true; -+ mutex->u.mutex.ownerdead = false; -+ mutex->u.mutex.count++; -+ mutex->u.mutex.owner = q->owner; -+ wake_up_process(q->task); -+ } -+ } -+} -+ -+static void try_wake_any_event(struct ntsync_obj *event) -+{ -+ struct ntsync_q_entry *entry; -+ -+ ntsync_assert_held(event); -+ lockdep_assert(event->type == NTSYNC_TYPE_EVENT); -+ -+ list_for_each_entry(entry, &event->any_waiters, node) { -+ struct ntsync_q *q = entry->q; -+ int signaled = -1; -+ -+ if (!event->u.event.signaled) -+ break; -+ -+ if (atomic_try_cmpxchg(&q->signaled, &signaled, entry->index)) { -+ if (!event->u.event.manual) -+ event->u.event.signaled = false; -+ wake_up_process(q->task); -+ } -+ } -+} -+ - /* - * Actually change the semaphore state, returning -EOVERFLOW if it is made - * invalid. -@@ -61,7 +394,7 @@ static int post_sem_state(struct ntsync_obj *sem, __u32 count) - { - __u32 sum; - -- lockdep_assert_held(&sem->lock); -+ ntsync_assert_held(sem); - - if (check_add_overflow(sem->u.sem.count, count, &sum) || - sum > sem->u.sem.max) -@@ -73,9 +406,11 @@ static int post_sem_state(struct ntsync_obj *sem, __u32 count) - - static int ntsync_sem_post(struct ntsync_obj *sem, void __user *argp) - { -+ struct ntsync_device *dev = sem->dev; - __u32 __user *user_args = argp; - __u32 prev_count; - __u32 args; -+ bool all; - int ret; - - if (copy_from_user(&args, argp, sizeof(args))) -@@ -84,12 +419,17 @@ static int ntsync_sem_post(struct ntsync_obj *sem, void __user *argp) - if (sem->type != NTSYNC_TYPE_SEM) - return -EINVAL; - -- spin_lock(&sem->lock); -+ all = ntsync_lock_obj(dev, sem); - - prev_count = sem->u.sem.count; - ret = post_sem_state(sem, args); -+ if (!ret) { -+ if (all) -+ try_wake_all_obj(dev, sem); -+ try_wake_any_sem(sem); -+ } - -- spin_unlock(&sem->lock); -+ ntsync_unlock_obj(dev, sem, all); - - if (!ret && put_user(prev_count, user_args)) - ret = -EFAULT; -@@ -97,6 +437,226 @@ static int ntsync_sem_post(struct ntsync_obj *sem, void __user *argp) - return ret; - } - -+/* -+ * Actually change the mutex state, returning -EPERM if not the owner. -+ */ -+static int unlock_mutex_state(struct ntsync_obj *mutex, -+ const struct ntsync_mutex_args *args) -+{ -+ ntsync_assert_held(mutex); -+ -+ if (mutex->u.mutex.owner != args->owner) -+ return -EPERM; -+ -+ if (!--mutex->u.mutex.count) -+ mutex->u.mutex.owner = 0; -+ return 0; -+} -+ -+static int ntsync_mutex_unlock(struct ntsync_obj *mutex, void __user *argp) -+{ -+ struct ntsync_mutex_args __user *user_args = argp; -+ struct ntsync_device *dev = mutex->dev; -+ struct ntsync_mutex_args args; -+ __u32 prev_count; -+ bool all; -+ int ret; -+ -+ if (copy_from_user(&args, argp, sizeof(args))) -+ return -EFAULT; -+ if (!args.owner) -+ return -EINVAL; -+ -+ if (mutex->type != NTSYNC_TYPE_MUTEX) -+ return -EINVAL; -+ -+ all = ntsync_lock_obj(dev, mutex); -+ -+ prev_count = mutex->u.mutex.count; -+ ret = unlock_mutex_state(mutex, &args); -+ if (!ret) { -+ if (all) -+ try_wake_all_obj(dev, mutex); -+ try_wake_any_mutex(mutex); -+ } -+ -+ ntsync_unlock_obj(dev, mutex, all); -+ -+ if (!ret && put_user(prev_count, &user_args->count)) -+ ret = -EFAULT; -+ -+ return ret; -+} -+ -+/* -+ * Actually change the mutex state to mark its owner as dead, -+ * returning -EPERM if not the owner. -+ */ -+static int kill_mutex_state(struct ntsync_obj *mutex, __u32 owner) -+{ -+ ntsync_assert_held(mutex); -+ -+ if (mutex->u.mutex.owner != owner) -+ return -EPERM; -+ -+ mutex->u.mutex.ownerdead = true; -+ mutex->u.mutex.owner = 0; -+ mutex->u.mutex.count = 0; -+ return 0; -+} -+ -+static int ntsync_mutex_kill(struct ntsync_obj *mutex, void __user *argp) -+{ -+ struct ntsync_device *dev = mutex->dev; -+ __u32 owner; -+ bool all; -+ int ret; -+ -+ if (get_user(owner, (__u32 __user *)argp)) -+ return -EFAULT; -+ if (!owner) -+ return -EINVAL; -+ -+ if (mutex->type != NTSYNC_TYPE_MUTEX) -+ return -EINVAL; -+ -+ all = ntsync_lock_obj(dev, mutex); -+ -+ ret = kill_mutex_state(mutex, owner); -+ if (!ret) { -+ if (all) -+ try_wake_all_obj(dev, mutex); -+ try_wake_any_mutex(mutex); -+ } -+ -+ ntsync_unlock_obj(dev, mutex, all); -+ -+ return ret; -+} -+ -+static int ntsync_event_set(struct ntsync_obj *event, void __user *argp, bool pulse) -+{ -+ struct ntsync_device *dev = event->dev; -+ __u32 prev_state; -+ bool all; -+ -+ if (event->type != NTSYNC_TYPE_EVENT) -+ return -EINVAL; -+ -+ all = ntsync_lock_obj(dev, event); -+ -+ prev_state = event->u.event.signaled; -+ event->u.event.signaled = true; -+ if (all) -+ try_wake_all_obj(dev, event); -+ try_wake_any_event(event); -+ if (pulse) -+ event->u.event.signaled = false; -+ -+ ntsync_unlock_obj(dev, event, all); -+ -+ if (put_user(prev_state, (__u32 __user *)argp)) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static int ntsync_event_reset(struct ntsync_obj *event, void __user *argp) -+{ -+ struct ntsync_device *dev = event->dev; -+ __u32 prev_state; -+ bool all; -+ -+ if (event->type != NTSYNC_TYPE_EVENT) -+ return -EINVAL; -+ -+ all = ntsync_lock_obj(dev, event); -+ -+ prev_state = event->u.event.signaled; -+ event->u.event.signaled = false; -+ -+ ntsync_unlock_obj(dev, event, all); -+ -+ if (put_user(prev_state, (__u32 __user *)argp)) -+ return -EFAULT; -+ -+ return 0; -+} -+ -+static int ntsync_sem_read(struct ntsync_obj *sem, void __user *argp) -+{ -+ struct ntsync_sem_args __user *user_args = argp; -+ struct ntsync_device *dev = sem->dev; -+ struct ntsync_sem_args args; -+ bool all; -+ -+ if (sem->type != NTSYNC_TYPE_SEM) -+ return -EINVAL; -+ -+ args.sem = 0; -+ -+ all = ntsync_lock_obj(dev, sem); -+ -+ args.count = sem->u.sem.count; -+ args.max = sem->u.sem.max; -+ -+ ntsync_unlock_obj(dev, sem, all); -+ -+ if (copy_to_user(user_args, &args, sizeof(args))) -+ return -EFAULT; -+ return 0; -+} -+ -+static int ntsync_mutex_read(struct ntsync_obj *mutex, void __user *argp) -+{ -+ struct ntsync_mutex_args __user *user_args = argp; -+ struct ntsync_device *dev = mutex->dev; -+ struct ntsync_mutex_args args; -+ bool all; -+ int ret; -+ -+ if (mutex->type != NTSYNC_TYPE_MUTEX) -+ return -EINVAL; -+ -+ args.mutex = 0; -+ -+ all = ntsync_lock_obj(dev, mutex); -+ -+ args.count = mutex->u.mutex.count; -+ args.owner = mutex->u.mutex.owner; -+ ret = mutex->u.mutex.ownerdead ? -EOWNERDEAD : 0; -+ -+ ntsync_unlock_obj(dev, mutex, all); -+ -+ if (copy_to_user(user_args, &args, sizeof(args))) -+ return -EFAULT; -+ return ret; -+} -+ -+static int ntsync_event_read(struct ntsync_obj *event, void __user *argp) -+{ -+ struct ntsync_event_args __user *user_args = argp; -+ struct ntsync_device *dev = event->dev; -+ struct ntsync_event_args args; -+ bool all; -+ -+ if (event->type != NTSYNC_TYPE_EVENT) -+ return -EINVAL; -+ -+ args.event = 0; -+ -+ all = ntsync_lock_obj(dev, event); -+ -+ args.manual = event->u.event.manual; -+ args.signaled = event->u.event.signaled; -+ -+ ntsync_unlock_obj(dev, event, all); -+ -+ if (copy_to_user(user_args, &args, sizeof(args))) -+ return -EFAULT; -+ return 0; -+} -+ - static int ntsync_obj_release(struct inode *inode, struct file *file) - { - struct ntsync_obj *obj = file->private_data; -@@ -116,6 +676,22 @@ static long ntsync_obj_ioctl(struct file *file, unsigned int cmd, - switch (cmd) { - case NTSYNC_IOC_SEM_POST: - return ntsync_sem_post(obj, argp); -+ case NTSYNC_IOC_SEM_READ: -+ return ntsync_sem_read(obj, argp); -+ case NTSYNC_IOC_MUTEX_UNLOCK: -+ return ntsync_mutex_unlock(obj, argp); -+ case NTSYNC_IOC_MUTEX_KILL: -+ return ntsync_mutex_kill(obj, argp); -+ case NTSYNC_IOC_MUTEX_READ: -+ return ntsync_mutex_read(obj, argp); -+ case NTSYNC_IOC_EVENT_SET: -+ return ntsync_event_set(obj, argp, false); -+ case NTSYNC_IOC_EVENT_RESET: -+ return ntsync_event_reset(obj, argp); -+ case NTSYNC_IOC_EVENT_PULSE: -+ return ntsync_event_set(obj, argp, true); -+ case NTSYNC_IOC_EVENT_READ: -+ return ntsync_event_read(obj, argp); - default: - return -ENOIOCTLCMD; - } -@@ -141,6 +717,9 @@ static struct ntsync_obj *ntsync_alloc_obj(struct ntsync_device *dev, - obj->dev = dev; - get_file(dev->file); - spin_lock_init(&obj->lock); -+ INIT_LIST_HEAD(&obj->any_waiters); -+ INIT_LIST_HEAD(&obj->all_waiters); -+ atomic_set(&obj->all_hint, 0); - - return obj; - } -@@ -191,6 +770,400 @@ static int ntsync_create_sem(struct ntsync_device *dev, void __user *argp) - return put_user(fd, &user_args->sem); - } - -+static int ntsync_create_mutex(struct ntsync_device *dev, void __user *argp) -+{ -+ struct ntsync_mutex_args __user *user_args = argp; -+ struct ntsync_mutex_args args; -+ struct ntsync_obj *mutex; -+ int fd; -+ -+ if (copy_from_user(&args, argp, sizeof(args))) -+ return -EFAULT; -+ -+ if (!args.owner != !args.count) -+ return -EINVAL; -+ -+ mutex = ntsync_alloc_obj(dev, NTSYNC_TYPE_MUTEX); -+ if (!mutex) -+ return -ENOMEM; -+ mutex->u.mutex.count = args.count; -+ mutex->u.mutex.owner = args.owner; -+ fd = ntsync_obj_get_fd(mutex); -+ if (fd < 0) { -+ kfree(mutex); -+ return fd; -+ } -+ -+ return put_user(fd, &user_args->mutex); -+} -+ -+static int ntsync_create_event(struct ntsync_device *dev, void __user *argp) -+{ -+ struct ntsync_event_args __user *user_args = argp; -+ struct ntsync_event_args args; -+ struct ntsync_obj *event; -+ int fd; -+ -+ if (copy_from_user(&args, argp, sizeof(args))) -+ return -EFAULT; -+ -+ event = ntsync_alloc_obj(dev, NTSYNC_TYPE_EVENT); -+ if (!event) -+ return -ENOMEM; -+ event->u.event.manual = args.manual; -+ event->u.event.signaled = args.signaled; -+ fd = ntsync_obj_get_fd(event); -+ if (fd < 0) { -+ kfree(event); -+ return fd; -+ } -+ -+ return put_user(fd, &user_args->event); -+} -+ -+static struct ntsync_obj *get_obj(struct ntsync_device *dev, int fd) -+{ -+ struct file *file = fget(fd); -+ struct ntsync_obj *obj; -+ -+ if (!file) -+ return NULL; -+ -+ if (file->f_op != &ntsync_obj_fops) { -+ fput(file); -+ return NULL; -+ } -+ -+ obj = file->private_data; -+ if (obj->dev != dev) { -+ fput(file); -+ return NULL; -+ } -+ -+ return obj; -+} -+ -+static void put_obj(struct ntsync_obj *obj) -+{ -+ fput(obj->file); -+} -+ -+static int ntsync_schedule(const struct ntsync_q *q, const struct ntsync_wait_args *args) -+{ -+ ktime_t timeout = ns_to_ktime(args->timeout); -+ clockid_t clock = CLOCK_MONOTONIC; -+ ktime_t *timeout_ptr; -+ int ret = 0; -+ -+ timeout_ptr = (args->timeout == U64_MAX ? NULL : &timeout); -+ -+ if (args->flags & NTSYNC_WAIT_REALTIME) -+ clock = CLOCK_REALTIME; -+ -+ do { -+ if (signal_pending(current)) { -+ ret = -ERESTARTSYS; -+ break; -+ } -+ -+ set_current_state(TASK_INTERRUPTIBLE); -+ if (atomic_read(&q->signaled) != -1) { -+ ret = 0; -+ break; -+ } -+ ret = schedule_hrtimeout_range_clock(timeout_ptr, 0, HRTIMER_MODE_ABS, clock); -+ } while (ret < 0); -+ __set_current_state(TASK_RUNNING); -+ -+ return ret; -+} -+ -+/* -+ * Allocate and initialize the ntsync_q structure, but do not queue us yet. -+ */ -+static int setup_wait(struct ntsync_device *dev, -+ const struct ntsync_wait_args *args, bool all, -+ struct ntsync_q **ret_q) -+{ -+ int fds[NTSYNC_MAX_WAIT_COUNT + 1]; -+ const __u32 count = args->count; -+ struct ntsync_q *q; -+ __u32 total_count; -+ __u32 i, j; -+ -+ if (args->pad || (args->flags & ~NTSYNC_WAIT_REALTIME)) -+ return -EINVAL; -+ -+ if (args->count > NTSYNC_MAX_WAIT_COUNT) -+ return -EINVAL; -+ -+ total_count = count; -+ if (args->alert) -+ total_count++; -+ -+ if (copy_from_user(fds, u64_to_user_ptr(args->objs), -+ array_size(count, sizeof(*fds)))) -+ return -EFAULT; -+ if (args->alert) -+ fds[count] = args->alert; -+ -+ q = kmalloc(struct_size(q, entries, total_count), GFP_KERNEL); -+ if (!q) -+ return -ENOMEM; -+ q->task = current; -+ q->owner = args->owner; -+ atomic_set(&q->signaled, -1); -+ q->all = all; -+ q->ownerdead = false; -+ q->count = count; -+ -+ for (i = 0; i < total_count; i++) { -+ struct ntsync_q_entry *entry = &q->entries[i]; -+ struct ntsync_obj *obj = get_obj(dev, fds[i]); -+ -+ if (!obj) -+ goto err; -+ -+ if (all) { -+ /* Check that the objects are all distinct. */ -+ for (j = 0; j < i; j++) { -+ if (obj == q->entries[j].obj) { -+ put_obj(obj); -+ goto err; -+ } -+ } -+ } -+ -+ entry->obj = obj; -+ entry->q = q; -+ entry->index = i; -+ } -+ -+ *ret_q = q; -+ return 0; -+ -+err: -+ for (j = 0; j < i; j++) -+ put_obj(q->entries[j].obj); -+ kfree(q); -+ return -EINVAL; -+} -+ -+static void try_wake_any_obj(struct ntsync_obj *obj) -+{ -+ switch (obj->type) { -+ case NTSYNC_TYPE_SEM: -+ try_wake_any_sem(obj); -+ break; -+ case NTSYNC_TYPE_MUTEX: -+ try_wake_any_mutex(obj); -+ break; -+ case NTSYNC_TYPE_EVENT: -+ try_wake_any_event(obj); -+ break; -+ } -+} -+ -+static int ntsync_wait_any(struct ntsync_device *dev, void __user *argp) -+{ -+ struct ntsync_wait_args args; -+ __u32 i, total_count; -+ struct ntsync_q *q; -+ int signaled; -+ bool all; -+ int ret; -+ -+ if (copy_from_user(&args, argp, sizeof(args))) -+ return -EFAULT; -+ -+ ret = setup_wait(dev, &args, false, &q); -+ if (ret < 0) -+ return ret; -+ -+ total_count = args.count; -+ if (args.alert) -+ total_count++; -+ -+ /* queue ourselves */ -+ -+ for (i = 0; i < total_count; i++) { -+ struct ntsync_q_entry *entry = &q->entries[i]; -+ struct ntsync_obj *obj = entry->obj; -+ -+ all = ntsync_lock_obj(dev, obj); -+ list_add_tail(&entry->node, &obj->any_waiters); -+ ntsync_unlock_obj(dev, obj, all); -+ } -+ -+ /* -+ * Check if we are already signaled. -+ * -+ * Note that the API requires that normal objects are checked before -+ * the alert event. Hence we queue the alert event last, and check -+ * objects in order. -+ */ -+ -+ for (i = 0; i < total_count; i++) { -+ struct ntsync_obj *obj = q->entries[i].obj; -+ -+ if (atomic_read(&q->signaled) != -1) -+ break; -+ -+ all = ntsync_lock_obj(dev, obj); -+ try_wake_any_obj(obj); -+ ntsync_unlock_obj(dev, obj, all); -+ } -+ -+ /* sleep */ -+ -+ ret = ntsync_schedule(q, &args); -+ -+ /* and finally, unqueue */ -+ -+ for (i = 0; i < total_count; i++) { -+ struct ntsync_q_entry *entry = &q->entries[i]; -+ struct ntsync_obj *obj = entry->obj; -+ -+ all = ntsync_lock_obj(dev, obj); -+ list_del(&entry->node); -+ ntsync_unlock_obj(dev, obj, all); -+ -+ put_obj(obj); -+ } -+ -+ signaled = atomic_read(&q->signaled); -+ if (signaled != -1) { -+ struct ntsync_wait_args __user *user_args = argp; -+ -+ /* even if we caught a signal, we need to communicate success */ -+ ret = q->ownerdead ? -EOWNERDEAD : 0; -+ -+ if (put_user(signaled, &user_args->index)) -+ ret = -EFAULT; -+ } else if (!ret) { -+ ret = -ETIMEDOUT; -+ } -+ -+ kfree(q); -+ return ret; -+} -+ -+static int ntsync_wait_all(struct ntsync_device *dev, void __user *argp) -+{ -+ struct ntsync_wait_args args; -+ struct ntsync_q *q; -+ int signaled; -+ __u32 i; -+ int ret; -+ -+ if (copy_from_user(&args, argp, sizeof(args))) -+ return -EFAULT; -+ -+ ret = setup_wait(dev, &args, true, &q); -+ if (ret < 0) -+ return ret; -+ -+ /* queue ourselves */ -+ -+ mutex_lock(&dev->wait_all_lock); -+ -+ for (i = 0; i < args.count; i++) { -+ struct ntsync_q_entry *entry = &q->entries[i]; -+ struct ntsync_obj *obj = entry->obj; -+ -+ atomic_inc(&obj->all_hint); -+ -+ /* -+ * obj->all_waiters is protected by dev->wait_all_lock rather -+ * than obj->lock, so there is no need to acquire obj->lock -+ * here. -+ */ -+ list_add_tail(&entry->node, &obj->all_waiters); -+ } -+ if (args.alert) { -+ struct ntsync_q_entry *entry = &q->entries[args.count]; -+ struct ntsync_obj *obj = entry->obj; -+ -+ dev_lock_obj(dev, obj); -+ list_add_tail(&entry->node, &obj->any_waiters); -+ dev_unlock_obj(dev, obj); -+ } -+ -+ /* check if we are already signaled */ -+ -+ try_wake_all(dev, q, NULL); -+ -+ mutex_unlock(&dev->wait_all_lock); -+ -+ /* -+ * Check if the alert event is signaled, making sure to do so only -+ * after checking if the other objects are signaled. -+ */ -+ -+ if (args.alert) { -+ struct ntsync_obj *obj = q->entries[args.count].obj; -+ -+ if (atomic_read(&q->signaled) == -1) { -+ bool all = ntsync_lock_obj(dev, obj); -+ try_wake_any_obj(obj); -+ ntsync_unlock_obj(dev, obj, all); -+ } -+ } -+ -+ /* sleep */ -+ -+ ret = ntsync_schedule(q, &args); -+ -+ /* and finally, unqueue */ -+ -+ mutex_lock(&dev->wait_all_lock); -+ -+ for (i = 0; i < args.count; i++) { -+ struct ntsync_q_entry *entry = &q->entries[i]; -+ struct ntsync_obj *obj = entry->obj; -+ -+ /* -+ * obj->all_waiters is protected by dev->wait_all_lock rather -+ * than obj->lock, so there is no need to acquire it here. -+ */ -+ list_del(&entry->node); -+ -+ atomic_dec(&obj->all_hint); -+ -+ put_obj(obj); -+ } -+ -+ mutex_unlock(&dev->wait_all_lock); -+ -+ if (args.alert) { -+ struct ntsync_q_entry *entry = &q->entries[args.count]; -+ struct ntsync_obj *obj = entry->obj; -+ bool all; -+ -+ all = ntsync_lock_obj(dev, obj); -+ list_del(&entry->node); -+ ntsync_unlock_obj(dev, obj, all); -+ -+ put_obj(obj); -+ } -+ -+ signaled = atomic_read(&q->signaled); -+ if (signaled != -1) { -+ struct ntsync_wait_args __user *user_args = argp; -+ -+ /* even if we caught a signal, we need to communicate success */ -+ ret = q->ownerdead ? -EOWNERDEAD : 0; -+ -+ if (put_user(signaled, &user_args->index)) -+ ret = -EFAULT; -+ } else if (!ret) { -+ ret = -ETIMEDOUT; -+ } -+ -+ kfree(q); -+ return ret; -+} -+ - static int ntsync_char_open(struct inode *inode, struct file *file) - { - struct ntsync_device *dev; -@@ -199,6 +1172,8 @@ static int ntsync_char_open(struct inode *inode, struct file *file) - if (!dev) - return -ENOMEM; - -+ mutex_init(&dev->wait_all_lock); -+ - file->private_data = dev; - dev->file = file; - return nonseekable_open(inode, file); -@@ -220,8 +1195,16 @@ static long ntsync_char_ioctl(struct file *file, unsigned int cmd, - void __user *argp = (void __user *)parm; - - switch (cmd) { -+ case NTSYNC_IOC_CREATE_EVENT: -+ return ntsync_create_event(dev, argp); -+ case NTSYNC_IOC_CREATE_MUTEX: -+ return ntsync_create_mutex(dev, argp); - case NTSYNC_IOC_CREATE_SEM: - return ntsync_create_sem(dev, argp); -+ case NTSYNC_IOC_WAIT_ALL: -+ return ntsync_wait_all(dev, argp); -+ case NTSYNC_IOC_WAIT_ANY: -+ return ntsync_wait_any(dev, argp); - default: - return -ENOIOCTLCMD; - } -diff --git a/include/uapi/linux/ntsync.h b/include/uapi/linux/ntsync.h -index dcfa38fdc93c..4a8095a3fc34 100644 ---- a/include/uapi/linux/ntsync.h -+++ b/include/uapi/linux/ntsync.h -@@ -16,8 +16,47 @@ struct ntsync_sem_args { - __u32 max; - }; - -+struct ntsync_mutex_args { -+ __u32 mutex; -+ __u32 owner; -+ __u32 count; -+}; -+ -+struct ntsync_event_args { -+ __u32 event; -+ __u32 manual; -+ __u32 signaled; -+}; -+ -+#define NTSYNC_WAIT_REALTIME 0x1 -+ -+struct ntsync_wait_args { -+ __u64 timeout; -+ __u64 objs; -+ __u32 count; -+ __u32 index; -+ __u32 flags; -+ __u32 owner; -+ __u32 alert; -+ __u32 pad; -+}; -+ -+#define NTSYNC_MAX_WAIT_COUNT 64 -+ - #define NTSYNC_IOC_CREATE_SEM _IOWR('N', 0x80, struct ntsync_sem_args) -+#define NTSYNC_IOC_WAIT_ANY _IOWR('N', 0x82, struct ntsync_wait_args) -+#define NTSYNC_IOC_WAIT_ALL _IOWR('N', 0x83, struct ntsync_wait_args) -+#define NTSYNC_IOC_CREATE_MUTEX _IOWR('N', 0x84, struct ntsync_sem_args) -+#define NTSYNC_IOC_CREATE_EVENT _IOWR('N', 0x87, struct ntsync_event_args) - - #define NTSYNC_IOC_SEM_POST _IOWR('N', 0x81, __u32) -+#define NTSYNC_IOC_MUTEX_UNLOCK _IOWR('N', 0x85, struct ntsync_mutex_args) -+#define NTSYNC_IOC_MUTEX_KILL _IOW ('N', 0x86, __u32) -+#define NTSYNC_IOC_EVENT_SET _IOR ('N', 0x88, __u32) -+#define NTSYNC_IOC_EVENT_RESET _IOR ('N', 0x89, __u32) -+#define NTSYNC_IOC_EVENT_PULSE _IOR ('N', 0x8a, __u32) -+#define NTSYNC_IOC_SEM_READ _IOR ('N', 0x8b, struct ntsync_sem_args) -+#define NTSYNC_IOC_MUTEX_READ _IOR ('N', 0x8c, struct ntsync_mutex_args) -+#define NTSYNC_IOC_EVENT_READ _IOR ('N', 0x8d, struct ntsync_event_args) - - #endif -diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile -index 9039f3709aff..d5aeaa8fe3ca 100644 ---- a/tools/testing/selftests/Makefile -+++ b/tools/testing/selftests/Makefile -@@ -16,6 +16,7 @@ TARGETS += damon - TARGETS += devices - TARGETS += dmabuf-heaps - TARGETS += drivers/dma-buf -+TARGETS += drivers/ntsync - TARGETS += drivers/s390x/uvdevice - TARGETS += drivers/net - TARGETS += drivers/net/bonding -diff --git a/tools/testing/selftests/drivers/ntsync/.gitignore b/tools/testing/selftests/drivers/ntsync/.gitignore -new file mode 100644 -index 000000000000..848573a3d3ea ---- /dev/null -+++ b/tools/testing/selftests/drivers/ntsync/.gitignore -@@ -0,0 +1 @@ -+ntsync -diff --git a/tools/testing/selftests/drivers/ntsync/Makefile b/tools/testing/selftests/drivers/ntsync/Makefile -new file mode 100644 -index 000000000000..dbf2b055c0b2 ---- /dev/null -+++ b/tools/testing/selftests/drivers/ntsync/Makefile -@@ -0,0 +1,7 @@ -+# SPDX-LICENSE-IDENTIFIER: GPL-2.0-only -+TEST_GEN_PROGS := ntsync -+ -+CFLAGS += $(KHDR_INCLUDES) -+LDLIBS += -lpthread -+ -+include ../../lib.mk -diff --git a/tools/testing/selftests/drivers/ntsync/config b/tools/testing/selftests/drivers/ntsync/config -new file mode 100644 -index 000000000000..60539c826d06 ---- /dev/null -+++ b/tools/testing/selftests/drivers/ntsync/config -@@ -0,0 +1 @@ -+CONFIG_WINESYNC=y -diff --git a/tools/testing/selftests/drivers/ntsync/ntsync.c b/tools/testing/selftests/drivers/ntsync/ntsync.c -new file mode 100644 -index 000000000000..5fa2c9a0768c ---- /dev/null -+++ b/tools/testing/selftests/drivers/ntsync/ntsync.c -@@ -0,0 +1,1407 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later -+/* -+ * Various unit tests for the "ntsync" synchronization primitive driver. -+ * -+ * Copyright (C) 2021-2022 Elizabeth Figura <zfigura@codeweavers.com> -+ */ -+ -+#define _GNU_SOURCE -+#include <sys/ioctl.h> -+#include <sys/stat.h> -+#include <fcntl.h> -+#include <time.h> -+#include <pthread.h> -+#include <linux/ntsync.h> -+#include "../../kselftest_harness.h" -+ -+static int read_sem_state(int sem, __u32 *count, __u32 *max) -+{ -+ struct ntsync_sem_args args; -+ int ret; -+ -+ memset(&args, 0xcc, sizeof(args)); -+ ret = ioctl(sem, NTSYNC_IOC_SEM_READ, &args); -+ *count = args.count; -+ *max = args.max; -+ return ret; -+} -+ -+#define check_sem_state(sem, count, max) \ -+ ({ \ -+ __u32 __count, __max; \ -+ int ret = read_sem_state((sem), &__count, &__max); \ -+ EXPECT_EQ(0, ret); \ -+ EXPECT_EQ((count), __count); \ -+ EXPECT_EQ((max), __max); \ -+ }) -+ -+static int post_sem(int sem, __u32 *count) -+{ -+ return ioctl(sem, NTSYNC_IOC_SEM_POST, count); -+} -+ -+static int read_mutex_state(int mutex, __u32 *count, __u32 *owner) -+{ -+ struct ntsync_mutex_args args; -+ int ret; -+ -+ memset(&args, 0xcc, sizeof(args)); -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_READ, &args); -+ *count = args.count; -+ *owner = args.owner; -+ return ret; -+} -+ -+#define check_mutex_state(mutex, count, owner) \ -+ ({ \ -+ __u32 __count, __owner; \ -+ int ret = read_mutex_state((mutex), &__count, &__owner); \ -+ EXPECT_EQ(0, ret); \ -+ EXPECT_EQ((count), __count); \ -+ EXPECT_EQ((owner), __owner); \ -+ }) -+ -+static int unlock_mutex(int mutex, __u32 owner, __u32 *count) -+{ -+ struct ntsync_mutex_args args; -+ int ret; -+ -+ args.owner = owner; -+ args.count = 0xdeadbeef; -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_UNLOCK, &args); -+ *count = args.count; -+ return ret; -+} -+ -+static int read_event_state(int event, __u32 *signaled, __u32 *manual) -+{ -+ struct ntsync_event_args args; -+ int ret; -+ -+ memset(&args, 0xcc, sizeof(args)); -+ ret = ioctl(event, NTSYNC_IOC_EVENT_READ, &args); -+ *signaled = args.signaled; -+ *manual = args.manual; -+ return ret; -+} -+ -+#define check_event_state(event, signaled, manual) \ -+ ({ \ -+ __u32 __signaled, __manual; \ -+ int ret = read_event_state((event), &__signaled, &__manual); \ -+ EXPECT_EQ(0, ret); \ -+ EXPECT_EQ((signaled), __signaled); \ -+ EXPECT_EQ((manual), __manual); \ -+ }) -+ -+static int wait_objs(int fd, unsigned long request, __u32 count, -+ const int *objs, __u32 owner, int alert, __u32 *index) -+{ -+ struct ntsync_wait_args args = {0}; -+ struct timespec timeout; -+ int ret; -+ -+ clock_gettime(CLOCK_MONOTONIC, &timeout); -+ -+ args.timeout = timeout.tv_sec * 1000000000 + timeout.tv_nsec; -+ args.count = count; -+ args.objs = (uintptr_t)objs; -+ args.owner = owner; -+ args.index = 0xdeadbeef; -+ args.alert = alert; -+ ret = ioctl(fd, request, &args); -+ *index = args.index; -+ return ret; -+} -+ -+static int wait_any(int fd, __u32 count, const int *objs, __u32 owner, __u32 *index) -+{ -+ return wait_objs(fd, NTSYNC_IOC_WAIT_ANY, count, objs, owner, 0, index); -+} -+ -+static int wait_all(int fd, __u32 count, const int *objs, __u32 owner, __u32 *index) -+{ -+ return wait_objs(fd, NTSYNC_IOC_WAIT_ALL, count, objs, owner, 0, index); -+} -+ -+static int wait_any_alert(int fd, __u32 count, const int *objs, -+ __u32 owner, int alert, __u32 *index) -+{ -+ return wait_objs(fd, NTSYNC_IOC_WAIT_ANY, -+ count, objs, owner, alert, index); -+} -+ -+static int wait_all_alert(int fd, __u32 count, const int *objs, -+ __u32 owner, int alert, __u32 *index) -+{ -+ return wait_objs(fd, NTSYNC_IOC_WAIT_ALL, -+ count, objs, owner, alert, index); -+} -+ -+TEST(semaphore_state) -+{ -+ struct ntsync_sem_args sem_args; -+ struct timespec timeout; -+ __u32 count, index; -+ int fd, ret, sem; -+ -+ clock_gettime(CLOCK_MONOTONIC, &timeout); -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 3; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ sem_args.count = 2; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ sem = sem_args.sem; -+ check_sem_state(sem, 2, 2); -+ -+ count = 0; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, count); -+ check_sem_state(sem, 2, 2); -+ -+ count = 1; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOVERFLOW, errno); -+ check_sem_state(sem, 2, 2); -+ -+ ret = wait_any(fd, 1, &sem, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem, 1, 2); -+ -+ ret = wait_any(fd, 1, &sem, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem, 0, 2); -+ -+ ret = wait_any(fd, 1, &sem, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ count = 3; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOVERFLOW, errno); -+ check_sem_state(sem, 0, 2); -+ -+ count = 2; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ check_sem_state(sem, 2, 2); -+ -+ ret = wait_any(fd, 1, &sem, 123, &index); -+ EXPECT_EQ(0, ret); -+ ret = wait_any(fd, 1, &sem, 123, &index); -+ EXPECT_EQ(0, ret); -+ -+ count = 1; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ check_sem_state(sem, 1, 2); -+ -+ count = ~0u; -+ ret = post_sem(sem, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOVERFLOW, errno); -+ check_sem_state(sem, 1, 2); -+ -+ close(sem); -+ -+ close(fd); -+} -+ -+TEST(mutex_state) -+{ -+ struct ntsync_mutex_args mutex_args; -+ __u32 owner, count, index; -+ struct timespec timeout; -+ int fd, ret, mutex; -+ -+ clock_gettime(CLOCK_MONOTONIC, &timeout); -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ mutex_args.owner = 123; -+ mutex_args.count = 0; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ mutex_args.owner = 0; -+ mutex_args.count = 2; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ mutex_args.owner = 123; -+ mutex_args.count = 2; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ mutex = mutex_args.mutex; -+ check_mutex_state(mutex, 2, 123); -+ -+ ret = unlock_mutex(mutex, 0, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ ret = unlock_mutex(mutex, 456, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EPERM, errno); -+ check_mutex_state(mutex, 2, 123); -+ -+ ret = unlock_mutex(mutex, 123, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, count); -+ check_mutex_state(mutex, 1, 123); -+ -+ ret = unlock_mutex(mutex, 123, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, count); -+ check_mutex_state(mutex, 0, 0); -+ -+ ret = unlock_mutex(mutex, 123, &count); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EPERM, errno); -+ -+ ret = wait_any(fd, 1, &mutex, 456, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_mutex_state(mutex, 1, 456); -+ -+ ret = wait_any(fd, 1, &mutex, 456, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_mutex_state(mutex, 2, 456); -+ -+ ret = unlock_mutex(mutex, 456, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, count); -+ check_mutex_state(mutex, 1, 456); -+ -+ ret = wait_any(fd, 1, &mutex, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ owner = 0; -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ owner = 123; -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EPERM, errno); -+ check_mutex_state(mutex, 1, 456); -+ -+ owner = 456; -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(0, ret); -+ -+ memset(&mutex_args, 0xcc, sizeof(mutex_args)); -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_READ, &mutex_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(0, mutex_args.count); -+ EXPECT_EQ(0, mutex_args.owner); -+ -+ memset(&mutex_args, 0xcc, sizeof(mutex_args)); -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_READ, &mutex_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(0, mutex_args.count); -+ EXPECT_EQ(0, mutex_args.owner); -+ -+ ret = wait_any(fd, 1, &mutex, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(0, index); -+ check_mutex_state(mutex, 1, 123); -+ -+ owner = 123; -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(0, ret); -+ -+ memset(&mutex_args, 0xcc, sizeof(mutex_args)); -+ ret = ioctl(mutex, NTSYNC_IOC_MUTEX_READ, &mutex_args); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(0, mutex_args.count); -+ EXPECT_EQ(0, mutex_args.owner); -+ -+ ret = wait_any(fd, 1, &mutex, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(0, index); -+ check_mutex_state(mutex, 1, 123); -+ -+ close(mutex); -+ -+ mutex_args.owner = 0; -+ mutex_args.count = 0; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ mutex = mutex_args.mutex; -+ check_mutex_state(mutex, 0, 0); -+ -+ ret = wait_any(fd, 1, &mutex, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_mutex_state(mutex, 1, 123); -+ -+ close(mutex); -+ -+ mutex_args.owner = 123; -+ mutex_args.count = ~0u; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ mutex = mutex_args.mutex; -+ check_mutex_state(mutex, ~0u, 123); -+ -+ ret = wait_any(fd, 1, &mutex, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ close(mutex); -+ -+ close(fd); -+} -+ -+TEST(manual_event_state) -+{ -+ struct ntsync_event_args event_args; -+ __u32 index, signaled; -+ int fd, event, ret; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ event_args.manual = 1; -+ event_args.signaled = 0; -+ event_args.event = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, event_args.event); -+ event = event_args.event; -+ check_event_state(event, 0, 1); -+ -+ signaled = 0xdeadbeef; -+ ret = ioctl(event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event, 1, 1); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ check_event_state(event, 1, 1); -+ -+ ret = wait_any(fd, 1, &event, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_event_state(event, 1, 1); -+ -+ signaled = 0xdeadbeef; -+ ret = ioctl(event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ check_event_state(event, 0, 1); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event, 0, 1); -+ -+ ret = wait_any(fd, 1, &event, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ check_event_state(event, 0, 1); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event, 0, 1); -+ -+ close(event); -+ -+ close(fd); -+} -+ -+TEST(auto_event_state) -+{ -+ struct ntsync_event_args event_args; -+ __u32 index, signaled; -+ int fd, event, ret; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ event_args.manual = 0; -+ event_args.signaled = 1; -+ event_args.event = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, event_args.event); -+ event = event_args.event; -+ -+ check_event_state(event, 1, 0); -+ -+ signaled = 0xdeadbeef; -+ ret = ioctl(event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ check_event_state(event, 1, 0); -+ -+ ret = wait_any(fd, 1, &event, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_event_state(event, 0, 0); -+ -+ signaled = 0xdeadbeef; -+ ret = ioctl(event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event, 0, 0); -+ -+ ret = wait_any(fd, 1, &event, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ check_event_state(event, 0, 0); -+ -+ ret = ioctl(event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event, 0, 0); -+ -+ close(event); -+ -+ close(fd); -+} -+ -+TEST(test_wait_any) -+{ -+ int objs[NTSYNC_MAX_WAIT_COUNT + 1], fd, ret; -+ struct ntsync_mutex_args mutex_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ __u32 owner, index, count, i; -+ struct timespec timeout; -+ -+ clock_gettime(CLOCK_MONOTONIC, &timeout); -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 2; -+ sem_args.max = 3; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ -+ mutex_args.owner = 0; -+ mutex_args.count = 0; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ -+ objs[0] = sem_args.sem; -+ objs[1] = mutex_args.mutex; -+ -+ ret = wait_any(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 1, 3); -+ check_mutex_state(mutex_args.mutex, 0, 0); -+ -+ ret = wait_any(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 0, 0); -+ -+ ret = wait_any(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 1, 123); -+ -+ count = 1; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ -+ ret = wait_any(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 1, 123); -+ -+ ret = wait_any(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 2, 123); -+ -+ ret = wait_any(fd, 2, objs, 456, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ owner = 123; -+ ret = ioctl(mutex_args.mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_any(fd, 2, objs, 456, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ EXPECT_EQ(1, index); -+ -+ ret = wait_any(fd, 2, objs, 456, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, index); -+ -+ /* test waiting on the same object twice */ -+ count = 2; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ -+ objs[0] = objs[1] = sem_args.sem; -+ ret = wait_any(fd, 2, objs, 456, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 1, 3); -+ -+ ret = wait_any(fd, 0, NULL, 456, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ for (i = 0; i < NTSYNC_MAX_WAIT_COUNT + 1; ++i) -+ objs[i] = sem_args.sem; -+ -+ ret = wait_any(fd, NTSYNC_MAX_WAIT_COUNT, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = wait_any(fd, NTSYNC_MAX_WAIT_COUNT + 1, objs, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ ret = wait_any(fd, -1, objs, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ close(sem_args.sem); -+ close(mutex_args.mutex); -+ -+ close(fd); -+} -+ -+TEST(test_wait_all) -+{ -+ struct ntsync_event_args event_args = {0}; -+ struct ntsync_mutex_args mutex_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ __u32 owner, index, count; -+ int objs[2], fd, ret; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 2; -+ sem_args.max = 3; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ -+ mutex_args.owner = 0; -+ mutex_args.count = 0; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ -+ event_args.manual = true; -+ event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ objs[0] = sem_args.sem; -+ objs[1] = mutex_args.mutex; -+ -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 1, 3); -+ check_mutex_state(mutex_args.mutex, 1, 123); -+ -+ ret = wait_all(fd, 2, objs, 456, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ check_sem_state(sem_args.sem, 1, 3); -+ check_mutex_state(mutex_args.mutex, 1, 123); -+ -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 2, 123); -+ -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_mutex_state(mutex_args.mutex, 2, 123); -+ -+ count = 3; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 2, 3); -+ check_mutex_state(mutex_args.mutex, 3, 123); -+ -+ owner = 123; -+ ret = ioctl(mutex_args.mutex, NTSYNC_IOC_MUTEX_KILL, &owner); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EOWNERDEAD, errno); -+ check_sem_state(sem_args.sem, 1, 3); -+ check_mutex_state(mutex_args.mutex, 1, 123); -+ -+ objs[0] = sem_args.sem; -+ objs[1] = event_args.event; -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ check_sem_state(sem_args.sem, 0, 3); -+ check_event_state(event_args.event, 1, 1); -+ -+ /* test waiting on the same object twice */ -+ objs[0] = objs[1] = sem_args.sem; -+ ret = wait_all(fd, 2, objs, 123, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(EINVAL, errno); -+ -+ close(sem_args.sem); -+ close(mutex_args.mutex); -+ close(event_args.event); -+ -+ close(fd); -+} -+ -+struct wake_args { -+ int fd; -+ int obj; -+}; -+ -+struct wait_args { -+ int fd; -+ unsigned long request; -+ struct ntsync_wait_args *args; -+ int ret; -+ int err; -+}; -+ -+static void *wait_thread(void *arg) -+{ -+ struct wait_args *args = arg; -+ -+ args->ret = ioctl(args->fd, args->request, args->args); -+ args->err = errno; -+ return NULL; -+} -+ -+static __u64 get_abs_timeout(unsigned int ms) -+{ -+ struct timespec timeout; -+ clock_gettime(CLOCK_MONOTONIC, &timeout); -+ return (timeout.tv_sec * 1000000000) + timeout.tv_nsec + (ms * 1000000); -+} -+ -+static int wait_for_thread(pthread_t thread, unsigned int ms) -+{ -+ struct timespec timeout; -+ -+ clock_gettime(CLOCK_REALTIME, &timeout); -+ timeout.tv_nsec += ms * 1000000; -+ timeout.tv_sec += (timeout.tv_nsec / 1000000000); -+ timeout.tv_nsec %= 1000000000; -+ return pthread_timedjoin_np(thread, NULL, &timeout); -+} -+ -+TEST(wake_any) -+{ -+ struct ntsync_event_args event_args = {0}; -+ struct ntsync_mutex_args mutex_args = {0}; -+ struct ntsync_wait_args wait_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ struct wait_args thread_args; -+ __u32 count, index, signaled; -+ int objs[2], fd, ret; -+ pthread_t thread; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 0; -+ sem_args.max = 3; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ -+ mutex_args.owner = 123; -+ mutex_args.count = 1; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ -+ objs[0] = sem_args.sem; -+ objs[1] = mutex_args.mutex; -+ -+ /* test waking the semaphore */ -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ wait_args.objs = (uintptr_t)objs; -+ wait_args.count = 2; -+ wait_args.owner = 456; -+ wait_args.index = 0xdeadbeef; -+ thread_args.fd = fd; -+ thread_args.args = &wait_args; -+ thread_args.request = NTSYNC_IOC_WAIT_ANY; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ count = 1; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ check_sem_state(sem_args.sem, 0, 3); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(0, wait_args.index); -+ -+ /* test waking the mutex */ -+ -+ /* first grab it again for owner 123 */ -+ ret = wait_any(fd, 1, &mutex_args.mutex, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ wait_args.owner = 456; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = unlock_mutex(mutex_args.mutex, 123, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, count); -+ -+ ret = pthread_tryjoin_np(thread, NULL); -+ EXPECT_EQ(EBUSY, ret); -+ -+ ret = unlock_mutex(mutex_args.mutex, 123, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, mutex_args.count); -+ check_mutex_state(mutex_args.mutex, 1, 456); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(1, wait_args.index); -+ -+ /* test waking events */ -+ -+ event_args.manual = false; -+ event_args.signaled = false; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ objs[1] = event_args.event; -+ wait_args.timeout = get_abs_timeout(1000); -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event_args.event, 0, 0); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(1, wait_args.index); -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event_args.event, 0, 0); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(1, wait_args.index); -+ -+ close(event_args.event); -+ -+ event_args.manual = true; -+ event_args.signaled = false; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ objs[1] = event_args.event; -+ wait_args.timeout = get_abs_timeout(1000); -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event_args.event, 1, 1); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(1, wait_args.index); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_PULSE, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ check_event_state(event_args.event, 0, 1); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(1, wait_args.index); -+ -+ close(event_args.event); -+ -+ /* delete an object while it's being waited on */ -+ -+ wait_args.timeout = get_abs_timeout(200); -+ wait_args.owner = 123; -+ objs[1] = mutex_args.mutex; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ close(sem_args.sem); -+ close(mutex_args.mutex); -+ -+ ret = wait_for_thread(thread, 200); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(-1, thread_args.ret); -+ EXPECT_EQ(ETIMEDOUT, thread_args.err); -+ -+ close(fd); -+} -+ -+TEST(wake_all) -+{ -+ struct ntsync_event_args manual_event_args = {0}; -+ struct ntsync_event_args auto_event_args = {0}; -+ struct ntsync_mutex_args mutex_args = {0}; -+ struct ntsync_wait_args wait_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ struct wait_args thread_args; -+ __u32 count, index, signaled; -+ int objs[4], fd, ret; -+ pthread_t thread; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 0; -+ sem_args.max = 3; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ -+ mutex_args.owner = 123; -+ mutex_args.count = 1; -+ mutex_args.mutex = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, mutex_args.mutex); -+ -+ manual_event_args.manual = true; -+ manual_event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &manual_event_args); -+ EXPECT_EQ(0, ret); -+ -+ auto_event_args.manual = false; -+ auto_event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &auto_event_args); -+ EXPECT_EQ(0, ret); -+ -+ objs[0] = sem_args.sem; -+ objs[1] = mutex_args.mutex; -+ objs[2] = manual_event_args.event; -+ objs[3] = auto_event_args.event; -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ wait_args.objs = (uintptr_t)objs; -+ wait_args.count = 4; -+ wait_args.owner = 456; -+ thread_args.fd = fd; -+ thread_args.args = &wait_args; -+ thread_args.request = NTSYNC_IOC_WAIT_ALL; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ count = 1; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ -+ ret = pthread_tryjoin_np(thread, NULL); -+ EXPECT_EQ(EBUSY, ret); -+ -+ check_sem_state(sem_args.sem, 1, 3); -+ -+ ret = wait_any(fd, 1, &sem_args.sem, 123, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = unlock_mutex(mutex_args.mutex, 123, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, count); -+ -+ ret = pthread_tryjoin_np(thread, NULL); -+ EXPECT_EQ(EBUSY, ret); -+ -+ check_mutex_state(mutex_args.mutex, 0, 0); -+ -+ ret = ioctl(manual_event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ -+ count = 2; -+ ret = post_sem(sem_args.sem, &count); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, count); -+ check_sem_state(sem_args.sem, 2, 3); -+ -+ ret = ioctl(auto_event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, signaled); -+ -+ ret = ioctl(manual_event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ -+ ret = ioctl(auto_event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, signaled); -+ -+ check_sem_state(sem_args.sem, 1, 3); -+ check_mutex_state(mutex_args.mutex, 1, 456); -+ check_event_state(manual_event_args.event, 1, 1); -+ check_event_state(auto_event_args.event, 0, 0); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ -+ /* delete an object while it's being waited on */ -+ -+ wait_args.timeout = get_abs_timeout(200); -+ wait_args.owner = 123; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ close(sem_args.sem); -+ close(mutex_args.mutex); -+ close(manual_event_args.event); -+ close(auto_event_args.event); -+ -+ ret = wait_for_thread(thread, 200); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(-1, thread_args.ret); -+ EXPECT_EQ(ETIMEDOUT, thread_args.err); -+ -+ close(fd); -+} -+ -+TEST(alert_any) -+{ -+ struct ntsync_event_args event_args = {0}; -+ struct ntsync_wait_args wait_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ __u32 index, count, signaled; -+ struct wait_args thread_args; -+ int objs[2], fd, ret; -+ pthread_t thread; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 0; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ objs[0] = sem_args.sem; -+ -+ sem_args.count = 1; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ objs[1] = sem_args.sem; -+ -+ event_args.manual = true; -+ event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_any_alert(fd, 0, NULL, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_any_alert(fd, 0, NULL, 123, event_args.event, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_any_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(1, index); -+ -+ ret = wait_any_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, index); -+ -+ /* test wakeup via alert */ -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ wait_args.objs = (uintptr_t)objs; -+ wait_args.count = 2; -+ wait_args.owner = 123; -+ wait_args.index = 0xdeadbeef; -+ wait_args.alert = event_args.event; -+ thread_args.fd = fd; -+ thread_args.args = &wait_args; -+ thread_args.request = NTSYNC_IOC_WAIT_ANY; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(2, wait_args.index); -+ -+ close(event_args.event); -+ -+ /* test with an auto-reset event */ -+ -+ event_args.manual = false; -+ event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ count = 1; -+ ret = post_sem(objs[0], &count); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_any_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = wait_any_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, index); -+ -+ ret = wait_any_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ close(event_args.event); -+ -+ close(objs[0]); -+ close(objs[1]); -+ -+ close(fd); -+} -+ -+TEST(alert_all) -+{ -+ struct ntsync_event_args event_args = {0}; -+ struct ntsync_wait_args wait_args = {0}; -+ struct ntsync_sem_args sem_args = {0}; -+ struct wait_args thread_args; -+ __u32 index, count, signaled; -+ int objs[2], fd, ret; -+ pthread_t thread; -+ -+ fd = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, fd); -+ -+ sem_args.count = 2; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ objs[0] = sem_args.sem; -+ -+ sem_args.count = 1; -+ sem_args.max = 2; -+ sem_args.sem = 0xdeadbeef; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_SEM, &sem_args); -+ EXPECT_EQ(0, ret); -+ EXPECT_NE(0xdeadbeef, sem_args.sem); -+ objs[1] = sem_args.sem; -+ -+ event_args.manual = true; -+ event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_all_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = wait_all_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, index); -+ -+ /* test wakeup via alert */ -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_RESET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ wait_args.timeout = get_abs_timeout(1000); -+ wait_args.objs = (uintptr_t)objs; -+ wait_args.count = 2; -+ wait_args.owner = 123; -+ wait_args.index = 0xdeadbeef; -+ wait_args.alert = event_args.event; -+ thread_args.fd = fd; -+ thread_args.args = &wait_args; -+ thread_args.request = NTSYNC_IOC_WAIT_ALL; -+ ret = pthread_create(&thread, NULL, wait_thread, &thread_args); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(ETIMEDOUT, ret); -+ -+ ret = ioctl(event_args.event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_for_thread(thread, 100); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, thread_args.ret); -+ EXPECT_EQ(2, wait_args.index); -+ -+ close(event_args.event); -+ -+ /* test with an auto-reset event */ -+ -+ event_args.manual = false; -+ event_args.signaled = true; -+ ret = ioctl(fd, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ -+ count = 2; -+ ret = post_sem(objs[1], &count); -+ EXPECT_EQ(0, ret); -+ -+ ret = wait_all_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(0, index); -+ -+ ret = wait_all_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(0, ret); -+ EXPECT_EQ(2, index); -+ -+ ret = wait_all_alert(fd, 2, objs, 123, event_args.event, &index); -+ EXPECT_EQ(-1, ret); -+ EXPECT_EQ(ETIMEDOUT, errno); -+ -+ close(event_args.event); -+ -+ close(objs[0]); -+ close(objs[1]); -+ -+ close(fd); -+} -+ -+#define STRESS_LOOPS 10000 -+#define STRESS_THREADS 4 -+ -+static unsigned int stress_counter; -+static int stress_device, stress_start_event, stress_mutex; -+ -+static void *stress_thread(void *arg) -+{ -+ struct ntsync_wait_args wait_args = {0}; -+ __u32 index, count, i; -+ int ret; -+ -+ wait_args.timeout = UINT64_MAX; -+ wait_args.count = 1; -+ wait_args.objs = (uintptr_t)&stress_start_event; -+ wait_args.owner = gettid(); -+ wait_args.index = 0xdeadbeef; -+ -+ ioctl(stress_device, NTSYNC_IOC_WAIT_ANY, &wait_args); -+ -+ wait_args.objs = (uintptr_t)&stress_mutex; -+ -+ for (i = 0; i < STRESS_LOOPS; ++i) { -+ ioctl(stress_device, NTSYNC_IOC_WAIT_ANY, &wait_args); -+ -+ ++stress_counter; -+ -+ unlock_mutex(stress_mutex, wait_args.owner, &count); -+ } -+ -+ return NULL; -+} -+ -+TEST(stress_wait) -+{ -+ struct ntsync_event_args event_args; -+ struct ntsync_mutex_args mutex_args; -+ pthread_t threads[STRESS_THREADS]; -+ __u32 signaled, i; -+ int ret; -+ -+ stress_device = open("/dev/ntsync", O_CLOEXEC | O_RDONLY); -+ ASSERT_LE(0, stress_device); -+ -+ mutex_args.owner = 0; -+ mutex_args.count = 0; -+ ret = ioctl(stress_device, NTSYNC_IOC_CREATE_MUTEX, &mutex_args); -+ EXPECT_EQ(0, ret); -+ stress_mutex = mutex_args.mutex; -+ -+ event_args.manual = 1; -+ event_args.signaled = 0; -+ ret = ioctl(stress_device, NTSYNC_IOC_CREATE_EVENT, &event_args); -+ EXPECT_EQ(0, ret); -+ stress_start_event = event_args.event; -+ -+ for (i = 0; i < STRESS_THREADS; ++i) -+ pthread_create(&threads[i], NULL, stress_thread, NULL); -+ -+ ret = ioctl(stress_start_event, NTSYNC_IOC_EVENT_SET, &signaled); -+ EXPECT_EQ(0, ret); -+ -+ for (i = 0; i < STRESS_THREADS; ++i) { -+ ret = pthread_join(threads[i], NULL); -+ EXPECT_EQ(0, ret); -+ } -+ -+ EXPECT_EQ(STRESS_LOOPS * STRESS_THREADS, stress_counter); -+ -+ close(stress_start_event); -+ close(stress_mutex); -+ close(stress_device); -+} -+ -+TEST_HARNESS_MAIN --- -2.46.0.rc1 - diff --git a/SOURCES/0002-drm-i915-add-kernel-parameter-to-disable-async-page-.patch b/SOURCES/0002-drm-i915-add-kernel-parameter-to-disable-async-page-.patch index b91bf1a..a6c9f38 100644 --- a/SOURCES/0002-drm-i915-add-kernel-parameter-to-disable-async-page-.patch +++ b/SOURCES/0002-drm-i915-add-kernel-parameter-to-disable-async-page-.patch @@ -28,31 +28,29 @@ diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_para index de43048543e8..2c6fe740609e 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c -@@ -134,6 +134,10 @@ i915_param_named_unsafe(lmem_size, uint, 0400, +@@ -130,6 +130,10 @@ + "Set the lmem size(in MiB) for each region. (default: 0, all memory)"); i915_param_named_unsafe(lmem_bar_size, uint, 0400, "Set the lmem bar size(in MiB)."); - ++ +i915_param_named_unsafe(disable_async_page_flip, bool, 0400, + "Disable async page flipping" + "(0=disabled [default], 1=enabled)"); -+ - static void _param_print_bool(struct drm_printer *p, const char *name, - bool val) - { + + #if IS_ENABLED(CONFIG_DRM_I915_REPLAY_GPU_HANGS_API) + i915_param_named(enable_debug_only_api, bool, 0400, diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index 1315d7fac850..53d47b1ef79e 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h -@@ -64,7 +64,8 @@ struct drm_printer; - /* leave bools at the end to not create holes */ \ +@@ -64,6 +64,7 @@ param(bool, enable_hangcheck, true, 0600) \ param(bool, error_capture, true, IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) ? 0600 : 0) \ -- param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) -+ param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \ -+ param(bool, disable_async_page_flip, false, 0400) + param(bool, enable_gvt, false, IS_ENABLED(CONFIG_DRM_I915_GVT) ? 0400 : 0) \ ++ param(bool, disable_async_page_flip, false, 0400) \ + param(bool, enable_debug_only_api, false, IS_ENABLED(CONFIG_DRM_I915_REPLAY_GPU_HANGS_API) ? 0400 : 0) #define MEMBER(T, member, ...) T member; - struct i915_params { diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index e8491979a6f2..4682970746c3 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h diff --git a/SOURCES/Module.kabi_dup_riscv64 b/SOURCES/Module.kabi_dup_riscv64 new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/SOURCES/Module.kabi_dup_riscv64 diff --git a/SOURCES/Module.kabi_riscv64 b/SOURCES/Module.kabi_riscv64 new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/SOURCES/Module.kabi_riscv64 diff --git a/SOURCES/OpenRGB.patch b/SOURCES/OpenRGB.patch deleted file mode 100644 index 720345f..0000000 --- a/SOURCES/OpenRGB.patch +++ /dev/null @@ -1,703 +0,0 @@ -diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig -index 2ddca08f8a76..72647850f08e 100644 ---- a/drivers/i2c/busses/Kconfig -+++ b/drivers/i2c/busses/Kconfig -@@ -238,6 +238,15 @@ - combined with a FUSB302 Type-C port-controller as such it is advised - to also select CONFIG_TYPEC_FUSB302=m. - -+config I2C_NCT6775 -+ tristate "Nuvoton NCT6775 and compatible SMBus controller" -+ help -+ If you say yes to this option, support will be included for the -+ Nuvoton NCT6775 and compatible SMBus controllers. -+ -+ This driver can also be built as a module. If so, the module -+ will be called i2c-nct6775. -+ - config I2C_NFORCE2 - tristate "Nvidia nForce2, nForce3 and nForce4" - depends on PCI && HAS_IOPORT -diff --git a/drivers/i2c/busses/Makefile b/drivers/i2c/busses/Makefile -index 25d60889713c..3c2a9b237ac6 100644 ---- a/drivers/i2c/busses/Makefile -+++ b/drivers/i2c/busses/Makefile -@@ -17,6 +17,7 @@ obj-$(CONFIG_I2C_CHT_WC) += i2c-cht-wc.o - obj-$(CONFIG_I2C_I801) += i2c-i801.o - obj-$(CONFIG_I2C_ISCH) += i2c-isch.o - obj-$(CONFIG_I2C_ISMT) += i2c-ismt.o -+obj-$(CONFIG_I2C_NCT6775) += i2c-nct6775.o - obj-$(CONFIG_I2C_NFORCE2) += i2c-nforce2.o - obj-$(CONFIG_I2C_NFORCE2_S4985) += i2c-nforce2-s4985.o - obj-$(CONFIG_I2C_NVIDIA_GPU) += i2c-nvidia-gpu.o -diff --git a/drivers/i2c/busses/i2c-nct6775.c b/drivers/i2c/busses/i2c-nct6775.c -new file mode 100644 -index 000000000000..0462f0952043 ---- /dev/null -+++ b/drivers/i2c/busses/i2c-nct6775.c -@@ -0,0 +1,647 @@ -+/* -+ * i2c-nct6775 - Driver for the SMBus master functionality of -+ * Nuvoton NCT677x Super-I/O chips -+ * -+ * Copyright (C) 2019 Adam Honse <calcprogrammer1@gmail.com> -+ * -+ * Derived from nct6775 hwmon driver -+ * Copyright (C) 2012 Guenter Roeck <linux@roeck-us.net> -+ * -+ * This program is free software; you can redistribute it and/or modify -+ * it under the terms of the GNU General Public License as published by -+ * the Free Software Foundation; either version 2 of the License, or -+ * (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -+ * -+ */ -+ -+#include <linux/module.h> -+#include <linux/init.h> -+#include <linux/slab.h> -+#include <linux/jiffies.h> -+#include <linux/platform_device.h> -+#include <linux/hwmon.h> -+#include <linux/hwmon-sysfs.h> -+#include <linux/hwmon-vid.h> -+#include <linux/err.h> -+#include <linux/mutex.h> -+#include <linux/delay.h> -+#include <linux/ioport.h> -+#include <linux/i2c.h> -+#include <linux/acpi.h> -+#include <linux/bitops.h> -+#include <linux/dmi.h> -+#include <linux/io.h> -+#include <linux/nospec.h> -+ -+#define DRVNAME "i2c-nct6775" -+ -+/* Nuvoton SMBus address offsets */ -+#define SMBHSTDAT (0 + nuvoton_nct6793d_smba) -+#define SMBBLKSZ (1 + nuvoton_nct6793d_smba) -+#define SMBHSTCMD (2 + nuvoton_nct6793d_smba) -+#define SMBHSTIDX (3 + nuvoton_nct6793d_smba) //Index field is the Command field on other controllers -+#define SMBHSTCTL (4 + nuvoton_nct6793d_smba) -+#define SMBHSTADD (5 + nuvoton_nct6793d_smba) -+#define SMBHSTERR (9 + nuvoton_nct6793d_smba) -+#define SMBHSTSTS (0xE + nuvoton_nct6793d_smba) -+ -+/* Command register */ -+#define NCT6793D_READ_BYTE 0 -+#define NCT6793D_READ_WORD 1 -+#define NCT6793D_READ_BLOCK 2 -+#define NCT6793D_BLOCK_WRITE_READ_PROC_CALL 3 -+#define NCT6793D_PROC_CALL 4 -+#define NCT6793D_WRITE_BYTE 8 -+#define NCT6793D_WRITE_WORD 9 -+#define NCT6793D_WRITE_BLOCK 10 -+ -+/* Control register */ -+#define NCT6793D_MANUAL_START 128 -+#define NCT6793D_SOFT_RESET 64 -+ -+/* Error register */ -+#define NCT6793D_NO_ACK 32 -+ -+/* Status register */ -+#define NCT6793D_FIFO_EMPTY 1 -+#define NCT6793D_FIFO_FULL 2 -+#define NCT6793D_MANUAL_ACTIVE 4 -+ -+#define NCT6775_LD_SMBUS 0x0B -+ -+/* Other settings */ -+#define MAX_RETRIES 400 -+ -+enum kinds { nct6106, nct6775, nct6776, nct6779, nct6791, nct6792, nct6793, -+ nct6795, nct6796, nct6798 }; -+ -+struct nct6775_sio_data { -+ int sioreg; -+ enum kinds kind; -+}; -+ -+/* used to set data->name = nct6775_device_names[data->sio_kind] */ -+static const char * const nct6775_device_names[] = { -+ "nct6106", -+ "nct6775", -+ "nct6776", -+ "nct6779", -+ "nct6791", -+ "nct6792", -+ "nct6793", -+ "nct6795", -+ "nct6796", -+ "nct6798", -+}; -+ -+static const char * const nct6775_sio_names[] __initconst = { -+ "NCT6106D", -+ "NCT6775F", -+ "NCT6776D/F", -+ "NCT6779D", -+ "NCT6791D", -+ "NCT6792D", -+ "NCT6793D", -+ "NCT6795D", -+ "NCT6796D", -+ "NCT6798D", -+}; -+ -+#define SIO_REG_LDSEL 0x07 /* Logical device select */ -+#define SIO_REG_DEVID 0x20 /* Device ID (2 bytes) */ -+#define SIO_REG_SMBA 0x62 /* SMBus base address register */ -+ -+#define SIO_NCT6106_ID 0xc450 -+#define SIO_NCT6775_ID 0xb470 -+#define SIO_NCT6776_ID 0xc330 -+#define SIO_NCT6779_ID 0xc560 -+#define SIO_NCT6791_ID 0xc800 -+#define SIO_NCT6792_ID 0xc910 -+#define SIO_NCT6793_ID 0xd120 -+#define SIO_NCT6795_ID 0xd350 -+#define SIO_NCT6796_ID 0xd420 -+#define SIO_NCT6798_ID 0xd428 -+#define SIO_ID_MASK 0xFFF0 -+ -+static inline void -+superio_outb(int ioreg, int reg, int val) -+{ -+ outb(reg, ioreg); -+ outb(val, ioreg + 1); -+} -+ -+static inline int -+superio_inb(int ioreg, int reg) -+{ -+ outb(reg, ioreg); -+ return inb(ioreg + 1); -+} -+ -+static inline void -+superio_select(int ioreg, int ld) -+{ -+ outb(SIO_REG_LDSEL, ioreg); -+ outb(ld, ioreg + 1); -+} -+ -+static inline int -+superio_enter(int ioreg) -+{ -+ /* -+ * Try to reserve <ioreg> and <ioreg + 1> for exclusive access. -+ */ -+ if (!request_muxed_region(ioreg, 2, DRVNAME)) -+ return -EBUSY; -+ -+ outb(0x87, ioreg); -+ outb(0x87, ioreg); -+ -+ return 0; -+} -+ -+static inline void -+superio_exit(int ioreg) -+{ -+ outb(0xaa, ioreg); -+ outb(0x02, ioreg); -+ outb(0x02, ioreg + 1); -+ release_region(ioreg, 2); -+} -+ -+/* -+ * ISA constants -+ */ -+ -+#define IOREGION_ALIGNMENT (~7) -+#define IOREGION_LENGTH 2 -+#define ADDR_REG_OFFSET 0 -+#define DATA_REG_OFFSET 1 -+ -+#define NCT6775_REG_BANK 0x4E -+#define NCT6775_REG_CONFIG 0x40 -+ -+static struct i2c_adapter *nct6775_adapter; -+ -+struct i2c_nct6775_adapdata { -+ unsigned short smba; -+}; -+ -+/* Return negative errno on error. */ -+static s32 nct6775_access(struct i2c_adapter * adap, u16 addr, -+ unsigned short flags, char read_write, -+ u8 command, int size, union i2c_smbus_data * data) -+{ -+ struct i2c_nct6775_adapdata *adapdata = i2c_get_adapdata(adap); -+ unsigned short nuvoton_nct6793d_smba = adapdata->smba; -+ int i, len, cnt; -+ union i2c_smbus_data tmp_data; -+ int timeout = 0; -+ -+ tmp_data.word = 0; -+ cnt = 0; -+ len = 0; -+ -+ outb_p(NCT6793D_SOFT_RESET, SMBHSTCTL); -+ -+ switch (size) { -+ case I2C_SMBUS_QUICK: -+ outb_p((addr << 1) | read_write, -+ SMBHSTADD); -+ break; -+ case I2C_SMBUS_BYTE_DATA: -+ tmp_data.byte = data->byte; -+ case I2C_SMBUS_BYTE: -+ outb_p((addr << 1) | read_write, -+ SMBHSTADD); -+ outb_p(command, SMBHSTIDX); -+ if (read_write == I2C_SMBUS_WRITE) { -+ outb_p(tmp_data.byte, SMBHSTDAT); -+ outb_p(NCT6793D_WRITE_BYTE, SMBHSTCMD); -+ } -+ else { -+ outb_p(NCT6793D_READ_BYTE, SMBHSTCMD); -+ } -+ break; -+ case I2C_SMBUS_WORD_DATA: -+ outb_p((addr << 1) | read_write, -+ SMBHSTADD); -+ outb_p(command, SMBHSTIDX); -+ if (read_write == I2C_SMBUS_WRITE) { -+ outb_p(data->word & 0xff, SMBHSTDAT); -+ outb_p((data->word & 0xff00) >> 8, SMBHSTDAT); -+ outb_p(NCT6793D_WRITE_WORD, SMBHSTCMD); -+ } -+ else { -+ outb_p(NCT6793D_READ_WORD, SMBHSTCMD); -+ } -+ break; -+ case I2C_SMBUS_BLOCK_DATA: -+ outb_p((addr << 1) | read_write, -+ SMBHSTADD); -+ outb_p(command, SMBHSTIDX); -+ if (read_write == I2C_SMBUS_WRITE) { -+ len = data->block[0]; -+ if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) -+ return -EINVAL; -+ outb_p(len, SMBBLKSZ); -+ -+ cnt = 1; -+ if (len >= 4) { -+ for (i = cnt; i <= 4; i++) { -+ outb_p(data->block[i], SMBHSTDAT); -+ } -+ -+ len -= 4; -+ cnt += 4; -+ } -+ else { -+ for (i = cnt; i <= len; i++ ) { -+ outb_p(data->block[i], SMBHSTDAT); -+ } -+ -+ len = 0; -+ } -+ -+ outb_p(NCT6793D_WRITE_BLOCK, SMBHSTCMD); -+ } -+ else { -+ return -ENOTSUPP; -+ } -+ break; -+ default: -+ dev_warn(&adap->dev, "Unsupported transaction %d\n", size); -+ return -EOPNOTSUPP; -+ } -+ -+ outb_p(NCT6793D_MANUAL_START, SMBHSTCTL); -+ -+ while ((size == I2C_SMBUS_BLOCK_DATA) && (len > 0)) { -+ if (read_write == I2C_SMBUS_WRITE) { -+ timeout = 0; -+ while ((inb_p(SMBHSTSTS) & NCT6793D_FIFO_EMPTY) == 0) -+ { -+ if(timeout > MAX_RETRIES) -+ { -+ return -ETIMEDOUT; -+ } -+ usleep_range(250, 500); -+ timeout++; -+ } -+ -+ //Load more bytes into FIFO -+ if (len >= 4) { -+ for (i = cnt; i <= (cnt + 4); i++) { -+ outb_p(data->block[i], SMBHSTDAT); -+ } -+ -+ len -= 4; -+ cnt += 4; -+ } -+ else { -+ for (i = cnt; i <= (cnt + len); i++) { -+ outb_p(data->block[i], SMBHSTDAT); -+ } -+ -+ len = 0; -+ } -+ } -+ else { -+ return -ENOTSUPP; -+ } -+ -+ } -+ -+ //wait for manual mode to complete -+ timeout = 0; -+ while ((inb_p(SMBHSTSTS) & NCT6793D_MANUAL_ACTIVE) != 0) -+ { -+ if(timeout > MAX_RETRIES) -+ { -+ return -ETIMEDOUT; -+ } -+ usleep_range(250, 500); -+ timeout++; -+ } -+ -+ if ((inb_p(SMBHSTERR) & NCT6793D_NO_ACK) != 0) { -+ return -ENXIO; -+ } -+ else if ((read_write == I2C_SMBUS_WRITE) || (size == I2C_SMBUS_QUICK)) { -+ return 0; -+ } -+ -+ switch (size) { -+ case I2C_SMBUS_QUICK: -+ case I2C_SMBUS_BYTE_DATA: -+ data->byte = inb_p(SMBHSTDAT); -+ break; -+ case I2C_SMBUS_WORD_DATA: -+ data->word = inb_p(SMBHSTDAT) + (inb_p(SMBHSTDAT) << 8); -+ break; -+ } -+ return 0; -+} -+ -+static u32 nct6775_func(struct i2c_adapter *adapter) -+{ -+ return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | -+ I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | -+ I2C_FUNC_SMBUS_BLOCK_DATA; -+} -+ -+static const struct i2c_algorithm smbus_algorithm = { -+ .smbus_xfer = nct6775_access, -+ .functionality = nct6775_func, -+}; -+ -+static int nct6775_add_adapter(unsigned short smba, const char *name, struct i2c_adapter **padap) -+{ -+ struct i2c_adapter *adap; -+ struct i2c_nct6775_adapdata *adapdata; -+ int retval; -+ -+ adap = kzalloc(sizeof(*adap), GFP_KERNEL); -+ if (adap == NULL) { -+ return -ENOMEM; -+ } -+ -+ adap->owner = THIS_MODULE; -+ adap->class = I2C_CLASS_HWMON; -+ adap->algo = &smbus_algorithm; -+ -+ adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); -+ if (adapdata == NULL) { -+ kfree(adap); -+ return -ENOMEM; -+ } -+ -+ adapdata->smba = smba; -+ -+ snprintf(adap->name, sizeof(adap->name), -+ "SMBus NCT67xx adapter%s at %04x", name, smba); -+ -+ i2c_set_adapdata(adap, adapdata); -+ -+ retval = i2c_add_adapter(adap); -+ if (retval) { -+ kfree(adapdata); -+ kfree(adap); -+ return retval; -+ } -+ -+ *padap = adap; -+ return 0; -+} -+ -+static void nct6775_remove_adapter(struct i2c_adapter *adap) -+{ -+ struct i2c_nct6775_adapdata *adapdata = i2c_get_adapdata(adap); -+ -+ if (adapdata->smba) { -+ i2c_del_adapter(adap); -+ kfree(adapdata); -+ kfree(adap); -+ } -+} -+ -+//static SIMPLE_DEV_PM_OPS(nct6775_dev_pm_ops, nct6775_suspend, nct6775_resume); -+ -+/* -+ * when Super-I/O functions move to a separate file, the Super-I/O -+ * bus will manage the lifetime of the device and this module will only keep -+ * track of the nct6775 driver. But since we use platform_device_alloc(), we -+ * must keep track of the device -+ */ -+static struct platform_device *pdev[2]; -+ -+static int nct6775_probe(struct platform_device *pdev) -+{ -+ struct device *dev = &pdev->dev; -+ struct nct6775_sio_data *sio_data = dev_get_platdata(dev); -+ struct resource *res; -+ -+ res = platform_get_resource(pdev, IORESOURCE_IO, 0); -+ if (!devm_request_region(&pdev->dev, res->start, IOREGION_LENGTH, -+ DRVNAME)) -+ return -EBUSY; -+ -+ switch (sio_data->kind) { -+ case nct6791: -+ case nct6792: -+ case nct6793: -+ case nct6795: -+ case nct6796: -+ case nct6798: -+ nct6775_add_adapter(res->start, "", &nct6775_adapter); -+ break; -+ default: -+ return -ENODEV; -+ } -+ -+ return 0; -+} -+/* -+static void nct6791_enable_io_mapping(int sioaddr) -+{ -+ int val; -+ -+ val = superio_inb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE); -+ if (val & 0x10) { -+ pr_info("Enabling hardware monitor logical device mappings.\n"); -+ superio_outb(sioaddr, NCT6791_REG_HM_IO_SPACE_LOCK_ENABLE, -+ val & ~0x10); -+ } -+}*/ -+ -+static struct platform_driver i2c_nct6775_driver = { -+ .driver = { -+ .name = DRVNAME, -+// .pm = &nct6775_dev_pm_ops, -+ }, -+ .probe = nct6775_probe, -+}; -+ -+static void __exit i2c_nct6775_exit(void) -+{ -+ int i; -+ -+ if(nct6775_adapter) -+ nct6775_remove_adapter(nct6775_adapter); -+ -+ for (i = 0; i < ARRAY_SIZE(pdev); i++) { -+ if (pdev[i]) -+ platform_device_unregister(pdev[i]); -+ } -+ platform_driver_unregister(&i2c_nct6775_driver); -+} -+ -+/* nct6775_find() looks for a '627 in the Super-I/O config space */ -+static int __init nct6775_find(int sioaddr, struct nct6775_sio_data *sio_data) -+{ -+ u16 val; -+ int err; -+ int addr; -+ -+ err = superio_enter(sioaddr); -+ if (err) -+ return err; -+ -+ val = (superio_inb(sioaddr, SIO_REG_DEVID) << 8) | -+ superio_inb(sioaddr, SIO_REG_DEVID + 1); -+ -+ switch (val & SIO_ID_MASK) { -+ case SIO_NCT6106_ID: -+ sio_data->kind = nct6106; -+ break; -+ case SIO_NCT6775_ID: -+ sio_data->kind = nct6775; -+ break; -+ case SIO_NCT6776_ID: -+ sio_data->kind = nct6776; -+ break; -+ case SIO_NCT6779_ID: -+ sio_data->kind = nct6779; -+ break; -+ case SIO_NCT6791_ID: -+ sio_data->kind = nct6791; -+ break; -+ case SIO_NCT6792_ID: -+ sio_data->kind = nct6792; -+ break; -+ case SIO_NCT6793_ID: -+ sio_data->kind = nct6793; -+ break; -+ case SIO_NCT6795_ID: -+ sio_data->kind = nct6795; -+ break; -+ case SIO_NCT6796_ID: -+ sio_data->kind = nct6796; -+ break; -+ case SIO_NCT6798_ID: -+ sio_data->kind = nct6798; -+ break; -+ default: -+ if (val != 0xffff) -+ pr_debug("unsupported chip ID: 0x%04x\n", val); -+ superio_exit(sioaddr); -+ return -ENODEV; -+ } -+ -+ /* We have a known chip, find the SMBus I/O address */ -+ superio_select(sioaddr, NCT6775_LD_SMBUS); -+ val = (superio_inb(sioaddr, SIO_REG_SMBA) << 8) -+ | superio_inb(sioaddr, SIO_REG_SMBA + 1); -+ addr = val & IOREGION_ALIGNMENT; -+ if (addr == 0) { -+ pr_err("Refusing to enable a Super-I/O device with a base I/O port 0\n"); -+ superio_exit(sioaddr); -+ return -ENODEV; -+ } -+ -+ //if (sio_data->kind == nct6791 || sio_data->kind == nct6792 || -+ // sio_data->kind == nct6793 || sio_data->kind == nct6795 || -+ // sio_data->kind == nct6796) -+ // nct6791_enable_io_mapping(sioaddr); -+ -+ superio_exit(sioaddr); -+ pr_info("Found %s or compatible chip at %#x:%#x\n", -+ nct6775_sio_names[sio_data->kind], sioaddr, addr); -+ sio_data->sioreg = sioaddr; -+ -+ return addr; -+} -+ -+static int __init i2c_nct6775_init(void) -+{ -+ int i, err; -+ bool found = false; -+ int address; -+ struct resource res; -+ struct nct6775_sio_data sio_data; -+ int sioaddr[2] = { 0x2e, 0x4e }; -+ -+ err = platform_driver_register(&i2c_nct6775_driver); -+ if (err) -+ return err; -+ -+ /* -+ * initialize sio_data->kind and sio_data->sioreg. -+ * -+ * when Super-I/O functions move to a separate file, the Super-I/O -+ * driver will probe 0x2e and 0x4e and auto-detect the presence of a -+ * nct6775 hardware monitor, and call probe() -+ */ -+ for (i = 0; i < ARRAY_SIZE(pdev); i++) { -+ address = nct6775_find(sioaddr[i], &sio_data); -+ if (address <= 0) -+ continue; -+ -+ found = true; -+ -+ pdev[i] = platform_device_alloc(DRVNAME, address); -+ if (!pdev[i]) { -+ err = -ENOMEM; -+ goto exit_device_unregister; -+ } -+ -+ err = platform_device_add_data(pdev[i], &sio_data, -+ sizeof(struct nct6775_sio_data)); -+ if (err) -+ goto exit_device_put; -+ -+ memset(&res, 0, sizeof(res)); -+ res.name = DRVNAME; -+ res.start = address; -+ res.end = address + IOREGION_LENGTH - 1; -+ res.flags = IORESOURCE_IO; -+ -+ err = acpi_check_resource_conflict(&res); -+ if (err) { -+ platform_device_put(pdev[i]); -+ pdev[i] = NULL; -+ continue; -+ } -+ -+ err = platform_device_add_resources(pdev[i], &res, 1); -+ if (err) -+ goto exit_device_put; -+ -+ /* platform_device_add calls probe() */ -+ err = platform_device_add(pdev[i]); -+ if (err) -+ goto exit_device_put; -+ } -+ if (!found) { -+ err = -ENODEV; -+ goto exit_unregister; -+ } -+ -+ return 0; -+ -+exit_device_put: -+ platform_device_put(pdev[i]); -+exit_device_unregister: -+ while (--i >= 0) { -+ if (pdev[i]) -+ platform_device_unregister(pdev[i]); -+ } -+exit_unregister: -+ platform_driver_unregister(&i2c_nct6775_driver); -+ return err; -+} -+ -+MODULE_AUTHOR("Adam Honse <calcprogrammer1@gmail.com>"); -+MODULE_DESCRIPTION("SMBus driver for NCT6775F and compatible chips"); -+MODULE_LICENSE("GPL"); -+ -+module_init(i2c_nct6775_init); -+module_exit(i2c_nct6775_exit); -diff --git a/drivers/i2c/busses/i2c-piix4.c b/drivers/i2c/busses/i2c-piix4.c -index 30ded6422e7b..e25ce84c26af 100644 ---- a/drivers/i2c/busses/i2c-piix4.c -+++ b/drivers/i2c/busses/i2c-piix4.c -@@ -467,11 +467,11 @@ static int piix4_transaction(struct i2c_adapter *piix4_adapter) - if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ - usleep_range(2000, 2100); - else -- usleep_range(250, 500); -+ usleep_range(25, 50); - - while ((++timeout < MAX_TIMEOUT) && - ((temp = inb_p(SMBHSTSTS)) & 0x01)) -- usleep_range(250, 500); -+ usleep_range(25, 50); - - /* If the SMBus is still busy, we give up */ - if (timeout == MAX_TIMEOUT) { diff --git a/SOURCES/Patchlist.changelog b/SOURCES/Patchlist.changelog index e388f8c..eb16b5b 100644 --- a/SOURCES/Patchlist.changelog +++ b/SOURCES/Patchlist.changelog @@ -1,153 +1,132 @@ -https://gitlab.com/cki-project/kernel-ark/-/commit/7c261c4b600417524d07c5494a381e58abe404b1 - 7c261c4b600417524d07c5494a381e58abe404b1 drm/nouveau/fb: restore init() for ramgp102 +https://gitlab.com/cki-project/kernel-ark/-/commit/37f88e3ca1bde6c898222d6dbd8f4d804c2e9834 + 37f88e3ca1bde6c898222d6dbd8f4d804c2e9834 media: qcom: camss: Fix ordering of pm_runtime_enable -https://gitlab.com/cki-project/kernel-ark/-/commit/3b2f4b84968261c49a19cde5a2c01c32c09cc1f8 - 3b2f4b84968261c49a19cde5a2c01c32c09cc1f8 xfs: xfs_finobt_count_blocks() walks the wrong btree +https://gitlab.com/cki-project/kernel-ark/-/commit/9f2335d9e326af21c4376eec9bece213a512e726 + 9f2335d9e326af21c4376eec9bece213a512e726 media: qcom: camss: Remove use_count guard in stop_streaming -https://gitlab.com/cki-project/kernel-ark/-/commit/378f837843ce9ccefbf401f707cda2c10c03b258 - 378f837843ce9ccefbf401f707cda2c10c03b258 Revert the F39 commits which should not have pushed +https://gitlab.com/cki-project/kernel-ark/-/commit/7e88a0ffc13ab94b37a3d45e1180bf98d5a1ab75 + 7e88a0ffc13ab94b37a3d45e1180bf98d5a1ab75 arm64: dts: allwinner: a64: Add GPU thermal trips to the SoC dtsi -https://gitlab.com/cki-project/kernel-ark/-/commit/617f0465246a2629c0ce735529f0addaacba0604 - 617f0465246a2629c0ce735529f0addaacba0604 KVM: PPC: Book3S HV nestedv2: Keep nested guest HASHPKEYR in sync +https://gitlab.com/cki-project/kernel-ark/-/commit/5b1fd9a9d2bd49e45e3703121c69142a78f75acb + 5b1fd9a9d2bd49e45e3703121c69142a78f75acb arm64: dts: rockchip: Raise Pinebook Pro's panel backlight PWM frequency -https://gitlab.com/cki-project/kernel-ark/-/commit/713ce2b8136985b1a7ff2ec6dc3c75ebbf4e3ddd - 713ce2b8136985b1a7ff2ec6dc3c75ebbf4e3ddd KVM: PPC: Book3S HV: Add one-reg interface for HASHPKEYR register +https://gitlab.com/cki-project/kernel-ark/-/commit/1702e478b95131f3004b3c2eb2afd9eb88c69972 + 1702e478b95131f3004b3c2eb2afd9eb88c69972 arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor -https://gitlab.com/cki-project/kernel-ark/-/commit/3a7a0b70797b9e19312547345f0fd84595458302 - 3a7a0b70797b9e19312547345f0fd84595458302 KVM: PPC: Book3S HV nestedv2: Keep nested guest HASHKEYR in sync +https://gitlab.com/cki-project/kernel-ark/-/commit/eac4ee8c9ca0b44bc1611e735a08a940792f5ef0 + eac4ee8c9ca0b44bc1611e735a08a940792f5ef0 ARM: dts: bcm2837/bcm2712: adjust local intc node names -https://gitlab.com/cki-project/kernel-ark/-/commit/aab7db47edcfacd592b7483fa0371bf8d23e8b6f - aab7db47edcfacd592b7483fa0371bf8d23e8b6f KVM: PPC: Book3S HV: Add one-reg interface for HASHKEYR register +https://gitlab.com/cki-project/kernel-ark/-/commit/68ca5d3e34a03dffe1ff51bf8a585923d7c985e5 + 68ca5d3e34a03dffe1ff51bf8a585923d7c985e5 arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 -https://gitlab.com/cki-project/kernel-ark/-/commit/1d5f5405eb8b0023aefe21d56558d742e2b558ea - 1d5f5405eb8b0023aefe21d56558d742e2b558ea KVM: PPC: Book3S HV nestedv2: Keep nested guest DEXCR in sync +https://gitlab.com/cki-project/kernel-ark/-/commit/9d4f912ea7ae72beae0943fb93468c93c08d53fd + 9d4f912ea7ae72beae0943fb93468c93c08d53fd redhat: include resolve_btfids in kernel-devel -https://gitlab.com/cki-project/kernel-ark/-/commit/3eec751027838fde380aee0676b2bb9806a01a75 - 3eec751027838fde380aee0676b2bb9806a01a75 KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register +https://gitlab.com/cki-project/kernel-ark/-/commit/9b332458aa4b5d43c795b8c03e1041956d92e09b + 9b332458aa4b5d43c795b8c03e1041956d92e09b redhat: workaround CKI cross compilation for scripts -https://gitlab.com/cki-project/kernel-ark/-/commit/c3be1c8ba3dc3a70fb65546e836193ce584de02b - c3be1c8ba3dc3a70fb65546e836193ce584de02b Revert "cpupower: Bump soname version" +https://gitlab.com/cki-project/kernel-ark/-/commit/1bd2b8b9cdd378bc0bcc46ffb3580b810b22bec5 + 1bd2b8b9cdd378bc0bcc46ffb3580b810b22bec5 crypto: akcipher - Disable signing and decryption -https://gitlab.com/cki-project/kernel-ark/-/commit/d42657488c703c24d1fffaecced0b3b82d30b393 - d42657488c703c24d1fffaecced0b3b82d30b393 selinux: revert our use of vma_is_initial_heap() +https://gitlab.com/cki-project/kernel-ark/-/commit/35655c383bfd88c12f760899ea64659da5a29627 + 35655c383bfd88c12f760899ea64659da5a29627 crypto: dh - implement FIPS PCT -https://gitlab.com/cki-project/kernel-ark/-/commit/3a19264d7608d1c0cb6adff9f45883887a30ba29 - 3a19264d7608d1c0cb6adff9f45883887a30ba29 Revert "ata: libata-scsi: Honor the D_SENSE bit for CK_COND=1 and no error" +https://gitlab.com/cki-project/kernel-ark/-/commit/dc99bf18097cb54436cdea0c68844819d2adfe75 + dc99bf18097cb54436cdea0c68844819d2adfe75 crypto: ecdh - disallow plain "ecdh" usage in FIPS mode -https://gitlab.com/cki-project/kernel-ark/-/commit/2c6b48dfc4f3aad194a99c23f8d3e604c1a5593f - 2c6b48dfc4f3aad194a99c23f8d3e604c1a5593f wifi: brcmfmac: cfg80211: Handle SSID based pmksa deletion +https://gitlab.com/cki-project/kernel-ark/-/commit/d684af303ca6e652bcb52c6637f1c49a65f59100 + d684af303ca6e652bcb52c6637f1c49a65f59100 crypto: seqiv - flag instantiations as FIPS compliant -https://gitlab.com/cki-project/kernel-ark/-/commit/64905c656dbdbc1a21d838d33e10699e391f185b - 64905c656dbdbc1a21d838d33e10699e391f185b Bluetooth: hci_event: Fix setting DISCOVERY_FINDING for passive scanning +https://gitlab.com/cki-project/kernel-ark/-/commit/7c0d780c693acc53b94b27e5a9c72d377b98aab4 + 7c0d780c693acc53b94b27e5a9c72d377b98aab4 not upstream: drop openssl ENGINE API usage -https://gitlab.com/cki-project/kernel-ark/-/commit/df97a13dc31a28e5c34e946a9e229c8b0e4c94b7 - df97a13dc31a28e5c34e946a9e229c8b0e4c94b7 not upstream: drop openssl ENGINE API usage +https://gitlab.com/cki-project/kernel-ark/-/commit/f8e0850f38863ef52f2cd55fdcdb3abaaad9e73e + f8e0850f38863ef52f2cd55fdcdb3abaaad9e73e lsm: update security_lock_kernel_down -https://gitlab.com/cki-project/kernel-ark/-/commit/3454711caea17db89f985e7dff3e99ee6b88c409 - 3454711caea17db89f985e7dff3e99ee6b88c409 media: ipu-bridge: Add HIDs from out of tree IPU6 driver ipu-bridge copy +https://gitlab.com/cki-project/kernel-ark/-/commit/32ab33b828ef7b77647c69cf192ca42d9f6566e9 + 32ab33b828ef7b77647c69cf192ca42d9f6566e9 scsi: sd: Add "probe_type" module parameter to allow synchronous probing -https://gitlab.com/cki-project/kernel-ark/-/commit/be66be71dcf134a103446381d3d3ad7c2f3d1f36 - be66be71dcf134a103446381d3d3ad7c2f3d1f36 media: ipu-bridge: Sort ipu_supported_sensors[] array by ACPI HID +https://gitlab.com/cki-project/kernel-ark/-/commit/060bc66dee0bd947f7a19240d1059128c39a555b + 060bc66dee0bd947f7a19240d1059128c39a555b Revert "Remove EXPERT from ARCH_FORCE_MAX_ORDER for aarch64" -https://gitlab.com/cki-project/kernel-ark/-/commit/cbbaa28dd511151ef6453ba310d827e8033ec9c0 - cbbaa28dd511151ef6453ba310d827e8033ec9c0 lsm: update security_lock_kernel_down +https://gitlab.com/cki-project/kernel-ark/-/commit/87bee3c15d593cdf1f4c337d65900cc8639459e2 + 87bee3c15d593cdf1f4c337d65900cc8639459e2 Enable IO_URING for RHEL -https://gitlab.com/cki-project/kernel-ark/-/commit/c63e36d30db93dc40db4fe4a9eec03faab3cdc70 - c63e36d30db93dc40db4fe4a9eec03faab3cdc70 random: replace import_single_range() with import_ubuf() +https://gitlab.com/cki-project/kernel-ark/-/commit/c1791b7d3183881333af9a8fec60565ac55cad61 + c1791b7d3183881333af9a8fec60565ac55cad61 Remove EXPERT from ARCH_FORCE_MAX_ORDER for aarch64 -https://gitlab.com/cki-project/kernel-ark/-/commit/b9735227d9941ce60606745511251a36fa22a790 - b9735227d9941ce60606745511251a36fa22a790 crypto: rng - Override drivers/char/random in FIPS mode +https://gitlab.com/cki-project/kernel-ark/-/commit/ad94095fbf83123eeb07fdbf38af75b0f5344f27 + ad94095fbf83123eeb07fdbf38af75b0f5344f27 redhat: version two of Makefile.rhelver tweaks -https://gitlab.com/cki-project/kernel-ark/-/commit/65d1b706fca339b0903f4fbfeaf8d178b8172c7e - 65d1b706fca339b0903f4fbfeaf8d178b8172c7e random: Add hook to override device reads and getrandom(2) +https://gitlab.com/cki-project/kernel-ark/-/commit/baf728d501a2661e474ebbae11d667849e17d29b + baf728d501a2661e474ebbae11d667849e17d29b redhat: adapt to upstream Makefile change -https://gitlab.com/cki-project/kernel-ark/-/commit/c90965635e3602b0c9e4cc886d676c442dd42258 - c90965635e3602b0c9e4cc886d676c442dd42258 scsi: sd: Add "probe_type" module parameter to allow synchronous probing +https://gitlab.com/cki-project/kernel-ark/-/commit/472b92a5d9724cbbd0607fd5d82947764c2b972f + 472b92a5d9724cbbd0607fd5d82947764c2b972f Change acpi_bus_get_acpi_device to acpi_get_acpi_dev -https://gitlab.com/cki-project/kernel-ark/-/commit/38785ac0bb912f801fded5a5941d88b04d7d7290 - 38785ac0bb912f801fded5a5941d88b04d7d7290 Revert "Remove EXPERT from ARCH_FORCE_MAX_ORDER for aarch64" +https://gitlab.com/cki-project/kernel-ark/-/commit/d75c410357fb64130d57d556ff9229139c14a8e8 + d75c410357fb64130d57d556ff9229139c14a8e8 RHEL: disable io_uring support -https://gitlab.com/cki-project/kernel-ark/-/commit/afb130da7fa29ace02a6503e9a6ace1a20f308f6 - afb130da7fa29ace02a6503e9a6ace1a20f308f6 Enable IO_URING for RHEL +https://gitlab.com/cki-project/kernel-ark/-/commit/6e698e13917736eccc5bb20af0bc67490d8528cf + 6e698e13917736eccc5bb20af0bc67490d8528cf REDHAT: coresight: etm4x: Disable coresight on HPE Apollo 70 -https://gitlab.com/cki-project/kernel-ark/-/commit/35af8d13f76ff5350cede226edd174d3c0da8746 - 35af8d13f76ff5350cede226edd174d3c0da8746 Remove EXPERT from ARCH_FORCE_MAX_ORDER for aarch64 +https://gitlab.com/cki-project/kernel-ark/-/commit/85626adff3f11ecbdb88472ddbd9ce884ef9e114 + 85626adff3f11ecbdb88472ddbd9ce884ef9e114 KEYS: Make use of platform keyring for module signature verify -https://gitlab.com/cki-project/kernel-ark/-/commit/6fc82f934cef12036a096abd8b6c96aaa91caa27 - 6fc82f934cef12036a096abd8b6c96aaa91caa27 redhat: version two of Makefile.rhelver tweaks +https://gitlab.com/cki-project/kernel-ark/-/commit/ee87b152d9cb9f421259db9bfc8e3904c8d7305f + ee87b152d9cb9f421259db9bfc8e3904c8d7305f Input: rmi4 - remove the need for artificial IRQ in case of HID -https://gitlab.com/cki-project/kernel-ark/-/commit/4514ddff557ce3d0376ba0987caed185f7add413 - 4514ddff557ce3d0376ba0987caed185f7add413 redhat: adapt to upstream Makefile change +https://gitlab.com/cki-project/kernel-ark/-/commit/1ed5225c5a34662ad010075699d8790f5b7171dc + 1ed5225c5a34662ad010075699d8790f5b7171dc ARM: tegra: usb no reset -https://gitlab.com/cki-project/kernel-ark/-/commit/3070d9bf71f868356d7981c303f905e09db7f181 - 3070d9bf71f868356d7981c303f905e09db7f181 Change acpi_bus_get_acpi_device to acpi_get_acpi_dev +https://gitlab.com/cki-project/kernel-ark/-/commit/b0ed5d1de8bc342f1620f00d8378a8c7b3f41e26 + b0ed5d1de8bc342f1620f00d8378a8c7b3f41e26 s390: Lock down the kernel when the IPL secure flag is set -https://gitlab.com/cki-project/kernel-ark/-/commit/38541e47233d3488faf6e03e3c9766d89594da4c - 38541e47233d3488faf6e03e3c9766d89594da4c RHEL: disable io_uring support +https://gitlab.com/cki-project/kernel-ark/-/commit/a2c6c57e2d1d60148bc3e623dbc046aef65eacdb + a2c6c57e2d1d60148bc3e623dbc046aef65eacdb efi: Lock down the kernel if booted in secure boot mode -https://gitlab.com/cki-project/kernel-ark/-/commit/43e1a1bf7e0e75155e871e6073f102fcf2521bf2 - 43e1a1bf7e0e75155e871e6073f102fcf2521bf2 REDHAT: coresight: etm4x: Disable coresight on HPE Apollo 70 +https://gitlab.com/cki-project/kernel-ark/-/commit/c9a7afaa703bfd5c439fcada879031982e1f31a5 + c9a7afaa703bfd5c439fcada879031982e1f31a5 efi: Add an EFI_SECURE_BOOT flag to indicate secure boot mode -https://gitlab.com/cki-project/kernel-ark/-/commit/60b325a0fe9439e714c086ad9c1953ef336d9c18 - 60b325a0fe9439e714c086ad9c1953ef336d9c18 KEYS: Make use of platform keyring for module signature verify +https://gitlab.com/cki-project/kernel-ark/-/commit/044abfe144b8f9413327cb5f6de53fa65bee13fa + 044abfe144b8f9413327cb5f6de53fa65bee13fa security: lockdown: expose a hook to lock the kernel down -https://gitlab.com/cki-project/kernel-ark/-/commit/720413433847a69179713f8acc9ddf34b97aa0cc - 720413433847a69179713f8acc9ddf34b97aa0cc Input: rmi4 - remove the need for artificial IRQ in case of HID +https://gitlab.com/cki-project/kernel-ark/-/commit/df4dc5c5082636ea3dd0096eae3e113c3b3903d7 + df4dc5c5082636ea3dd0096eae3e113c3b3903d7 Make get_cert_list() use efi_status_to_str() to print error messages. -https://gitlab.com/cki-project/kernel-ark/-/commit/1c4d521584814938e16894cedd74fecc7fae4e4d - 1c4d521584814938e16894cedd74fecc7fae4e4d ARM: tegra: usb no reset +https://gitlab.com/cki-project/kernel-ark/-/commit/8378c41fcd8c0fadf4d4e3d046870c570855dd5f + 8378c41fcd8c0fadf4d4e3d046870c570855dd5f Add efi_status_to_str() and rework efi_status_to_err(). -https://gitlab.com/cki-project/kernel-ark/-/commit/b9ac33fa8da358c7cd9d5fcf81a81e9440c4f4e8 - b9ac33fa8da358c7cd9d5fcf81a81e9440c4f4e8 arm: make CONFIG_HIGHPTE optional without CONFIG_EXPERT +https://gitlab.com/cki-project/kernel-ark/-/commit/1d98b5d2ef6e9b3bcb2e71e0b89a7777d28b87cb + 1d98b5d2ef6e9b3bcb2e71e0b89a7777d28b87cb arm: aarch64: Drop the EXPERT setting from ARM64_FORCE_52BIT -https://gitlab.com/cki-project/kernel-ark/-/commit/9b433e174c62feee214f54c0c37c6b9ef563c17c - 9b433e174c62feee214f54c0c37c6b9ef563c17c s390: Lock down the kernel when the IPL secure flag is set +https://gitlab.com/cki-project/kernel-ark/-/commit/0f01dc56b6690c204e534efead7f833a151668e4 + 0f01dc56b6690c204e534efead7f833a151668e4 iommu/arm-smmu: workaround DMA mode issues -https://gitlab.com/cki-project/kernel-ark/-/commit/f12e9938ce152070d1321726f9350ddf45954456 - f12e9938ce152070d1321726f9350ddf45954456 efi: Lock down the kernel if booted in secure boot mode +https://gitlab.com/cki-project/kernel-ark/-/commit/f4aceb8131752369713f8eedb949c72a6ff6f65b + f4aceb8131752369713f8eedb949c72a6ff6f65b ipmi: do not configure ipmi for HPE m400 -https://gitlab.com/cki-project/kernel-ark/-/commit/9a13b2349fb725958f5325ff8523376101ef8383 - 9a13b2349fb725958f5325ff8523376101ef8383 efi: Add an EFI_SECURE_BOOT flag to indicate secure boot mode +https://gitlab.com/cki-project/kernel-ark/-/commit/8097fbfdc958f3b46fae70e593c65221b373626e + 8097fbfdc958f3b46fae70e593c65221b373626e ahci: thunderx2: Fix for errata that affects stop engine -https://gitlab.com/cki-project/kernel-ark/-/commit/0af95004576d1c8c70ddb214f32067d033d6649c - 0af95004576d1c8c70ddb214f32067d033d6649c security: lockdown: expose a hook to lock the kernel down +https://gitlab.com/cki-project/kernel-ark/-/commit/50f5d1278d3927a4fe64f52d8f098dc8fd70f1af + 50f5d1278d3927a4fe64f52d8f098dc8fd70f1af Vulcan: AHCI PCI bar fix for Broadcom Vulcan early silicon -https://gitlab.com/cki-project/kernel-ark/-/commit/66c1104a75fd35975a3fd001a80e6cfe6e4e2e95 - 66c1104a75fd35975a3fd001a80e6cfe6e4e2e95 Make get_cert_list() use efi_status_to_str() to print error messages. +https://gitlab.com/cki-project/kernel-ark/-/commit/a67c78d8f995bab09b4ba5d440610237472d2e19 + a67c78d8f995bab09b4ba5d440610237472d2e19 tags.sh: Ignore redhat/rpm -https://gitlab.com/cki-project/kernel-ark/-/commit/9b009a11be7b5673b633f97dd79bbbb4a2a383d5 - 9b009a11be7b5673b633f97dd79bbbb4a2a383d5 Add efi_status_to_str() and rework efi_status_to_err(). +https://gitlab.com/cki-project/kernel-ark/-/commit/bd765dc97b11b68f772e662df0c03e5ceccdb9d0 + bd765dc97b11b68f772e662df0c03e5ceccdb9d0 aarch64: acpi scan: Fix regression related to X-Gene UARTs -https://gitlab.com/cki-project/kernel-ark/-/commit/31acc47a35aa48eb72f286c23bd3dc6170d4679b - 31acc47a35aa48eb72f286c23bd3dc6170d4679b arm: aarch64: Drop the EXPERT setting from ARM64_FORCE_52BIT +https://gitlab.com/cki-project/kernel-ark/-/commit/1b14c142506526498b6839daffedb5318e9331d3 + 1b14c142506526498b6839daffedb5318e9331d3 ACPI / irq: Workaround firmware issue on X-Gene based m400 -https://gitlab.com/cki-project/kernel-ark/-/commit/a1251f95f26d81227f6f9f9c5a6da0ba878c101f - a1251f95f26d81227f6f9f9c5a6da0ba878c101f iommu/arm-smmu: workaround DMA mode issues +https://gitlab.com/cki-project/kernel-ark/-/commit/ceadcd821a820a3d4f93125393d6b853f5f8c789 + ceadcd821a820a3d4f93125393d6b853f5f8c789 ACPI: APEI: arm64: Ignore broken HPE moonshot APEI support -https://gitlab.com/cki-project/kernel-ark/-/commit/3a9a8d542ceb13c88aec9a01641e622f902966ef - 3a9a8d542ceb13c88aec9a01641e622f902966ef ipmi: do not configure ipmi for HPE m400 +https://gitlab.com/cki-project/kernel-ark/-/commit/a61ca8bd4bc11f602e04a0263b4a54098f84ceda + a61ca8bd4bc11f602e04a0263b4a54098f84ceda Pull the RHEL version defines out of the Makefile -https://gitlab.com/cki-project/kernel-ark/-/commit/92a98c325754a3b7ac5120be23d44c4b39be2ff4 - 92a98c325754a3b7ac5120be23d44c4b39be2ff4 ahci: thunderx2: Fix for errata that affects stop engine - -https://gitlab.com/cki-project/kernel-ark/-/commit/c8e9b8316a520281c415bbcd5d4e79c83ef1efe2 - c8e9b8316a520281c415bbcd5d4e79c83ef1efe2 Vulcan: AHCI PCI bar fix for Broadcom Vulcan early silicon - -https://gitlab.com/cki-project/kernel-ark/-/commit/596ed9913c9baa40872fae05c2b2d25361d9ba5a - 596ed9913c9baa40872fae05c2b2d25361d9ba5a tags.sh: Ignore redhat/rpm - -https://gitlab.com/cki-project/kernel-ark/-/commit/ad9ca98ac11c17c7c0a86150fd39fdb2c5555eae - ad9ca98ac11c17c7c0a86150fd39fdb2c5555eae aarch64: acpi scan: Fix regression related to X-Gene UARTs - -https://gitlab.com/cki-project/kernel-ark/-/commit/51d0866487663784d1cc1665d804f5a7fe62d171 - 51d0866487663784d1cc1665d804f5a7fe62d171 ACPI / irq: Workaround firmware issue on X-Gene based m400 - -https://gitlab.com/cki-project/kernel-ark/-/commit/301279f0f655f76a7ca1ed8583a483253139a2a9 - 301279f0f655f76a7ca1ed8583a483253139a2a9 ACPI: APEI: arm64: Ignore broken HPE moonshot APEI support - -https://gitlab.com/cki-project/kernel-ark/-/commit/9c3c3b074c576933be673f718aa7444273317ab5 - 9c3c3b074c576933be673f718aa7444273317ab5 Pull the RHEL version defines out of the Makefile - -https://gitlab.com/cki-project/kernel-ark/-/commit/030267e59ba8d0219857aceb6e41fb9ced3b386f - 030267e59ba8d0219857aceb6e41fb9ced3b386f [initial commit] Add Red Hat variables in the top level makefile +https://gitlab.com/cki-project/kernel-ark/-/commit/70cf1cf208f8aa5ef855bda2a5ff8feecee2292c + 70cf1cf208f8aa5ef855bda2a5ff8feecee2292c [initial commit] Add Red Hat variables in the top level makefile diff --git a/SOURCES/cachy-bbr3.patch b/SOURCES/cachy-bbr3.patch deleted file mode 100644 index 51633e0..0000000 --- a/SOURCES/cachy-bbr3.patch +++ /dev/null @@ -1,3386 +0,0 @@ -From b8584936a7a1eb2149d0c10de2ac05ca7acc5c9f Mon Sep 17 00:00:00 2001 -From: Peter Jung <admin@ptr1337.dev> -Date: Sat, 3 Aug 2024 09:32:56 +0200 -Subject: [PATCH 02/12] bbr3 - -Signed-off-by: Peter Jung <admin@ptr1337.dev> ---- - include/linux/tcp.h | 4 +- - include/net/inet_connection_sock.h | 4 +- - include/net/tcp.h | 72 +- - include/uapi/linux/inet_diag.h | 23 + - include/uapi/linux/rtnetlink.h | 4 +- - include/uapi/linux/tcp.h | 1 + - net/ipv4/Kconfig | 21 +- - net/ipv4/bpf_tcp_ca.c | 9 +- - net/ipv4/tcp.c | 3 + - net/ipv4/tcp_bbr.c | 2230 +++++++++++++++++++++------- - net/ipv4/tcp_cong.c | 1 + - net/ipv4/tcp_input.c | 40 +- - net/ipv4/tcp_minisocks.c | 2 + - net/ipv4/tcp_output.c | 48 +- - net/ipv4/tcp_rate.c | 30 +- - net/ipv4/tcp_timer.c | 1 + - 16 files changed, 1940 insertions(+), 553 deletions(-) - -diff --git a/include/linux/tcp.h b/include/linux/tcp.h -index 6a5e08b937b3..27aab715490e 100644 ---- a/include/linux/tcp.h -+++ b/include/linux/tcp.h -@@ -369,7 +369,9 @@ struct tcp_sock { - u8 compressed_ack; - u8 dup_ack_counter:2, - tlp_retrans:1, /* TLP is a retransmission */ -- unused:5; -+ fast_ack_mode:2, /* which fast ack mode ? */ -+ tlp_orig_data_app_limited:1, /* app-limited before TLP rtx? */ -+ unused:2; - u8 thin_lto : 1,/* Use linear timeouts for thin streams */ - fastopen_connect:1, /* FASTOPEN_CONNECT sockopt */ - fastopen_no_cookie:1, /* Allow send/recv SYN+data without a cookie */ -diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h -index c0deaafebfdc..d53f042d936e 100644 ---- a/include/net/inet_connection_sock.h -+++ b/include/net/inet_connection_sock.h -@@ -137,8 +137,8 @@ struct inet_connection_sock { - u32 icsk_probes_tstamp; - u32 icsk_user_timeout; - -- u64 icsk_ca_priv[104 / sizeof(u64)]; --#define ICSK_CA_PRIV_SIZE sizeof_field(struct inet_connection_sock, icsk_ca_priv) -+#define ICSK_CA_PRIV_SIZE (144) -+ u64 icsk_ca_priv[ICSK_CA_PRIV_SIZE / sizeof(u64)]; - }; - - #define ICSK_TIME_RETRANS 1 /* Retransmit timer */ -diff --git a/include/net/tcp.h b/include/net/tcp.h -index 32815a40dea1..109b8d1ddc31 100644 ---- a/include/net/tcp.h -+++ b/include/net/tcp.h -@@ -375,6 +375,8 @@ static inline void tcp_dec_quickack_mode(struct sock *sk) - #define TCP_ECN_QUEUE_CWR 2 - #define TCP_ECN_DEMAND_CWR 4 - #define TCP_ECN_SEEN 8 -+#define TCP_ECN_LOW 16 -+#define TCP_ECN_ECT_PERMANENT 32 - - enum tcp_tw_status { - TCP_TW_SUCCESS = 0, -@@ -779,6 +781,15 @@ static inline void tcp_fast_path_check(struct sock *sk) - - u32 tcp_delack_max(const struct sock *sk); - -+static inline void tcp_set_ecn_low_from_dst(struct sock *sk, -+ const struct dst_entry *dst) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ -+ if (dst_feature(dst, RTAX_FEATURE_ECN_LOW)) -+ tp->ecn_flags |= TCP_ECN_LOW; -+} -+ - /* Compute the actual rto_min value */ - static inline u32 tcp_rto_min(const struct sock *sk) - { -@@ -884,6 +895,11 @@ static inline u32 tcp_stamp_us_delta(u64 t1, u64 t0) - return max_t(s64, t1 - t0, 0); - } - -+static inline u32 tcp_stamp32_us_delta(u32 t1, u32 t0) -+{ -+ return max_t(s32, t1 - t0, 0); -+} -+ - /* provide the departure time in us unit */ - static inline u64 tcp_skb_timestamp_us(const struct sk_buff *skb) - { -@@ -973,9 +989,14 @@ struct tcp_skb_cb { - /* pkts S/ACKed so far upon tx of skb, incl retrans: */ - __u32 delivered; - /* start of send pipeline phase */ -- u64 first_tx_mstamp; -+ u32 first_tx_mstamp; - /* when we reached the "delivered" count */ -- u64 delivered_mstamp; -+ u32 delivered_mstamp; -+#define TCPCB_IN_FLIGHT_BITS 20 -+#define TCPCB_IN_FLIGHT_MAX ((1U << TCPCB_IN_FLIGHT_BITS) - 1) -+ u32 in_flight:20, /* packets in flight at transmit */ -+ unused2:12; -+ u32 lost; /* packets lost so far upon tx of skb */ - } tx; /* only used for outgoing skbs */ - union { - struct inet_skb_parm h4; -@@ -1079,6 +1100,7 @@ enum tcp_ca_event { - CA_EVENT_LOSS, /* loss timeout */ - CA_EVENT_ECN_NO_CE, /* ECT set, but not CE marked */ - CA_EVENT_ECN_IS_CE, /* received CE marked IP packet */ -+ CA_EVENT_TLP_RECOVERY, /* a lost segment was repaired by TLP probe */ - }; - - /* Information about inbound ACK, passed to cong_ops->in_ack_event() */ -@@ -1101,7 +1123,11 @@ enum tcp_ca_ack_event_flags { - #define TCP_CONG_NON_RESTRICTED 0x1 - /* Requires ECN/ECT set on all packets */ - #define TCP_CONG_NEEDS_ECN 0x2 --#define TCP_CONG_MASK (TCP_CONG_NON_RESTRICTED | TCP_CONG_NEEDS_ECN) -+/* Wants notification of CE events (CA_EVENT_ECN_IS_CE, CA_EVENT_ECN_NO_CE). */ -+#define TCP_CONG_WANTS_CE_EVENTS 0x4 -+#define TCP_CONG_MASK (TCP_CONG_NON_RESTRICTED | \ -+ TCP_CONG_NEEDS_ECN | \ -+ TCP_CONG_WANTS_CE_EVENTS) - - union tcp_cc_info; - -@@ -1121,10 +1147,13 @@ struct ack_sample { - */ - struct rate_sample { - u64 prior_mstamp; /* starting timestamp for interval */ -+ u32 prior_lost; /* tp->lost at "prior_mstamp" */ - u32 prior_delivered; /* tp->delivered at "prior_mstamp" */ - u32 prior_delivered_ce;/* tp->delivered_ce at "prior_mstamp" */ -+ u32 tx_in_flight; /* packets in flight at starting timestamp */ -+ s32 lost; /* number of packets lost over interval */ - s32 delivered; /* number of packets delivered over interval */ -- s32 delivered_ce; /* number of packets delivered w/ CE marks*/ -+ s32 delivered_ce; /* packets delivered w/ CE mark over interval */ - long interval_us; /* time for tp->delivered to incr "delivered" */ - u32 snd_interval_us; /* snd interval for delivered packets */ - u32 rcv_interval_us; /* rcv interval for delivered packets */ -@@ -1135,7 +1164,9 @@ struct rate_sample { - u32 last_end_seq; /* end_seq of most recently ACKed packet */ - bool is_app_limited; /* is sample from packet with bubble in pipe? */ - bool is_retrans; /* is sample from retransmission? */ -+ bool is_acking_tlp_retrans_seq; /* ACKed a TLP retransmit sequence? */ - bool is_ack_delayed; /* is this (likely) a delayed ACK? */ -+ bool is_ece; /* did this ACK have ECN marked? */ - }; - - struct tcp_congestion_ops { -@@ -1159,8 +1190,11 @@ struct tcp_congestion_ops { - /* hook for packet ack accounting (optional) */ - void (*pkts_acked)(struct sock *sk, const struct ack_sample *sample); - -- /* override sysctl_tcp_min_tso_segs */ -- u32 (*min_tso_segs)(struct sock *sk); -+ /* pick target number of segments per TSO/GSO skb (optional): */ -+ u32 (*tso_segs)(struct sock *sk, unsigned int mss_now); -+ -+ /* react to a specific lost skb (optional) */ -+ void (*skb_marked_lost)(struct sock *sk, const struct sk_buff *skb); - - /* call when packets are delivered to update cwnd and pacing rate, - * after all the ca_state processing. (optional) -@@ -1226,6 +1260,14 @@ static inline char *tcp_ca_get_name_by_key(u32 key, char *buffer) - } - #endif - -+static inline bool tcp_ca_wants_ce_events(const struct sock *sk) -+{ -+ const struct inet_connection_sock *icsk = inet_csk(sk); -+ -+ return icsk->icsk_ca_ops->flags & (TCP_CONG_NEEDS_ECN | -+ TCP_CONG_WANTS_CE_EVENTS); -+} -+ - static inline bool tcp_ca_needs_ecn(const struct sock *sk) - { - const struct inet_connection_sock *icsk = inet_csk(sk); -@@ -1245,6 +1287,7 @@ static inline void tcp_ca_event(struct sock *sk, const enum tcp_ca_event event) - void tcp_set_ca_state(struct sock *sk, const u8 ca_state); - - /* From tcp_rate.c */ -+void tcp_set_tx_in_flight(struct sock *sk, struct sk_buff *skb); - void tcp_rate_skb_sent(struct sock *sk, struct sk_buff *skb); - void tcp_rate_skb_delivered(struct sock *sk, struct sk_buff *skb, - struct rate_sample *rs); -@@ -1257,6 +1300,21 @@ static inline bool tcp_skb_sent_after(u64 t1, u64 t2, u32 seq1, u32 seq2) - return t1 > t2 || (t1 == t2 && after(seq1, seq2)); - } - -+/* If a retransmit failed due to local qdisc congestion or other local issues, -+ * then we may have called tcp_set_skb_tso_segs() to increase the number of -+ * segments in the skb without increasing the tx.in_flight. In all other cases, -+ * the tx.in_flight should be at least as big as the pcount of the sk_buff. We -+ * do not have the state to know whether a retransmit failed due to local qdisc -+ * congestion or other local issues, so to avoid spurious warnings we consider -+ * that any skb marked lost may have suffered that fate. -+ */ -+static inline bool tcp_skb_tx_in_flight_is_suspicious(u32 skb_pcount, -+ u32 skb_sacked_flags, -+ u32 tx_in_flight) -+{ -+ return (skb_pcount > tx_in_flight) && !(skb_sacked_flags & TCPCB_LOST); -+} -+ - /* These functions determine how the current flow behaves in respect of SACK - * handling. SACK is negotiated with the peer, and therefore it can vary - * between different flows. -@@ -2419,7 +2477,7 @@ struct tcp_plb_state { - u8 consec_cong_rounds:5, /* consecutive congested rounds */ - unused:3; - u32 pause_until; /* jiffies32 when PLB can resume rerouting */ --}; -+} __attribute__ ((__packed__)); - - static inline void tcp_plb_init(const struct sock *sk, - struct tcp_plb_state *plb) -diff --git a/include/uapi/linux/inet_diag.h b/include/uapi/linux/inet_diag.h -index 50655de04c9b..82f8bd8f0d16 100644 ---- a/include/uapi/linux/inet_diag.h -+++ b/include/uapi/linux/inet_diag.h -@@ -229,6 +229,29 @@ struct tcp_bbr_info { - __u32 bbr_min_rtt; /* min-filtered RTT in uSec */ - __u32 bbr_pacing_gain; /* pacing gain shifted left 8 bits */ - __u32 bbr_cwnd_gain; /* cwnd gain shifted left 8 bits */ -+ __u32 bbr_bw_hi_lsb; /* lower 32 bits of bw_hi */ -+ __u32 bbr_bw_hi_msb; /* upper 32 bits of bw_hi */ -+ __u32 bbr_bw_lo_lsb; /* lower 32 bits of bw_lo */ -+ __u32 bbr_bw_lo_msb; /* upper 32 bits of bw_lo */ -+ __u8 bbr_mode; /* current bbr_mode in state machine */ -+ __u8 bbr_phase; /* current state machine phase */ -+ __u8 unused1; /* alignment padding; not used yet */ -+ __u8 bbr_version; /* BBR algorithm version */ -+ __u32 bbr_inflight_lo; /* lower short-term data volume bound */ -+ __u32 bbr_inflight_hi; /* higher long-term data volume bound */ -+ __u32 bbr_extra_acked; /* max excess packets ACKed in epoch */ -+}; -+ -+/* TCP BBR congestion control bbr_phase as reported in netlink/ss stats. */ -+enum tcp_bbr_phase { -+ BBR_PHASE_INVALID = 0, -+ BBR_PHASE_STARTUP = 1, -+ BBR_PHASE_DRAIN = 2, -+ BBR_PHASE_PROBE_RTT = 3, -+ BBR_PHASE_PROBE_BW_UP = 4, -+ BBR_PHASE_PROBE_BW_DOWN = 5, -+ BBR_PHASE_PROBE_BW_CRUISE = 6, -+ BBR_PHASE_PROBE_BW_REFILL = 7, - }; - - union tcp_cc_info { -diff --git a/include/uapi/linux/rtnetlink.h b/include/uapi/linux/rtnetlink.h -index 3b687d20c9ed..a7c30c243b54 100644 ---- a/include/uapi/linux/rtnetlink.h -+++ b/include/uapi/linux/rtnetlink.h -@@ -507,12 +507,14 @@ enum { - #define RTAX_FEATURE_TIMESTAMP (1 << 2) /* unused */ - #define RTAX_FEATURE_ALLFRAG (1 << 3) /* unused */ - #define RTAX_FEATURE_TCP_USEC_TS (1 << 4) -+#define RTAX_FEATURE_ECN_LOW (1 << 5) - - #define RTAX_FEATURE_MASK (RTAX_FEATURE_ECN | \ - RTAX_FEATURE_SACK | \ - RTAX_FEATURE_TIMESTAMP | \ - RTAX_FEATURE_ALLFRAG | \ -- RTAX_FEATURE_TCP_USEC_TS) -+ RTAX_FEATURE_TCP_USEC_TS | \ -+ RTAX_FEATURE_ECN_LOW) - - struct rta_session { - __u8 proto; -diff --git a/include/uapi/linux/tcp.h b/include/uapi/linux/tcp.h -index dbf896f3146c..4702cd2f1ffc 100644 ---- a/include/uapi/linux/tcp.h -+++ b/include/uapi/linux/tcp.h -@@ -178,6 +178,7 @@ enum tcp_fastopen_client_fail { - #define TCPI_OPT_ECN_SEEN 16 /* we received at least one packet with ECT */ - #define TCPI_OPT_SYN_DATA 32 /* SYN-ACK acked data in SYN sent or rcvd */ - #define TCPI_OPT_USEC_TS 64 /* usec timestamps */ -+#define TCPI_OPT_ECN_LOW 128 /* Low-latency ECN configured at init */ - - /* - * Sender's congestion state indicating normal or abnormal situations -diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig -index 8e94ed7c56a0..50dc9970cad2 100644 ---- a/net/ipv4/Kconfig -+++ b/net/ipv4/Kconfig -@@ -668,15 +668,18 @@ config TCP_CONG_BBR - default n - help - -- BBR (Bottleneck Bandwidth and RTT) TCP congestion control aims to -- maximize network utilization and minimize queues. It builds an explicit -- model of the bottleneck delivery rate and path round-trip propagation -- delay. It tolerates packet loss and delay unrelated to congestion. It -- can operate over LAN, WAN, cellular, wifi, or cable modem links. It can -- coexist with flows that use loss-based congestion control, and can -- operate with shallow buffers, deep buffers, bufferbloat, policers, or -- AQM schemes that do not provide a delay signal. It requires the fq -- ("Fair Queue") pacing packet scheduler. -+ BBR (Bottleneck Bandwidth and RTT) TCP congestion control is a -+ model-based congestion control algorithm that aims to maximize -+ network utilization, keep queues and retransmit rates low, and to be -+ able to coexist with Reno/CUBIC in common scenarios. It builds an -+ explicit model of the network path. It tolerates a targeted degree -+ of random packet loss and delay. It can operate over LAN, WAN, -+ cellular, wifi, or cable modem links, and can use shallow-threshold -+ ECN signals. It can coexist to some degree with flows that use -+ loss-based congestion control, and can operate with shallow buffers, -+ deep buffers, bufferbloat, policers, or AQM schemes that do not -+ provide a delay signal. It requires pacing, using either TCP internal -+ pacing or the fq ("Fair Queue") pacing packet scheduler. - - choice - prompt "Default TCP congestion control" -diff --git a/net/ipv4/bpf_tcp_ca.c b/net/ipv4/bpf_tcp_ca.c -index 18227757ec0c..f180befc28bd 100644 ---- a/net/ipv4/bpf_tcp_ca.c -+++ b/net/ipv4/bpf_tcp_ca.c -@@ -305,11 +305,15 @@ static void bpf_tcp_ca_pkts_acked(struct sock *sk, const struct ack_sample *samp - { - } - --static u32 bpf_tcp_ca_min_tso_segs(struct sock *sk) -+static u32 bpf_tcp_ca_tso_segs(struct sock *sk, unsigned int mss_now) - { - return 0; - } - -+static void bpf_tcp_ca_skb_marked_lost(struct sock *sk, const struct sk_buff *skb) -+{ -+} -+ - static void bpf_tcp_ca_cong_control(struct sock *sk, u32 ack, int flag, - const struct rate_sample *rs) - { -@@ -340,7 +344,8 @@ static struct tcp_congestion_ops __bpf_ops_tcp_congestion_ops = { - .cwnd_event = bpf_tcp_ca_cwnd_event, - .in_ack_event = bpf_tcp_ca_in_ack_event, - .pkts_acked = bpf_tcp_ca_pkts_acked, -- .min_tso_segs = bpf_tcp_ca_min_tso_segs, -+ .tso_segs = bpf_tcp_ca_tso_segs, -+ .skb_marked_lost = bpf_tcp_ca_skb_marked_lost, - .cong_control = bpf_tcp_ca_cong_control, - .undo_cwnd = bpf_tcp_ca_undo_cwnd, - .sndbuf_expand = bpf_tcp_ca_sndbuf_expand, -diff --git a/net/ipv4/tcp.c b/net/ipv4/tcp.c -index ec6911034138..df7731a30198 100644 ---- a/net/ipv4/tcp.c -+++ b/net/ipv4/tcp.c -@@ -3120,6 +3120,7 @@ int tcp_disconnect(struct sock *sk, int flags) - tp->rx_opt.dsack = 0; - tp->rx_opt.num_sacks = 0; - tp->rcv_ooopack = 0; -+ tp->fast_ack_mode = 0; - - - /* Clean up fastopen related fields */ -@@ -3846,6 +3847,8 @@ void tcp_get_info(struct sock *sk, struct tcp_info *info) - info->tcpi_options |= TCPI_OPT_ECN; - if (tp->ecn_flags & TCP_ECN_SEEN) - info->tcpi_options |= TCPI_OPT_ECN_SEEN; -+ if (tp->ecn_flags & TCP_ECN_LOW) -+ info->tcpi_options |= TCPI_OPT_ECN_LOW; - if (tp->syn_data_acked) - info->tcpi_options |= TCPI_OPT_SYN_DATA; - if (tp->tcp_usec_ts) -diff --git a/net/ipv4/tcp_bbr.c b/net/ipv4/tcp_bbr.c -index 760941e55153..a180fa648d5e 100644 ---- a/net/ipv4/tcp_bbr.c -+++ b/net/ipv4/tcp_bbr.c -@@ -1,18 +1,19 @@ --/* Bottleneck Bandwidth and RTT (BBR) congestion control -+/* BBR (Bottleneck Bandwidth and RTT) congestion control - * -- * BBR congestion control computes the sending rate based on the delivery -- * rate (throughput) estimated from ACKs. In a nutshell: -+ * BBR is a model-based congestion control algorithm that aims for low queues, -+ * low loss, and (bounded) Reno/CUBIC coexistence. To maintain a model of the -+ * network path, it uses measurements of bandwidth and RTT, as well as (if they -+ * occur) packet loss and/or shallow-threshold ECN signals. Note that although -+ * it can use ECN or loss signals explicitly, it does not require either; it -+ * can bound its in-flight data based on its estimate of the BDP. - * -- * On each ACK, update our model of the network path: -- * bottleneck_bandwidth = windowed_max(delivered / elapsed, 10 round trips) -- * min_rtt = windowed_min(rtt, 10 seconds) -- * pacing_rate = pacing_gain * bottleneck_bandwidth -- * cwnd = max(cwnd_gain * bottleneck_bandwidth * min_rtt, 4) -- * -- * The core algorithm does not react directly to packet losses or delays, -- * although BBR may adjust the size of next send per ACK when loss is -- * observed, or adjust the sending rate if it estimates there is a -- * traffic policer, in order to keep the drop rate reasonable. -+ * The model has both higher and lower bounds for the operating range: -+ * lo: bw_lo, inflight_lo: conservative short-term lower bound -+ * hi: bw_hi, inflight_hi: robust long-term upper bound -+ * The bandwidth-probing time scale is (a) extended dynamically based on -+ * estimated BDP to improve coexistence with Reno/CUBIC; (b) bounded by -+ * an interactive wall-clock time-scale to be more scalable and responsive -+ * than Reno and CUBIC. - * - * Here is a state transition diagram for BBR: - * -@@ -65,6 +66,13 @@ - #include <linux/random.h> - #include <linux/win_minmax.h> - -+#include <trace/events/tcp.h> -+#include "tcp_dctcp.h" -+ -+#define BBR_VERSION 3 -+ -+#define bbr_param(sk,name) (bbr_ ## name) -+ - /* Scale factor for rate in pkt/uSec unit to avoid truncation in bandwidth - * estimation. The rate unit ~= (1500 bytes / 1 usec / 2^24) ~= 715 bps. - * This handles bandwidths from 0.06pps (715bps) to 256Mpps (3Tbps) in a u32. -@@ -85,36 +93,41 @@ enum bbr_mode { - BBR_PROBE_RTT, /* cut inflight to min to probe min_rtt */ - }; - -+/* How does the incoming ACK stream relate to our bandwidth probing? */ -+enum bbr_ack_phase { -+ BBR_ACKS_INIT, /* not probing; not getting probe feedback */ -+ BBR_ACKS_REFILLING, /* sending at est. bw to fill pipe */ -+ BBR_ACKS_PROBE_STARTING, /* inflight rising to probe bw */ -+ BBR_ACKS_PROBE_FEEDBACK, /* getting feedback from bw probing */ -+ BBR_ACKS_PROBE_STOPPING, /* stopped probing; still getting feedback */ -+}; -+ - /* BBR congestion control block */ - struct bbr { - u32 min_rtt_us; /* min RTT in min_rtt_win_sec window */ - u32 min_rtt_stamp; /* timestamp of min_rtt_us */ - u32 probe_rtt_done_stamp; /* end time for BBR_PROBE_RTT mode */ -- struct minmax bw; /* Max recent delivery rate in pkts/uS << 24 */ -- u32 rtt_cnt; /* count of packet-timed rounds elapsed */ -+ u32 probe_rtt_min_us; /* min RTT in probe_rtt_win_ms win */ -+ u32 probe_rtt_min_stamp; /* timestamp of probe_rtt_min_us*/ - u32 next_rtt_delivered; /* scb->tx.delivered at end of round */ - u64 cycle_mstamp; /* time of this cycle phase start */ -- u32 mode:3, /* current bbr_mode in state machine */ -+ u32 mode:2, /* current bbr_mode in state machine */ - prev_ca_state:3, /* CA state on previous ACK */ -- packet_conservation:1, /* use packet conservation? */ - round_start:1, /* start of packet-timed tx->ack round? */ -+ ce_state:1, /* If most recent data has CE bit set */ -+ bw_probe_up_rounds:5, /* cwnd-limited rounds in PROBE_UP */ -+ try_fast_path:1, /* can we take fast path? */ - idle_restart:1, /* restarting after idle? */ - probe_rtt_round_done:1, /* a BBR_PROBE_RTT round at 4 pkts? */ -- unused:13, -- lt_is_sampling:1, /* taking long-term ("LT") samples now? */ -- lt_rtt_cnt:7, /* round trips in long-term interval */ -- lt_use_bw:1; /* use lt_bw as our bw estimate? */ -- u32 lt_bw; /* LT est delivery rate in pkts/uS << 24 */ -- u32 lt_last_delivered; /* LT intvl start: tp->delivered */ -- u32 lt_last_stamp; /* LT intvl start: tp->delivered_mstamp */ -- u32 lt_last_lost; /* LT intvl start: tp->lost */ -+ init_cwnd:7, /* initial cwnd */ -+ unused_1:10; - u32 pacing_gain:10, /* current gain for setting pacing rate */ - cwnd_gain:10, /* current gain for setting cwnd */ - full_bw_reached:1, /* reached full bw in Startup? */ - full_bw_cnt:2, /* number of rounds without large bw gains */ -- cycle_idx:3, /* current index in pacing_gain cycle array */ -+ cycle_idx:2, /* current index in pacing_gain cycle array */ - has_seen_rtt:1, /* have we seen an RTT sample yet? */ -- unused_b:5; -+ unused_2:6; - u32 prior_cwnd; /* prior cwnd upon entering loss recovery */ - u32 full_bw; /* recent bw, to estimate if pipe is full */ - -@@ -124,19 +137,67 @@ struct bbr { - u32 ack_epoch_acked:20, /* packets (S)ACKed in sampling epoch */ - extra_acked_win_rtts:5, /* age of extra_acked, in round trips */ - extra_acked_win_idx:1, /* current index in extra_acked array */ -- unused_c:6; -+ /* BBR v3 state: */ -+ full_bw_now:1, /* recently reached full bw plateau? */ -+ startup_ecn_rounds:2, /* consecutive hi ECN STARTUP rounds */ -+ loss_in_cycle:1, /* packet loss in this cycle? */ -+ ecn_in_cycle:1, /* ECN in this cycle? */ -+ unused_3:1; -+ u32 loss_round_delivered; /* scb->tx.delivered ending loss round */ -+ u32 undo_bw_lo; /* bw_lo before latest losses */ -+ u32 undo_inflight_lo; /* inflight_lo before latest losses */ -+ u32 undo_inflight_hi; /* inflight_hi before latest losses */ -+ u32 bw_latest; /* max delivered bw in last round trip */ -+ u32 bw_lo; /* lower bound on sending bandwidth */ -+ u32 bw_hi[2]; /* max recent measured bw sample */ -+ u32 inflight_latest; /* max delivered data in last round trip */ -+ u32 inflight_lo; /* lower bound of inflight data range */ -+ u32 inflight_hi; /* upper bound of inflight data range */ -+ u32 bw_probe_up_cnt; /* packets delivered per inflight_hi incr */ -+ u32 bw_probe_up_acks; /* packets (S)ACKed since inflight_hi incr */ -+ u32 probe_wait_us; /* PROBE_DOWN until next clock-driven probe */ -+ u32 prior_rcv_nxt; /* tp->rcv_nxt when CE state last changed */ -+ u32 ecn_eligible:1, /* sender can use ECN (RTT, handshake)? */ -+ ecn_alpha:9, /* EWMA delivered_ce/delivered; 0..256 */ -+ bw_probe_samples:1, /* rate samples reflect bw probing? */ -+ prev_probe_too_high:1, /* did last PROBE_UP go too high? */ -+ stopped_risky_probe:1, /* last PROBE_UP stopped due to risk? */ -+ rounds_since_probe:8, /* packet-timed rounds since probed bw */ -+ loss_round_start:1, /* loss_round_delivered round trip? */ -+ loss_in_round:1, /* loss marked in this round trip? */ -+ ecn_in_round:1, /* ECN marked in this round trip? */ -+ ack_phase:3, /* bbr_ack_phase: meaning of ACKs */ -+ loss_events_in_round:4,/* losses in STARTUP round */ -+ initialized:1; /* has bbr_init() been called? */ -+ u32 alpha_last_delivered; /* tp->delivered at alpha update */ -+ u32 alpha_last_delivered_ce; /* tp->delivered_ce at alpha update */ -+ -+ u8 unused_4; /* to preserve alignment */ -+ struct tcp_plb_state plb; - }; - --#define CYCLE_LEN 8 /* number of phases in a pacing gain cycle */ -+struct bbr_context { -+ u32 sample_bw; -+}; - --/* Window length of bw filter (in rounds): */ --static const int bbr_bw_rtts = CYCLE_LEN + 2; - /* Window length of min_rtt filter (in sec): */ - static const u32 bbr_min_rtt_win_sec = 10; - /* Minimum time (in ms) spent at bbr_cwnd_min_target in BBR_PROBE_RTT mode: */ - static const u32 bbr_probe_rtt_mode_ms = 200; --/* Skip TSO below the following bandwidth (bits/sec): */ --static const int bbr_min_tso_rate = 1200000; -+/* Window length of probe_rtt_min_us filter (in ms), and consequently the -+ * typical interval between PROBE_RTT mode entries. The default is 5000ms. -+ * Note that bbr_probe_rtt_win_ms must be <= bbr_min_rtt_win_sec * MSEC_PER_SEC -+ */ -+static const u32 bbr_probe_rtt_win_ms = 5000; -+/* Proportion of cwnd to estimated BDP in PROBE_RTT, in units of BBR_UNIT: */ -+static const u32 bbr_probe_rtt_cwnd_gain = BBR_UNIT * 1 / 2; -+ -+/* Use min_rtt to help adapt TSO burst size, with smaller min_rtt resulting -+ * in bigger TSO bursts. We cut the RTT-based allowance in half -+ * for every 2^9 usec (aka 512 us) of RTT, so that the RTT-based allowance -+ * is below 1500 bytes after 6 * ~500 usec = 3ms. -+ */ -+static const u32 bbr_tso_rtt_shift = 9; - - /* Pace at ~1% below estimated bw, on average, to reduce queue at bottleneck. - * In order to help drive the network toward lower queues and low latency while -@@ -146,13 +207,15 @@ static const int bbr_min_tso_rate = 1200000; - */ - static const int bbr_pacing_margin_percent = 1; - --/* We use a high_gain value of 2/ln(2) because it's the smallest pacing gain -+/* We use a startup_pacing_gain of 4*ln(2) because it's the smallest value - * that will allow a smoothly increasing pacing rate that will double each RTT - * and send the same number of packets per RTT that an un-paced, slow-starting - * Reno or CUBIC flow would: - */ --static const int bbr_high_gain = BBR_UNIT * 2885 / 1000 + 1; --/* The pacing gain of 1/high_gain in BBR_DRAIN is calculated to typically drain -+static const int bbr_startup_pacing_gain = BBR_UNIT * 277 / 100 + 1; -+/* The gain for deriving startup cwnd: */ -+static const int bbr_startup_cwnd_gain = BBR_UNIT * 2; -+/* The pacing gain in BBR_DRAIN is calculated to typically drain - * the queue created in BBR_STARTUP in a single round: - */ - static const int bbr_drain_gain = BBR_UNIT * 1000 / 2885; -@@ -160,13 +223,17 @@ static const int bbr_drain_gain = BBR_UNIT * 1000 / 2885; - static const int bbr_cwnd_gain = BBR_UNIT * 2; - /* The pacing_gain values for the PROBE_BW gain cycle, to discover/share bw: */ - static const int bbr_pacing_gain[] = { -- BBR_UNIT * 5 / 4, /* probe for more available bw */ -- BBR_UNIT * 3 / 4, /* drain queue and/or yield bw to other flows */ -- BBR_UNIT, BBR_UNIT, BBR_UNIT, /* cruise at 1.0*bw to utilize pipe, */ -- BBR_UNIT, BBR_UNIT, BBR_UNIT /* without creating excess queue... */ -+ BBR_UNIT * 5 / 4, /* UP: probe for more available bw */ -+ BBR_UNIT * 91 / 100, /* DOWN: drain queue and/or yield bw */ -+ BBR_UNIT, /* CRUISE: try to use pipe w/ some headroom */ -+ BBR_UNIT, /* REFILL: refill pipe to estimated 100% */ -+}; -+enum bbr_pacing_gain_phase { -+ BBR_BW_PROBE_UP = 0, /* push up inflight to probe for bw/vol */ -+ BBR_BW_PROBE_DOWN = 1, /* drain excess inflight from the queue */ -+ BBR_BW_PROBE_CRUISE = 2, /* use pipe, w/ headroom in queue/pipe */ -+ BBR_BW_PROBE_REFILL = 3, /* v2: refill the pipe again to 100% */ - }; --/* Randomize the starting gain cycling phase over N phases: */ --static const u32 bbr_cycle_rand = 7; - - /* Try to keep at least this many packets in flight, if things go smoothly. For - * smooth functioning, a sliding window protocol ACKing every other packet -@@ -174,24 +241,12 @@ static const u32 bbr_cycle_rand = 7; - */ - static const u32 bbr_cwnd_min_target = 4; - --/* To estimate if BBR_STARTUP mode (i.e. high_gain) has filled pipe... */ -+/* To estimate if BBR_STARTUP or BBR_BW_PROBE_UP has filled pipe... */ - /* If bw has increased significantly (1.25x), there may be more bw available: */ - static const u32 bbr_full_bw_thresh = BBR_UNIT * 5 / 4; - /* But after 3 rounds w/o significant bw growth, estimate pipe is full: */ - static const u32 bbr_full_bw_cnt = 3; - --/* "long-term" ("LT") bandwidth estimator parameters... */ --/* The minimum number of rounds in an LT bw sampling interval: */ --static const u32 bbr_lt_intvl_min_rtts = 4; --/* If lost/delivered ratio > 20%, interval is "lossy" and we may be policed: */ --static const u32 bbr_lt_loss_thresh = 50; --/* If 2 intervals have a bw ratio <= 1/8, their bw is "consistent": */ --static const u32 bbr_lt_bw_ratio = BBR_UNIT / 8; --/* If 2 intervals have a bw diff <= 4 Kbit/sec their bw is "consistent": */ --static const u32 bbr_lt_bw_diff = 4000 / 8; --/* If we estimate we're policed, use lt_bw for this many round trips: */ --static const u32 bbr_lt_bw_max_rtts = 48; -- - /* Gain factor for adding extra_acked to target cwnd: */ - static const int bbr_extra_acked_gain = BBR_UNIT; - /* Window length of extra_acked window. */ -@@ -201,8 +256,121 @@ static const u32 bbr_ack_epoch_acked_reset_thresh = 1U << 20; - /* Time period for clamping cwnd increment due to ack aggregation */ - static const u32 bbr_extra_acked_max_us = 100 * 1000; - -+/* Flags to control BBR ECN-related behavior... */ -+ -+/* Ensure ACKs only ACK packets with consistent ECN CE status? */ -+static const bool bbr_precise_ece_ack = true; -+ -+/* Max RTT (in usec) at which to use sender-side ECN logic. -+ * Disabled when 0 (ECN allowed at any RTT). -+ */ -+static const u32 bbr_ecn_max_rtt_us = 5000; -+ -+/* On losses, scale down inflight and pacing rate by beta scaled by BBR_SCALE. -+ * No loss response when 0. -+ */ -+static const u32 bbr_beta = BBR_UNIT * 30 / 100; -+ -+/* Gain factor for ECN mark ratio samples, scaled by BBR_SCALE (1/16 = 6.25%) */ -+static const u32 bbr_ecn_alpha_gain = BBR_UNIT * 1 / 16; -+ -+/* The initial value for ecn_alpha; 1.0 allows a flow to respond quickly -+ * to congestion if the bottleneck is congested when the flow starts up. -+ */ -+static const u32 bbr_ecn_alpha_init = BBR_UNIT; -+ -+/* On ECN, cut inflight_lo to (1 - ecn_factor * ecn_alpha) scaled by BBR_SCALE. -+ * No ECN based bounding when 0. -+ */ -+static const u32 bbr_ecn_factor = BBR_UNIT * 1 / 3; /* 1/3 = 33% */ -+ -+/* Estimate bw probing has gone too far if CE ratio exceeds this threshold. -+ * Scaled by BBR_SCALE. Disabled when 0. -+ */ -+static const u32 bbr_ecn_thresh = BBR_UNIT * 1 / 2; /* 1/2 = 50% */ -+ -+/* If non-zero, if in a cycle with no losses but some ECN marks, after ECN -+ * clears then make the first round's increment to inflight_hi the following -+ * fraction of inflight_hi. -+ */ -+static const u32 bbr_ecn_reprobe_gain = BBR_UNIT * 1 / 2; -+ -+/* Estimate bw probing has gone too far if loss rate exceeds this level. */ -+static const u32 bbr_loss_thresh = BBR_UNIT * 2 / 100; /* 2% loss */ -+ -+/* Slow down for a packet loss recovered by TLP? */ -+static const bool bbr_loss_probe_recovery = true; -+ -+/* Exit STARTUP if number of loss marking events in a Recovery round is >= N, -+ * and loss rate is higher than bbr_loss_thresh. -+ * Disabled if 0. -+ */ -+static const u32 bbr_full_loss_cnt = 6; -+ -+/* Exit STARTUP if number of round trips with ECN mark rate above ecn_thresh -+ * meets this count. -+ */ -+static const u32 bbr_full_ecn_cnt = 2; -+ -+/* Fraction of unutilized headroom to try to leave in path upon high loss. */ -+static const u32 bbr_inflight_headroom = BBR_UNIT * 15 / 100; -+ -+/* How much do we increase cwnd_gain when probing for bandwidth in -+ * BBR_BW_PROBE_UP? This specifies the increment in units of -+ * BBR_UNIT/4. The default is 1, meaning 0.25. -+ * The min value is 0 (meaning 0.0); max is 3 (meaning 0.75). -+ */ -+static const u32 bbr_bw_probe_cwnd_gain = 1; -+ -+/* Max number of packet-timed rounds to wait before probing for bandwidth. If -+ * we want to tolerate 1% random loss per round, and not have this cut our -+ * inflight too much, we must probe for bw periodically on roughly this scale. -+ * If low, limits Reno/CUBIC coexistence; if high, limits loss tolerance. -+ * We aim to be fair with Reno/CUBIC up to a BDP of at least: -+ * BDP = 25Mbps * .030sec /(1514bytes) = 61.9 packets -+ */ -+static const u32 bbr_bw_probe_max_rounds = 63; -+ -+/* Max amount of randomness to inject in round counting for Reno-coexistence. -+ */ -+static const u32 bbr_bw_probe_rand_rounds = 2; -+ -+/* Use BBR-native probe time scale starting at this many usec. -+ * We aim to be fair with Reno/CUBIC up to an inter-loss time epoch of at least: -+ * BDP*RTT = 25Mbps * .030sec /(1514bytes) * 0.030sec = 1.9 secs -+ */ -+static const u32 bbr_bw_probe_base_us = 2 * USEC_PER_SEC; /* 2 secs */ -+ -+/* Use BBR-native probes spread over this many usec: */ -+static const u32 bbr_bw_probe_rand_us = 1 * USEC_PER_SEC; /* 1 secs */ -+ -+/* Use fast path if app-limited, no loss/ECN, and target cwnd was reached? */ -+static const bool bbr_fast_path = true; -+ -+/* Use fast ack mode? */ -+static const bool bbr_fast_ack_mode = true; -+ -+static u32 bbr_max_bw(const struct sock *sk); -+static u32 bbr_bw(const struct sock *sk); -+static void bbr_exit_probe_rtt(struct sock *sk); -+static void bbr_reset_congestion_signals(struct sock *sk); -+static void bbr_run_loss_probe_recovery(struct sock *sk); -+ - static void bbr_check_probe_rtt_done(struct sock *sk); - -+/* This connection can use ECN if both endpoints have signaled ECN support in -+ * the handshake and the per-route settings indicated this is a -+ * shallow-threshold ECN environment, meaning both: -+ * (a) ECN CE marks indicate low-latency/shallow-threshold congestion, and -+ * (b) TCP endpoints provide precise ACKs that only ACK data segments -+ * with consistent ECN CE status -+ */ -+static bool bbr_can_use_ecn(const struct sock *sk) -+{ -+ return (tcp_sk(sk)->ecn_flags & TCP_ECN_OK) && -+ (tcp_sk(sk)->ecn_flags & TCP_ECN_LOW); -+} -+ - /* Do we estimate that STARTUP filled the pipe? */ - static bool bbr_full_bw_reached(const struct sock *sk) - { -@@ -214,17 +382,17 @@ static bool bbr_full_bw_reached(const struct sock *sk) - /* Return the windowed max recent bandwidth sample, in pkts/uS << BW_SCALE. */ - static u32 bbr_max_bw(const struct sock *sk) - { -- struct bbr *bbr = inet_csk_ca(sk); -+ const struct bbr *bbr = inet_csk_ca(sk); - -- return minmax_get(&bbr->bw); -+ return max(bbr->bw_hi[0], bbr->bw_hi[1]); - } - - /* Return the estimated bandwidth of the path, in pkts/uS << BW_SCALE. */ - static u32 bbr_bw(const struct sock *sk) - { -- struct bbr *bbr = inet_csk_ca(sk); -+ const struct bbr *bbr = inet_csk_ca(sk); - -- return bbr->lt_use_bw ? bbr->lt_bw : bbr_max_bw(sk); -+ return min(bbr_max_bw(sk), bbr->bw_lo); - } - - /* Return maximum extra acked in past k-2k round trips, -@@ -241,15 +409,23 @@ static u16 bbr_extra_acked(const struct sock *sk) - * The order here is chosen carefully to avoid overflow of u64. This should - * work for input rates of up to 2.9Tbit/sec and gain of 2.89x. - */ --static u64 bbr_rate_bytes_per_sec(struct sock *sk, u64 rate, int gain) -+static u64 bbr_rate_bytes_per_sec(struct sock *sk, u64 rate, int gain, -+ int margin) - { - unsigned int mss = tcp_sk(sk)->mss_cache; - - rate *= mss; - rate *= gain; - rate >>= BBR_SCALE; -- rate *= USEC_PER_SEC / 100 * (100 - bbr_pacing_margin_percent); -- return rate >> BW_SCALE; -+ rate *= USEC_PER_SEC / 100 * (100 - margin); -+ rate >>= BW_SCALE; -+ rate = max(rate, 1ULL); -+ return rate; -+} -+ -+static u64 bbr_bw_bytes_per_sec(struct sock *sk, u64 rate) -+{ -+ return bbr_rate_bytes_per_sec(sk, rate, BBR_UNIT, 0); - } - - /* Convert a BBR bw and gain factor to a pacing rate in bytes per second. */ -@@ -257,12 +433,13 @@ static unsigned long bbr_bw_to_pacing_rate(struct sock *sk, u32 bw, int gain) - { - u64 rate = bw; - -- rate = bbr_rate_bytes_per_sec(sk, rate, gain); -+ rate = bbr_rate_bytes_per_sec(sk, rate, gain, -+ bbr_pacing_margin_percent); - rate = min_t(u64, rate, READ_ONCE(sk->sk_max_pacing_rate)); - return rate; - } - --/* Initialize pacing rate to: high_gain * init_cwnd / RTT. */ -+/* Initialize pacing rate to: startup_pacing_gain * init_cwnd / RTT. */ - static void bbr_init_pacing_rate_from_rtt(struct sock *sk) - { - struct tcp_sock *tp = tcp_sk(sk); -@@ -279,7 +456,7 @@ static void bbr_init_pacing_rate_from_rtt(struct sock *sk) - bw = (u64)tcp_snd_cwnd(tp) * BW_UNIT; - do_div(bw, rtt_us); - WRITE_ONCE(sk->sk_pacing_rate, -- bbr_bw_to_pacing_rate(sk, bw, bbr_high_gain)); -+ bbr_bw_to_pacing_rate(sk, bw, bbr_param(sk, startup_pacing_gain))); - } - - /* Pace using current bw estimate and a gain factor. */ -@@ -295,26 +472,48 @@ static void bbr_set_pacing_rate(struct sock *sk, u32 bw, int gain) - WRITE_ONCE(sk->sk_pacing_rate, rate); - } - --/* override sysctl_tcp_min_tso_segs */ --__bpf_kfunc static u32 bbr_min_tso_segs(struct sock *sk) -+/* Return the number of segments BBR would like in a TSO/GSO skb, given a -+ * particular max gso size as a constraint. TODO: make this simpler and more -+ * consistent by switching bbr to just call tcp_tso_autosize(). -+ */ -+static u32 bbr_tso_segs_generic(struct sock *sk, unsigned int mss_now, -+ u32 gso_max_size) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 segs, r; -+ u64 bytes; -+ -+ /* Budget a TSO/GSO burst size allowance based on bw (pacing_rate). */ -+ bytes = READ_ONCE(sk->sk_pacing_rate) >> READ_ONCE(sk->sk_pacing_shift); -+ -+ /* Budget a TSO/GSO burst size allowance based on min_rtt. For every -+ * K = 2^tso_rtt_shift microseconds of min_rtt, halve the burst. -+ * The min_rtt-based burst allowance is: 64 KBytes / 2^(min_rtt/K) -+ */ -+ if (bbr_param(sk, tso_rtt_shift)) { -+ r = bbr->min_rtt_us >> bbr_param(sk, tso_rtt_shift); -+ if (r < BITS_PER_TYPE(u32)) /* prevent undefined behavior */ -+ bytes += GSO_LEGACY_MAX_SIZE >> r; -+ } -+ -+ bytes = min_t(u32, bytes, gso_max_size - 1 - MAX_TCP_HEADER); -+ segs = max_t(u32, bytes / mss_now, -+ sock_net(sk)->ipv4.sysctl_tcp_min_tso_segs); -+ return segs; -+} -+ -+/* Custom tcp_tso_autosize() for BBR, used at transmit time to cap skb size. */ -+__bpf_kfunc static u32 bbr_tso_segs(struct sock *sk, unsigned int mss_now) - { -- return READ_ONCE(sk->sk_pacing_rate) < (bbr_min_tso_rate >> 3) ? 1 : 2; -+ return bbr_tso_segs_generic(sk, mss_now, sk->sk_gso_max_size); - } - -+/* Like bbr_tso_segs(), using mss_cache, ignoring driver's sk_gso_max_size. */ - static u32 bbr_tso_segs_goal(struct sock *sk) - { - struct tcp_sock *tp = tcp_sk(sk); -- u32 segs, bytes; -- -- /* Sort of tcp_tso_autosize() but ignoring -- * driver provided sk_gso_max_size. -- */ -- bytes = min_t(unsigned long, -- READ_ONCE(sk->sk_pacing_rate) >> READ_ONCE(sk->sk_pacing_shift), -- GSO_LEGACY_MAX_SIZE - 1 - MAX_TCP_HEADER); -- segs = max_t(u32, bytes / tp->mss_cache, bbr_min_tso_segs(sk)); - -- return min(segs, 0x7FU); -+ return bbr_tso_segs_generic(sk, tp->mss_cache, GSO_LEGACY_MAX_SIZE); - } - - /* Save "last known good" cwnd so we can restore it after losses or PROBE_RTT */ -@@ -334,7 +533,9 @@ __bpf_kfunc static void bbr_cwnd_event(struct sock *sk, enum tcp_ca_event event) - struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); - -- if (event == CA_EVENT_TX_START && tp->app_limited) { -+ if (event == CA_EVENT_TX_START) { -+ if (!tp->app_limited) -+ return; - bbr->idle_restart = 1; - bbr->ack_epoch_mstamp = tp->tcp_mstamp; - bbr->ack_epoch_acked = 0; -@@ -345,6 +546,16 @@ __bpf_kfunc static void bbr_cwnd_event(struct sock *sk, enum tcp_ca_event event) - bbr_set_pacing_rate(sk, bbr_bw(sk), BBR_UNIT); - else if (bbr->mode == BBR_PROBE_RTT) - bbr_check_probe_rtt_done(sk); -+ } else if ((event == CA_EVENT_ECN_IS_CE || -+ event == CA_EVENT_ECN_NO_CE) && -+ bbr_can_use_ecn(sk) && -+ bbr_param(sk, precise_ece_ack)) { -+ u32 state = bbr->ce_state; -+ dctcp_ece_ack_update(sk, event, &bbr->prior_rcv_nxt, &state); -+ bbr->ce_state = state; -+ } else if (event == CA_EVENT_TLP_RECOVERY && -+ bbr_param(sk, loss_probe_recovery)) { -+ bbr_run_loss_probe_recovery(sk); - } - } - -@@ -367,10 +578,10 @@ static u32 bbr_bdp(struct sock *sk, u32 bw, int gain) - * default. This should only happen when the connection is not using TCP - * timestamps and has retransmitted all of the SYN/SYNACK/data packets - * ACKed so far. In this case, an RTO can cut cwnd to 1, in which -- * case we need to slow-start up toward something safe: TCP_INIT_CWND. -+ * case we need to slow-start up toward something safe: initial cwnd. - */ - if (unlikely(bbr->min_rtt_us == ~0U)) /* no valid RTT samples yet? */ -- return TCP_INIT_CWND; /* be safe: cap at default initial cwnd*/ -+ return bbr->init_cwnd; /* be safe: cap at initial cwnd */ - - w = (u64)bw * bbr->min_rtt_us; - -@@ -387,23 +598,23 @@ static u32 bbr_bdp(struct sock *sk, u32 bw, int gain) - * - one skb in sending host Qdisc, - * - one skb in sending host TSO/GSO engine - * - one skb being received by receiver host LRO/GRO/delayed-ACK engine -- * Don't worry, at low rates (bbr_min_tso_rate) this won't bloat cwnd because -- * in such cases tso_segs_goal is 1. The minimum cwnd is 4 packets, -+ * Don't worry, at low rates this won't bloat cwnd because -+ * in such cases tso_segs_goal is small. The minimum cwnd is 4 packets, - * which allows 2 outstanding 2-packet sequences, to try to keep pipe - * full even with ACK-every-other-packet delayed ACKs. - */ - static u32 bbr_quantization_budget(struct sock *sk, u32 cwnd) - { - struct bbr *bbr = inet_csk_ca(sk); -+ u32 tso_segs_goal; - -- /* Allow enough full-sized skbs in flight to utilize end systems. */ -- cwnd += 3 * bbr_tso_segs_goal(sk); -- -- /* Reduce delayed ACKs by rounding up cwnd to the next even number. */ -- cwnd = (cwnd + 1) & ~1U; -+ tso_segs_goal = 3 * bbr_tso_segs_goal(sk); - -+ /* Allow enough full-sized skbs in flight to utilize end systems. */ -+ cwnd = max_t(u32, cwnd, tso_segs_goal); -+ cwnd = max_t(u32, cwnd, bbr_param(sk, cwnd_min_target)); - /* Ensure gain cycling gets inflight above BDP even for small BDPs. */ -- if (bbr->mode == BBR_PROBE_BW && bbr->cycle_idx == 0) -+ if (bbr->mode == BBR_PROBE_BW && bbr->cycle_idx == BBR_BW_PROBE_UP) - cwnd += 2; - - return cwnd; -@@ -458,10 +669,10 @@ static u32 bbr_ack_aggregation_cwnd(struct sock *sk) - { - u32 max_aggr_cwnd, aggr_cwnd = 0; - -- if (bbr_extra_acked_gain && bbr_full_bw_reached(sk)) { -+ if (bbr_param(sk, extra_acked_gain)) { - max_aggr_cwnd = ((u64)bbr_bw(sk) * bbr_extra_acked_max_us) - / BW_UNIT; -- aggr_cwnd = (bbr_extra_acked_gain * bbr_extra_acked(sk)) -+ aggr_cwnd = (bbr_param(sk, extra_acked_gain) * bbr_extra_acked(sk)) - >> BBR_SCALE; - aggr_cwnd = min(aggr_cwnd, max_aggr_cwnd); - } -@@ -469,66 +680,27 @@ static u32 bbr_ack_aggregation_cwnd(struct sock *sk) - return aggr_cwnd; - } - --/* An optimization in BBR to reduce losses: On the first round of recovery, we -- * follow the packet conservation principle: send P packets per P packets acked. -- * After that, we slow-start and send at most 2*P packets per P packets acked. -- * After recovery finishes, or upon undo, we restore the cwnd we had when -- * recovery started (capped by the target cwnd based on estimated BDP). -- * -- * TODO(ycheng/ncardwell): implement a rate-based approach. -- */ --static bool bbr_set_cwnd_to_recover_or_restore( -- struct sock *sk, const struct rate_sample *rs, u32 acked, u32 *new_cwnd) -+/* Returns the cwnd for PROBE_RTT mode. */ -+static u32 bbr_probe_rtt_cwnd(struct sock *sk) - { -- struct tcp_sock *tp = tcp_sk(sk); -- struct bbr *bbr = inet_csk_ca(sk); -- u8 prev_state = bbr->prev_ca_state, state = inet_csk(sk)->icsk_ca_state; -- u32 cwnd = tcp_snd_cwnd(tp); -- -- /* An ACK for P pkts should release at most 2*P packets. We do this -- * in two steps. First, here we deduct the number of lost packets. -- * Then, in bbr_set_cwnd() we slow start up toward the target cwnd. -- */ -- if (rs->losses > 0) -- cwnd = max_t(s32, cwnd - rs->losses, 1); -- -- if (state == TCP_CA_Recovery && prev_state != TCP_CA_Recovery) { -- /* Starting 1st round of Recovery, so do packet conservation. */ -- bbr->packet_conservation = 1; -- bbr->next_rtt_delivered = tp->delivered; /* start round now */ -- /* Cut unused cwnd from app behavior, TSQ, or TSO deferral: */ -- cwnd = tcp_packets_in_flight(tp) + acked; -- } else if (prev_state >= TCP_CA_Recovery && state < TCP_CA_Recovery) { -- /* Exiting loss recovery; restore cwnd saved before recovery. */ -- cwnd = max(cwnd, bbr->prior_cwnd); -- bbr->packet_conservation = 0; -- } -- bbr->prev_ca_state = state; -- -- if (bbr->packet_conservation) { -- *new_cwnd = max(cwnd, tcp_packets_in_flight(tp) + acked); -- return true; /* yes, using packet conservation */ -- } -- *new_cwnd = cwnd; -- return false; -+ return max_t(u32, bbr_param(sk, cwnd_min_target), -+ bbr_bdp(sk, bbr_bw(sk), bbr_param(sk, probe_rtt_cwnd_gain))); - } - - /* Slow-start up toward target cwnd (if bw estimate is growing, or packet loss - * has drawn us down below target), or snap down to target if we're above it. - */ - static void bbr_set_cwnd(struct sock *sk, const struct rate_sample *rs, -- u32 acked, u32 bw, int gain) -+ u32 acked, u32 bw, int gain, u32 cwnd, -+ struct bbr_context *ctx) - { - struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); -- u32 cwnd = tcp_snd_cwnd(tp), target_cwnd = 0; -+ u32 target_cwnd = 0; - - if (!acked) - goto done; /* no packet fully ACKed; just apply caps */ - -- if (bbr_set_cwnd_to_recover_or_restore(sk, rs, acked, &cwnd)) -- goto done; -- - target_cwnd = bbr_bdp(sk, bw, gain); - - /* Increment the cwnd to account for excess ACKed data that seems -@@ -537,74 +709,26 @@ static void bbr_set_cwnd(struct sock *sk, const struct rate_sample *rs, - target_cwnd += bbr_ack_aggregation_cwnd(sk); - target_cwnd = bbr_quantization_budget(sk, target_cwnd); - -- /* If we're below target cwnd, slow start cwnd toward target cwnd. */ -- if (bbr_full_bw_reached(sk)) /* only cut cwnd if we filled the pipe */ -- cwnd = min(cwnd + acked, target_cwnd); -- else if (cwnd < target_cwnd || tp->delivered < TCP_INIT_CWND) -- cwnd = cwnd + acked; -- cwnd = max(cwnd, bbr_cwnd_min_target); -+ /* Update cwnd and enable fast path if cwnd reaches target_cwnd. */ -+ bbr->try_fast_path = 0; -+ if (bbr_full_bw_reached(sk)) { /* only cut cwnd if we filled the pipe */ -+ cwnd += acked; -+ if (cwnd >= target_cwnd) { -+ cwnd = target_cwnd; -+ bbr->try_fast_path = 1; -+ } -+ } else if (cwnd < target_cwnd || cwnd < 2 * bbr->init_cwnd) { -+ cwnd += acked; -+ } else { -+ bbr->try_fast_path = 1; -+ } - -+ cwnd = max_t(u32, cwnd, bbr_param(sk, cwnd_min_target)); - done: -- tcp_snd_cwnd_set(tp, min(cwnd, tp->snd_cwnd_clamp)); /* apply global cap */ -+ tcp_snd_cwnd_set(tp, min(cwnd, tp->snd_cwnd_clamp)); /* global cap */ - if (bbr->mode == BBR_PROBE_RTT) /* drain queue, refresh min_rtt */ -- tcp_snd_cwnd_set(tp, min(tcp_snd_cwnd(tp), bbr_cwnd_min_target)); --} -- --/* End cycle phase if it's time and/or we hit the phase's in-flight target. */ --static bool bbr_is_next_cycle_phase(struct sock *sk, -- const struct rate_sample *rs) --{ -- struct tcp_sock *tp = tcp_sk(sk); -- struct bbr *bbr = inet_csk_ca(sk); -- bool is_full_length = -- tcp_stamp_us_delta(tp->delivered_mstamp, bbr->cycle_mstamp) > -- bbr->min_rtt_us; -- u32 inflight, bw; -- -- /* The pacing_gain of 1.0 paces at the estimated bw to try to fully -- * use the pipe without increasing the queue. -- */ -- if (bbr->pacing_gain == BBR_UNIT) -- return is_full_length; /* just use wall clock time */ -- -- inflight = bbr_packets_in_net_at_edt(sk, rs->prior_in_flight); -- bw = bbr_max_bw(sk); -- -- /* A pacing_gain > 1.0 probes for bw by trying to raise inflight to at -- * least pacing_gain*BDP; this may take more than min_rtt if min_rtt is -- * small (e.g. on a LAN). We do not persist if packets are lost, since -- * a path with small buffers may not hold that much. -- */ -- if (bbr->pacing_gain > BBR_UNIT) -- return is_full_length && -- (rs->losses || /* perhaps pacing_gain*BDP won't fit */ -- inflight >= bbr_inflight(sk, bw, bbr->pacing_gain)); -- -- /* A pacing_gain < 1.0 tries to drain extra queue we added if bw -- * probing didn't find more bw. If inflight falls to match BDP then we -- * estimate queue is drained; persisting would underutilize the pipe. -- */ -- return is_full_length || -- inflight <= bbr_inflight(sk, bw, BBR_UNIT); --} -- --static void bbr_advance_cycle_phase(struct sock *sk) --{ -- struct tcp_sock *tp = tcp_sk(sk); -- struct bbr *bbr = inet_csk_ca(sk); -- -- bbr->cycle_idx = (bbr->cycle_idx + 1) & (CYCLE_LEN - 1); -- bbr->cycle_mstamp = tp->delivered_mstamp; --} -- --/* Gain cycling: cycle pacing gain to converge to fair share of available bw. */ --static void bbr_update_cycle_phase(struct sock *sk, -- const struct rate_sample *rs) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- -- if (bbr->mode == BBR_PROBE_BW && bbr_is_next_cycle_phase(sk, rs)) -- bbr_advance_cycle_phase(sk); -+ tcp_snd_cwnd_set(tp, min_t(u32, tcp_snd_cwnd(tp), -+ bbr_probe_rtt_cwnd(sk))); - } - - static void bbr_reset_startup_mode(struct sock *sk) -@@ -614,191 +738,49 @@ static void bbr_reset_startup_mode(struct sock *sk) - bbr->mode = BBR_STARTUP; - } - --static void bbr_reset_probe_bw_mode(struct sock *sk) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- -- bbr->mode = BBR_PROBE_BW; -- bbr->cycle_idx = CYCLE_LEN - 1 - get_random_u32_below(bbr_cycle_rand); -- bbr_advance_cycle_phase(sk); /* flip to next phase of gain cycle */ --} -- --static void bbr_reset_mode(struct sock *sk) --{ -- if (!bbr_full_bw_reached(sk)) -- bbr_reset_startup_mode(sk); -- else -- bbr_reset_probe_bw_mode(sk); --} -- --/* Start a new long-term sampling interval. */ --static void bbr_reset_lt_bw_sampling_interval(struct sock *sk) --{ -- struct tcp_sock *tp = tcp_sk(sk); -- struct bbr *bbr = inet_csk_ca(sk); -- -- bbr->lt_last_stamp = div_u64(tp->delivered_mstamp, USEC_PER_MSEC); -- bbr->lt_last_delivered = tp->delivered; -- bbr->lt_last_lost = tp->lost; -- bbr->lt_rtt_cnt = 0; --} -- --/* Completely reset long-term bandwidth sampling. */ --static void bbr_reset_lt_bw_sampling(struct sock *sk) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- -- bbr->lt_bw = 0; -- bbr->lt_use_bw = 0; -- bbr->lt_is_sampling = false; -- bbr_reset_lt_bw_sampling_interval(sk); --} -- --/* Long-term bw sampling interval is done. Estimate whether we're policed. */ --static void bbr_lt_bw_interval_done(struct sock *sk, u32 bw) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- u32 diff; -- -- if (bbr->lt_bw) { /* do we have bw from a previous interval? */ -- /* Is new bw close to the lt_bw from the previous interval? */ -- diff = abs(bw - bbr->lt_bw); -- if ((diff * BBR_UNIT <= bbr_lt_bw_ratio * bbr->lt_bw) || -- (bbr_rate_bytes_per_sec(sk, diff, BBR_UNIT) <= -- bbr_lt_bw_diff)) { -- /* All criteria are met; estimate we're policed. */ -- bbr->lt_bw = (bw + bbr->lt_bw) >> 1; /* avg 2 intvls */ -- bbr->lt_use_bw = 1; -- bbr->pacing_gain = BBR_UNIT; /* try to avoid drops */ -- bbr->lt_rtt_cnt = 0; -- return; -- } -- } -- bbr->lt_bw = bw; -- bbr_reset_lt_bw_sampling_interval(sk); --} -- --/* Token-bucket traffic policers are common (see "An Internet-Wide Analysis of -- * Traffic Policing", SIGCOMM 2016). BBR detects token-bucket policers and -- * explicitly models their policed rate, to reduce unnecessary losses. We -- * estimate that we're policed if we see 2 consecutive sampling intervals with -- * consistent throughput and high packet loss. If we think we're being policed, -- * set lt_bw to the "long-term" average delivery rate from those 2 intervals. -+/* See if we have reached next round trip. Upon start of the new round, -+ * returns packets delivered since previous round start plus this ACK. - */ --static void bbr_lt_bw_sampling(struct sock *sk, const struct rate_sample *rs) --{ -- struct tcp_sock *tp = tcp_sk(sk); -- struct bbr *bbr = inet_csk_ca(sk); -- u32 lost, delivered; -- u64 bw; -- u32 t; -- -- if (bbr->lt_use_bw) { /* already using long-term rate, lt_bw? */ -- if (bbr->mode == BBR_PROBE_BW && bbr->round_start && -- ++bbr->lt_rtt_cnt >= bbr_lt_bw_max_rtts) { -- bbr_reset_lt_bw_sampling(sk); /* stop using lt_bw */ -- bbr_reset_probe_bw_mode(sk); /* restart gain cycling */ -- } -- return; -- } -- -- /* Wait for the first loss before sampling, to let the policer exhaust -- * its tokens and estimate the steady-state rate allowed by the policer. -- * Starting samples earlier includes bursts that over-estimate the bw. -- */ -- if (!bbr->lt_is_sampling) { -- if (!rs->losses) -- return; -- bbr_reset_lt_bw_sampling_interval(sk); -- bbr->lt_is_sampling = true; -- } -- -- /* To avoid underestimates, reset sampling if we run out of data. */ -- if (rs->is_app_limited) { -- bbr_reset_lt_bw_sampling(sk); -- return; -- } -- -- if (bbr->round_start) -- bbr->lt_rtt_cnt++; /* count round trips in this interval */ -- if (bbr->lt_rtt_cnt < bbr_lt_intvl_min_rtts) -- return; /* sampling interval needs to be longer */ -- if (bbr->lt_rtt_cnt > 4 * bbr_lt_intvl_min_rtts) { -- bbr_reset_lt_bw_sampling(sk); /* interval is too long */ -- return; -- } -- -- /* End sampling interval when a packet is lost, so we estimate the -- * policer tokens were exhausted. Stopping the sampling before the -- * tokens are exhausted under-estimates the policed rate. -- */ -- if (!rs->losses) -- return; -- -- /* Calculate packets lost and delivered in sampling interval. */ -- lost = tp->lost - bbr->lt_last_lost; -- delivered = tp->delivered - bbr->lt_last_delivered; -- /* Is loss rate (lost/delivered) >= lt_loss_thresh? If not, wait. */ -- if (!delivered || (lost << BBR_SCALE) < bbr_lt_loss_thresh * delivered) -- return; -- -- /* Find average delivery rate in this sampling interval. */ -- t = div_u64(tp->delivered_mstamp, USEC_PER_MSEC) - bbr->lt_last_stamp; -- if ((s32)t < 1) -- return; /* interval is less than one ms, so wait */ -- /* Check if can multiply without overflow */ -- if (t >= ~0U / USEC_PER_MSEC) { -- bbr_reset_lt_bw_sampling(sk); /* interval too long; reset */ -- return; -- } -- t *= USEC_PER_MSEC; -- bw = (u64)delivered * BW_UNIT; -- do_div(bw, t); -- bbr_lt_bw_interval_done(sk, bw); --} -- --/* Estimate the bandwidth based on how fast packets are delivered */ --static void bbr_update_bw(struct sock *sk, const struct rate_sample *rs) -+static u32 bbr_update_round_start(struct sock *sk, -+ const struct rate_sample *rs, struct bbr_context *ctx) - { - struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); -- u64 bw; -+ u32 round_delivered = 0; - - bbr->round_start = 0; -- if (rs->delivered < 0 || rs->interval_us <= 0) -- return; /* Not a valid observation */ - - /* See if we've reached the next RTT */ -- if (!before(rs->prior_delivered, bbr->next_rtt_delivered)) { -+ if (rs->interval_us > 0 && -+ !before(rs->prior_delivered, bbr->next_rtt_delivered)) { -+ round_delivered = tp->delivered - bbr->next_rtt_delivered; - bbr->next_rtt_delivered = tp->delivered; -- bbr->rtt_cnt++; - bbr->round_start = 1; -- bbr->packet_conservation = 0; - } -+ return round_delivered; -+} - -- bbr_lt_bw_sampling(sk, rs); -+/* Calculate the bandwidth based on how fast packets are delivered */ -+static void bbr_calculate_bw_sample(struct sock *sk, -+ const struct rate_sample *rs, struct bbr_context *ctx) -+{ -+ u64 bw = 0; - - /* Divide delivered by the interval to find a (lower bound) bottleneck - * bandwidth sample. Delivered is in packets and interval_us in uS and - * ratio will be <<1 for most connections. So delivered is first scaled. -+ * Round up to allow growth at low rates, even with integer division. - */ -- bw = div64_long((u64)rs->delivered * BW_UNIT, rs->interval_us); -- -- /* If this sample is application-limited, it is likely to have a very -- * low delivered count that represents application behavior rather than -- * the available network rate. Such a sample could drag down estimated -- * bw, causing needless slow-down. Thus, to continue to send at the -- * last measured network rate, we filter out app-limited samples unless -- * they describe the path bw at least as well as our bw model. -- * -- * So the goal during app-limited phase is to proceed with the best -- * network rate no matter how long. We automatically leave this -- * phase when app writes faster than the network can deliver :) -- */ -- if (!rs->is_app_limited || bw >= bbr_max_bw(sk)) { -- /* Incorporate new sample into our max bw filter. */ -- minmax_running_max(&bbr->bw, bbr_bw_rtts, bbr->rtt_cnt, bw); -+ if (rs->interval_us > 0) { -+ if (WARN_ONCE(rs->delivered < 0, -+ "negative delivered: %d interval_us: %ld\n", -+ rs->delivered, rs->interval_us)) -+ return; -+ -+ bw = DIV_ROUND_UP_ULL((u64)rs->delivered * BW_UNIT, rs->interval_us); - } -+ -+ ctx->sample_bw = bw; - } - - /* Estimates the windowed max degree of ack aggregation. -@@ -812,7 +794,7 @@ static void bbr_update_bw(struct sock *sk, const struct rate_sample *rs) - * - * Max extra_acked is clamped by cwnd and bw * bbr_extra_acked_max_us (100 ms). - * Max filter is an approximate sliding window of 5-10 (packet timed) round -- * trips. -+ * trips for non-startup phase, and 1-2 round trips for startup. - */ - static void bbr_update_ack_aggregation(struct sock *sk, - const struct rate_sample *rs) -@@ -820,15 +802,19 @@ static void bbr_update_ack_aggregation(struct sock *sk, - u32 epoch_us, expected_acked, extra_acked; - struct bbr *bbr = inet_csk_ca(sk); - struct tcp_sock *tp = tcp_sk(sk); -+ u32 extra_acked_win_rtts_thresh = bbr_param(sk, extra_acked_win_rtts); - -- if (!bbr_extra_acked_gain || rs->acked_sacked <= 0 || -+ if (!bbr_param(sk, extra_acked_gain) || rs->acked_sacked <= 0 || - rs->delivered < 0 || rs->interval_us <= 0) - return; - - if (bbr->round_start) { - bbr->extra_acked_win_rtts = min(0x1F, - bbr->extra_acked_win_rtts + 1); -- if (bbr->extra_acked_win_rtts >= bbr_extra_acked_win_rtts) { -+ if (!bbr_full_bw_reached(sk)) -+ extra_acked_win_rtts_thresh = 1; -+ if (bbr->extra_acked_win_rtts >= -+ extra_acked_win_rtts_thresh) { - bbr->extra_acked_win_rtts = 0; - bbr->extra_acked_win_idx = bbr->extra_acked_win_idx ? - 0 : 1; -@@ -862,49 +848,6 @@ static void bbr_update_ack_aggregation(struct sock *sk, - bbr->extra_acked[bbr->extra_acked_win_idx] = extra_acked; - } - --/* Estimate when the pipe is full, using the change in delivery rate: BBR -- * estimates that STARTUP filled the pipe if the estimated bw hasn't changed by -- * at least bbr_full_bw_thresh (25%) after bbr_full_bw_cnt (3) non-app-limited -- * rounds. Why 3 rounds: 1: rwin autotuning grows the rwin, 2: we fill the -- * higher rwin, 3: we get higher delivery rate samples. Or transient -- * cross-traffic or radio noise can go away. CUBIC Hystart shares a similar -- * design goal, but uses delay and inter-ACK spacing instead of bandwidth. -- */ --static void bbr_check_full_bw_reached(struct sock *sk, -- const struct rate_sample *rs) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- u32 bw_thresh; -- -- if (bbr_full_bw_reached(sk) || !bbr->round_start || rs->is_app_limited) -- return; -- -- bw_thresh = (u64)bbr->full_bw * bbr_full_bw_thresh >> BBR_SCALE; -- if (bbr_max_bw(sk) >= bw_thresh) { -- bbr->full_bw = bbr_max_bw(sk); -- bbr->full_bw_cnt = 0; -- return; -- } -- ++bbr->full_bw_cnt; -- bbr->full_bw_reached = bbr->full_bw_cnt >= bbr_full_bw_cnt; --} -- --/* If pipe is probably full, drain the queue and then enter steady-state. */ --static void bbr_check_drain(struct sock *sk, const struct rate_sample *rs) --{ -- struct bbr *bbr = inet_csk_ca(sk); -- -- if (bbr->mode == BBR_STARTUP && bbr_full_bw_reached(sk)) { -- bbr->mode = BBR_DRAIN; /* drain queue we created */ -- tcp_sk(sk)->snd_ssthresh = -- bbr_inflight(sk, bbr_max_bw(sk), BBR_UNIT); -- } /* fall through to check if in-flight is already small: */ -- if (bbr->mode == BBR_DRAIN && -- bbr_packets_in_net_at_edt(sk, tcp_packets_in_flight(tcp_sk(sk))) <= -- bbr_inflight(sk, bbr_max_bw(sk), BBR_UNIT)) -- bbr_reset_probe_bw_mode(sk); /* we estimate queue is drained */ --} -- - static void bbr_check_probe_rtt_done(struct sock *sk) - { - struct tcp_sock *tp = tcp_sk(sk); -@@ -914,9 +857,9 @@ static void bbr_check_probe_rtt_done(struct sock *sk) - after(tcp_jiffies32, bbr->probe_rtt_done_stamp))) - return; - -- bbr->min_rtt_stamp = tcp_jiffies32; /* wait a while until PROBE_RTT */ -+ bbr->probe_rtt_min_stamp = tcp_jiffies32; /* schedule next PROBE_RTT */ - tcp_snd_cwnd_set(tp, max(tcp_snd_cwnd(tp), bbr->prior_cwnd)); -- bbr_reset_mode(sk); -+ bbr_exit_probe_rtt(sk); - } - - /* The goal of PROBE_RTT mode is to have BBR flows cooperatively and -@@ -942,23 +885,35 @@ static void bbr_update_min_rtt(struct sock *sk, const struct rate_sample *rs) - { - struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); -- bool filter_expired; -+ bool probe_rtt_expired, min_rtt_expired; -+ u32 expire; - -- /* Track min RTT seen in the min_rtt_win_sec filter window: */ -- filter_expired = after(tcp_jiffies32, -- bbr->min_rtt_stamp + bbr_min_rtt_win_sec * HZ); -+ /* Track min RTT in probe_rtt_win_ms to time next PROBE_RTT state. */ -+ expire = bbr->probe_rtt_min_stamp + -+ msecs_to_jiffies(bbr_param(sk, probe_rtt_win_ms)); -+ probe_rtt_expired = after(tcp_jiffies32, expire); - if (rs->rtt_us >= 0 && -- (rs->rtt_us < bbr->min_rtt_us || -- (filter_expired && !rs->is_ack_delayed))) { -- bbr->min_rtt_us = rs->rtt_us; -- bbr->min_rtt_stamp = tcp_jiffies32; -+ (rs->rtt_us < bbr->probe_rtt_min_us || -+ (probe_rtt_expired && !rs->is_ack_delayed))) { -+ bbr->probe_rtt_min_us = rs->rtt_us; -+ bbr->probe_rtt_min_stamp = tcp_jiffies32; -+ } -+ /* Track min RTT seen in the min_rtt_win_sec filter window: */ -+ expire = bbr->min_rtt_stamp + bbr_param(sk, min_rtt_win_sec) * HZ; -+ min_rtt_expired = after(tcp_jiffies32, expire); -+ if (bbr->probe_rtt_min_us <= bbr->min_rtt_us || -+ min_rtt_expired) { -+ bbr->min_rtt_us = bbr->probe_rtt_min_us; -+ bbr->min_rtt_stamp = bbr->probe_rtt_min_stamp; - } - -- if (bbr_probe_rtt_mode_ms > 0 && filter_expired && -+ if (bbr_param(sk, probe_rtt_mode_ms) > 0 && probe_rtt_expired && - !bbr->idle_restart && bbr->mode != BBR_PROBE_RTT) { - bbr->mode = BBR_PROBE_RTT; /* dip, drain queue */ - bbr_save_cwnd(sk); /* note cwnd so we can restore it */ - bbr->probe_rtt_done_stamp = 0; -+ bbr->ack_phase = BBR_ACKS_PROBE_STOPPING; -+ bbr->next_rtt_delivered = tp->delivered; - } - - if (bbr->mode == BBR_PROBE_RTT) { -@@ -967,9 +922,9 @@ static void bbr_update_min_rtt(struct sock *sk, const struct rate_sample *rs) - (tp->delivered + tcp_packets_in_flight(tp)) ? : 1; - /* Maintain min packets in flight for max(200 ms, 1 round). */ - if (!bbr->probe_rtt_done_stamp && -- tcp_packets_in_flight(tp) <= bbr_cwnd_min_target) { -+ tcp_packets_in_flight(tp) <= bbr_probe_rtt_cwnd(sk)) { - bbr->probe_rtt_done_stamp = tcp_jiffies32 + -- msecs_to_jiffies(bbr_probe_rtt_mode_ms); -+ msecs_to_jiffies(bbr_param(sk, probe_rtt_mode_ms)); - bbr->probe_rtt_round_done = 0; - bbr->next_rtt_delivered = tp->delivered; - } else if (bbr->probe_rtt_done_stamp) { -@@ -990,18 +945,20 @@ static void bbr_update_gains(struct sock *sk) - - switch (bbr->mode) { - case BBR_STARTUP: -- bbr->pacing_gain = bbr_high_gain; -- bbr->cwnd_gain = bbr_high_gain; -+ bbr->pacing_gain = bbr_param(sk, startup_pacing_gain); -+ bbr->cwnd_gain = bbr_param(sk, startup_cwnd_gain); - break; - case BBR_DRAIN: -- bbr->pacing_gain = bbr_drain_gain; /* slow, to drain */ -- bbr->cwnd_gain = bbr_high_gain; /* keep cwnd */ -+ bbr->pacing_gain = bbr_param(sk, drain_gain); /* slow, to drain */ -+ bbr->cwnd_gain = bbr_param(sk, startup_cwnd_gain); /* keep cwnd */ - break; - case BBR_PROBE_BW: -- bbr->pacing_gain = (bbr->lt_use_bw ? -- BBR_UNIT : -- bbr_pacing_gain[bbr->cycle_idx]); -- bbr->cwnd_gain = bbr_cwnd_gain; -+ bbr->pacing_gain = bbr_pacing_gain[bbr->cycle_idx]; -+ bbr->cwnd_gain = bbr_param(sk, cwnd_gain); -+ if (bbr_param(sk, bw_probe_cwnd_gain) && -+ bbr->cycle_idx == BBR_BW_PROBE_UP) -+ bbr->cwnd_gain += -+ BBR_UNIT * bbr_param(sk, bw_probe_cwnd_gain) / 4; - break; - case BBR_PROBE_RTT: - bbr->pacing_gain = BBR_UNIT; -@@ -1013,144 +970,1387 @@ static void bbr_update_gains(struct sock *sk) - } - } - --static void bbr_update_model(struct sock *sk, const struct rate_sample *rs) -+__bpf_kfunc static u32 bbr_sndbuf_expand(struct sock *sk) - { -- bbr_update_bw(sk, rs); -- bbr_update_ack_aggregation(sk, rs); -- bbr_update_cycle_phase(sk, rs); -- bbr_check_full_bw_reached(sk, rs); -- bbr_check_drain(sk, rs); -- bbr_update_min_rtt(sk, rs); -- bbr_update_gains(sk); -+ /* Provision 3 * cwnd since BBR may slow-start even during recovery. */ -+ return 3; - } - --__bpf_kfunc static void bbr_main(struct sock *sk, u32 ack, int flag, const struct rate_sample *rs) -+/* Incorporate a new bw sample into the current window of our max filter. */ -+static void bbr_take_max_bw_sample(struct sock *sk, u32 bw) - { - struct bbr *bbr = inet_csk_ca(sk); -- u32 bw; -- -- bbr_update_model(sk, rs); - -- bw = bbr_bw(sk); -- bbr_set_pacing_rate(sk, bw, bbr->pacing_gain); -- bbr_set_cwnd(sk, rs, rs->acked_sacked, bw, bbr->cwnd_gain); -+ bbr->bw_hi[1] = max(bw, bbr->bw_hi[1]); - } - --__bpf_kfunc static void bbr_init(struct sock *sk) -+/* Keep max of last 1-2 cycles. Each PROBE_BW cycle, flip filter window. */ -+static void bbr_advance_max_bw_filter(struct sock *sk) - { -- struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); - -- bbr->prior_cwnd = 0; -- tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; -- bbr->rtt_cnt = 0; -- bbr->next_rtt_delivered = tp->delivered; -- bbr->prev_ca_state = TCP_CA_Open; -- bbr->packet_conservation = 0; -- -- bbr->probe_rtt_done_stamp = 0; -- bbr->probe_rtt_round_done = 0; -- bbr->min_rtt_us = tcp_min_rtt(tp); -- bbr->min_rtt_stamp = tcp_jiffies32; -- -- minmax_reset(&bbr->bw, bbr->rtt_cnt, 0); /* init max bw to 0 */ -+ if (!bbr->bw_hi[1]) -+ return; /* no samples in this window; remember old window */ -+ bbr->bw_hi[0] = bbr->bw_hi[1]; -+ bbr->bw_hi[1] = 0; -+} - -- bbr->has_seen_rtt = 0; -- bbr_init_pacing_rate_from_rtt(sk); -+/* Reset the estimator for reaching full bandwidth based on bw plateau. */ -+static void bbr_reset_full_bw(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); - -- bbr->round_start = 0; -- bbr->idle_restart = 0; -- bbr->full_bw_reached = 0; - bbr->full_bw = 0; - bbr->full_bw_cnt = 0; -- bbr->cycle_mstamp = 0; -- bbr->cycle_idx = 0; -- bbr_reset_lt_bw_sampling(sk); -- bbr_reset_startup_mode(sk); -+ bbr->full_bw_now = 0; -+} - -- bbr->ack_epoch_mstamp = tp->tcp_mstamp; -- bbr->ack_epoch_acked = 0; -- bbr->extra_acked_win_rtts = 0; -- bbr->extra_acked_win_idx = 0; -- bbr->extra_acked[0] = 0; -- bbr->extra_acked[1] = 0; -+/* How much do we want in flight? Our BDP, unless congestion cut cwnd. */ -+static u32 bbr_target_inflight(struct sock *sk) -+{ -+ u32 bdp = bbr_inflight(sk, bbr_bw(sk), BBR_UNIT); - -- cmpxchg(&sk->sk_pacing_status, SK_PACING_NONE, SK_PACING_NEEDED); -+ return min(bdp, tcp_sk(sk)->snd_cwnd); - } - --__bpf_kfunc static u32 bbr_sndbuf_expand(struct sock *sk) -+static bool bbr_is_probing_bandwidth(struct sock *sk) - { -- /* Provision 3 * cwnd since BBR may slow-start even during recovery. */ -- return 3; -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ return (bbr->mode == BBR_STARTUP) || -+ (bbr->mode == BBR_PROBE_BW && -+ (bbr->cycle_idx == BBR_BW_PROBE_REFILL || -+ bbr->cycle_idx == BBR_BW_PROBE_UP)); -+} -+ -+/* Has the given amount of time elapsed since we marked the phase start? */ -+static bool bbr_has_elapsed_in_phase(const struct sock *sk, u32 interval_us) -+{ -+ const struct tcp_sock *tp = tcp_sk(sk); -+ const struct bbr *bbr = inet_csk_ca(sk); -+ -+ return tcp_stamp_us_delta(tp->tcp_mstamp, -+ bbr->cycle_mstamp + interval_us) > 0; -+} -+ -+static void bbr_handle_queue_too_high_in_startup(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 bdp; /* estimated BDP in packets, with quantization budget */ -+ -+ bbr->full_bw_reached = 1; -+ -+ bdp = bbr_inflight(sk, bbr_max_bw(sk), BBR_UNIT); -+ bbr->inflight_hi = max(bdp, bbr->inflight_latest); -+} -+ -+/* Exit STARTUP upon N consecutive rounds with ECN mark rate > ecn_thresh. */ -+static void bbr_check_ecn_too_high_in_startup(struct sock *sk, u32 ce_ratio) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (bbr_full_bw_reached(sk) || !bbr->ecn_eligible || -+ !bbr_param(sk, full_ecn_cnt) || !bbr_param(sk, ecn_thresh)) -+ return; -+ -+ if (ce_ratio >= bbr_param(sk, ecn_thresh)) -+ bbr->startup_ecn_rounds++; -+ else -+ bbr->startup_ecn_rounds = 0; -+ -+ if (bbr->startup_ecn_rounds >= bbr_param(sk, full_ecn_cnt)) { -+ bbr_handle_queue_too_high_in_startup(sk); -+ return; -+ } -+} -+ -+/* Updates ecn_alpha and returns ce_ratio. -1 if not available. */ -+static int bbr_update_ecn_alpha(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct net *net = sock_net(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ s32 delivered, delivered_ce; -+ u64 alpha, ce_ratio; -+ u32 gain; -+ bool want_ecn_alpha; -+ -+ /* See if we should use ECN sender logic for this connection. */ -+ if (!bbr->ecn_eligible && bbr_can_use_ecn(sk) && -+ bbr_param(sk, ecn_factor) && -+ (bbr->min_rtt_us <= bbr_ecn_max_rtt_us || -+ !bbr_ecn_max_rtt_us)) -+ bbr->ecn_eligible = 1; -+ -+ /* Skip updating alpha only if not ECN-eligible and PLB is disabled. */ -+ want_ecn_alpha = (bbr->ecn_eligible || -+ (bbr_can_use_ecn(sk) && -+ READ_ONCE(net->ipv4.sysctl_tcp_plb_enabled))); -+ if (!want_ecn_alpha) -+ return -1; -+ -+ delivered = tp->delivered - bbr->alpha_last_delivered; -+ delivered_ce = tp->delivered_ce - bbr->alpha_last_delivered_ce; -+ -+ if (delivered == 0 || /* avoid divide by zero */ -+ WARN_ON_ONCE(delivered < 0 || delivered_ce < 0)) /* backwards? */ -+ return -1; -+ -+ BUILD_BUG_ON(BBR_SCALE != TCP_PLB_SCALE); -+ ce_ratio = (u64)delivered_ce << BBR_SCALE; -+ do_div(ce_ratio, delivered); -+ -+ gain = bbr_param(sk, ecn_alpha_gain); -+ alpha = ((BBR_UNIT - gain) * bbr->ecn_alpha) >> BBR_SCALE; -+ alpha += (gain * ce_ratio) >> BBR_SCALE; -+ bbr->ecn_alpha = min_t(u32, alpha, BBR_UNIT); -+ -+ bbr->alpha_last_delivered = tp->delivered; -+ bbr->alpha_last_delivered_ce = tp->delivered_ce; -+ -+ bbr_check_ecn_too_high_in_startup(sk, ce_ratio); -+ return (int)ce_ratio; - } - --/* In theory BBR does not need to undo the cwnd since it does not -- * always reduce cwnd on losses (see bbr_main()). Keep it for now. -+/* Protective Load Balancing (PLB). PLB rehashes outgoing data (to a new IPv6 -+ * flow label) if it encounters sustained congestion in the form of ECN marks. - */ --__bpf_kfunc static u32 bbr_undo_cwnd(struct sock *sk) -+static void bbr_plb(struct sock *sk, const struct rate_sample *rs, int ce_ratio) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (bbr->round_start && ce_ratio >= 0) -+ tcp_plb_update_state(sk, &bbr->plb, ce_ratio); -+ -+ tcp_plb_check_rehash(sk, &bbr->plb); -+} -+ -+/* Each round trip of BBR_BW_PROBE_UP, double volume of probing data. */ -+static void bbr_raise_inflight_hi_slope(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 growth_this_round, cnt; -+ -+ /* Calculate "slope": packets S/Acked per inflight_hi increment. */ -+ growth_this_round = 1 << bbr->bw_probe_up_rounds; -+ bbr->bw_probe_up_rounds = min(bbr->bw_probe_up_rounds + 1, 30); -+ cnt = tcp_snd_cwnd(tp) / growth_this_round; -+ cnt = max(cnt, 1U); -+ bbr->bw_probe_up_cnt = cnt; -+} -+ -+/* In BBR_BW_PROBE_UP, not seeing high loss/ECN/queue, so raise inflight_hi. */ -+static void bbr_probe_inflight_hi_upward(struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 delta; -+ -+ if (!tp->is_cwnd_limited || tcp_snd_cwnd(tp) < bbr->inflight_hi) -+ return; /* not fully using inflight_hi, so don't grow it */ -+ -+ /* For each bw_probe_up_cnt packets ACKed, increase inflight_hi by 1. */ -+ bbr->bw_probe_up_acks += rs->acked_sacked; -+ if (bbr->bw_probe_up_acks >= bbr->bw_probe_up_cnt) { -+ delta = bbr->bw_probe_up_acks / bbr->bw_probe_up_cnt; -+ bbr->bw_probe_up_acks -= delta * bbr->bw_probe_up_cnt; -+ bbr->inflight_hi += delta; -+ bbr->try_fast_path = 0; /* Need to update cwnd */ -+ } -+ -+ if (bbr->round_start) -+ bbr_raise_inflight_hi_slope(sk); -+} -+ -+/* Does loss/ECN rate for this sample say inflight is "too high"? -+ * This is used by both the bbr_check_loss_too_high_in_startup() function, -+ * which can be used in either v1 or v2, and the PROBE_UP phase of v2, which -+ * uses it to notice when loss/ECN rates suggest inflight is too high. -+ */ -+static bool bbr_is_inflight_too_high(const struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ const struct bbr *bbr = inet_csk_ca(sk); -+ u32 loss_thresh, ecn_thresh; -+ -+ if (rs->lost > 0 && rs->tx_in_flight) { -+ loss_thresh = (u64)rs->tx_in_flight * bbr_param(sk, loss_thresh) >> -+ BBR_SCALE; -+ if (rs->lost > loss_thresh) { -+ return true; -+ } -+ } -+ -+ if (rs->delivered_ce > 0 && rs->delivered > 0 && -+ bbr->ecn_eligible && bbr_param(sk, ecn_thresh)) { -+ ecn_thresh = (u64)rs->delivered * bbr_param(sk, ecn_thresh) >> -+ BBR_SCALE; -+ if (rs->delivered_ce > ecn_thresh) { -+ return true; -+ } -+ } -+ -+ return false; -+} -+ -+/* Calculate the tx_in_flight level that corresponded to excessive loss. -+ * We find "lost_prefix" segs of the skb where loss rate went too high, -+ * by solving for "lost_prefix" in the following equation: -+ * lost / inflight >= loss_thresh -+ * (lost_prev + lost_prefix) / (inflight_prev + lost_prefix) >= loss_thresh -+ * Then we take that equation, convert it to fixed point, and -+ * round up to the nearest packet. -+ */ -+static u32 bbr_inflight_hi_from_lost_skb(const struct sock *sk, -+ const struct rate_sample *rs, -+ const struct sk_buff *skb) -+{ -+ const struct tcp_sock *tp = tcp_sk(sk); -+ u32 loss_thresh = bbr_param(sk, loss_thresh); -+ u32 pcount, divisor, inflight_hi; -+ s32 inflight_prev, lost_prev; -+ u64 loss_budget, lost_prefix; -+ -+ pcount = tcp_skb_pcount(skb); -+ -+ /* How much data was in flight before this skb? */ -+ inflight_prev = rs->tx_in_flight - pcount; -+ if (inflight_prev < 0) { -+ WARN_ONCE(tcp_skb_tx_in_flight_is_suspicious( -+ pcount, -+ TCP_SKB_CB(skb)->sacked, -+ rs->tx_in_flight), -+ "tx_in_flight: %u pcount: %u reneg: %u", -+ rs->tx_in_flight, pcount, tcp_sk(sk)->is_sack_reneg); -+ return ~0U; -+ } -+ -+ /* How much inflight data was marked lost before this skb? */ -+ lost_prev = rs->lost - pcount; -+ if (WARN_ONCE(lost_prev < 0, -+ "cwnd: %u ca: %d out: %u lost: %u pif: %u " -+ "tx_in_flight: %u tx.lost: %u tp->lost: %u rs->lost: %d " -+ "lost_prev: %d pcount: %d seq: %u end_seq: %u reneg: %u", -+ tcp_snd_cwnd(tp), inet_csk(sk)->icsk_ca_state, -+ tp->packets_out, tp->lost_out, tcp_packets_in_flight(tp), -+ rs->tx_in_flight, TCP_SKB_CB(skb)->tx.lost, tp->lost, -+ rs->lost, lost_prev, pcount, -+ TCP_SKB_CB(skb)->seq, TCP_SKB_CB(skb)->end_seq, -+ tp->is_sack_reneg)) -+ return ~0U; -+ -+ /* At what prefix of this lost skb did losss rate exceed loss_thresh? */ -+ loss_budget = (u64)inflight_prev * loss_thresh + BBR_UNIT - 1; -+ loss_budget >>= BBR_SCALE; -+ if (lost_prev >= loss_budget) { -+ lost_prefix = 0; /* previous losses crossed loss_thresh */ -+ } else { -+ lost_prefix = loss_budget - lost_prev; -+ lost_prefix <<= BBR_SCALE; -+ divisor = BBR_UNIT - loss_thresh; -+ if (WARN_ON_ONCE(!divisor)) /* loss_thresh is 8 bits */ -+ return ~0U; -+ do_div(lost_prefix, divisor); -+ } -+ -+ inflight_hi = inflight_prev + lost_prefix; -+ return inflight_hi; -+} -+ -+/* If loss/ECN rates during probing indicated we may have overfilled a -+ * buffer, return an operating point that tries to leave unutilized headroom in -+ * the path for other flows, for fairness convergence and lower RTTs and loss. -+ */ -+static u32 bbr_inflight_with_headroom(const struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 headroom, headroom_fraction; -+ -+ if (bbr->inflight_hi == ~0U) -+ return ~0U; -+ -+ headroom_fraction = bbr_param(sk, inflight_headroom); -+ headroom = ((u64)bbr->inflight_hi * headroom_fraction) >> BBR_SCALE; -+ headroom = max(headroom, 1U); -+ return max_t(s32, bbr->inflight_hi - headroom, -+ bbr_param(sk, cwnd_min_target)); -+} -+ -+/* Bound cwnd to a sensible level, based on our current probing state -+ * machine phase and model of a good inflight level (inflight_lo, inflight_hi). -+ */ -+static void bbr_bound_cwnd_for_inflight_model(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 cap; -+ -+ /* tcp_rcv_synsent_state_process() currently calls tcp_ack() -+ * and thus cong_control() without first initializing us(!). -+ */ -+ if (!bbr->initialized) -+ return; -+ -+ cap = ~0U; -+ if (bbr->mode == BBR_PROBE_BW && -+ bbr->cycle_idx != BBR_BW_PROBE_CRUISE) { -+ /* Probe to see if more packets fit in the path. */ -+ cap = bbr->inflight_hi; -+ } else { -+ if (bbr->mode == BBR_PROBE_RTT || -+ (bbr->mode == BBR_PROBE_BW && -+ bbr->cycle_idx == BBR_BW_PROBE_CRUISE)) -+ cap = bbr_inflight_with_headroom(sk); -+ } -+ /* Adapt to any loss/ECN since our last bw probe. */ -+ cap = min(cap, bbr->inflight_lo); -+ -+ cap = max_t(u32, cap, bbr_param(sk, cwnd_min_target)); -+ tcp_snd_cwnd_set(tp, min(cap, tcp_snd_cwnd(tp))); -+} -+ -+/* How should we multiplicatively cut bw or inflight limits based on ECN? */ -+static u32 bbr_ecn_cut(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ return BBR_UNIT - -+ ((bbr->ecn_alpha * bbr_param(sk, ecn_factor)) >> BBR_SCALE); -+} -+ -+/* Init lower bounds if have not inited yet. */ -+static void bbr_init_lower_bounds(struct sock *sk, bool init_bw) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (init_bw && bbr->bw_lo == ~0U) -+ bbr->bw_lo = bbr_max_bw(sk); -+ if (bbr->inflight_lo == ~0U) -+ bbr->inflight_lo = tcp_snd_cwnd(tp); -+} -+ -+/* Reduce bw and inflight to (1 - beta). */ -+static void bbr_loss_lower_bounds(struct sock *sk, u32 *bw, u32 *inflight) -+{ -+ struct bbr* bbr = inet_csk_ca(sk); -+ u32 loss_cut = BBR_UNIT - bbr_param(sk, beta); -+ -+ *bw = max_t(u32, bbr->bw_latest, -+ (u64)bbr->bw_lo * loss_cut >> BBR_SCALE); -+ *inflight = max_t(u32, bbr->inflight_latest, -+ (u64)bbr->inflight_lo * loss_cut >> BBR_SCALE); -+} -+ -+/* Reduce inflight to (1 - alpha*ecn_factor). */ -+static void bbr_ecn_lower_bounds(struct sock *sk, u32 *inflight) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 ecn_cut = bbr_ecn_cut(sk); -+ -+ *inflight = (u64)bbr->inflight_lo * ecn_cut >> BBR_SCALE; -+} -+ -+/* Estimate a short-term lower bound on the capacity available now, based -+ * on measurements of the current delivery process and recent history. When we -+ * are seeing loss/ECN at times when we are not probing bw, then conservatively -+ * move toward flow balance by multiplicatively cutting our short-term -+ * estimated safe rate and volume of data (bw_lo and inflight_lo). We use a -+ * multiplicative decrease in order to converge to a lower capacity in time -+ * logarithmic in the magnitude of the decrease. -+ * -+ * However, we do not cut our short-term estimates lower than the current rate -+ * and volume of delivered data from this round trip, since from the current -+ * delivery process we can estimate the measured capacity available now. -+ * -+ * Anything faster than that approach would knowingly risk high loss, which can -+ * cause low bw for Reno/CUBIC and high loss recovery latency for -+ * request/response flows using any congestion control. -+ */ -+static void bbr_adapt_lower_bounds(struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 ecn_inflight_lo = ~0U; -+ -+ /* We only use lower-bound estimates when not probing bw. -+ * When probing we need to push inflight higher to probe bw. -+ */ -+ if (bbr_is_probing_bandwidth(sk)) -+ return; -+ -+ /* ECN response. */ -+ if (bbr->ecn_in_round && bbr_param(sk, ecn_factor)) { -+ bbr_init_lower_bounds(sk, false); -+ bbr_ecn_lower_bounds(sk, &ecn_inflight_lo); -+ } -+ -+ /* Loss response. */ -+ if (bbr->loss_in_round) { -+ bbr_init_lower_bounds(sk, true); -+ bbr_loss_lower_bounds(sk, &bbr->bw_lo, &bbr->inflight_lo); -+ } -+ -+ /* Adjust to the lower of the levels implied by loss/ECN. */ -+ bbr->inflight_lo = min(bbr->inflight_lo, ecn_inflight_lo); -+ bbr->bw_lo = max(1U, bbr->bw_lo); -+} -+ -+/* Reset any short-term lower-bound adaptation to congestion, so that we can -+ * push our inflight up. -+ */ -+static void bbr_reset_lower_bounds(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->bw_lo = ~0U; -+ bbr->inflight_lo = ~0U; -+} -+ -+/* After bw probing (STARTUP/PROBE_UP), reset signals before entering a state -+ * machine phase where we adapt our lower bound based on congestion signals. -+ */ -+static void bbr_reset_congestion_signals(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->loss_in_round = 0; -+ bbr->ecn_in_round = 0; -+ bbr->loss_in_cycle = 0; -+ bbr->ecn_in_cycle = 0; -+ bbr->bw_latest = 0; -+ bbr->inflight_latest = 0; -+} -+ -+static void bbr_exit_loss_recovery(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ tcp_snd_cwnd_set(tp, max(tcp_snd_cwnd(tp), bbr->prior_cwnd)); -+ bbr->try_fast_path = 0; /* bound cwnd using latest model */ -+} -+ -+/* Update rate and volume of delivered data from latest round trip. */ -+static void bbr_update_latest_delivery_signals( -+ struct sock *sk, const struct rate_sample *rs, struct bbr_context *ctx) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->loss_round_start = 0; -+ if (rs->interval_us <= 0 || !rs->acked_sacked) -+ return; /* Not a valid observation */ -+ -+ bbr->bw_latest = max_t(u32, bbr->bw_latest, ctx->sample_bw); -+ bbr->inflight_latest = max_t(u32, bbr->inflight_latest, rs->delivered); -+ -+ if (!before(rs->prior_delivered, bbr->loss_round_delivered)) { -+ bbr->loss_round_delivered = tp->delivered; -+ bbr->loss_round_start = 1; /* mark start of new round trip */ -+ } -+} -+ -+/* Once per round, reset filter for latest rate and volume of delivered data. */ -+static void bbr_advance_latest_delivery_signals( -+ struct sock *sk, const struct rate_sample *rs, struct bbr_context *ctx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ /* If ACK matches a TLP retransmit, persist the filter. If we detect -+ * that a TLP retransmit plugged a tail loss, we'll want to remember -+ * how much data the path delivered before the tail loss. -+ */ -+ if (bbr->loss_round_start && !rs->is_acking_tlp_retrans_seq) { -+ bbr->bw_latest = ctx->sample_bw; -+ bbr->inflight_latest = rs->delivered; -+ } -+} -+ -+/* Update (most of) our congestion signals: track the recent rate and volume of -+ * delivered data, presence of loss, and EWMA degree of ECN marking. -+ */ -+static void bbr_update_congestion_signals( -+ struct sock *sk, const struct rate_sample *rs, struct bbr_context *ctx) - { - struct bbr *bbr = inet_csk_ca(sk); -+ u64 bw; -+ -+ if (rs->interval_us <= 0 || !rs->acked_sacked) -+ return; /* Not a valid observation */ -+ bw = ctx->sample_bw; - -- bbr->full_bw = 0; /* spurious slow-down; reset full pipe detection */ -+ if (!rs->is_app_limited || bw >= bbr_max_bw(sk)) -+ bbr_take_max_bw_sample(sk, bw); -+ -+ bbr->loss_in_round |= (rs->losses > 0); -+ -+ if (!bbr->loss_round_start) -+ return; /* skip the per-round-trip updates */ -+ /* Now do per-round-trip updates. */ -+ bbr_adapt_lower_bounds(sk, rs); -+ -+ bbr->loss_in_round = 0; -+ bbr->ecn_in_round = 0; -+} -+ -+/* Bandwidth probing can cause loss. To help coexistence with loss-based -+ * congestion control we spread out our probing in a Reno-conscious way. Due to -+ * the shape of the Reno sawtooth, the time required between loss epochs for an -+ * idealized Reno flow is a number of round trips that is the BDP of that -+ * flow. We count packet-timed round trips directly, since measured RTT can -+ * vary widely, and Reno is driven by packet-timed round trips. -+ */ -+static bool bbr_is_reno_coexistence_probe_time(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 rounds; -+ -+ /* Random loss can shave some small percentage off of our inflight -+ * in each round. To survive this, flows need robust periodic probes. -+ */ -+ rounds = min_t(u32, bbr_param(sk, bw_probe_max_rounds), bbr_target_inflight(sk)); -+ return bbr->rounds_since_probe >= rounds; -+} -+ -+/* How long do we want to wait before probing for bandwidth (and risking -+ * loss)? We randomize the wait, for better mixing and fairness convergence. -+ * -+ * We bound the Reno-coexistence inter-bw-probe time to be 62-63 round trips. -+ * This is calculated to allow fairness with a 25Mbps, 30ms Reno flow, -+ * (eg 4K video to a broadband user): -+ * BDP = 25Mbps * .030sec /(1514bytes) = 61.9 packets -+ * -+ * We bound the BBR-native inter-bw-probe wall clock time to be: -+ * (a) higher than 2 sec: to try to avoid causing loss for a long enough time -+ * to allow Reno at 30ms to get 4K video bw, the inter-bw-probe time must -+ * be at least: 25Mbps * .030sec / (1514bytes) * 0.030sec = 1.9secs -+ * (b) lower than 3 sec: to ensure flows can start probing in a reasonable -+ * amount of time to discover unutilized bw on human-scale interactive -+ * time-scales (e.g. perhaps traffic from a web page download that we -+ * were competing with is now complete). -+ */ -+static void bbr_pick_probe_wait(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ /* Decide the random round-trip bound for wait until probe: */ -+ bbr->rounds_since_probe = -+ get_random_u32_below(bbr_param(sk, bw_probe_rand_rounds)); -+ /* Decide the random wall clock bound for wait until probe: */ -+ bbr->probe_wait_us = bbr_param(sk, bw_probe_base_us) + -+ get_random_u32_below(bbr_param(sk, bw_probe_rand_us)); -+} -+ -+static void bbr_set_cycle_idx(struct sock *sk, int cycle_idx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->cycle_idx = cycle_idx; -+ /* New phase, so need to update cwnd and pacing rate. */ -+ bbr->try_fast_path = 0; -+} -+ -+/* Send at estimated bw to fill the pipe, but not queue. We need this phase -+ * before PROBE_UP, because as soon as we send faster than the available bw -+ * we will start building a queue, and if the buffer is shallow we can cause -+ * loss. If we do not fill the pipe before we cause this loss, our bw_hi and -+ * inflight_hi estimates will underestimate. -+ */ -+static void bbr_start_bw_probe_refill(struct sock *sk, u32 bw_probe_up_rounds) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr_reset_lower_bounds(sk); -+ bbr->bw_probe_up_rounds = bw_probe_up_rounds; -+ bbr->bw_probe_up_acks = 0; -+ bbr->stopped_risky_probe = 0; -+ bbr->ack_phase = BBR_ACKS_REFILLING; -+ bbr->next_rtt_delivered = tp->delivered; -+ bbr_set_cycle_idx(sk, BBR_BW_PROBE_REFILL); -+} -+ -+/* Now probe max deliverable data rate and volume. */ -+static void bbr_start_bw_probe_up(struct sock *sk, struct bbr_context *ctx) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->ack_phase = BBR_ACKS_PROBE_STARTING; -+ bbr->next_rtt_delivered = tp->delivered; -+ bbr->cycle_mstamp = tp->tcp_mstamp; -+ bbr_reset_full_bw(sk); -+ bbr->full_bw = ctx->sample_bw; -+ bbr_set_cycle_idx(sk, BBR_BW_PROBE_UP); -+ bbr_raise_inflight_hi_slope(sk); -+} -+ -+/* Start a new PROBE_BW probing cycle of some wall clock length. Pick a wall -+ * clock time at which to probe beyond an inflight that we think to be -+ * safe. This will knowingly risk packet loss, so we want to do this rarely, to -+ * keep packet loss rates low. Also start a round-trip counter, to probe faster -+ * if we estimate a Reno flow at our BDP would probe faster. -+ */ -+static void bbr_start_bw_probe_down(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr_reset_congestion_signals(sk); -+ bbr->bw_probe_up_cnt = ~0U; /* not growing inflight_hi any more */ -+ bbr_pick_probe_wait(sk); -+ bbr->cycle_mstamp = tp->tcp_mstamp; /* start wall clock */ -+ bbr->ack_phase = BBR_ACKS_PROBE_STOPPING; -+ bbr->next_rtt_delivered = tp->delivered; -+ bbr_set_cycle_idx(sk, BBR_BW_PROBE_DOWN); -+} -+ -+/* Cruise: maintain what we estimate to be a neutral, conservative -+ * operating point, without attempting to probe up for bandwidth or down for -+ * RTT, and only reducing inflight in response to loss/ECN signals. -+ */ -+static void bbr_start_bw_probe_cruise(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (bbr->inflight_lo != ~0U) -+ bbr->inflight_lo = min(bbr->inflight_lo, bbr->inflight_hi); -+ -+ bbr_set_cycle_idx(sk, BBR_BW_PROBE_CRUISE); -+} -+ -+/* Loss and/or ECN rate is too high while probing. -+ * Adapt (once per bw probe) by cutting inflight_hi and then restarting cycle. -+ */ -+static void bbr_handle_inflight_too_high(struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ const u32 beta = bbr_param(sk, beta); -+ -+ bbr->prev_probe_too_high = 1; -+ bbr->bw_probe_samples = 0; /* only react once per probe */ -+ /* If we are app-limited then we are not robustly -+ * probing the max volume of inflight data we think -+ * might be safe (analogous to how app-limited bw -+ * samples are not known to be robustly probing bw). -+ */ -+ if (!rs->is_app_limited) { -+ bbr->inflight_hi = max_t(u32, rs->tx_in_flight, -+ (u64)bbr_target_inflight(sk) * -+ (BBR_UNIT - beta) >> BBR_SCALE); -+ } -+ if (bbr->mode == BBR_PROBE_BW && bbr->cycle_idx == BBR_BW_PROBE_UP) -+ bbr_start_bw_probe_down(sk); -+} -+ -+/* If we're seeing bw and loss samples reflecting our bw probing, adapt -+ * using the signals we see. If loss or ECN mark rate gets too high, then adapt -+ * inflight_hi downward. If we're able to push inflight higher without such -+ * signals, push higher: adapt inflight_hi upward. -+ */ -+static bool bbr_adapt_upper_bounds(struct sock *sk, -+ const struct rate_sample *rs, -+ struct bbr_context *ctx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ /* Track when we'll see bw/loss samples resulting from our bw probes. */ -+ if (bbr->ack_phase == BBR_ACKS_PROBE_STARTING && bbr->round_start) -+ bbr->ack_phase = BBR_ACKS_PROBE_FEEDBACK; -+ if (bbr->ack_phase == BBR_ACKS_PROBE_STOPPING && bbr->round_start) { -+ /* End of samples from bw probing phase. */ -+ bbr->bw_probe_samples = 0; -+ bbr->ack_phase = BBR_ACKS_INIT; -+ /* At this point in the cycle, our current bw sample is also -+ * our best recent chance at finding the highest available bw -+ * for this flow. So now is the best time to forget the bw -+ * samples from the previous cycle, by advancing the window. -+ */ -+ if (bbr->mode == BBR_PROBE_BW && !rs->is_app_limited) -+ bbr_advance_max_bw_filter(sk); -+ /* If we had an inflight_hi, then probed and pushed inflight all -+ * the way up to hit that inflight_hi without seeing any -+ * high loss/ECN in all the resulting ACKs from that probing, -+ * then probe up again, this time letting inflight persist at -+ * inflight_hi for a round trip, then accelerating beyond. -+ */ -+ if (bbr->mode == BBR_PROBE_BW && -+ bbr->stopped_risky_probe && !bbr->prev_probe_too_high) { -+ bbr_start_bw_probe_refill(sk, 0); -+ return true; /* yes, decided state transition */ -+ } -+ } -+ if (bbr_is_inflight_too_high(sk, rs)) { -+ if (bbr->bw_probe_samples) /* sample is from bw probing? */ -+ bbr_handle_inflight_too_high(sk, rs); -+ } else { -+ /* Loss/ECN rate is declared safe. Adjust upper bound upward. */ -+ -+ if (bbr->inflight_hi == ~0U) -+ return false; /* no excess queue signals yet */ -+ -+ /* To be resilient to random loss, we must raise bw/inflight_hi -+ * if we observe in any phase that a higher level is safe. -+ */ -+ if (rs->tx_in_flight > bbr->inflight_hi) { -+ bbr->inflight_hi = rs->tx_in_flight; -+ } -+ -+ if (bbr->mode == BBR_PROBE_BW && -+ bbr->cycle_idx == BBR_BW_PROBE_UP) -+ bbr_probe_inflight_hi_upward(sk, rs); -+ } -+ -+ return false; -+} -+ -+/* Check if it's time to probe for bandwidth now, and if so, kick it off. */ -+static bool bbr_check_time_to_probe_bw(struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 n; -+ -+ /* If we seem to be at an operating point where we are not seeing loss -+ * but we are seeing ECN marks, then when the ECN marks cease we reprobe -+ * quickly (in case cross-traffic has ceased and freed up bw). -+ */ -+ if (bbr_param(sk, ecn_reprobe_gain) && bbr->ecn_eligible && -+ bbr->ecn_in_cycle && !bbr->loss_in_cycle && -+ inet_csk(sk)->icsk_ca_state == TCP_CA_Open) { -+ /* Calculate n so that when bbr_raise_inflight_hi_slope() -+ * computes growth_this_round as 2^n it will be roughly the -+ * desired volume of data (inflight_hi*ecn_reprobe_gain). -+ */ -+ n = ilog2((((u64)bbr->inflight_hi * -+ bbr_param(sk, ecn_reprobe_gain)) >> BBR_SCALE)); -+ bbr_start_bw_probe_refill(sk, n); -+ return true; -+ } -+ -+ if (bbr_has_elapsed_in_phase(sk, bbr->probe_wait_us) || -+ bbr_is_reno_coexistence_probe_time(sk)) { -+ bbr_start_bw_probe_refill(sk, 0); -+ return true; -+ } -+ return false; -+} -+ -+/* Is it time to transition from PROBE_DOWN to PROBE_CRUISE? */ -+static bool bbr_check_time_to_cruise(struct sock *sk, u32 inflight, u32 bw) -+{ -+ /* Always need to pull inflight down to leave headroom in queue. */ -+ if (inflight > bbr_inflight_with_headroom(sk)) -+ return false; -+ -+ return inflight <= bbr_inflight(sk, bw, BBR_UNIT); -+} -+ -+/* PROBE_BW state machine: cruise, refill, probe for bw, or drain? */ -+static void bbr_update_cycle_phase(struct sock *sk, -+ const struct rate_sample *rs, -+ struct bbr_context *ctx) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ bool is_bw_probe_done = false; -+ u32 inflight, bw; -+ -+ if (!bbr_full_bw_reached(sk)) -+ return; -+ -+ /* In DRAIN, PROBE_BW, or PROBE_RTT, adjust upper bounds. */ -+ if (bbr_adapt_upper_bounds(sk, rs, ctx)) -+ return; /* already decided state transition */ -+ -+ if (bbr->mode != BBR_PROBE_BW) -+ return; -+ -+ inflight = bbr_packets_in_net_at_edt(sk, rs->prior_in_flight); -+ bw = bbr_max_bw(sk); -+ -+ switch (bbr->cycle_idx) { -+ /* First we spend most of our time cruising with a pacing_gain of 1.0, -+ * which paces at the estimated bw, to try to fully use the pipe -+ * without building queue. If we encounter loss/ECN marks, we adapt -+ * by slowing down. -+ */ -+ case BBR_BW_PROBE_CRUISE: -+ if (bbr_check_time_to_probe_bw(sk, rs)) -+ return; /* already decided state transition */ -+ break; -+ -+ /* After cruising, when it's time to probe, we first "refill": we send -+ * at the estimated bw to fill the pipe, before probing higher and -+ * knowingly risking overflowing the bottleneck buffer (causing loss). -+ */ -+ case BBR_BW_PROBE_REFILL: -+ if (bbr->round_start) { -+ /* After one full round trip of sending in REFILL, we -+ * start to see bw samples reflecting our REFILL, which -+ * may be putting too much data in flight. -+ */ -+ bbr->bw_probe_samples = 1; -+ bbr_start_bw_probe_up(sk, ctx); -+ } -+ break; -+ -+ /* After we refill the pipe, we probe by using a pacing_gain > 1.0, to -+ * probe for bw. If we have not seen loss/ECN, we try to raise inflight -+ * to at least pacing_gain*BDP; note that this may take more than -+ * min_rtt if min_rtt is small (e.g. on a LAN). -+ * -+ * We terminate PROBE_UP bandwidth probing upon any of the following: -+ * -+ * (1) We've pushed inflight up to hit the inflight_hi target set in the -+ * most recent previous bw probe phase. Thus we want to start -+ * draining the queue immediately because it's very likely the most -+ * recently sent packets will fill the queue and cause drops. -+ * (2) If inflight_hi has not limited bandwidth growth recently, and -+ * yet delivered bandwidth has not increased much recently -+ * (bbr->full_bw_now). -+ * (3) Loss filter says loss rate is "too high". -+ * (4) ECN filter says ECN mark rate is "too high". -+ * -+ * (1) (2) checked here, (3) (4) checked in bbr_is_inflight_too_high() -+ */ -+ case BBR_BW_PROBE_UP: -+ if (bbr->prev_probe_too_high && -+ inflight >= bbr->inflight_hi) { -+ bbr->stopped_risky_probe = 1; -+ is_bw_probe_done = true; -+ } else { -+ if (tp->is_cwnd_limited && -+ tcp_snd_cwnd(tp) >= bbr->inflight_hi) { -+ /* inflight_hi is limiting bw growth */ -+ bbr_reset_full_bw(sk); -+ bbr->full_bw = ctx->sample_bw; -+ } else if (bbr->full_bw_now) { -+ /* Plateau in estimated bw. Pipe looks full. */ -+ is_bw_probe_done = true; -+ } -+ } -+ if (is_bw_probe_done) { -+ bbr->prev_probe_too_high = 0; /* no loss/ECN (yet) */ -+ bbr_start_bw_probe_down(sk); /* restart w/ down */ -+ } -+ break; -+ -+ /* After probing in PROBE_UP, we have usually accumulated some data in -+ * the bottleneck buffer (if bw probing didn't find more bw). We next -+ * enter PROBE_DOWN to try to drain any excess data from the queue. To -+ * do this, we use a pacing_gain < 1.0. We hold this pacing gain until -+ * our inflight is less then that target cruising point, which is the -+ * minimum of (a) the amount needed to leave headroom, and (b) the -+ * estimated BDP. Once inflight falls to match the target, we estimate -+ * the queue is drained; persisting would underutilize the pipe. -+ */ -+ case BBR_BW_PROBE_DOWN: -+ if (bbr_check_time_to_probe_bw(sk, rs)) -+ return; /* already decided state transition */ -+ if (bbr_check_time_to_cruise(sk, inflight, bw)) -+ bbr_start_bw_probe_cruise(sk); -+ break; -+ -+ default: -+ WARN_ONCE(1, "BBR invalid cycle index %u\n", bbr->cycle_idx); -+ } -+} -+ -+/* Exiting PROBE_RTT, so return to bandwidth probing in STARTUP or PROBE_BW. */ -+static void bbr_exit_probe_rtt(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr_reset_lower_bounds(sk); -+ if (bbr_full_bw_reached(sk)) { -+ bbr->mode = BBR_PROBE_BW; -+ /* Raising inflight after PROBE_RTT may cause loss, so reset -+ * the PROBE_BW clock and schedule the next bandwidth probe for -+ * a friendly and randomized future point in time. -+ */ -+ bbr_start_bw_probe_down(sk); -+ /* Since we are exiting PROBE_RTT, we know inflight is -+ * below our estimated BDP, so it is reasonable to cruise. -+ */ -+ bbr_start_bw_probe_cruise(sk); -+ } else { -+ bbr->mode = BBR_STARTUP; -+ } -+} -+ -+/* Exit STARTUP based on loss rate > 1% and loss gaps in round >= N. Wait until -+ * the end of the round in recovery to get a good estimate of how many packets -+ * have been lost, and how many we need to drain with a low pacing rate. -+ */ -+static void bbr_check_loss_too_high_in_startup(struct sock *sk, -+ const struct rate_sample *rs) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (bbr_full_bw_reached(sk)) -+ return; -+ -+ /* For STARTUP exit, check the loss rate at the end of each round trip -+ * of Recovery episodes in STARTUP. We check the loss rate at the end -+ * of the round trip to filter out noisy/low loss and have a better -+ * sense of inflight (extent of loss), so we can drain more accurately. -+ */ -+ if (rs->losses && bbr->loss_events_in_round < 0xf) -+ bbr->loss_events_in_round++; /* update saturating counter */ -+ if (bbr_param(sk, full_loss_cnt) && bbr->loss_round_start && -+ inet_csk(sk)->icsk_ca_state == TCP_CA_Recovery && -+ bbr->loss_events_in_round >= bbr_param(sk, full_loss_cnt) && -+ bbr_is_inflight_too_high(sk, rs)) { -+ bbr_handle_queue_too_high_in_startup(sk); -+ return; -+ } -+ if (bbr->loss_round_start) -+ bbr->loss_events_in_round = 0; -+} -+ -+/* Estimate when the pipe is full, using the change in delivery rate: BBR -+ * estimates bw probing filled the pipe if the estimated bw hasn't changed by -+ * at least bbr_full_bw_thresh (25%) after bbr_full_bw_cnt (3) non-app-limited -+ * rounds. Why 3 rounds: 1: rwin autotuning grows the rwin, 2: we fill the -+ * higher rwin, 3: we get higher delivery rate samples. Or transient -+ * cross-traffic or radio noise can go away. CUBIC Hystart shares a similar -+ * design goal, but uses delay and inter-ACK spacing instead of bandwidth. -+ */ -+static void bbr_check_full_bw_reached(struct sock *sk, -+ const struct rate_sample *rs, -+ struct bbr_context *ctx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 bw_thresh, full_cnt, thresh; -+ -+ if (bbr->full_bw_now || rs->is_app_limited) -+ return; -+ -+ thresh = bbr_param(sk, full_bw_thresh); -+ full_cnt = bbr_param(sk, full_bw_cnt); -+ bw_thresh = (u64)bbr->full_bw * thresh >> BBR_SCALE; -+ if (ctx->sample_bw >= bw_thresh) { -+ bbr_reset_full_bw(sk); -+ bbr->full_bw = ctx->sample_bw; -+ return; -+ } -+ if (!bbr->round_start) -+ return; -+ ++bbr->full_bw_cnt; -+ bbr->full_bw_now = bbr->full_bw_cnt >= full_cnt; -+ bbr->full_bw_reached |= bbr->full_bw_now; -+} -+ -+/* If pipe is probably full, drain the queue and then enter steady-state. */ -+static void bbr_check_drain(struct sock *sk, const struct rate_sample *rs, -+ struct bbr_context *ctx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ if (bbr->mode == BBR_STARTUP && bbr_full_bw_reached(sk)) { -+ bbr->mode = BBR_DRAIN; /* drain queue we created */ -+ /* Set ssthresh to export purely for monitoring, to signal -+ * completion of initial STARTUP by setting to a non- -+ * TCP_INFINITE_SSTHRESH value (ssthresh is not used by BBR). -+ */ -+ tcp_sk(sk)->snd_ssthresh = -+ bbr_inflight(sk, bbr_max_bw(sk), BBR_UNIT); -+ bbr_reset_congestion_signals(sk); -+ } /* fall through to check if in-flight is already small: */ -+ if (bbr->mode == BBR_DRAIN && -+ bbr_packets_in_net_at_edt(sk, tcp_packets_in_flight(tcp_sk(sk))) <= -+ bbr_inflight(sk, bbr_max_bw(sk), BBR_UNIT)) { -+ bbr->mode = BBR_PROBE_BW; -+ bbr_start_bw_probe_down(sk); -+ } -+} -+ -+static void bbr_update_model(struct sock *sk, const struct rate_sample *rs, -+ struct bbr_context *ctx) -+{ -+ bbr_update_congestion_signals(sk, rs, ctx); -+ bbr_update_ack_aggregation(sk, rs); -+ bbr_check_loss_too_high_in_startup(sk, rs); -+ bbr_check_full_bw_reached(sk, rs, ctx); -+ bbr_check_drain(sk, rs, ctx); -+ bbr_update_cycle_phase(sk, rs, ctx); -+ bbr_update_min_rtt(sk, rs); -+} -+ -+/* Fast path for app-limited case. -+ * -+ * On each ack, we execute bbr state machine, which primarily consists of: -+ * 1) update model based on new rate sample, and -+ * 2) update control based on updated model or state change. -+ * -+ * There are certain workload/scenarios, e.g. app-limited case, where -+ * either we can skip updating model or we can skip update of both model -+ * as well as control. This provides signifcant softirq cpu savings for -+ * processing incoming acks. -+ * -+ * In case of app-limited, if there is no congestion (loss/ecn) and -+ * if observed bw sample is less than current estimated bw, then we can -+ * skip some of the computation in bbr state processing: -+ * -+ * - if there is no rtt/mode/phase change: In this case, since all the -+ * parameters of the network model are constant, we can skip model -+ * as well control update. -+ * -+ * - else we can skip rest of the model update. But we still need to -+ * update the control to account for the new rtt/mode/phase. -+ * -+ * Returns whether we can take fast path or not. -+ */ -+static bool bbr_run_fast_path(struct sock *sk, bool *update_model, -+ const struct rate_sample *rs, struct bbr_context *ctx) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ u32 prev_min_rtt_us, prev_mode; -+ -+ if (bbr_param(sk, fast_path) && bbr->try_fast_path && -+ rs->is_app_limited && ctx->sample_bw < bbr_max_bw(sk) && -+ !bbr->loss_in_round && !bbr->ecn_in_round ) { -+ prev_mode = bbr->mode; -+ prev_min_rtt_us = bbr->min_rtt_us; -+ bbr_check_drain(sk, rs, ctx); -+ bbr_update_cycle_phase(sk, rs, ctx); -+ bbr_update_min_rtt(sk, rs); -+ -+ if (bbr->mode == prev_mode && -+ bbr->min_rtt_us == prev_min_rtt_us && -+ bbr->try_fast_path) { -+ return true; -+ } -+ -+ /* Skip model update, but control still needs to be updated */ -+ *update_model = false; -+ } -+ return false; -+} -+ -+__bpf_kfunc static void bbr_main(struct sock *sk, u32 ack, int flag, const struct rate_sample *rs) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ struct bbr_context ctx = { 0 }; -+ bool update_model = true; -+ u32 bw, round_delivered; -+ int ce_ratio = -1; -+ -+ round_delivered = bbr_update_round_start(sk, rs, &ctx); -+ if (bbr->round_start) { -+ bbr->rounds_since_probe = -+ min_t(s32, bbr->rounds_since_probe + 1, 0xFF); -+ ce_ratio = bbr_update_ecn_alpha(sk); -+ } -+ bbr_plb(sk, rs, ce_ratio); -+ -+ bbr->ecn_in_round |= (bbr->ecn_eligible && rs->is_ece); -+ bbr_calculate_bw_sample(sk, rs, &ctx); -+ bbr_update_latest_delivery_signals(sk, rs, &ctx); -+ -+ if (bbr_run_fast_path(sk, &update_model, rs, &ctx)) -+ goto out; -+ -+ if (update_model) -+ bbr_update_model(sk, rs, &ctx); -+ -+ bbr_update_gains(sk); -+ bw = bbr_bw(sk); -+ bbr_set_pacing_rate(sk, bw, bbr->pacing_gain); -+ bbr_set_cwnd(sk, rs, rs->acked_sacked, bw, bbr->cwnd_gain, -+ tcp_snd_cwnd(tp), &ctx); -+ bbr_bound_cwnd_for_inflight_model(sk); -+ -+out: -+ bbr_advance_latest_delivery_signals(sk, rs, &ctx); -+ bbr->prev_ca_state = inet_csk(sk)->icsk_ca_state; -+ bbr->loss_in_cycle |= rs->lost > 0; -+ bbr->ecn_in_cycle |= rs->delivered_ce > 0; -+} -+ -+__bpf_kfunc static void bbr_init(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr->initialized = 1; -+ -+ bbr->init_cwnd = min(0x7FU, tcp_snd_cwnd(tp)); -+ bbr->prior_cwnd = tp->prior_cwnd; -+ tp->snd_ssthresh = TCP_INFINITE_SSTHRESH; -+ bbr->next_rtt_delivered = tp->delivered; -+ bbr->prev_ca_state = TCP_CA_Open; -+ -+ bbr->probe_rtt_done_stamp = 0; -+ bbr->probe_rtt_round_done = 0; -+ bbr->probe_rtt_min_us = tcp_min_rtt(tp); -+ bbr->probe_rtt_min_stamp = tcp_jiffies32; -+ bbr->min_rtt_us = tcp_min_rtt(tp); -+ bbr->min_rtt_stamp = tcp_jiffies32; -+ -+ bbr->has_seen_rtt = 0; -+ bbr_init_pacing_rate_from_rtt(sk); -+ -+ bbr->round_start = 0; -+ bbr->idle_restart = 0; -+ bbr->full_bw_reached = 0; -+ bbr->full_bw = 0; - bbr->full_bw_cnt = 0; -- bbr_reset_lt_bw_sampling(sk); -- return tcp_snd_cwnd(tcp_sk(sk)); -+ bbr->cycle_mstamp = 0; -+ bbr->cycle_idx = 0; -+ -+ bbr_reset_startup_mode(sk); -+ -+ bbr->ack_epoch_mstamp = tp->tcp_mstamp; -+ bbr->ack_epoch_acked = 0; -+ bbr->extra_acked_win_rtts = 0; -+ bbr->extra_acked_win_idx = 0; -+ bbr->extra_acked[0] = 0; -+ bbr->extra_acked[1] = 0; -+ -+ bbr->ce_state = 0; -+ bbr->prior_rcv_nxt = tp->rcv_nxt; -+ bbr->try_fast_path = 0; -+ -+ cmpxchg(&sk->sk_pacing_status, SK_PACING_NONE, SK_PACING_NEEDED); -+ -+ /* Start sampling ECN mark rate after first full flight is ACKed: */ -+ bbr->loss_round_delivered = tp->delivered + 1; -+ bbr->loss_round_start = 0; -+ bbr->undo_bw_lo = 0; -+ bbr->undo_inflight_lo = 0; -+ bbr->undo_inflight_hi = 0; -+ bbr->loss_events_in_round = 0; -+ bbr->startup_ecn_rounds = 0; -+ bbr_reset_congestion_signals(sk); -+ bbr->bw_lo = ~0U; -+ bbr->bw_hi[0] = 0; -+ bbr->bw_hi[1] = 0; -+ bbr->inflight_lo = ~0U; -+ bbr->inflight_hi = ~0U; -+ bbr_reset_full_bw(sk); -+ bbr->bw_probe_up_cnt = ~0U; -+ bbr->bw_probe_up_acks = 0; -+ bbr->bw_probe_up_rounds = 0; -+ bbr->probe_wait_us = 0; -+ bbr->stopped_risky_probe = 0; -+ bbr->ack_phase = BBR_ACKS_INIT; -+ bbr->rounds_since_probe = 0; -+ bbr->bw_probe_samples = 0; -+ bbr->prev_probe_too_high = 0; -+ bbr->ecn_eligible = 0; -+ bbr->ecn_alpha = bbr_param(sk, ecn_alpha_init); -+ bbr->alpha_last_delivered = 0; -+ bbr->alpha_last_delivered_ce = 0; -+ bbr->plb.pause_until = 0; -+ -+ tp->fast_ack_mode = bbr_fast_ack_mode ? 1 : 0; -+ -+ if (bbr_can_use_ecn(sk)) -+ tp->ecn_flags |= TCP_ECN_ECT_PERMANENT; -+} -+ -+/* BBR marks the current round trip as a loss round. */ -+static void bbr_note_loss(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ /* Capture "current" data over the full round trip of loss, to -+ * have a better chance of observing the full capacity of the path. -+ */ -+ if (!bbr->loss_in_round) /* first loss in this round trip? */ -+ bbr->loss_round_delivered = tp->delivered; /* set round trip */ -+ bbr->loss_in_round = 1; -+ bbr->loss_in_cycle = 1; - } - --/* Entering loss recovery, so save cwnd for when we exit or undo recovery. */ -+/* Core TCP stack informs us that the given skb was just marked lost. */ -+__bpf_kfunc static void bbr_skb_marked_lost(struct sock *sk, -+ const struct sk_buff *skb) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ struct tcp_skb_cb *scb = TCP_SKB_CB(skb); -+ struct rate_sample rs = {}; -+ -+ bbr_note_loss(sk); -+ -+ if (!bbr->bw_probe_samples) -+ return; /* not an skb sent while probing for bandwidth */ -+ if (unlikely(!scb->tx.delivered_mstamp)) -+ return; /* skb was SACKed, reneged, marked lost; ignore it */ -+ /* We are probing for bandwidth. Construct a rate sample that -+ * estimates what happened in the flight leading up to this lost skb, -+ * then see if the loss rate went too high, and if so at which packet. -+ */ -+ rs.tx_in_flight = scb->tx.in_flight; -+ rs.lost = tp->lost - scb->tx.lost; -+ rs.is_app_limited = scb->tx.is_app_limited; -+ if (bbr_is_inflight_too_high(sk, &rs)) { -+ rs.tx_in_flight = bbr_inflight_hi_from_lost_skb(sk, &rs, skb); -+ bbr_handle_inflight_too_high(sk, &rs); -+ } -+} -+ -+static void bbr_run_loss_probe_recovery(struct sock *sk) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ struct bbr *bbr = inet_csk_ca(sk); -+ struct rate_sample rs = {0}; -+ -+ bbr_note_loss(sk); -+ -+ if (!bbr->bw_probe_samples) -+ return; /* not sent while probing for bandwidth */ -+ /* We are probing for bandwidth. Construct a rate sample that -+ * estimates what happened in the flight leading up to this -+ * loss, then see if the loss rate went too high. -+ */ -+ rs.lost = 1; /* TLP probe repaired loss of a single segment */ -+ rs.tx_in_flight = bbr->inflight_latest + rs.lost; -+ rs.is_app_limited = tp->tlp_orig_data_app_limited; -+ if (bbr_is_inflight_too_high(sk, &rs)) -+ bbr_handle_inflight_too_high(sk, &rs); -+} -+ -+/* Revert short-term model if current loss recovery event was spurious. */ -+__bpf_kfunc static u32 bbr_undo_cwnd(struct sock *sk) -+{ -+ struct bbr *bbr = inet_csk_ca(sk); -+ -+ bbr_reset_full_bw(sk); /* spurious slow-down; reset full bw detector */ -+ bbr->loss_in_round = 0; -+ -+ /* Revert to cwnd and other state saved before loss episode. */ -+ bbr->bw_lo = max(bbr->bw_lo, bbr->undo_bw_lo); -+ bbr->inflight_lo = max(bbr->inflight_lo, bbr->undo_inflight_lo); -+ bbr->inflight_hi = max(bbr->inflight_hi, bbr->undo_inflight_hi); -+ bbr->try_fast_path = 0; /* take slow path to set proper cwnd, pacing */ -+ return bbr->prior_cwnd; -+} -+ -+/* Entering loss recovery, so save state for when we undo recovery. */ - __bpf_kfunc static u32 bbr_ssthresh(struct sock *sk) - { -+ struct bbr *bbr = inet_csk_ca(sk); -+ - bbr_save_cwnd(sk); -+ /* For undo, save state that adapts based on loss signal. */ -+ bbr->undo_bw_lo = bbr->bw_lo; -+ bbr->undo_inflight_lo = bbr->inflight_lo; -+ bbr->undo_inflight_hi = bbr->inflight_hi; - return tcp_sk(sk)->snd_ssthresh; - } - -+static enum tcp_bbr_phase bbr_get_phase(struct bbr *bbr) -+{ -+ switch (bbr->mode) { -+ case BBR_STARTUP: -+ return BBR_PHASE_STARTUP; -+ case BBR_DRAIN: -+ return BBR_PHASE_DRAIN; -+ case BBR_PROBE_BW: -+ break; -+ case BBR_PROBE_RTT: -+ return BBR_PHASE_PROBE_RTT; -+ default: -+ return BBR_PHASE_INVALID; -+ } -+ switch (bbr->cycle_idx) { -+ case BBR_BW_PROBE_UP: -+ return BBR_PHASE_PROBE_BW_UP; -+ case BBR_BW_PROBE_DOWN: -+ return BBR_PHASE_PROBE_BW_DOWN; -+ case BBR_BW_PROBE_CRUISE: -+ return BBR_PHASE_PROBE_BW_CRUISE; -+ case BBR_BW_PROBE_REFILL: -+ return BBR_PHASE_PROBE_BW_REFILL; -+ default: -+ return BBR_PHASE_INVALID; -+ } -+} -+ - static size_t bbr_get_info(struct sock *sk, u32 ext, int *attr, -- union tcp_cc_info *info) -+ union tcp_cc_info *info) - { - if (ext & (1 << (INET_DIAG_BBRINFO - 1)) || - ext & (1 << (INET_DIAG_VEGASINFO - 1))) { -- struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); -- u64 bw = bbr_bw(sk); -- -- bw = bw * tp->mss_cache * USEC_PER_SEC >> BW_SCALE; -- memset(&info->bbr, 0, sizeof(info->bbr)); -- info->bbr.bbr_bw_lo = (u32)bw; -- info->bbr.bbr_bw_hi = (u32)(bw >> 32); -- info->bbr.bbr_min_rtt = bbr->min_rtt_us; -- info->bbr.bbr_pacing_gain = bbr->pacing_gain; -- info->bbr.bbr_cwnd_gain = bbr->cwnd_gain; -+ u64 bw = bbr_bw_bytes_per_sec(sk, bbr_bw(sk)); -+ u64 bw_hi = bbr_bw_bytes_per_sec(sk, bbr_max_bw(sk)); -+ u64 bw_lo = bbr->bw_lo == ~0U ? -+ ~0ULL : bbr_bw_bytes_per_sec(sk, bbr->bw_lo); -+ struct tcp_bbr_info *bbr_info = &info->bbr; -+ -+ memset(bbr_info, 0, sizeof(*bbr_info)); -+ bbr_info->bbr_bw_lo = (u32)bw; -+ bbr_info->bbr_bw_hi = (u32)(bw >> 32); -+ bbr_info->bbr_min_rtt = bbr->min_rtt_us; -+ bbr_info->bbr_pacing_gain = bbr->pacing_gain; -+ bbr_info->bbr_cwnd_gain = bbr->cwnd_gain; -+ bbr_info->bbr_bw_hi_lsb = (u32)bw_hi; -+ bbr_info->bbr_bw_hi_msb = (u32)(bw_hi >> 32); -+ bbr_info->bbr_bw_lo_lsb = (u32)bw_lo; -+ bbr_info->bbr_bw_lo_msb = (u32)(bw_lo >> 32); -+ bbr_info->bbr_mode = bbr->mode; -+ bbr_info->bbr_phase = (__u8)bbr_get_phase(bbr); -+ bbr_info->bbr_version = (__u8)BBR_VERSION; -+ bbr_info->bbr_inflight_lo = bbr->inflight_lo; -+ bbr_info->bbr_inflight_hi = bbr->inflight_hi; -+ bbr_info->bbr_extra_acked = bbr_extra_acked(sk); - *attr = INET_DIAG_BBRINFO; -- return sizeof(info->bbr); -+ return sizeof(*bbr_info); - } - return 0; - } - - __bpf_kfunc static void bbr_set_state(struct sock *sk, u8 new_state) - { -+ struct tcp_sock *tp = tcp_sk(sk); - struct bbr *bbr = inet_csk_ca(sk); - - if (new_state == TCP_CA_Loss) { -- struct rate_sample rs = { .losses = 1 }; - - bbr->prev_ca_state = TCP_CA_Loss; -- bbr->full_bw = 0; -- bbr->round_start = 1; /* treat RTO like end of a round */ -- bbr_lt_bw_sampling(sk, &rs); -+ tcp_plb_update_state_upon_rto(sk, &bbr->plb); -+ /* The tcp_write_timeout() call to sk_rethink_txhash() likely -+ * repathed this flow, so re-learn the min network RTT on the -+ * new path: -+ */ -+ bbr_reset_full_bw(sk); -+ if (!bbr_is_probing_bandwidth(sk) && bbr->inflight_lo == ~0U) { -+ /* bbr_adapt_lower_bounds() needs cwnd before -+ * we suffered an RTO, to update inflight_lo: -+ */ -+ bbr->inflight_lo = -+ max(tcp_snd_cwnd(tp), bbr->prior_cwnd); -+ } -+ } else if (bbr->prev_ca_state == TCP_CA_Loss && -+ new_state != TCP_CA_Loss) { -+ bbr_exit_loss_recovery(sk); - } - } - -+ - static struct tcp_congestion_ops tcp_bbr_cong_ops __read_mostly = { -- .flags = TCP_CONG_NON_RESTRICTED, -+ .flags = TCP_CONG_NON_RESTRICTED | TCP_CONG_WANTS_CE_EVENTS, - .name = "bbr", - .owner = THIS_MODULE, - .init = bbr_init, - .cong_control = bbr_main, - .sndbuf_expand = bbr_sndbuf_expand, -+ .skb_marked_lost = bbr_skb_marked_lost, - .undo_cwnd = bbr_undo_cwnd, - .cwnd_event = bbr_cwnd_event, - .ssthresh = bbr_ssthresh, -- .min_tso_segs = bbr_min_tso_segs, -+ .tso_segs = bbr_tso_segs, - .get_info = bbr_get_info, - .set_state = bbr_set_state, - }; -@@ -1159,10 +2359,11 @@ BTF_KFUNCS_START(tcp_bbr_check_kfunc_ids) - BTF_ID_FLAGS(func, bbr_init) - BTF_ID_FLAGS(func, bbr_main) - BTF_ID_FLAGS(func, bbr_sndbuf_expand) -+BTF_ID_FLAGS(func, bbr_skb_marked_lost) - BTF_ID_FLAGS(func, bbr_undo_cwnd) - BTF_ID_FLAGS(func, bbr_cwnd_event) - BTF_ID_FLAGS(func, bbr_ssthresh) --BTF_ID_FLAGS(func, bbr_min_tso_segs) -+BTF_ID_FLAGS(func, bbr_tso_segs) - BTF_ID_FLAGS(func, bbr_set_state) - BTF_KFUNCS_END(tcp_bbr_check_kfunc_ids) - -@@ -1195,5 +2396,12 @@ MODULE_AUTHOR("Van Jacobson <vanj@google.com>"); - MODULE_AUTHOR("Neal Cardwell <ncardwell@google.com>"); - MODULE_AUTHOR("Yuchung Cheng <ycheng@google.com>"); - MODULE_AUTHOR("Soheil Hassas Yeganeh <soheil@google.com>"); -+MODULE_AUTHOR("Priyaranjan Jha <priyarjha@google.com>"); -+MODULE_AUTHOR("Yousuk Seung <ysseung@google.com>"); -+MODULE_AUTHOR("Kevin Yang <yyd@google.com>"); -+MODULE_AUTHOR("Arjun Roy <arjunroy@google.com>"); -+MODULE_AUTHOR("David Morley <morleyd@google.com>"); -+ - MODULE_LICENSE("Dual BSD/GPL"); - MODULE_DESCRIPTION("TCP BBR (Bottleneck Bandwidth and RTT)"); -+MODULE_VERSION(__stringify(BBR_VERSION)); -diff --git a/net/ipv4/tcp_cong.c b/net/ipv4/tcp_cong.c -index 28ffcfbeef14..7b13915ba288 100644 ---- a/net/ipv4/tcp_cong.c -+++ b/net/ipv4/tcp_cong.c -@@ -237,6 +237,7 @@ void tcp_init_congestion_control(struct sock *sk) - struct inet_connection_sock *icsk = inet_csk(sk); - - tcp_sk(sk)->prior_ssthresh = 0; -+ tcp_sk(sk)->fast_ack_mode = 0; - if (icsk->icsk_ca_ops->init) - icsk->icsk_ca_ops->init(sk); - if (tcp_ca_needs_ecn(sk)) -diff --git a/net/ipv4/tcp_input.c b/net/ipv4/tcp_input.c -index 570e87ad9a56..c539ac50f7a6 100644 ---- a/net/ipv4/tcp_input.c -+++ b/net/ipv4/tcp_input.c -@@ -365,7 +365,7 @@ static void __tcp_ecn_check_ce(struct sock *sk, const struct sk_buff *skb) - tcp_enter_quickack_mode(sk, 2); - break; - case INET_ECN_CE: -- if (tcp_ca_needs_ecn(sk)) -+ if (tcp_ca_wants_ce_events(sk)) - tcp_ca_event(sk, CA_EVENT_ECN_IS_CE); - - if (!(tp->ecn_flags & TCP_ECN_DEMAND_CWR)) { -@@ -376,7 +376,7 @@ static void __tcp_ecn_check_ce(struct sock *sk, const struct sk_buff *skb) - tp->ecn_flags |= TCP_ECN_SEEN; - break; - default: -- if (tcp_ca_needs_ecn(sk)) -+ if (tcp_ca_wants_ce_events(sk)) - tcp_ca_event(sk, CA_EVENT_ECN_NO_CE); - tp->ecn_flags |= TCP_ECN_SEEN; - break; -@@ -1115,7 +1115,12 @@ static void tcp_verify_retransmit_hint(struct tcp_sock *tp, struct sk_buff *skb) - */ - static void tcp_notify_skb_loss_event(struct tcp_sock *tp, const struct sk_buff *skb) - { -+ struct sock *sk = (struct sock *)tp; -+ const struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops; -+ - tp->lost += tcp_skb_pcount(skb); -+ if (ca_ops->skb_marked_lost) -+ ca_ops->skb_marked_lost(sk, skb); - } - - void tcp_mark_skb_lost(struct sock *sk, struct sk_buff *skb) -@@ -1496,6 +1501,17 @@ static bool tcp_shifted_skb(struct sock *sk, struct sk_buff *prev, - WARN_ON_ONCE(tcp_skb_pcount(skb) < pcount); - tcp_skb_pcount_add(skb, -pcount); - -+ /* Adjust tx.in_flight as pcount is shifted from skb to prev. */ -+ if (WARN_ONCE(TCP_SKB_CB(skb)->tx.in_flight < pcount, -+ "prev in_flight: %u skb in_flight: %u pcount: %u", -+ TCP_SKB_CB(prev)->tx.in_flight, -+ TCP_SKB_CB(skb)->tx.in_flight, -+ pcount)) -+ TCP_SKB_CB(skb)->tx.in_flight = 0; -+ else -+ TCP_SKB_CB(skb)->tx.in_flight -= pcount; -+ TCP_SKB_CB(prev)->tx.in_flight += pcount; -+ - /* When we're adding to gso_segs == 1, gso_size will be zero, - * in theory this shouldn't be necessary but as long as DSACK - * code can come after this skb later on it's better to keep -@@ -3790,7 +3806,8 @@ static void tcp_replace_ts_recent(struct tcp_sock *tp, u32 seq) - /* This routine deals with acks during a TLP episode and ends an episode by - * resetting tlp_high_seq. Ref: TLP algorithm in draft-ietf-tcpm-rack - */ --static void tcp_process_tlp_ack(struct sock *sk, u32 ack, int flag) -+static void tcp_process_tlp_ack(struct sock *sk, u32 ack, int flag, -+ struct rate_sample *rs) - { - struct tcp_sock *tp = tcp_sk(sk); - -@@ -3807,6 +3824,7 @@ static void tcp_process_tlp_ack(struct sock *sk, u32 ack, int flag) - /* ACK advances: there was a loss, so reduce cwnd. Reset - * tlp_high_seq in tcp_init_cwnd_reduction() - */ -+ tcp_ca_event(sk, CA_EVENT_TLP_RECOVERY); - tcp_init_cwnd_reduction(sk); - tcp_set_ca_state(sk, TCP_CA_CWR); - tcp_end_cwnd_reduction(sk); -@@ -3817,6 +3835,11 @@ static void tcp_process_tlp_ack(struct sock *sk, u32 ack, int flag) - FLAG_NOT_DUP | FLAG_DATA_SACKED))) { - /* Pure dupack: original and TLP probe arrived; no loss */ - tp->tlp_high_seq = 0; -+ } else { -+ /* This ACK matches a TLP retransmit. We cannot yet tell if -+ * this ACK is for the original or the TLP retransmit. -+ */ -+ rs->is_acking_tlp_retrans_seq = 1; - } - } - -@@ -3925,6 +3948,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) - - prior_fack = tcp_is_sack(tp) ? tcp_highest_sack_seq(tp) : tp->snd_una; - rs.prior_in_flight = tcp_packets_in_flight(tp); -+ tcp_rate_check_app_limited(sk); - - /* ts_recent update must be made after we are sure that the packet - * is in window. -@@ -3999,7 +4023,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) - tcp_rack_update_reo_wnd(sk, &rs); - - if (tp->tlp_high_seq) -- tcp_process_tlp_ack(sk, ack, flag); -+ tcp_process_tlp_ack(sk, ack, flag, &rs); - - if (tcp_ack_is_dubious(sk, flag)) { - if (!(flag & (FLAG_SND_UNA_ADVANCED | -@@ -4023,6 +4047,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) - delivered = tcp_newly_delivered(sk, delivered, flag); - lost = tp->lost - lost; /* freshly marked lost */ - rs.is_ack_delayed = !!(flag & FLAG_ACK_MAYBE_DELAYED); -+ rs.is_ece = !!(flag & FLAG_ECE); - tcp_rate_gen(sk, delivered, lost, is_sack_reneg, sack_state.rate); - tcp_cong_control(sk, ack, delivered, flag, sack_state.rate); - tcp_xmit_recovery(sk, rexmit); -@@ -4042,7 +4067,7 @@ static int tcp_ack(struct sock *sk, const struct sk_buff *skb, int flag) - tcp_ack_probe(sk); - - if (tp->tlp_high_seq) -- tcp_process_tlp_ack(sk, ack, flag); -+ tcp_process_tlp_ack(sk, ack, flag, &rs); - return 1; - - old_ack: -@@ -5714,13 +5739,14 @@ static void __tcp_ack_snd_check(struct sock *sk, int ofo_possible) - - /* More than one full frame received... */ - if (((tp->rcv_nxt - tp->rcv_wup) > inet_csk(sk)->icsk_ack.rcv_mss && -+ (tp->fast_ack_mode == 1 || - /* ... and right edge of window advances far enough. - * (tcp_recvmsg() will send ACK otherwise). - * If application uses SO_RCVLOWAT, we want send ack now if - * we have not received enough bytes to satisfy the condition. - */ -- (tp->rcv_nxt - tp->copied_seq < sk->sk_rcvlowat || -- __tcp_select_window(sk) >= tp->rcv_wnd)) || -+ (tp->rcv_nxt - tp->copied_seq < sk->sk_rcvlowat || -+ __tcp_select_window(sk) >= tp->rcv_wnd))) || - /* We ACK each frame or... */ - tcp_in_quickack_mode(sk) || - /* Protocol state mandates a one-time immediate ACK */ -diff --git a/net/ipv4/tcp_minisocks.c b/net/ipv4/tcp_minisocks.c -index 0fbebf6266e9..6eb1d369c584 100644 ---- a/net/ipv4/tcp_minisocks.c -+++ b/net/ipv4/tcp_minisocks.c -@@ -460,6 +460,8 @@ void tcp_ca_openreq_child(struct sock *sk, const struct dst_entry *dst) - u32 ca_key = dst_metric(dst, RTAX_CC_ALGO); - bool ca_got_dst = false; - -+ tcp_set_ecn_low_from_dst(sk, dst); -+ - if (ca_key != TCP_CA_UNSPEC) { - const struct tcp_congestion_ops *ca; - -diff --git a/net/ipv4/tcp_output.c b/net/ipv4/tcp_output.c -index 95618d0e78e4..3f4bdd2b6476 100644 ---- a/net/ipv4/tcp_output.c -+++ b/net/ipv4/tcp_output.c -@@ -336,10 +336,9 @@ static void tcp_ecn_send_syn(struct sock *sk, struct sk_buff *skb) - bool bpf_needs_ecn = tcp_bpf_ca_needs_ecn(sk); - bool use_ecn = READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_ecn) == 1 || - tcp_ca_needs_ecn(sk) || bpf_needs_ecn; -+ const struct dst_entry *dst = __sk_dst_get(sk); - - if (!use_ecn) { -- const struct dst_entry *dst = __sk_dst_get(sk); -- - if (dst && dst_feature(dst, RTAX_FEATURE_ECN)) - use_ecn = true; - } -@@ -351,6 +350,9 @@ static void tcp_ecn_send_syn(struct sock *sk, struct sk_buff *skb) - tp->ecn_flags = TCP_ECN_OK; - if (tcp_ca_needs_ecn(sk) || bpf_needs_ecn) - INET_ECN_xmit(sk); -+ -+ if (dst) -+ tcp_set_ecn_low_from_dst(sk, dst); - } - } - -@@ -388,7 +390,8 @@ static void tcp_ecn_send(struct sock *sk, struct sk_buff *skb, - th->cwr = 1; - skb_shinfo(skb)->gso_type |= SKB_GSO_TCP_ECN; - } -- } else if (!tcp_ca_needs_ecn(sk)) { -+ } else if (!(tp->ecn_flags & TCP_ECN_ECT_PERMANENT) && -+ !tcp_ca_needs_ecn(sk)) { - /* ACK or retransmitted segment: clear ECT|CE */ - INET_ECN_dontxmit(sk); - } -@@ -1601,7 +1604,7 @@ int tcp_fragment(struct sock *sk, enum tcp_queue tcp_queue, - { - struct tcp_sock *tp = tcp_sk(sk); - struct sk_buff *buff; -- int old_factor; -+ int old_factor, inflight_prev; - long limit; - int nlen; - u8 flags; -@@ -1676,6 +1679,30 @@ int tcp_fragment(struct sock *sk, enum tcp_queue tcp_queue, - - if (diff) - tcp_adjust_pcount(sk, skb, diff); -+ -+ inflight_prev = TCP_SKB_CB(skb)->tx.in_flight - old_factor; -+ if (inflight_prev < 0) { -+ WARN_ONCE(tcp_skb_tx_in_flight_is_suspicious( -+ old_factor, -+ TCP_SKB_CB(skb)->sacked, -+ TCP_SKB_CB(skb)->tx.in_flight), -+ "inconsistent: tx.in_flight: %u " -+ "old_factor: %d mss: %u sacked: %u " -+ "1st pcount: %d 2nd pcount: %d " -+ "1st len: %u 2nd len: %u ", -+ TCP_SKB_CB(skb)->tx.in_flight, old_factor, -+ mss_now, TCP_SKB_CB(skb)->sacked, -+ tcp_skb_pcount(skb), tcp_skb_pcount(buff), -+ skb->len, buff->len); -+ inflight_prev = 0; -+ } -+ /* Set 1st tx.in_flight as if 1st were sent by itself: */ -+ TCP_SKB_CB(skb)->tx.in_flight = inflight_prev + -+ tcp_skb_pcount(skb); -+ /* Set 2nd tx.in_flight with new 1st and 2nd pcounts: */ -+ TCP_SKB_CB(buff)->tx.in_flight = inflight_prev + -+ tcp_skb_pcount(skb) + -+ tcp_skb_pcount(buff); - } - - /* Link BUFF into the send queue. */ -@@ -2033,13 +2060,12 @@ static u32 tcp_tso_autosize(const struct sock *sk, unsigned int mss_now, - static u32 tcp_tso_segs(struct sock *sk, unsigned int mss_now) - { - const struct tcp_congestion_ops *ca_ops = inet_csk(sk)->icsk_ca_ops; -- u32 min_tso, tso_segs; -- -- min_tso = ca_ops->min_tso_segs ? -- ca_ops->min_tso_segs(sk) : -- READ_ONCE(sock_net(sk)->ipv4.sysctl_tcp_min_tso_segs); -+ u32 tso_segs; - -- tso_segs = tcp_tso_autosize(sk, mss_now, min_tso); -+ tso_segs = ca_ops->tso_segs ? -+ ca_ops->tso_segs(sk, mss_now) : -+ tcp_tso_autosize(sk, mss_now, -+ sock_net(sk)->ipv4.sysctl_tcp_min_tso_segs); - return min_t(u32, tso_segs, sk->sk_gso_max_segs); - } - -@@ -2767,6 +2793,7 @@ static bool tcp_write_xmit(struct sock *sk, unsigned int mss_now, int nonagle, - skb_set_delivery_time(skb, tp->tcp_wstamp_ns, true); - list_move_tail(&skb->tcp_tsorted_anchor, &tp->tsorted_sent_queue); - tcp_init_tso_segs(skb, mss_now); -+ tcp_set_tx_in_flight(sk, skb); - goto repair; /* Skip network transmission */ - } - -@@ -2981,6 +3008,7 @@ void tcp_send_loss_probe(struct sock *sk) - if (WARN_ON(!skb || !tcp_skb_pcount(skb))) - goto rearm_timer; - -+ tp->tlp_orig_data_app_limited = TCP_SKB_CB(skb)->tx.is_app_limited; - if (__tcp_retransmit_skb(sk, skb, 1)) - goto rearm_timer; - -diff --git a/net/ipv4/tcp_rate.c b/net/ipv4/tcp_rate.c -index a8f6d9d06f2e..8737f2134648 100644 ---- a/net/ipv4/tcp_rate.c -+++ b/net/ipv4/tcp_rate.c -@@ -34,6 +34,24 @@ - * ready to send in the write queue. - */ - -+void tcp_set_tx_in_flight(struct sock *sk, struct sk_buff *skb) -+{ -+ struct tcp_sock *tp = tcp_sk(sk); -+ u32 in_flight; -+ -+ /* Check, sanitize, and record packets in flight after skb was sent. */ -+ in_flight = tcp_packets_in_flight(tp) + tcp_skb_pcount(skb); -+ if (WARN_ONCE(in_flight > TCPCB_IN_FLIGHT_MAX, -+ "insane in_flight %u cc %s mss %u " -+ "cwnd %u pif %u %u %u %u\n", -+ in_flight, inet_csk(sk)->icsk_ca_ops->name, -+ tp->mss_cache, tp->snd_cwnd, -+ tp->packets_out, tp->retrans_out, -+ tp->sacked_out, tp->lost_out)) -+ in_flight = TCPCB_IN_FLIGHT_MAX; -+ TCP_SKB_CB(skb)->tx.in_flight = in_flight; -+} -+ - /* Snapshot the current delivery information in the skb, to generate - * a rate sample later when the skb is (s)acked in tcp_rate_skb_delivered(). - */ -@@ -66,7 +84,9 @@ void tcp_rate_skb_sent(struct sock *sk, struct sk_buff *skb) - TCP_SKB_CB(skb)->tx.delivered_mstamp = tp->delivered_mstamp; - TCP_SKB_CB(skb)->tx.delivered = tp->delivered; - TCP_SKB_CB(skb)->tx.delivered_ce = tp->delivered_ce; -+ TCP_SKB_CB(skb)->tx.lost = tp->lost; - TCP_SKB_CB(skb)->tx.is_app_limited = tp->app_limited ? 1 : 0; -+ tcp_set_tx_in_flight(sk, skb); - } - - /* When an skb is sacked or acked, we fill in the rate sample with the (prior) -@@ -91,18 +111,21 @@ void tcp_rate_skb_delivered(struct sock *sk, struct sk_buff *skb, - if (!rs->prior_delivered || - tcp_skb_sent_after(tx_tstamp, tp->first_tx_mstamp, - scb->end_seq, rs->last_end_seq)) { -+ rs->prior_lost = scb->tx.lost; - rs->prior_delivered_ce = scb->tx.delivered_ce; - rs->prior_delivered = scb->tx.delivered; - rs->prior_mstamp = scb->tx.delivered_mstamp; - rs->is_app_limited = scb->tx.is_app_limited; - rs->is_retrans = scb->sacked & TCPCB_RETRANS; -+ rs->tx_in_flight = scb->tx.in_flight; - rs->last_end_seq = scb->end_seq; - - /* Record send time of most recently ACKed packet: */ - tp->first_tx_mstamp = tx_tstamp; - /* Find the duration of the "send phase" of this window: */ -- rs->interval_us = tcp_stamp_us_delta(tp->first_tx_mstamp, -- scb->tx.first_tx_mstamp); -+ rs->interval_us = tcp_stamp32_us_delta( -+ tp->first_tx_mstamp, -+ scb->tx.first_tx_mstamp); - - } - /* Mark off the skb delivered once it's sacked to avoid being -@@ -144,6 +167,7 @@ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, - return; - } - rs->delivered = tp->delivered - rs->prior_delivered; -+ rs->lost = tp->lost - rs->prior_lost; - - rs->delivered_ce = tp->delivered_ce - rs->prior_delivered_ce; - /* delivered_ce occupies less than 32 bits in the skb control block */ -@@ -155,7 +179,7 @@ void tcp_rate_gen(struct sock *sk, u32 delivered, u32 lost, - * longer phase. - */ - snd_us = rs->interval_us; /* send phase */ -- ack_us = tcp_stamp_us_delta(tp->tcp_mstamp, -+ ack_us = tcp_stamp32_us_delta(tp->tcp_mstamp, - rs->prior_mstamp); /* ack phase */ - rs->interval_us = max(snd_us, ack_us); - -diff --git a/net/ipv4/tcp_timer.c b/net/ipv4/tcp_timer.c -index 4d40615dc8fc..f27941201ef2 100644 ---- a/net/ipv4/tcp_timer.c -+++ b/net/ipv4/tcp_timer.c -@@ -689,6 +689,7 @@ void tcp_write_timer_handler(struct sock *sk) - return; - } - -+ tcp_rate_check_app_limited(sk); - tcp_mstamp_refresh(tcp_sk(sk)); - event = icsk->icsk_pending; - --- -2.46.0.rc1 - diff --git a/SOURCES/cachy-bore.patch b/SOURCES/cachy-bore.patch index 7421807..f15d6da 100644 --- a/SOURCES/cachy-bore.patch +++ b/SOURCES/cachy-bore.patch @@ -1,24 +1,53 @@ -From 3816495f5635104fae1dda21b743f750c2914196 Mon Sep 17 00:00:00 2001 -From: Eric Naim <dnaim@proton.me> -Date: Sat, 3 Aug 2024 15:23:30 +0700 -Subject: [PATCH] bore +From 2328e7500823151cb2f119b847454e63e9da0f64 Mon Sep 17 00:00:00 2001 +From: Masahito S <firelzrd@gmail.com> +Date: Thu, 3 Oct 2024 17:33:57 +0900 +Subject: [PATCH] linux6.11.y-bore5.6.0 --- - include/linux/sched.h | 10 ++ - init/Kconfig | 17 +++ - kernel/Kconfig.hz | 16 ++ - kernel/sched/core.c | 143 ++++++++++++++++++ - kernel/sched/debug.c | 60 +++++++- - kernel/sched/fair.c | 322 ++++++++++++++++++++++++++++++++++++++-- - kernel/sched/features.h | 22 ++- - kernel/sched/sched.h | 7 + - 8 files changed, 583 insertions(+), 14 deletions(-) + include/linux/sched.h | 20 +- + include/linux/sched/bore.h | 37 ++++ + init/Kconfig | 17 ++ + kernel/Kconfig.hz | 17 ++ + kernel/fork.c | 5 + + kernel/sched/Makefile | 1 + + kernel/sched/bore.c | 380 +++++++++++++++++++++++++++++++++++++ + kernel/sched/core.c | 7 + + kernel/sched/debug.c | 60 +++++- + kernel/sched/fair.c | 89 ++++++++- + kernel/sched/features.h | 4 + + kernel/sched/sched.h | 7 + + 12 files changed, 639 insertions(+), 5 deletions(-) + create mode 100644 include/linux/sched/bore.h + create mode 100644 kernel/sched/bore.c diff --git a/include/linux/sched.h b/include/linux/sched.h -index 76214d7c8..9f65d367b 100644 +index f8d150343d..2481cf0125 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h -@@ -547,6 +547,16 @@ struct sched_entity { +@@ -535,6 +535,14 @@ struct sched_statistics { + #endif /* CONFIG_SCHEDSTATS */ + } ____cacheline_aligned; + ++#ifdef CONFIG_SCHED_BORE ++struct sched_burst_cache { ++ u8 score; ++ u32 count; ++ u64 timestamp; ++}; ++#endif // CONFIG_SCHED_BORE ++ + struct sched_entity { + /* For load-balancing: */ + struct load_weight load; +@@ -543,12 +551,22 @@ struct sched_entity { + u64 min_vruntime; + + struct list_head group_node; +- unsigned int on_rq; ++ unsigned char on_rq; ++ unsigned char rel_deadline; + + u64 exec_start; u64 sum_exec_runtime; u64 prev_sum_exec_runtime; u64 vruntime; @@ -28,18 +57,60 @@ index 76214d7c8..9f65d367b 100644 + u8 curr_burst_penalty; + u8 burst_penalty; + u8 burst_score; -+ u8 child_burst; -+ u32 child_burst_cnt; -+ u64 child_burst_last_cached; ++ struct sched_burst_cache child_burst; ++ struct sched_burst_cache group_burst; +#endif // CONFIG_SCHED_BORE s64 vlag; u64 slice; +diff --git a/include/linux/sched/bore.h b/include/linux/sched/bore.h +new file mode 100644 +index 0000000000..12a613a94f +--- /dev/null ++++ b/include/linux/sched/bore.h +@@ -0,0 +1,37 @@ ++ ++#include <linux/sched.h> ++#include <linux/sched/cputime.h> ++ ++#ifndef _LINUX_SCHED_BORE_H ++#define _LINUX_SCHED_BORE_H ++ ++#ifdef CONFIG_SCHED_BORE ++extern u8 __read_mostly sched_bore; ++extern u8 __read_mostly sched_burst_exclude_kthreads; ++extern u8 __read_mostly sched_burst_smoothness_long; ++extern u8 __read_mostly sched_burst_smoothness_short; ++extern u8 __read_mostly sched_burst_fork_atavistic; ++extern u8 __read_mostly sched_burst_parity_threshold; ++extern u8 __read_mostly sched_burst_penalty_offset; ++extern uint __read_mostly sched_burst_penalty_scale; ++extern uint __read_mostly sched_burst_cache_lifetime; ++extern uint __read_mostly sched_deadline_boost_mask; ++ ++extern void update_burst_score(struct sched_entity *se); ++extern void update_burst_penalty(struct sched_entity *se); ++ ++extern void restart_burst(struct sched_entity *se); ++extern void restart_burst_rescale_deadline(struct sched_entity *se); ++ ++extern int sched_bore_update_handler(const struct ctl_table *table, int write, ++ void __user *buffer, size_t *lenp, loff_t *ppos); ++ ++extern void sched_clone_bore( ++ struct task_struct *p, struct task_struct *parent, u64 clone_flags); ++ ++extern void init_task_bore(struct task_struct *p); ++ ++extern void reweight_entity( ++ struct cfs_rq *cfs_rq, struct sched_entity *se, unsigned long weight); ++#endif // CONFIG_SCHED_BORE ++#endif // _LINUX_SCHED_BORE_H diff --git a/init/Kconfig b/init/Kconfig -index febdea2af..171b5d995 100644 +index 5783a0b875..b648ed538c 100644 --- a/init/Kconfig +++ b/init/Kconfig -@@ -1283,6 +1283,23 @@ config CHECKPOINT_RESTORE +@@ -1297,6 +1297,23 @@ config CHECKPOINT_RESTORE If unsure, say N here. @@ -64,10 +135,10 @@ index febdea2af..171b5d995 100644 bool "Automatic process group scheduling" select CGROUPS diff --git a/kernel/Kconfig.hz b/kernel/Kconfig.hz -index 38ef6d068..5f6eecd1e 100644 +index 38ef6d0688..253c566b59 100644 --- a/kernel/Kconfig.hz +++ b/kernel/Kconfig.hz -@@ -55,5 +55,21 @@ config HZ +@@ -55,5 +55,22 @@ config HZ default 300 if HZ_300 default 1000 if HZ_1000 @@ -78,7 +149,8 @@ index 38ef6d068..5f6eecd1e 100644 + The BORE Scheduler automatically calculates the optimal base + slice for the configured HZ using the following equation: + -+ base_slice_ns = max(min_base_slice_ns, 1000000000/HZ) ++ base_slice_ns = ++ 1000000000/HZ * DIV_ROUNDUP(min_base_slice_ns, 1000000000/HZ) + + This option sets the default lower bound limit of the base slice + to prevent the loss of task throughput due to overscheduling. @@ -89,32 +161,188 @@ index 38ef6d068..5f6eecd1e 100644 + config SCHED_HRTICK def_bool HIGH_RES_TIMERS -diff --git a/kernel/sched/core.c b/kernel/sched/core.c -index ebf21373f..5d1c97612 100644 ---- a/kernel/sched/core.c -+++ b/kernel/sched/core.c -@@ -4512,6 +4512,138 @@ int wake_up_state(struct task_struct *p, unsigned int state) - return try_to_wake_up(p, state, 0); - } +diff --git a/kernel/fork.c b/kernel/fork.c +index cc760491f2..179b884da3 100644 +--- a/kernel/fork.c ++++ b/kernel/fork.c +@@ -111,6 +111,8 @@ + #include <asm/cacheflush.h> + #include <asm/tlbflush.h> + ++#include <linux/sched/bore.h> ++ + #include <trace/events/sched.h> + + #define CREATE_TRACE_POINTS +@@ -2344,6 +2346,9 @@ __latent_entropy struct task_struct *copy_process( + retval = sched_fork(clone_flags, p); + if (retval) + goto bad_fork_cleanup_policy; ++#ifdef CONFIG_SCHED_BORE ++ sched_clone_bore(p, current, clone_flags); ++#endif // CONFIG_SCHED_BORE + retval = perf_event_init_task(p, clone_flags); + if (retval) +diff --git a/kernel/sched/Makefile b/kernel/sched/Makefile +index 976092b7bd..293aad6754 100644 +--- a/kernel/sched/Makefile ++++ b/kernel/sched/Makefile +@@ -32,3 +32,4 @@ obj-y += core.o + obj-y += fair.o + obj-y += build_policy.o + obj-y += build_utility.o ++obj-y += bore.o +diff --git a/kernel/sched/bore.c b/kernel/sched/bore.c +new file mode 100644 +index 0000000000..62a0191a32 +--- /dev/null ++++ b/kernel/sched/bore.c +@@ -0,0 +1,380 @@ ++/* ++ * Burst-Oriented Response Enhancer (BORE) CPU Scheduler ++ * Copyright (C) 2021-2024 Masahito Suzuki <firelzrd@gmail.com> ++ */ ++#include <linux/cpuset.h> ++#include <linux/sched/bore.h> ++#include "sched.h" ++ +#ifdef CONFIG_SCHED_BORE -+extern u8 sched_burst_fork_atavistic; -+extern uint sched_burst_cache_lifetime; -+ -+static void __init sched_init_bore(void) { -+ init_task.se.burst_time = 0; -+ init_task.se.prev_burst_penalty = 0; -+ init_task.se.curr_burst_penalty = 0; -+ init_task.se.burst_penalty = 0; -+ init_task.se.burst_score = 0; -+ init_task.se.child_burst_last_cached = 0; ++u8 __read_mostly sched_bore = 1; ++u8 __read_mostly sched_burst_exclude_kthreads = 1; ++u8 __read_mostly sched_burst_smoothness_long = 1; ++u8 __read_mostly sched_burst_smoothness_short = 0; ++u8 __read_mostly sched_burst_fork_atavistic = 2; ++u8 __read_mostly sched_burst_parity_threshold = 2; ++u8 __read_mostly sched_burst_penalty_offset = 24; ++uint __read_mostly sched_burst_penalty_scale = 1280; ++uint __read_mostly sched_burst_cache_lifetime = 60000000; ++uint __read_mostly sched_deadline_boost_mask = ENQUEUE_INITIAL ++ | ENQUEUE_WAKEUP; ++static int __maybe_unused sixty_four = 64; ++static int __maybe_unused maxval_u8 = 255; ++static int __maybe_unused maxval_12_bits = 4095; ++ ++#define MAX_BURST_PENALTY (39U <<2) ++ ++static inline u32 log2plus1_u64_u32f8(u64 v) { ++ u32 integral = fls64(v); ++ u8 fractional = v << (64 - integral) >> 55; ++ return integral << 8 | fractional; +} + -+inline void sched_fork_bore(struct task_struct *p) { -+ p->se.burst_time = 0; -+ p->se.curr_burst_penalty = 0; -+ p->se.burst_score = 0; -+ p->se.child_burst_last_cached = 0; ++static inline u32 calc_burst_penalty(u64 burst_time) { ++ u32 greed, tolerance, penalty, scaled_penalty; ++ ++ greed = log2plus1_u64_u32f8(burst_time); ++ tolerance = sched_burst_penalty_offset << 8; ++ penalty = max(0, (s32)(greed - tolerance)); ++ scaled_penalty = penalty * sched_burst_penalty_scale >> 16; ++ ++ return min(MAX_BURST_PENALTY, scaled_penalty); ++} ++ ++static inline u64 __scale_slice(u64 delta, u8 score) ++{return mul_u64_u32_shr(delta, sched_prio_to_wmult[score], 22);} ++ ++static inline u64 __unscale_slice(u64 delta, u8 score) ++{return mul_u64_u32_shr(delta, sched_prio_to_weight[score], 10);} ++ ++static void reweight_task_by_prio(struct task_struct *p, int prio) { ++ struct sched_entity *se = &p->se; ++ unsigned long weight = scale_load(sched_prio_to_weight[prio]); ++ ++ reweight_entity(cfs_rq_of(se), se, weight); ++ se->load.inv_weight = sched_prio_to_wmult[prio]; ++} ++ ++static inline u8 effective_prio(struct task_struct *p) { ++ u8 prio = p->static_prio - MAX_RT_PRIO; ++ if (likely(sched_bore)) ++ prio += p->se.burst_score; ++ return min(39, prio); ++} ++ ++void update_burst_score(struct sched_entity *se) { ++ if (!entity_is_task(se)) return; ++ struct task_struct *p = task_of(se); ++ u8 prev_prio = effective_prio(p); ++ ++ u8 burst_score = 0; ++ if (!((p->flags & PF_KTHREAD) && likely(sched_burst_exclude_kthreads))) ++ burst_score = se->burst_penalty >> 2; ++ se->burst_score = burst_score; ++ ++ u8 new_prio = effective_prio(p); ++ if (new_prio != prev_prio) ++ reweight_task_by_prio(p, new_prio); ++} ++ ++void update_burst_penalty(struct sched_entity *se) { ++ se->curr_burst_penalty = calc_burst_penalty(se->burst_time); ++ se->burst_penalty = max(se->prev_burst_penalty, se->curr_burst_penalty); ++ update_burst_score(se); ++} ++ ++static inline u32 binary_smooth(u32 new, u32 old) { ++ int increment = new - old; ++ return (0 <= increment)? ++ old + ( increment >> (int)sched_burst_smoothness_long): ++ old - (-increment >> (int)sched_burst_smoothness_short); ++} ++ ++static void revolve_burst_penalty(struct sched_entity *se) { ++ se->prev_burst_penalty = ++ binary_smooth(se->curr_burst_penalty, se->prev_burst_penalty); ++ se->burst_time = 0; ++ se->curr_burst_penalty = 0; ++} ++ ++inline void restart_burst(struct sched_entity *se) { ++ revolve_burst_penalty(se); ++ se->burst_penalty = se->prev_burst_penalty; ++ update_burst_score(se); ++} ++ ++void restart_burst_rescale_deadline(struct sched_entity *se) { ++ s64 vscaled, wremain, vremain = se->deadline - se->vruntime; ++ struct task_struct *p = task_of(se); ++ u8 prev_prio = effective_prio(p); ++ restart_burst(se); ++ u8 new_prio = effective_prio(p); ++ if (prev_prio > new_prio) { ++ wremain = __unscale_slice(abs(vremain), prev_prio); ++ vscaled = __scale_slice(wremain, new_prio); ++ if (unlikely(vremain < 0)) ++ vscaled = -vscaled; ++ se->deadline = se->vruntime + vscaled; ++ } ++} ++ ++static void reset_task_weights_bore(void) { ++ struct task_struct *task; ++ struct rq *rq; ++ struct rq_flags rf; ++ ++ write_lock_irq(&tasklist_lock); ++ for_each_process(task) { ++ rq = task_rq(task); ++ rq_lock_irqsave(rq, &rf); ++ reweight_task_by_prio(task, effective_prio(task)); ++ rq_unlock_irqrestore(rq, &rf); ++ } ++ write_unlock_irq(&tasklist_lock); ++} ++ ++int sched_bore_update_handler(const struct ctl_table *table, int write, ++ void __user *buffer, size_t *lenp, loff_t *ppos) { ++ int ret = proc_dou8vec_minmax(table, write, buffer, lenp, ppos); ++ if (ret || !write) ++ return ret; ++ ++ reset_task_weights_bore(); ++ ++ return 0; +} + +static u32 count_child_tasks(struct task_struct *p) { @@ -124,52 +352,45 @@ index ebf21373f..5d1c97612 100644 + return cnt; +} + -+static inline bool task_is_inheritable(struct task_struct *p) { -+ return (p->sched_class == &fair_sched_class); -+} ++static inline bool task_is_bore_eligible(struct task_struct *p) ++{return p->sched_class == &fair_sched_class;} + -+static inline bool child_burst_cache_expired(struct task_struct *p, u64 now) { -+ u64 expiration_time = -+ p->se.child_burst_last_cached + sched_burst_cache_lifetime; -+ return ((s64)(expiration_time - now) < 0); -+} ++static inline bool burst_cache_expired(struct sched_burst_cache *bc, u64 now) ++{return (s64)(bc->timestamp + sched_burst_cache_lifetime - now) < 0;} + -+static void __update_child_burst_cache( -+ struct task_struct *p, u32 cnt, u32 sum, u64 now) { -+ u8 avg = 0; -+ if (cnt) avg = sum / cnt; -+ p->se.child_burst = max(avg, p->se.burst_penalty); -+ p->se.child_burst_cnt = cnt; -+ p->se.child_burst_last_cached = now; ++static void update_burst_cache(struct sched_burst_cache *bc, ++ struct task_struct *p, u32 cnt, u32 sum, u64 now) { ++ u8 avg = cnt ? sum / cnt : 0; ++ bc->score = max(avg, p->se.burst_penalty); ++ bc->count = cnt; ++ bc->timestamp = now; +} + +static inline void update_child_burst_direct(struct task_struct *p, u64 now) { ++ u32 cnt = 0, sum = 0; + struct task_struct *child; -+ u32 cnt = 0; -+ u32 sum = 0; + + list_for_each_entry(child, &p->children, sibling) { -+ if (!task_is_inheritable(child)) continue; ++ if (!task_is_bore_eligible(child)) continue; + cnt++; + sum += child->se.burst_penalty; + } + -+ __update_child_burst_cache(p, cnt, sum, now); ++ update_burst_cache(&p->se.child_burst, p, cnt, sum, now); +} + -+static inline u8 __inherit_burst_direct(struct task_struct *p, u64 now) { -+ struct task_struct *parent = p->real_parent; -+ if (child_burst_cache_expired(parent, now)) ++static inline u8 inherit_burst_direct(struct task_struct *p, u64 now) { ++ struct task_struct *parent = p; ++ if (burst_cache_expired(&parent->se.child_burst, now)) + update_child_burst_direct(parent, now); + -+ return parent->se.child_burst; ++ return parent->se.child_burst.score; +} + +static void update_child_burst_topological( + struct task_struct *p, u64 now, u32 depth, u32 *acnt, u32 *asum) { ++ u32 cnt = 0, dcnt = 0, sum = 0; + struct task_struct *child, *dec; -+ u32 cnt = 0, dcnt = 0; -+ u32 sum = 0; + + list_for_each_entry(child, &p->children, sibling) { + dec = child; @@ -177,95 +398,214 @@ index ebf21373f..5d1c97612 100644 + dec = list_first_entry(&dec->children, struct task_struct, sibling); + + if (!dcnt || !depth) { -+ if (!task_is_inheritable(dec)) continue; ++ if (!task_is_bore_eligible(dec)) continue; + cnt++; + sum += dec->se.burst_penalty; + continue; + } -+ if (!child_burst_cache_expired(dec, now)) { -+ cnt += dec->se.child_burst_cnt; -+ sum += (u32)dec->se.child_burst * dec->se.child_burst_cnt; ++ if (!burst_cache_expired(&dec->se.child_burst, now)) { ++ cnt += dec->se.child_burst.count; ++ sum += (u32)dec->se.child_burst.score * dec->se.child_burst.count; + continue; + } + update_child_burst_topological(dec, now, depth - 1, &cnt, &sum); + } + -+ __update_child_burst_cache(p, cnt, sum, now); ++ update_burst_cache(&p->se.child_burst, p, cnt, sum, now); + *acnt += cnt; + *asum += sum; +} + -+static inline u8 __inherit_burst_topological(struct task_struct *p, u64 now) { -+ struct task_struct *anc = p->real_parent; ++static inline u8 inherit_burst_topological(struct task_struct *p, u64 now) { ++ struct task_struct *anc = p; + u32 cnt = 0, sum = 0; + + while (anc->real_parent != anc && count_child_tasks(anc) == 1) + anc = anc->real_parent; + -+ if (child_burst_cache_expired(anc, now)) ++ if (burst_cache_expired(&anc->se.child_burst, now)) + update_child_burst_topological( + anc, now, sched_burst_fork_atavistic - 1, &cnt, &sum); + -+ return anc->se.child_burst; ++ return anc->se.child_burst.score; +} + -+static inline void inherit_burst(struct task_struct *p) { -+ u8 burst_cache; -+ u64 now = ktime_get_ns(); ++static inline void update_tg_burst(struct task_struct *p, u64 now) { ++ struct task_struct *task; ++ u32 cnt = 0, sum = 0; + ++ for_each_thread(p, task) { ++ if (!task_is_bore_eligible(task)) continue; ++ cnt++; ++ sum += task->se.burst_penalty; ++ } ++ ++ update_burst_cache(&p->se.group_burst, p, cnt, sum, now); ++} ++ ++static inline u8 inherit_burst_tg(struct task_struct *p, u64 now) { ++ struct task_struct *parent = p->group_leader; ++ if (burst_cache_expired(&parent->se.group_burst, now)) ++ update_tg_burst(parent, now); ++ ++ return parent->se.group_burst.score; ++} ++ ++void sched_clone_bore( ++ struct task_struct *p, struct task_struct *parent, u64 clone_flags) { ++ if (!task_is_bore_eligible(p)) return; ++ ++ u64 now = ktime_get_ns(); + read_lock(&tasklist_lock); -+ burst_cache = likely(sched_burst_fork_atavistic)? -+ __inherit_burst_topological(p, now): -+ __inherit_burst_direct(p, now); ++ u8 penalty = (clone_flags & CLONE_THREAD) ? ++ inherit_burst_tg(parent, now) : ++ likely(sched_burst_fork_atavistic) ? ++ inherit_burst_topological(parent, now): ++ inherit_burst_direct(parent, now); + read_unlock(&tasklist_lock); + -+ p->se.prev_burst_penalty = max(p->se.prev_burst_penalty, burst_cache); ++ struct sched_entity *se = &p->se; ++ revolve_burst_penalty(se); ++ se->burst_penalty = se->prev_burst_penalty = ++ max(se->prev_burst_penalty, penalty); ++ se->child_burst.timestamp = 0; ++ se->group_burst.timestamp = 0; +} + -+static void sched_post_fork_bore(struct task_struct *p) { -+ if (p->sched_class == &fair_sched_class) -+ inherit_burst(p); -+ p->se.burst_penalty = p->se.prev_burst_penalty; ++void init_task_bore(struct task_struct *p) { ++ p->se.burst_time = 0; ++ p->se.prev_burst_penalty = 0; ++ p->se.curr_burst_penalty = 0; ++ p->se.burst_penalty = 0; ++ p->se.burst_score = 0; ++ memset(&p->se.child_burst, 0, sizeof(struct sched_burst_cache)); ++ memset(&p->se.group_burst, 0, sizeof(struct sched_burst_cache)); +} -+#endif // CONFIG_SCHED_BORE + - /* - * Perform scheduler related setup for a newly forked process p. - * p is forked by current. -@@ -4528,6 +4660,9 @@ static void __sched_fork(unsigned long clone_flags, struct task_struct *p) - p->se.prev_sum_exec_runtime = 0; - p->se.nr_migrations = 0; - p->se.vruntime = 0; -+#ifdef CONFIG_SCHED_BORE -+ sched_fork_bore(p); ++#ifdef CONFIG_SYSCTL ++static struct ctl_table sched_bore_sysctls[] = { ++ { ++ .procname = "sched_bore", ++ .data = &sched_bore, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = sched_bore_update_handler, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = SYSCTL_ONE, ++ }, ++ { ++ .procname = "sched_burst_exclude_kthreads", ++ .data = &sched_burst_exclude_kthreads, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = SYSCTL_ONE, ++ }, ++ { ++ .procname = "sched_burst_smoothness_long", ++ .data = &sched_burst_smoothness_long, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = SYSCTL_ONE, ++ }, ++ { ++ .procname = "sched_burst_smoothness_short", ++ .data = &sched_burst_smoothness_short, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = SYSCTL_ONE, ++ }, ++ { ++ .procname = "sched_burst_fork_atavistic", ++ .data = &sched_burst_fork_atavistic, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = SYSCTL_THREE, ++ }, ++ { ++ .procname = "sched_burst_parity_threshold", ++ .data = &sched_burst_parity_threshold, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = &maxval_u8, ++ }, ++ { ++ .procname = "sched_burst_penalty_offset", ++ .data = &sched_burst_penalty_offset, ++ .maxlen = sizeof(u8), ++ .mode = 0644, ++ .proc_handler = proc_dou8vec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = &sixty_four, ++ }, ++ { ++ .procname = "sched_burst_penalty_scale", ++ .data = &sched_burst_penalty_scale, ++ .maxlen = sizeof(uint), ++ .mode = 0644, ++ .proc_handler = proc_douintvec_minmax, ++ .extra1 = SYSCTL_ZERO, ++ .extra2 = &maxval_12_bits, ++ }, ++ { ++ .procname = "sched_burst_cache_lifetime", ++ .data = &sched_burst_cache_lifetime, ++ .maxlen = sizeof(uint), ++ .mode = 0644, ++ .proc_handler = proc_douintvec, ++ }, ++ { ++ .procname = "sched_deadline_boost_mask", ++ .data = &sched_deadline_boost_mask, ++ .maxlen = sizeof(uint), ++ .mode = 0644, ++ .proc_handler = proc_douintvec, ++ }, ++}; ++ ++static int __init sched_bore_sysctl_init(void) { ++ register_sysctl_init("kernel", sched_bore_sysctls); ++ return 0; ++} ++late_initcall(sched_bore_sysctl_init); ++#endif // CONFIG_SYSCTL +#endif // CONFIG_SCHED_BORE - p->se.vlag = 0; - p->se.slice = sysctl_sched_base_slice; - INIT_LIST_HEAD(&p->se.group_node); -@@ -4843,6 +4978,9 @@ void sched_cgroup_fork(struct task_struct *p, struct kernel_clone_args *kargs) +diff --git a/kernel/sched/core.c b/kernel/sched/core.c +index f3951e4a55..9264e542c9 100644 +--- a/kernel/sched/core.c ++++ b/kernel/sched/core.c +@@ -97,6 +97,8 @@ + #include "../../io_uring/io-wq.h" + #include "../smpboot.h" - void sched_post_fork(struct task_struct *p) - { -+#ifdef CONFIG_SCHED_BORE -+ sched_post_fork_bore(p); -+#endif // CONFIG_SCHED_BORE - uclamp_post_fork(p); - } ++#include <linux/sched/bore.h> ++ + EXPORT_TRACEPOINT_SYMBOL_GPL(ipi_send_cpu); + EXPORT_TRACEPOINT_SYMBOL_GPL(ipi_send_cpumask); -@@ -9930,6 +10068,11 @@ void __init sched_init(void) +@@ -8197,6 +8199,11 @@ void __init sched_init(void) BUG_ON(&dl_sched_class != &stop_sched_class + 1); #endif +#ifdef CONFIG_SCHED_BORE -+ sched_init_bore(); -+ printk(KERN_INFO "BORE (Burst-Oriented Response Enhancer) CPU Scheduler modification 5.2.8 by Masahito Suzuki"); ++ printk(KERN_INFO "BORE (Burst-Oriented Response Enhancer) CPU Scheduler modification 5.6.0 by Masahito Suzuki"); ++ init_task_bore(&init_task); +#endif // CONFIG_SCHED_BORE + wait_bit_init(); #ifdef CONFIG_FAIR_GROUP_SCHED diff --git a/kernel/sched/debug.c b/kernel/sched/debug.c -index c1eb9a1af..e2da8d773 100644 +index c1eb9a1afd..e2da8d7738 100644 --- a/kernel/sched/debug.c +++ b/kernel/sched/debug.c @@ -167,7 +167,52 @@ static const struct file_operations sched_feat_fops = { @@ -372,21 +712,20 @@ index c1eb9a1af..e2da8d773 100644 P(se.avg.runnable_sum); P(se.avg.util_sum); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c -index 483c137b9..4c8d7fbd5 100644 +index 9057584ec0..465d2626ee 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c -@@ -19,6 +19,9 @@ +@@ -55,6 +55,8 @@ + #include "stats.h" + #include "autogroup.h" + ++#include <linux/sched/bore.h> ++ + /* + * The initial- and re-scaling of tunables is configurable * - * Adaptive scheduling granularity, math enhancements by Peter Zijlstra - * Copyright (C) 2007 Red Hat, Inc., Peter Zijlstra -+ * -+ * Burst-Oriented Response Enhancer (BORE) CPU Scheduler -+ * Copyright (C) 2021-2024 Masahito Suzuki <firelzrd@gmail.com> - */ - #include <linux/energy_model.h> - #include <linux/mmap_lock.h> -@@ -64,20 +67,146 @@ - * SCHED_TUNABLESCALING_LOG - scaled logarithmical, *1+ilog(ncpus) +@@ -64,17 +66,29 @@ + * SCHED_TUNABLESCALING_LOG - scaled logarithmically, *1+ilog(ncpus) * SCHED_TUNABLESCALING_LINEAR - scaled linear, *ncpus * - * (default SCHED_TUNABLESCALING_LOG = *(1+ilog(ncpus)) @@ -417,231 +756,26 @@ index 483c137b9..4c8d7fbd5 100644 const_debug unsigned int sysctl_sched_migration_cost = 500000UL; -+#ifdef CONFIG_SCHED_BORE -+u8 __read_mostly sched_bore = 1; -+u8 __read_mostly sched_burst_exclude_kthreads = 1; -+u8 __read_mostly sched_burst_smoothness_long = 1; -+u8 __read_mostly sched_burst_smoothness_short = 0; -+u8 __read_mostly sched_burst_fork_atavistic = 2; -+u8 __read_mostly sched_burst_penalty_offset = 22; -+uint __read_mostly sched_burst_penalty_scale = 1280; -+uint __read_mostly sched_burst_cache_lifetime = 60000000; -+uint __read_mostly sched_deadline_boost_mask = ENQUEUE_INITIAL -+ | ENQUEUE_WAKEUP; -+uint __read_mostly sched_deadline_preserve_mask = ENQUEUE_RESTORE -+ | ENQUEUE_MIGRATED; -+static int __maybe_unused sixty_four = 64; -+static int __maybe_unused maxval_12_bits = 4095; -+ -+#define MAX_BURST_PENALTY (39U <<2) -+ -+static inline u32 log2plus1_u64_u32f8(u64 v) { -+ u32 msb = fls64(v); -+ s32 excess_bits = msb - 9; -+ u8 fractional = (0 <= excess_bits)? v >> excess_bits: v << -excess_bits; -+ return msb << 8 | fractional; -+} -+ -+static inline u32 calc_burst_penalty(u64 burst_time) { -+ u32 greed, tolerance, penalty, scaled_penalty; -+ -+ greed = log2plus1_u64_u32f8(burst_time); -+ tolerance = sched_burst_penalty_offset << 8; -+ penalty = max(0, (s32)greed - (s32)tolerance); -+ scaled_penalty = penalty * sched_burst_penalty_scale >> 16; -+ -+ return min(MAX_BURST_PENALTY, scaled_penalty); -+} -+ -+static inline u64 scale_slice(u64 delta, struct sched_entity *se) { -+ return mul_u64_u32_shr(delta, sched_prio_to_wmult[se->burst_score], 22); -+} -+ -+static inline u64 __unscale_slice(u64 delta, u8 score) { -+ return mul_u64_u32_shr(delta, sched_prio_to_weight[score], 10); -+} -+ -+static inline u64 unscale_slice(u64 delta, struct sched_entity *se) { -+ return __unscale_slice(delta, se->burst_score); -+} -+ -+static void reweight_entity( -+ struct cfs_rq *cfs_rq, struct sched_entity *se, unsigned long weight); -+ -+static void renice_task(struct task_struct *p, int prio) -+{ -+ struct sched_entity *se = &p->se; -+ struct cfs_rq *cfs_rq = cfs_rq_of(se); -+ struct load_weight *load = &se->load; -+ unsigned long weight = scale_load(sched_prio_to_weight[prio]); -+ -+ reweight_entity(cfs_rq, se, weight); -+ load->inv_weight = sched_prio_to_wmult[prio]; -+} -+ -+static void update_burst_score(struct sched_entity *se) { -+ if (!entity_is_task(se)) return; -+ struct task_struct *p = task_of(se); -+ u8 prio = p->static_prio - MAX_RT_PRIO; -+ u8 prev_prio = min(39, prio + se->burst_score); -+ -+ u8 burst_score = 0; -+ if (!(sched_burst_exclude_kthreads && (p->flags & PF_KTHREAD))) -+ burst_score = se->burst_penalty >> 2; -+ -+ se->burst_score = burst_score; -+ -+ u8 new_prio = min(39, prio + se->burst_score); -+ if (new_prio != prev_prio) -+ renice_task(p, new_prio); -+} -+ -+static void update_burst_penalty(struct sched_entity *se) { -+ se->curr_burst_penalty = calc_burst_penalty(se->burst_time); -+ se->burst_penalty = max(se->prev_burst_penalty, se->curr_burst_penalty); -+ update_burst_score(se); -+} -+ -+static inline u32 binary_smooth(u32 new, u32 old) { -+ int increment = new - old; -+ return (0 <= increment)? -+ old + ( increment >> (int)sched_burst_smoothness_long): -+ old - (-increment >> (int)sched_burst_smoothness_short); -+} -+ -+static void restart_burst(struct sched_entity *se) { -+ se->burst_penalty = se->prev_burst_penalty = -+ binary_smooth(se->curr_burst_penalty, se->prev_burst_penalty); -+ se->curr_burst_penalty = 0; -+ se->burst_time = 0; -+ update_burst_score(se); -+} -+ -+static void restart_burst_rescale_deadline(struct sched_entity *se) { -+ s64 vscaled, wremain, vremain = se->deadline - se->vruntime; -+ u8 prev_score = se->burst_score; -+ restart_burst(se); -+ if (prev_score > se->burst_score) { -+ wremain = __unscale_slice(abs(vremain), prev_score); -+ vscaled = scale_slice(wremain, se); -+ if (unlikely(vremain < 0)) -+ vscaled = -vscaled; -+ se->deadline = se->vruntime + vscaled; -+ } -+} -+#endif // CONFIG_SCHED_BORE -+ - static int __init setup_sched_thermal_decay_shift(char *str) - { - pr_warn("Ignoring the deprecated sched_thermal_decay_shift= option\n"); -@@ -131,6 +260,92 @@ static unsigned int sysctl_numa_balancing_promote_rate_limit = 65536; - - #ifdef CONFIG_SYSCTL - static struct ctl_table sched_fair_sysctls[] = { -+#ifdef CONFIG_SCHED_BORE -+ { -+ .procname = "sched_bore", -+ .data = &sched_bore, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ONE, -+ .extra2 = SYSCTL_ONE, -+ }, -+ { -+ .procname = "sched_burst_exclude_kthreads", -+ .data = &sched_burst_exclude_kthreads, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = SYSCTL_ONE, -+ }, -+ { -+ .procname = "sched_burst_smoothness_long", -+ .data = &sched_burst_smoothness_long, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = SYSCTL_ONE, -+ }, -+ { -+ .procname = "sched_burst_smoothness_short", -+ .data = &sched_burst_smoothness_short, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = SYSCTL_ONE, -+ }, -+ { -+ .procname = "sched_burst_fork_atavistic", -+ .data = &sched_burst_fork_atavistic, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = SYSCTL_THREE, -+ }, -+ { -+ .procname = "sched_burst_penalty_offset", -+ .data = &sched_burst_penalty_offset, -+ .maxlen = sizeof(u8), -+ .mode = 0644, -+ .proc_handler = proc_dou8vec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = &sixty_four, -+ }, -+ { -+ .procname = "sched_burst_penalty_scale", -+ .data = &sched_burst_penalty_scale, -+ .maxlen = sizeof(uint), -+ .mode = 0644, -+ .proc_handler = proc_douintvec_minmax, -+ .extra1 = SYSCTL_ZERO, -+ .extra2 = &maxval_12_bits, -+ }, -+ { -+ .procname = "sched_burst_cache_lifetime", -+ .data = &sched_burst_cache_lifetime, -+ .maxlen = sizeof(uint), -+ .mode = 0644, -+ .proc_handler = proc_douintvec, -+ }, -+ { -+ .procname = "sched_deadline_boost_mask", -+ .data = &sched_deadline_boost_mask, -+ .maxlen = sizeof(uint), -+ .mode = 0644, -+ .proc_handler = proc_douintvec, -+ }, -+ { -+ .procname = "sched_deadline_preserve_mask", -+ .data = &sched_deadline_preserve_mask, -+ .maxlen = sizeof(uint), -+ .mode = 0644, -+ .proc_handler = proc_douintvec, -+ }, -+#endif // CONFIG_SCHED_BORE - #ifdef CONFIG_CFS_BANDWIDTH - { - .procname = "sched_cfs_bandwidth_slice_us", -@@ -188,6 +403,13 @@ static inline void update_load_set(struct load_weight *lw, unsigned long w) +@@ -188,6 +202,18 @@ static inline void update_load_set(struct load_weight *lw, unsigned long w) * * This idea comes from the SD scheduler of Con Kolivas: */ +#ifdef CONFIG_SCHED_BORE +static void update_sysctl(void) { -+ sysctl_sched_base_slice = -+ max(sysctl_sched_min_base_slice, configured_sched_base_slice); ++ unsigned int base_slice = configured_sched_base_slice; ++ unsigned int min_base_slice = sysctl_sched_min_base_slice; ++ ++ if (min_base_slice) ++ base_slice *= DIV_ROUND_UP(min_base_slice, base_slice); ++ ++ sysctl_sched_base_slice = base_slice; +} +void sched_update_min_base_slice(void) { update_sysctl(); } +#else // !CONFIG_SCHED_BORE static unsigned int get_update_sysctl_factor(void) { unsigned int cpus = min_t(unsigned int, num_online_cpus(), 8); -@@ -218,6 +440,7 @@ static void update_sysctl(void) +@@ -218,6 +244,7 @@ static void update_sysctl(void) SET_SYSCTL(sched_base_slice); #undef SET_SYSCTL } @@ -649,93 +783,28 @@ index 483c137b9..4c8d7fbd5 100644 void __init sched_init_granularity(void) { -@@ -695,6 +918,9 @@ static s64 entity_lag(u64 avruntime, struct sched_entity *se) +@@ -695,6 +722,9 @@ static s64 entity_lag(u64 avruntime, struct sched_entity *se) vlag = avruntime - se->vruntime; limit = calc_delta_fair(max_t(u64, 2*se->slice, TICK_NSEC), se); +#ifdef CONFIG_SCHED_BORE -+ limit >>= 1; ++ limit >>= !!sched_bore; +#endif // CONFIG_SCHED_BORE return clamp(vlag, -limit, limit); } -@@ -855,6 +1081,39 @@ struct sched_entity *__pick_first_entity(struct cfs_rq *cfs_rq) - return __node_2_se(left); - } - -+static inline bool pick_curr(struct cfs_rq *cfs_rq, -+ struct sched_entity *curr, struct sched_entity *wakee) -+{ -+ /* -+ * Nothing to preserve... -+ */ -+ if (!curr || !sched_feat(RESPECT_SLICE)) -+ return false; -+ -+ /* -+ * Allow preemption at the 0-lag point -- even if not all of the slice -+ * is consumed. Note: placement of positive lag can push V left and render -+ * @curr instantly ineligible irrespective the time on-cpu. -+ */ -+ if (sched_feat(RUN_TO_PARITY) && !entity_eligible(cfs_rq, curr)) -+ return false; -+ -+ /* -+ * Don't preserve @curr when the @wakee has a shorter slice and earlier -+ * deadline. IOW, explicitly allow preemption. -+ */ -+ if (sched_feat(PREEMPT_SHORT) && wakee && -+ wakee->slice < curr->slice && -+ (s64)(wakee->deadline - curr->deadline) < 0) -+ return false; -+ -+ /* -+ * Preserve @curr to allow it to finish its first slice. -+ * See the HACK in set_next_entity(). -+ */ -+ return curr->vlag == curr->deadline; -+} -+ - /* - * Earliest Eligible Virtual Deadline First - * -@@ -874,28 +1133,27 @@ struct sched_entity *__pick_first_entity(struct cfs_rq *cfs_rq) - * - * Which allows tree pruning through eligibility. - */ --static struct sched_entity *pick_eevdf(struct cfs_rq *cfs_rq) -+static struct sched_entity *pick_eevdf(struct cfs_rq *cfs_rq, struct sched_entity *wakee) - { - struct rb_node *node = cfs_rq->tasks_timeline.rb_root.rb_node; - struct sched_entity *se = __pick_first_entity(cfs_rq); - struct sched_entity *curr = cfs_rq->curr; - struct sched_entity *best = NULL; - -+ if (curr && !curr->on_rq) -+ curr = NULL; -+ - /* - * We can safely skip eligibility check if there is only one entity - * in this cfs_rq, saving some cycles. - */ - if (cfs_rq->nr_running == 1) -- return curr && curr->on_rq ? curr : se; -- -- if (curr && (!curr->on_rq || !entity_eligible(cfs_rq, curr))) -- curr = NULL; -+ return curr ?: se; - - /* -- * Once selected, run a task until it either becomes non-eligible or -- * until it gets a new slice. See the HACK in set_next_entity(). -+ * Preserve @curr to let it finish its slice. +@@ -896,6 +926,10 @@ static struct sched_entity *pick_eevdf(struct cfs_rq *cfs_rq) + * until it gets a new slice. See the HACK in set_next_entity(). */ -- if (sched_feat(RUN_TO_PARITY) && curr && curr->vlag == curr->deadline) -+ if (pick_curr(cfs_rq, curr, wakee)) + if (sched_feat(RUN_TO_PARITY) && curr && curr->vlag == curr->deadline) ++#ifdef CONFIG_SCHED_BORE ++ if (!(likely(sched_bore) && likely(sched_burst_parity_threshold) && ++ sched_burst_parity_threshold < cfs_rq->nr_running)) ++#endif // CONFIG_SCHED_BORE return curr; /* Pick the leftmost entity if it's eligible */ -@@ -954,6 +1212,7 @@ struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) +@@ -954,6 +988,7 @@ struct sched_entity *__pick_last_entity(struct cfs_rq *cfs_rq) * Scheduling class statistics methods: */ #ifdef CONFIG_SMP @@ -743,7 +812,7 @@ index 483c137b9..4c8d7fbd5 100644 int sched_update_scaling(void) { unsigned int factor = get_update_sysctl_factor(); -@@ -965,6 +1224,7 @@ int sched_update_scaling(void) +@@ -965,6 +1000,7 @@ int sched_update_scaling(void) return 0; } @@ -751,33 +820,27 @@ index 483c137b9..4c8d7fbd5 100644 #endif #endif -@@ -1165,7 +1425,13 @@ static void update_curr(struct cfs_rq *cfs_rq) +@@ -1165,6 +1201,10 @@ static void update_curr(struct cfs_rq *cfs_rq) if (unlikely(delta_exec <= 0)) return; +#ifdef CONFIG_SCHED_BORE + curr->burst_time += delta_exec; + update_burst_penalty(curr); -+ curr->vruntime += max(1ULL, calc_delta_fair(delta_exec, curr)); -+#else // !CONFIG_SCHED_BORE - curr->vruntime += calc_delta_fair(delta_exec, curr); +#endif // CONFIG_SCHED_BORE + curr->vruntime += calc_delta_fair(delta_exec, curr); update_deadline(cfs_rq, curr); update_min_vruntime(cfs_rq); +@@ -3782,7 +3822,7 @@ static void reweight_eevdf(struct sched_entity *se, u64 avruntime, + se->deadline = avruntime + vslice; + } -@@ -5179,6 +5445,11 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) - s64 lag = 0; - - se->slice = sysctl_sched_base_slice; -+#ifdef CONFIG_SCHED_BORE -+ if (flags & ~sched_deadline_boost_mask & sched_deadline_preserve_mask) -+ vslice = se->deadline - se->vruntime; -+ else -+#endif // CONFIG_SCHED_BORE - vslice = calc_delta_fair(se->slice, se); - - /* -@@ -5189,6 +5460,9 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) +-static void reweight_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, ++void reweight_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, + unsigned long weight) + { + bool curr = cfs_rq->curr == se; +@@ -5189,6 +5229,9 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) * * EEVDF: placement strategy #1 / #2 */ @@ -787,28 +850,44 @@ index 483c137b9..4c8d7fbd5 100644 if (sched_feat(PLACE_LAG) && cfs_rq->nr_running) { struct sched_entity *curr = cfs_rq->curr; unsigned long load; -@@ -5264,7 +5538,11 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) - * on average, halfway through their slice, as such start tasks - * off with half a slice to ease into the competition. - */ -+#if !defined(CONFIG_SCHED_BORE) - if (sched_feat(PLACE_DEADLINE_INITIAL) && (flags & ENQUEUE_INITIAL)) -+#else // CONFIG_SCHED_BORE -+ if (flags & sched_deadline_boost_mask) -+#endif // CONFIG_SCHED_BORE - vslice /= 2; +@@ -5259,6 +5302,16 @@ place_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) + + se->vruntime = vruntime - lag; ++ if (sched_feat(PLACE_REL_DEADLINE) && se->rel_deadline) { ++ se->deadline += se->vruntime; ++ se->rel_deadline = 0; ++ return; ++ } ++#ifdef CONFIG_SCHED_BORE ++ else if (likely(sched_bore)) ++ vslice >>= !!(flags & sched_deadline_boost_mask); ++ else ++#endif // CONFIG_SCHED_BORE /* -@@ -5478,7 +5756,7 @@ pick_next_entity(struct cfs_rq *cfs_rq) - cfs_rq->next && entity_eligible(cfs_rq, cfs_rq->next)) - return cfs_rq->next; + * When joining the competition; the existing tasks will be, + * on average, halfway through their slice, as such start tasks +@@ -5368,6 +5421,7 @@ static __always_inline void return_cfs_rq_runtime(struct cfs_rq *cfs_rq); + static void + dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) + { ++ bool sleep = flags & DEQUEUE_SLEEP; + int action = UPDATE_TG; -- return pick_eevdf(cfs_rq); -+ return pick_eevdf(cfs_rq, NULL); - } + if (entity_is_task(se) && task_on_rq_migrating(task_of(se))) +@@ -5395,6 +5449,11 @@ dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) + clear_buddies(cfs_rq, se); - static bool check_cfs_rq_runtime(struct cfs_rq *cfs_rq); -@@ -6846,6 +7124,14 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) + update_entity_lag(cfs_rq, se); ++ if (sched_feat(PLACE_REL_DEADLINE) && !sleep) { ++ se->deadline -= se->vruntime; ++ se->rel_deadline = 1; ++ } ++ + if (se != cfs_rq->curr) + __dequeue_entity(cfs_rq, se); + se->on_rq = 0; +@@ -6846,6 +6905,14 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) bool was_sched_idle = sched_idle_rq(rq); util_est_dequeue(&rq->cfs, p); @@ -823,16 +902,7 @@ index 483c137b9..4c8d7fbd5 100644 for_each_sched_entity(se) { cfs_rq = cfs_rq_of(se); -@@ -8414,7 +8700,7 @@ static void check_preempt_wakeup_fair(struct rq *rq, struct task_struct *p, int - /* - * XXX pick_eevdf(cfs_rq) != se ? - */ -- if (pick_eevdf(cfs_rq) == pse) -+ if (pick_eevdf(cfs_rq, pse) == pse) - goto preempt; - - return; -@@ -8632,16 +8918,25 @@ static void yield_task_fair(struct rq *rq) +@@ -8632,16 +8699,25 @@ static void yield_task_fair(struct rq *rq) /* * Are we the only task in the tree? */ @@ -858,7 +928,7 @@ index 483c137b9..4c8d7fbd5 100644 /* * Tell update_rq_clock() that we've just updated, * so we don't do microscopic update in schedule() -@@ -12709,6 +13004,9 @@ static void task_fork_fair(struct task_struct *p) +@@ -12716,6 +12792,9 @@ static void task_fork_fair(struct task_struct *p) curr = cfs_rq->curr; if (curr) update_curr(cfs_rq); @@ -868,46 +938,38 @@ index 483c137b9..4c8d7fbd5 100644 place_entity(cfs_rq, se, ENQUEUE_INITIAL); rq_unlock(rq, &rf); } +@@ -12828,6 +12907,10 @@ static void attach_task_cfs_rq(struct task_struct *p) + + static void switched_from_fair(struct rq *rq, struct task_struct *p) + { ++ p->se.rel_deadline = 0; ++#ifdef CONFIG_SCHED_BORE ++ init_task_bore(p); ++#endif // CONFIG_SCHED_BORE + detach_task_cfs_rq(p); + } + diff --git a/kernel/sched/features.h b/kernel/sched/features.h -index 143f55df8..3aad8900c 100644 +index 143f55df89..e97b7b68bd 100644 --- a/kernel/sched/features.h +++ b/kernel/sched/features.h -@@ -5,8 +5,28 @@ - * sleep+wake cycles. EEVDF placement strategy #1, #2 if disabled. +@@ -6,6 +6,10 @@ */ SCHED_FEAT(PLACE_LAG, true) -+/* -+ * Give new tasks half a slice to ease into the competition. -+ */ -+#if !defined(CONFIG_SCHED_BORE) SCHED_FEAT(PLACE_DEADLINE_INITIAL, true) --SCHED_FEAT(RUN_TO_PARITY, true) -+#endif // CONFIG_SCHED_BORE -+/* -+ * Inhibit (wakeup) preemption until the current task has exhausted its slice. -+ */ -+#ifdef CONFIG_SCHED_BORE -+SCHED_FEAT(RESPECT_SLICE, false) -+#else // !CONFIG_SCHED_BORE -+SCHED_FEAT(RESPECT_SLICE, true) -+#endif // CONFIG_SCHED_BORE +/* -+ * Relax RESPECT_SLICE to allow preemption once current has reached 0-lag. ++ * Preserve relative virtual deadline on 'migration'. + */ -+SCHED_FEAT(RUN_TO_PARITY, false) -+/* -+ * Allow tasks with a shorter slice to disregard RESPECT_SLICE -+ */ -+SCHED_FEAT(PREEMPT_SHORT, true) ++SCHED_FEAT(PLACE_REL_DEADLINE, true) + SCHED_FEAT(RUN_TO_PARITY, true) /* - * Prefer to schedule the task we woke last (assuming it failed diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h -index 38aeedd8a..aa0ae3fb9 100644 +index 4c36cc6803..cc18ad228e 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h -@@ -1969,7 +1969,11 @@ static inline void dirty_sched_domain_sysctl(int cpu) - } +@@ -1984,7 +1984,11 @@ static inline void update_sched_domain_debugfs(void) { } + static inline void dirty_sched_domain_sysctl(int cpu) { } #endif +#ifdef CONFIG_SCHED_BORE @@ -918,7 +980,7 @@ index 38aeedd8a..aa0ae3fb9 100644 static inline const struct cpumask *task_user_cpus(struct task_struct *p) { -@@ -2554,6 +2558,9 @@ extern const_debug unsigned int sysctl_sched_nr_migrate; +@@ -2601,6 +2605,9 @@ extern const_debug unsigned int sysctl_sched_nr_migrate; extern const_debug unsigned int sysctl_sched_migration_cost; extern unsigned int sysctl_sched_base_slice; @@ -929,5 +991,5 @@ index 38aeedd8a..aa0ae3fb9 100644 #ifdef CONFIG_SCHED_DEBUG extern int sysctl_resched_latency_warn_ms; -- -2.46.0 +2.34.1 diff --git a/SOURCES/dracut-virt.conf b/SOURCES/dracut-virt.conf index da1c17b..8b23a4e 100644 --- a/SOURCES/dracut-virt.conf +++ b/SOURCES/dracut-virt.conf @@ -14,12 +14,19 @@ dracutmodules+=" dm lvm rootfs-block fs-lib " # modules: tpm and crypto dracutmodules+=" crypt crypt-loop tpm2-tss systemd-pcrphase " +# dracut >= 102 separated systemd-cryptsetup into its own module +CSMODULE=`dracut --list-modules --no-kernel | grep '^systemd-cryptsetup$'` +dracutmodules+=" $CSMODULE " + # modules: support root on virtiofs dracutmodules+=" virtiofs " # modules: use sysext images (see 'man systemd-sysext') dracutmodules+=" systemd-sysext " +# modules: root disk integrity protection +dracutmodules+=" systemd-veritysetup " + # drivers: virtual buses, pci drivers+=" virtio-pci virtio-mmio " # qemu-kvm drivers+=" hv-vmbus pci-hyperv " # hyperv @@ -34,5 +41,8 @@ drivers+=" xen-blkfront " # xen # root encryption drivers+=" dm_crypt " +# root disk integrity protection +drivers+=" dm_verity overlay " + # filesystems filesystems+=" vfat ext4 xfs overlay " diff --git a/SOURCES/fsync.patch b/SOURCES/fsync.patch deleted file mode 100644 index fdda084..0000000 --- a/SOURCES/fsync.patch +++ /dev/null @@ -1,166 +0,0 @@ -From b70e738f08403950aa3053c36b98c6b0eeb0eb90 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Andr=C3=A9=20Almeida?= <andrealmeid@collabora.com> -Date: Mon, 25 Oct 2021 09:49:42 -0300 -Subject: [PATCH] futex: Add entry point for FUTEX_WAIT_MULTIPLE (opcode 31) -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Add an option to wait on multiple futexes using the old interface, that -uses opcode 31 through futex() syscall. Do that by just translation the -old interface to use the new code. This allows old and stable versions -of Proton to still use fsync in new kernel releases. - -Signed-off-by: André Almeida <andrealmeid@collabora.com> ---- - include/uapi/linux/futex.h | 13 +++++++ - kernel/futex/syscalls.c | 75 +++++++++++++++++++++++++++++++++++++- - 2 files changed, 87 insertions(+), 1 deletion(-) - -diff --git a/include/uapi/linux/futex.h b/include/uapi/linux/futex.h -index 71a5df8d2689..d375ab21cbf8 100644 ---- a/include/uapi/linux/futex.h -+++ b/include/uapi/linux/futex.h -@@ -22,6 +22,7 @@ - #define FUTEX_WAIT_REQUEUE_PI 11 - #define FUTEX_CMP_REQUEUE_PI 12 - #define FUTEX_LOCK_PI2 13 -+#define FUTEX_WAIT_MULTIPLE 31 - - #define FUTEX_PRIVATE_FLAG 128 - #define FUTEX_CLOCK_REALTIME 256 -@@ -68,6 +69,18 @@ struct futex_waitv { - __u32 __reserved; - }; - -+/** -+ * struct futex_wait_block - Block of futexes to be waited for -+ * @uaddr: User address of the futex -+ * @val: Futex value expected by userspace -+ * @bitset: Bitset for the optional bitmasked wakeup -+ */ -+struct futex_wait_block { -+ __u32 __user *uaddr; -+ __u32 val; -+ __u32 bitset; -+}; -+ - /* - * Support for robust futexes: the kernel cleans up held futexes at - * thread exit time. -diff --git a/kernel/futex/syscalls.c b/kernel/futex/syscalls.c -index 6f91a07a6a83..2f4d4c04ede2 100644 ---- a/kernel/futex/syscalls.c -+++ b/kernel/futex/syscalls.c -@@ -158,6 +158,7 @@ static __always_inline bool futex_cmd_has_timeout(u32 cmd) - case FUTEX_LOCK_PI2: - case FUTEX_WAIT_BITSET: - case FUTEX_WAIT_REQUEUE_PI: -+ case FUTEX_WAIT_MULTIPLE: - return true; - } - return false; -@@ -170,13 +171,79 @@ futex_init_timeout(u32 cmd, u32 op, struct timespec64 *ts, ktime_t *t) - return -EINVAL; - - *t = timespec64_to_ktime(*ts); -- if (cmd == FUTEX_WAIT) -+ if (cmd == FUTEX_WAIT || cmd == FUTEX_WAIT_MULTIPLE) - *t = ktime_add_safe(ktime_get(), *t); - else if (cmd != FUTEX_LOCK_PI && !(op & FUTEX_CLOCK_REALTIME)) - *t = timens_ktime_to_host(CLOCK_MONOTONIC, *t); - return 0; - } - -+/** -+ * futex_read_wait_block - Read an array of futex_wait_block from userspace -+ * @uaddr: Userspace address of the block -+ * @count: Number of blocks to be read -+ * -+ * This function creates and allocate an array of futex_q (we zero it to -+ * initialize the fields) and then, for each futex_wait_block element from -+ * userspace, fill a futex_q element with proper values. -+ */ -+inline struct futex_vector *futex_read_wait_block(u32 __user *uaddr, u32 count) -+{ -+ unsigned int i; -+ struct futex_vector *futexv; -+ struct futex_wait_block fwb; -+ struct futex_wait_block __user *entry = -+ (struct futex_wait_block __user *)uaddr; -+ -+ if (!count || count > FUTEX_WAITV_MAX) -+ return ERR_PTR(-EINVAL); -+ -+ futexv = kcalloc(count, sizeof(*futexv), GFP_KERNEL); -+ if (!futexv) -+ return ERR_PTR(-ENOMEM); -+ -+ for (i = 0; i < count; i++) { -+ if (copy_from_user(&fwb, &entry[i], sizeof(fwb))) { -+ kfree(futexv); -+ return ERR_PTR(-EFAULT); -+ } -+ -+ futexv[i].w.flags = FUTEX_32; -+ futexv[i].w.val = fwb.val; -+ futexv[i].w.uaddr = (uintptr_t) (fwb.uaddr); -+ futexv[i].q = futex_q_init; -+ } -+ -+ return futexv; -+} -+ -+int futex_wait_multiple(struct futex_vector *vs, unsigned int count, -+ struct hrtimer_sleeper *to); -+ -+int futex_opcode_31(ktime_t *abs_time, u32 __user *uaddr, int count) -+{ -+ int ret; -+ struct futex_vector *vs; -+ struct hrtimer_sleeper *to = NULL, timeout; -+ -+ to = futex_setup_timer(abs_time, &timeout, 0, 0); -+ -+ vs = futex_read_wait_block(uaddr, count); -+ -+ if (IS_ERR(vs)) -+ return PTR_ERR(vs); -+ -+ ret = futex_wait_multiple(vs, count, abs_time ? to : NULL); -+ kfree(vs); -+ -+ if (to) { -+ hrtimer_cancel(&to->timer); -+ destroy_hrtimer_on_stack(&to->timer); -+ } -+ -+ return ret; -+} -+ - SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val, - const struct __kernel_timespec __user *, utime, - u32 __user *, uaddr2, u32, val3) -@@ -196,6 +263,9 @@ SYSCALL_DEFINE6(futex, u32 __user *, uaddr, int, op, u32, val, - tp = &t; - } - -+ if (cmd == FUTEX_WAIT_MULTIPLE) -+ return futex_opcode_31(tp, uaddr, val); -+ - return do_futex(uaddr, op, val, tp, uaddr2, (unsigned long)utime, val3); - } - -@@ -392,6 +462,9 @@ SYSCALL_DEFINE6(futex_time32, u32 __user *, uaddr, int, op, u32, val, - tp = &t; - } - -+ if (cmd == FUTEX_WAIT_MULTIPLE) -+ return futex_opcode_31(tp, uaddr, val); -+ - return do_futex(uaddr, op, val, tp, uaddr2, (unsigned long)utime, val3); - } - #endif /* CONFIG_COMPAT_32BIT_TIME */ --- -2.33.1 - diff --git a/SOURCES/gating.yaml b/SOURCES/gating.yaml index 87a09ed..f2ce7d2 100644 --- a/SOURCES/gating.yaml +++ b/SOURCES/gating.yaml @@ -1,9 +1,14 @@ --- !Policy product_versions: - - rhel-9 + - rhel-* decision_context: osci_compose_gate rules: - !PassingTestCaseRule {test_case_name: cki.tier1-aarch64.functional} - !PassingTestCaseRule {test_case_name: cki.tier1-ppc64le.functional} - !PassingTestCaseRule {test_case_name: cki.tier1-s390x.functional} - !PassingTestCaseRule {test_case_name: cki.tier1-x86_64.functional} + - !PassingTestCaseRule {test_case_name: s1-aws-ci_x86_64.brew-build.tier1.functional} + - !PassingTestCaseRule {test_case_name: s1-aws-ci_aarch64.brew-build.tier1.functional} + - !PassingTestCaseRule {test_case_name: s1-azure-ci_x86_64.brew-build.tier1.functional} + - !PassingTestCaseRule {test_case_name: s1-azure-ci_aarch64.brew-build.tier1.functional} + - !PassingTestCaseRule {test_case_name: s1-gcp-ci.brew-build.tier1.functional} diff --git a/SOURCES/hdr-config.patch b/SOURCES/hdr-config.patch new file mode 100644 index 0000000..4254190 --- /dev/null +++ b/SOURCES/hdr-config.patch @@ -0,0 +1,118 @@ +From 299b81f3e619aea3ceda77d7c42842a496b34a53 Mon Sep 17 00:00:00 2001 +From: Peter Jung <admin@ptr1337.dev> +Date: Thu, 21 Mar 2024 19:00:50 +0100 +Subject: [PATCH] cachy: move AMD_PRIVATE_COLOR to Kconfig + +Co-authored-by: PedroHLC <root@pedrohlc.com> +Signed-off-by: Peter Jung <admin@ptr1337.dev> +--- + drivers/gpu/drm/amd/display/Kconfig | 6 ++++++ + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 +- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 +++--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- + 5 files changed, 14 insertions(+), 8 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig +index 901d1961b73927..05c49141f5802f 100644 +--- a/drivers/gpu/drm/amd/display/Kconfig ++++ b/drivers/gpu/drm/amd/display/Kconfig +@@ -51,4 +51,10 @@ config DRM_AMD_SECURE_DISPLAY + This option enables the calculation of crc of specific region via + debugfs. Cooperate with specific DMCU FW. + ++config AMD_PRIVATE_COLOR ++ bool "Enable KMS color management by AMD for AMD" ++ default n ++ help ++ This option extends the KMS color management API with AMD driver-specific properties to enhance the color management support on AMD Steam Deck. ++ + endmenu +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 59d2eee72a3297..0a4e75de95c257 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -4078,7 +4078,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) + return r; + } + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + if (amdgpu_dm_create_color_properties(adev)) { + dc_state_release(state->context); + kfree(state); +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +index c87b64e464ed5c..6fe07243adc3d5 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +@@ -97,7 +97,7 @@ static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x) + return val; + } + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + /* Pre-defined Transfer Functions (TF) + * + * AMD driver supports pre-defined mathematical functions for transferring +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +index 6e715ef3a5566e..11c7199ec3b348 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +@@ -290,7 +290,7 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) + } + #endif + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + /** + * dm_crtc_additional_color_mgmt - enable additional color properties + * @crtc: DRM CRTC +@@ -372,7 +372,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { + #if defined(CONFIG_DEBUG_FS) + .late_register = amdgpu_dm_crtc_late_register, + #endif +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, + .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, + #endif +@@ -551,7 +551,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, + + drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + dm_crtc_additional_color_mgmt(&acrtc->base); + #endif + return 0; +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +index 8a4c40b4c27e4f..779880c6457553 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +@@ -1468,7 +1468,7 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, + drm_atomic_helper_plane_destroy_state(plane, state); + } + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + static void + dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, + struct drm_plane *plane) +@@ -1659,7 +1659,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { + .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, + .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, + .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + .atomic_set_property = dm_atomic_plane_set_property, + .atomic_get_property = dm_atomic_plane_get_property, + #endif +@@ -1742,7 +1742,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, + + drm_plane_helper_add(plane, &dm_plane_helper_funcs); + +-#ifdef AMD_PRIVATE_COLOR ++#ifdef CONFIG_AMD_PRIVATE_COLOR + dm_atomic_plane_attach_color_mgmt_properties(dm, plane); + #endif + /* Create (reset) the plane state */ diff --git a/SOURCES/kernel-aarch64-16k-debug-fedora.config b/SOURCES/kernel-aarch64-16k-debug-fedora.config index 1ce8390..1b5e56e 100644 --- a/SOURCES/kernel-aarch64-16k-debug-fedora.config +++ b/SOURCES/kernel-aarch64-16k-debug-fedora.config @@ -125,6 +125,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -198,7 +199,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set # CONFIG_AFFS_FS is not set @@ -673,6 +674,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_AXI_DMAC=m CONFIG_AXP20X_ADC=m CONFIG_AXP20X_POWER=m @@ -716,6 +718,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -752,8 +755,10 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_DS2782 is not set CONFIG_BATTERY_GAUGE_LTC2941=m # CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_LENOVO_YOGA_C630=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set # CONFIG_BATTERY_PM8916_BMS_VM is not set CONFIG_BATTERY_QCOM_BATTMGR=m @@ -806,6 +811,7 @@ CONFIG_BCM_SBA_RAID=m CONFIG_BCM_VIDEOCORE=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -861,6 +867,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -1174,6 +1181,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1254,6 +1262,7 @@ CONFIG_CLK_IMX95_BLK_CTL=m CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_LS1028A_PLLDIG=y CONFIG_CLK_PX30=y +CONFIG_CLK_QCM2290_GPUCC=m CONFIG_CLK_QORIQ=y CONFIG_CLK_RASPBERRYPI=y # CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set @@ -1319,6 +1328,8 @@ CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXG=y CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1373,6 +1384,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_VDSO is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1713,6 +1725,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1922,6 +1935,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1956,6 +1970,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -2080,11 +2095,13 @@ CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set CONFIG_DRM_PANEL_HIMAX_HX8394=m CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -2100,6 +2117,7 @@ CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set CONFIG_DRM_PANEL_LG_LG4573=m # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2381,6 +2399,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set CONFIG_EC_ACER_ASPIRE1=m CONFIG_ECHO=m +CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_ECRYPT_FS=m # CONFIG_ECRYPT_FS_MESSAGING is not set CONFIG_EDAC_BLUEFIELD=m @@ -2435,6 +2454,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2597,7 +2617,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2643,7 +2665,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2778,6 +2799,7 @@ CONFIG_GPIO_AGGREGATOR=m # CONFIG_GPIO_AMDPT is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_BT8XX=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_CDEV_V1=y @@ -2834,6 +2856,7 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_STMPE=y CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set @@ -2848,6 +2871,7 @@ CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_VF610=y # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m CONFIG_GPIO_WATCHDOG=m CONFIG_GPIO_WCD934X=m # CONFIG_GPIO_WINBOND is not set @@ -3267,6 +3291,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -3447,6 +3472,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -3459,6 +3485,7 @@ CONFIG_INPUT_BBNSM_PWRKEY=m # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3553,6 +3580,7 @@ CONFIG_INTERCONNECT_QCOM_BCM_VOTER=y # CONFIG_INTERCONNECT_QCOM_MSM8909 is not set CONFIG_INTERCONNECT_QCOM_MSM8916=m # CONFIG_INTERCONNECT_QCOM_MSM8939 is not set +CONFIG_INTERCONNECT_QCOM_MSM8953=m # CONFIG_INTERCONNECT_QCOM_MSM8974 is not set CONFIG_INTERCONNECT_QCOM_MSM8996=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m @@ -3685,6 +3713,7 @@ CONFIG_IPQ_GCC_5018=m # CONFIG_IPQ_GCC_8074 is not set # CONFIG_IPQ_GCC_9574 is not set # CONFIG_IPQ_LCC_806X is not set +CONFIG_IPQ_NSSCC_QCA8K=m CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_SCTP=m @@ -3921,6 +3950,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -4033,6 +4063,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -4071,6 +4102,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -4116,6 +4148,7 @@ CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_SGM3140=m # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEDS_SY7802=m CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -4129,6 +4162,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -4267,6 +4301,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -4392,6 +4427,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -4432,6 +4468,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set CONFIG_MFD_AC100=m # CONFIG_MFD_ACT8945A is not set @@ -4450,6 +4487,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -4517,6 +4556,7 @@ CONFIG_MFD_RK8XX_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4689,6 +4729,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=m CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_SDHCI_BRCMSTB=m CONFIG_MMC_SDHCI_CADENCE=m CONFIG_MMC_SDHCI_ESDHC_IMX=m CONFIG_MMC_SDHCI_F_SDH30=m @@ -5068,6 +5109,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -5172,8 +5214,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -5282,6 +5326,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5610,6 +5655,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_ZYNQMP=m CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5633,6 +5679,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -5838,6 +5885,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5877,6 +5925,7 @@ CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_DM816X_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_FSL_IMX8QM_HSIO=m CONFIG_PHY_FSL_LYNX_28G=m CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY=m CONFIG_PHY_HI3660_USB=m @@ -5987,9 +6036,11 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PINCTRL_IMX_SCMI=y # CONFIG_PINCTRL_IPQ4019 is not set # CONFIG_PINCTRL_IPQ5018 is not set # CONFIG_PINCTRL_IPQ5332 is not set @@ -6049,6 +6100,7 @@ CONFIG_PINCTRL_SDM845=m # CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SDX75 is not set CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_SM4250_LPASS_LPI=m # CONFIG_PINCTRL_SM4450 is not set CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6115=m @@ -6158,6 +6210,8 @@ CONFIG_POWER_RESET_VERSATILE=y CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -6262,12 +6316,14 @@ CONFIG_PVPANIC_PCI=m CONFIG_PVPANIC=y CONFIG_PWM_APPLE=m # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m CONFIG_PWM_BCM2835=m CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -6315,6 +6371,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_CPR=m +CONFIG_QCOM_CPUCP_MBOX=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set @@ -6341,6 +6398,7 @@ CONFIG_QCOM_MPM=m CONFIG_QCOM_OCMEM=m CONFIG_QCOM_PBS=m CONFIG_QCOM_PDC=y +CONFIG_QCOM_PD_MAPPER=m CONFIG_QCOM_PIL_INFO=m CONFIG_QCOM_PMIC_GLINK=m CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m @@ -6378,6 +6436,8 @@ CONFIG_QCOM_SSC_BLOCK_BUS=y CONFIG_QCOM_STATS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_TSENS=m +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_QCOM_WDT=m @@ -6510,6 +6570,7 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m CONFIG_REGULATOR_ACT8865=m # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m @@ -6519,6 +6580,7 @@ CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BD718XX=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m CONFIG_REGULATOR_CROS_EC=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set @@ -6574,6 +6636,7 @@ CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_PM8008=m CONFIG_REGULATOR_QCOM_REFGEN=m CONFIG_REGULATOR_QCOM_RPMH=y # CONFIG_REGULATOR_QCOM_RPM is not set @@ -6597,6 +6660,7 @@ CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTQ2208=m CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_RZG2L_VBCTRL=m # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SUN20I is not set CONFIG_REGULATOR_SY7636A=m @@ -6649,6 +6713,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=m CONFIG_RESET_HISI=y CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=m # CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_MESON=m @@ -6667,7 +6732,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -6736,6 +6803,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -6888,8 +6956,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6908,6 +6977,7 @@ CONFIG_RTLLIB=m CONFIG_RTLWIFI_DEBUG=y CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +CONFIG_RTSN=m CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -6933,6 +7003,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -7224,6 +7301,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -7339,10 +7417,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -7390,6 +7472,8 @@ CONFIG_SENSORS_SMPRO=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -7567,6 +7651,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -7588,13 +7673,16 @@ CONFIG_SMARTJOYPLUS_FF=y # CONFIG_SMB_SERVER is not set CONFIG_SMC91X=m # CONFIG_SM_CAMCC_6350 is not set +CONFIG_SM_CAMCC_7150=m CONFIG_SM_CAMCC_8250=m # CONFIG_SM_CAMCC_8450 is not set # CONFIG_SM_CAMCC_8550 is not set +CONFIG_SM_CAMCC_8650=m CONFIG_SMC_DIAG=m # CONFIG_SMC_LO is not set CONFIG_SMC=m CONFIG_SM_DISPCC_6115=m +CONFIG_SM_DISPCC_7150=m CONFIG_SM_DISPCC_8250=m CONFIG_SM_DISPCC_8450=m # CONFIG_SM_DISPCC_8550 is not set @@ -7605,7 +7693,7 @@ CONFIG_SM_GCC_6115=m # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_6375 is not set -# CONFIG_SM_GCC_7150 is not set +CONFIG_SM_GCC_7150=m CONFIG_SM_GCC_8150=y CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m @@ -7636,6 +7724,7 @@ CONFIG_SMS_SIANO_RC=y CONFIG_SMS_USB_DRV=m # CONFIG_SM_TCSRCC_8550 is not set CONFIG_SM_TCSRCC_8650=m +CONFIG_SM_VIDEOCC_7150=m # CONFIG_SM_VIDEOCC_8150 is not set CONFIG_SM_VIDEOCC_8250=m CONFIG_SM_VIDEOCC_8350=m @@ -7719,6 +7808,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -7838,6 +7928,7 @@ CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -7884,6 +7975,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set @@ -7902,6 +7994,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -7910,6 +8003,7 @@ CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -8093,6 +8187,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_RT5631=m CONFIG_SND_SOC_RT5659=m @@ -8248,6 +8343,7 @@ CONFIG_SND_SOC_TSCS42XX=m CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m CONFIG_SND_SOC_WCD938X_SDW=m CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -8383,6 +8479,7 @@ CONFIG_SPI_BITBANG=m CONFIG_SPI_CADENCE=m CONFIG_SPI_CADENCE_QUADSPI=m CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set CONFIG_SPI_DESIGNWARE=m @@ -8708,6 +8805,7 @@ CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_VDE=m CONFIG_TEGRA_WATCHDOG=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -8793,6 +8891,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8811,6 +8910,7 @@ CONFIG_TI_DAC7311=m # CONFIG_TI_DAC7612 is not set CONFIG_TI_DAVINCI_MDIO=m CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m CONFIG_TIFM_7XX1=m CONFIG_TIFM_CORE=m CONFIG_TIGON3_HWMON=y @@ -9074,6 +9174,7 @@ CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UCSI_ACPI=m CONFIG_UCSI_CCG=m +CONFIG_UCSI_LENOVO_YOGA_C630=m CONFIG_UCSI_PMIC_GLINK=m CONFIG_UCSI_STM32G0=m CONFIG_UDF_FS=m @@ -9530,6 +9631,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -9556,6 +9658,7 @@ CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VDSO=y CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set CONFIG_VEML6070=m # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -9655,6 +9758,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -9664,6 +9768,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -9686,6 +9792,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -9713,6 +9820,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set CONFIG_VIDEO_MESON_GE2D=m CONFIG_VIDEO_MESON_VDEC=m @@ -9770,6 +9879,7 @@ CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m # CONFIG_VIDEO_RCAR_CSI2 is not set # CONFIG_VIDEO_RCAR_ISP is not set # CONFIG_VIDEO_RCAR_VIN is not set @@ -9860,6 +9970,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -10167,7 +10278,6 @@ CONFIG_ZYNQMP_POWER=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-16k-fedora.config b/SOURCES/kernel-aarch64-16k-fedora.config index 24594e0..1c99698 100644 --- a/SOURCES/kernel-aarch64-16k-fedora.config +++ b/SOURCES/kernel-aarch64-16k-fedora.config @@ -125,6 +125,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -198,7 +199,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set # CONFIG_AFFS_FS is not set @@ -673,6 +674,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_AXI_DMAC=m CONFIG_AXP20X_ADC=m CONFIG_AXP20X_POWER=m @@ -716,6 +718,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -752,8 +755,10 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_DS2782 is not set CONFIG_BATTERY_GAUGE_LTC2941=m # CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_LENOVO_YOGA_C630=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set # CONFIG_BATTERY_PM8916_BMS_VM is not set CONFIG_BATTERY_QCOM_BATTMGR=m @@ -806,6 +811,7 @@ CONFIG_BCM_SBA_RAID=m CONFIG_BCM_VIDEOCORE=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -861,6 +867,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -1174,6 +1181,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1254,6 +1262,7 @@ CONFIG_CLK_IMX95_BLK_CTL=m CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_LS1028A_PLLDIG=y CONFIG_CLK_PX30=y +CONFIG_CLK_QCM2290_GPUCC=m CONFIG_CLK_QORIQ=y CONFIG_CLK_RASPBERRYPI=y # CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set @@ -1319,6 +1328,8 @@ CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXG=y CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1373,6 +1384,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_VDSO is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1713,6 +1725,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1913,6 +1926,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1947,6 +1961,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -2071,11 +2086,13 @@ CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set CONFIG_DRM_PANEL_HIMAX_HX8394=m CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -2091,6 +2108,7 @@ CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set CONFIG_DRM_PANEL_LG_LG4573=m # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2372,6 +2390,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set CONFIG_EC_ACER_ASPIRE1=m CONFIG_ECHO=m +CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_ECRYPT_FS=m # CONFIG_ECRYPT_FS_MESSAGING is not set CONFIG_EDAC_BLUEFIELD=m @@ -2426,6 +2445,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2580,7 +2600,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2626,7 +2648,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2761,6 +2782,7 @@ CONFIG_GPIO_AGGREGATOR=m # CONFIG_GPIO_AMDPT is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_BT8XX=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_CDEV_V1=y @@ -2817,6 +2839,7 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_STMPE=y CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set @@ -2831,6 +2854,7 @@ CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_VF610=y # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m CONFIG_GPIO_WATCHDOG=m CONFIG_GPIO_WCD934X=m # CONFIG_GPIO_WINBOND is not set @@ -3250,6 +3274,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -3430,6 +3455,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -3442,6 +3468,7 @@ CONFIG_INPUT_BBNSM_PWRKEY=m # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3536,6 +3563,7 @@ CONFIG_INTERCONNECT_QCOM_BCM_VOTER=y # CONFIG_INTERCONNECT_QCOM_MSM8909 is not set CONFIG_INTERCONNECT_QCOM_MSM8916=m # CONFIG_INTERCONNECT_QCOM_MSM8939 is not set +CONFIG_INTERCONNECT_QCOM_MSM8953=m # CONFIG_INTERCONNECT_QCOM_MSM8974 is not set CONFIG_INTERCONNECT_QCOM_MSM8996=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m @@ -3668,6 +3696,7 @@ CONFIG_IPQ_GCC_5018=m # CONFIG_IPQ_GCC_8074 is not set # CONFIG_IPQ_GCC_9574 is not set # CONFIG_IPQ_LCC_806X is not set +CONFIG_IPQ_NSSCC_QCA8K=m CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_SCTP=m @@ -3897,6 +3926,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -4009,6 +4039,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -4047,6 +4078,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -4092,6 +4124,7 @@ CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_SGM3140=m # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEDS_SY7802=m CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -4105,6 +4138,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -4243,6 +4277,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -4367,6 +4402,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -4407,6 +4443,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set CONFIG_MFD_AC100=m # CONFIG_MFD_ACT8945A is not set @@ -4425,6 +4462,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -4492,6 +4531,7 @@ CONFIG_MFD_RK8XX_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4664,6 +4704,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=m CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_SDHCI_BRCMSTB=m CONFIG_MMC_SDHCI_CADENCE=m CONFIG_MMC_SDHCI_ESDHC_IMX=m CONFIG_MMC_SDHCI_F_SDH30=m @@ -5042,6 +5083,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -5146,8 +5188,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -5256,6 +5300,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5584,6 +5629,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_ZYNQMP=m CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5607,6 +5653,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -5811,6 +5858,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5850,6 +5898,7 @@ CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_DM816X_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_FSL_IMX8QM_HSIO=m CONFIG_PHY_FSL_LYNX_28G=m CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY=m CONFIG_PHY_HI3660_USB=m @@ -5960,9 +6009,11 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PINCTRL_IMX_SCMI=y # CONFIG_PINCTRL_IPQ4019 is not set # CONFIG_PINCTRL_IPQ5018 is not set # CONFIG_PINCTRL_IPQ5332 is not set @@ -6022,6 +6073,7 @@ CONFIG_PINCTRL_SDM845=m # CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SDX75 is not set CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_SM4250_LPASS_LPI=m # CONFIG_PINCTRL_SM4450 is not set CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6115=m @@ -6131,6 +6183,8 @@ CONFIG_POWER_RESET_VERSATILE=y CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -6235,12 +6289,14 @@ CONFIG_PVPANIC_PCI=m CONFIG_PVPANIC=y CONFIG_PWM_APPLE=m # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m CONFIG_PWM_BCM2835=m CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -6288,6 +6344,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_CPR=m +CONFIG_QCOM_CPUCP_MBOX=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set @@ -6314,6 +6371,7 @@ CONFIG_QCOM_MPM=m CONFIG_QCOM_OCMEM=m CONFIG_QCOM_PBS=m CONFIG_QCOM_PDC=y +CONFIG_QCOM_PD_MAPPER=m CONFIG_QCOM_PIL_INFO=m CONFIG_QCOM_PMIC_GLINK=m CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m @@ -6351,6 +6409,8 @@ CONFIG_QCOM_SSC_BLOCK_BUS=y CONFIG_QCOM_STATS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_TSENS=m +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_QCOM_WDT=m @@ -6483,6 +6543,7 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m CONFIG_REGULATOR_ACT8865=m # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m @@ -6492,6 +6553,7 @@ CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BD718XX=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m CONFIG_REGULATOR_CROS_EC=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set @@ -6547,6 +6609,7 @@ CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_PM8008=m CONFIG_REGULATOR_QCOM_REFGEN=m CONFIG_REGULATOR_QCOM_RPMH=y # CONFIG_REGULATOR_QCOM_RPM is not set @@ -6570,6 +6633,7 @@ CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTQ2208=m CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_RZG2L_VBCTRL=m # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SUN20I is not set CONFIG_REGULATOR_SY7636A=m @@ -6622,6 +6686,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=m CONFIG_RESET_HISI=y CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=m # CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_MESON=m @@ -6640,7 +6705,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -6709,6 +6776,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -6861,8 +6929,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6881,6 +6950,7 @@ CONFIG_RTLLIB=m # CONFIG_RTLWIFI_DEBUG is not set CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +CONFIG_RTSN=m CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -6906,6 +6976,13 @@ CONFIG_RTW89_8922AE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -7197,6 +7274,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -7312,10 +7390,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -7363,6 +7445,8 @@ CONFIG_SENSORS_SMPRO=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -7540,6 +7624,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -7561,13 +7646,16 @@ CONFIG_SMARTJOYPLUS_FF=y # CONFIG_SMB_SERVER is not set CONFIG_SMC91X=m # CONFIG_SM_CAMCC_6350 is not set +CONFIG_SM_CAMCC_7150=m CONFIG_SM_CAMCC_8250=m # CONFIG_SM_CAMCC_8450 is not set # CONFIG_SM_CAMCC_8550 is not set +CONFIG_SM_CAMCC_8650=m CONFIG_SMC_DIAG=m # CONFIG_SMC_LO is not set CONFIG_SMC=m CONFIG_SM_DISPCC_6115=m +CONFIG_SM_DISPCC_7150=m CONFIG_SM_DISPCC_8250=m CONFIG_SM_DISPCC_8450=m # CONFIG_SM_DISPCC_8550 is not set @@ -7578,7 +7666,7 @@ CONFIG_SM_GCC_6115=m # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_6375 is not set -# CONFIG_SM_GCC_7150 is not set +CONFIG_SM_GCC_7150=m CONFIG_SM_GCC_8150=y CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m @@ -7609,6 +7697,7 @@ CONFIG_SMS_SIANO_RC=y CONFIG_SMS_USB_DRV=m # CONFIG_SM_TCSRCC_8550 is not set CONFIG_SM_TCSRCC_8650=m +CONFIG_SM_VIDEOCC_7150=m # CONFIG_SM_VIDEOCC_8150 is not set CONFIG_SM_VIDEOCC_8250=m CONFIG_SM_VIDEOCC_8350=m @@ -7692,6 +7781,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -7810,6 +7900,7 @@ CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -7856,6 +7947,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set @@ -7874,6 +7966,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -7882,6 +7975,7 @@ CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -8065,6 +8159,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_RT5631=m CONFIG_SND_SOC_RT5659=m @@ -8219,6 +8314,7 @@ CONFIG_SND_SOC_TSCS42XX=m CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m CONFIG_SND_SOC_WCD938X_SDW=m CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -8354,6 +8450,7 @@ CONFIG_SPI_BITBANG=m CONFIG_SPI_CADENCE=m CONFIG_SPI_CADENCE_QUADSPI=m CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set CONFIG_SPI_DESIGNWARE=m @@ -8679,6 +8776,7 @@ CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_VDE=m CONFIG_TEGRA_WATCHDOG=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -8764,6 +8862,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8782,6 +8881,7 @@ CONFIG_TI_DAC7311=m # CONFIG_TI_DAC7612 is not set CONFIG_TI_DAVINCI_MDIO=m CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m CONFIG_TIFM_7XX1=m CONFIG_TIFM_CORE=m CONFIG_TIGON3_HWMON=y @@ -9045,6 +9145,7 @@ CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UCSI_ACPI=m CONFIG_UCSI_CCG=m +CONFIG_UCSI_LENOVO_YOGA_C630=m CONFIG_UCSI_PMIC_GLINK=m CONFIG_UCSI_STM32G0=m CONFIG_UDF_FS=m @@ -9501,6 +9602,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -9527,6 +9629,7 @@ CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VDSO=y CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set CONFIG_VEML6070=m # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -9626,6 +9729,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -9635,6 +9739,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -9657,6 +9763,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -9684,6 +9791,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set CONFIG_VIDEO_MESON_GE2D=m CONFIG_VIDEO_MESON_VDEC=m @@ -9741,6 +9850,7 @@ CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m # CONFIG_VIDEO_RCAR_CSI2 is not set # CONFIG_VIDEO_RCAR_ISP is not set # CONFIG_VIDEO_RCAR_VIN is not set @@ -9831,6 +9941,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -10138,7 +10249,6 @@ CONFIG_ZYNQMP_POWER=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-64k-debug-rhel.config b/SOURCES/kernel-aarch64-64k-debug-rhel.config index a404466..fcdba04 100644 --- a/SOURCES/kernel-aarch64-64k-debug-rhel.config +++ b/SOURCES/kernel-aarch64-64k-debug-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -401,7 +402,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -516,6 +520,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -529,6 +534,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -553,6 +559,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -628,6 +635,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1038,6 +1046,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1211,7 +1220,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1323,6 +1332,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1440,6 +1450,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1455,7 +1466,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1516,6 +1527,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1531,7 +1543,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1548,6 +1560,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1587,6 +1600,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1636,11 +1650,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1656,6 +1672,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1892,6 +1909,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m CONFIG_EDAC_DEBUG=y @@ -1937,10 +1955,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1948,10 +1969,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2044,6 +2069,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2106,11 +2132,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2287,6 +2312,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2296,6 +2322,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2662,12 +2689,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2680,6 +2707,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2877,6 +2905,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2909,6 +2938,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3207,6 +3237,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3228,8 +3259,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3288,14 +3319,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 CONFIG_KVM_PROVE_MMU=y CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3306,6 +3332,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3364,6 +3393,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3374,6 +3404,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3387,6 +3418,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3439,7 +3471,7 @@ CONFIG_LOCKD=m CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y CONFIG_LOCKD_V4=y CONFIG_LOCK_EVENT_COUNTS=y -# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_STAT=y CONFIG_LOCK_TORTURE_TEST=m CONFIG_LOCKUP_DETECTOR=y CONFIG_LOG_BUF_SHIFT=20 @@ -3519,6 +3551,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3615,9 +3648,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3627,6 +3657,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3652,6 +3683,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3665,6 +3697,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3727,6 +3761,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4235,8 +4270,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4246,8 +4283,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4333,8 +4369,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4625,6 +4662,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4643,6 +4681,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4816,6 +4855,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4858,6 +4898,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4914,9 +4955,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -5001,6 +5044,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5104,6 +5149,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5120,14 +5166,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5148,6 +5195,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5162,6 +5210,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5208,6 +5258,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5266,7 +5317,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5305,13 +5356,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5356,6 +5407,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5370,7 +5422,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5408,6 +5460,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5468,7 +5521,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5504,10 +5557,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5519,7 +5572,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5543,6 +5596,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5582,6 +5636,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5933,9 +5994,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5981,6 +6046,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6127,6 +6193,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6232,6 +6299,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6336,6 +6404,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6398,6 +6467,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6406,6 +6476,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6578,6 +6649,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6714,6 +6786,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6836,6 +6909,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set CONFIG_SPI_DEBUG=y # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7149,6 +7223,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7205,7 +7280,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7687,6 +7762,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7698,6 +7774,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7708,6 +7785,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7804,6 +7882,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7819,6 +7899,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7838,6 +7919,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7954,6 +8037,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8130,7 +8214,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8187,7 +8271,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-64k-rhel.config b/SOURCES/kernel-aarch64-64k-rhel.config index abb7ae0..4bf6707 100644 --- a/SOURCES/kernel-aarch64-64k-rhel.config +++ b/SOURCES/kernel-aarch64-64k-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -401,7 +402,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -516,6 +520,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -529,6 +534,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -553,6 +559,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -628,6 +635,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1038,6 +1046,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1211,7 +1220,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1323,6 +1332,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1432,6 +1442,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1447,7 +1458,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1508,6 +1519,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1523,7 +1535,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1540,6 +1552,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1579,6 +1592,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1628,11 +1642,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1648,6 +1664,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1884,6 +1901,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m # CONFIG_EDAC_DEBUG is not set @@ -1929,10 +1947,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1940,10 +1961,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2028,6 +2053,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2090,11 +2116,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2271,6 +2296,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2280,6 +2306,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2646,12 +2673,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2664,6 +2691,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2861,6 +2889,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2893,6 +2922,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3186,6 +3216,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3207,8 +3238,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3267,14 +3298,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3285,6 +3311,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3343,6 +3372,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3353,6 +3383,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3366,6 +3397,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3498,6 +3530,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3594,9 +3627,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3606,6 +3636,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3631,6 +3662,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3644,6 +3676,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3706,6 +3740,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4214,8 +4249,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4225,8 +4262,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4312,8 +4348,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4604,6 +4641,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4622,6 +4660,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4793,6 +4832,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4835,6 +4875,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4891,9 +4932,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -4978,6 +5021,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5081,6 +5126,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5097,14 +5143,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5125,6 +5172,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5139,6 +5187,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5185,6 +5235,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5243,7 +5294,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5282,13 +5333,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5333,6 +5384,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5347,7 +5399,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5385,6 +5437,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5445,7 +5498,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5481,10 +5534,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5496,7 +5549,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5520,6 +5573,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5559,6 +5613,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5910,9 +5971,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5958,6 +6023,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6104,6 +6170,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6209,6 +6276,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6312,6 +6380,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6374,6 +6443,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6382,6 +6452,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6554,6 +6625,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6689,6 +6761,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6811,6 +6884,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7124,6 +7198,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7180,7 +7255,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7662,6 +7737,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7673,6 +7749,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7683,6 +7760,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7779,6 +7857,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7794,6 +7874,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7813,6 +7894,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7929,6 +8012,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8105,7 +8189,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8162,7 +8246,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-debug-fedora.config b/SOURCES/kernel-aarch64-debug-fedora.config index 4ba469b..6ac6ab2 100644 --- a/SOURCES/kernel-aarch64-debug-fedora.config +++ b/SOURCES/kernel-aarch64-debug-fedora.config @@ -125,6 +125,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -198,7 +199,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set # CONFIG_AFFS_FS is not set @@ -673,6 +674,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_AXI_DMAC=m CONFIG_AXP20X_ADC=m CONFIG_AXP20X_POWER=m @@ -716,6 +718,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -752,8 +755,10 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_DS2782 is not set CONFIG_BATTERY_GAUGE_LTC2941=m # CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_LENOVO_YOGA_C630=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set # CONFIG_BATTERY_PM8916_BMS_VM is not set CONFIG_BATTERY_QCOM_BATTMGR=m @@ -806,6 +811,7 @@ CONFIG_BCM_SBA_RAID=m CONFIG_BCM_VIDEOCORE=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -861,6 +867,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -1174,6 +1181,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1254,6 +1262,7 @@ CONFIG_CLK_IMX95_BLK_CTL=m CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_LS1028A_PLLDIG=y CONFIG_CLK_PX30=y +CONFIG_CLK_QCM2290_GPUCC=m CONFIG_CLK_QORIQ=y CONFIG_CLK_RASPBERRYPI=y # CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set @@ -1319,6 +1328,8 @@ CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXG=y CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1373,6 +1384,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_VDSO is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1713,6 +1725,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1922,6 +1935,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1956,6 +1970,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -2080,11 +2095,13 @@ CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set CONFIG_DRM_PANEL_HIMAX_HX8394=m CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -2100,6 +2117,7 @@ CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set CONFIG_DRM_PANEL_LG_LG4573=m # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2381,6 +2399,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set CONFIG_EC_ACER_ASPIRE1=m CONFIG_ECHO=m +CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_ECRYPT_FS=m # CONFIG_ECRYPT_FS_MESSAGING is not set CONFIG_EDAC_BLUEFIELD=m @@ -2435,6 +2454,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2597,7 +2617,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2643,7 +2665,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2778,6 +2799,7 @@ CONFIG_GPIO_AGGREGATOR=m # CONFIG_GPIO_AMDPT is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_BT8XX=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_CDEV_V1=y @@ -2834,6 +2856,7 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_STMPE=y CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set @@ -2848,6 +2871,7 @@ CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_VF610=y # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m CONFIG_GPIO_WATCHDOG=m CONFIG_GPIO_WCD934X=m # CONFIG_GPIO_WINBOND is not set @@ -3267,6 +3291,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -3447,6 +3472,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -3459,6 +3485,7 @@ CONFIG_INPUT_BBNSM_PWRKEY=m # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3553,6 +3580,7 @@ CONFIG_INTERCONNECT_QCOM_BCM_VOTER=y # CONFIG_INTERCONNECT_QCOM_MSM8909 is not set CONFIG_INTERCONNECT_QCOM_MSM8916=m # CONFIG_INTERCONNECT_QCOM_MSM8939 is not set +CONFIG_INTERCONNECT_QCOM_MSM8953=m # CONFIG_INTERCONNECT_QCOM_MSM8974 is not set CONFIG_INTERCONNECT_QCOM_MSM8996=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m @@ -3685,6 +3713,7 @@ CONFIG_IPQ_GCC_5018=m # CONFIG_IPQ_GCC_8074 is not set # CONFIG_IPQ_GCC_9574 is not set # CONFIG_IPQ_LCC_806X is not set +CONFIG_IPQ_NSSCC_QCA8K=m CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_SCTP=m @@ -3921,6 +3950,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -4033,6 +4063,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -4071,6 +4102,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -4116,6 +4148,7 @@ CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_SGM3140=m # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEDS_SY7802=m CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -4129,6 +4162,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -4267,6 +4301,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -4392,6 +4427,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -4432,6 +4468,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set CONFIG_MFD_AC100=m # CONFIG_MFD_ACT8945A is not set @@ -4450,6 +4487,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -4517,6 +4556,7 @@ CONFIG_MFD_RK8XX_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4689,6 +4729,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=m CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_SDHCI_BRCMSTB=m CONFIG_MMC_SDHCI_CADENCE=m CONFIG_MMC_SDHCI_ESDHC_IMX=m CONFIG_MMC_SDHCI_F_SDH30=m @@ -5068,6 +5109,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -5172,8 +5214,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -5282,6 +5326,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5610,6 +5655,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_ZYNQMP=m CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5633,6 +5679,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -5837,6 +5884,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5876,6 +5924,7 @@ CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_DM816X_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_FSL_IMX8QM_HSIO=m CONFIG_PHY_FSL_LYNX_28G=m CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY=m CONFIG_PHY_HI3660_USB=m @@ -5986,9 +6035,11 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PINCTRL_IMX_SCMI=y # CONFIG_PINCTRL_IPQ4019 is not set # CONFIG_PINCTRL_IPQ5018 is not set # CONFIG_PINCTRL_IPQ5332 is not set @@ -6048,6 +6099,7 @@ CONFIG_PINCTRL_SDM845=m # CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SDX75 is not set CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_SM4250_LPASS_LPI=m # CONFIG_PINCTRL_SM4450 is not set CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6115=m @@ -6157,6 +6209,8 @@ CONFIG_POWER_RESET_VERSATILE=y CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -6261,12 +6315,14 @@ CONFIG_PVPANIC_PCI=m CONFIG_PVPANIC=y CONFIG_PWM_APPLE=m # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m CONFIG_PWM_BCM2835=m CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -6314,6 +6370,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_CPR=m +CONFIG_QCOM_CPUCP_MBOX=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set @@ -6340,6 +6397,7 @@ CONFIG_QCOM_MPM=m CONFIG_QCOM_OCMEM=m CONFIG_QCOM_PBS=m CONFIG_QCOM_PDC=y +CONFIG_QCOM_PD_MAPPER=m CONFIG_QCOM_PIL_INFO=m CONFIG_QCOM_PMIC_GLINK=m CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m @@ -6377,6 +6435,8 @@ CONFIG_QCOM_SSC_BLOCK_BUS=y CONFIG_QCOM_STATS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_TSENS=m +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_QCOM_WDT=m @@ -6509,6 +6569,7 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m CONFIG_REGULATOR_ACT8865=m # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m @@ -6518,6 +6579,7 @@ CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BD718XX=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m CONFIG_REGULATOR_CROS_EC=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set @@ -6573,6 +6635,7 @@ CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_PM8008=m CONFIG_REGULATOR_QCOM_REFGEN=m CONFIG_REGULATOR_QCOM_RPMH=y # CONFIG_REGULATOR_QCOM_RPM is not set @@ -6596,6 +6659,7 @@ CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTQ2208=m CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_RZG2L_VBCTRL=m # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SUN20I is not set CONFIG_REGULATOR_SY7636A=m @@ -6648,6 +6712,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=m CONFIG_RESET_HISI=y CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=m # CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_MESON=m @@ -6666,7 +6731,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -6735,6 +6802,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -6887,8 +6955,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6907,6 +6976,7 @@ CONFIG_RTLLIB=m CONFIG_RTLWIFI_DEBUG=y CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +CONFIG_RTSN=m CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -6932,6 +7002,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -7223,6 +7300,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -7338,10 +7416,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -7389,6 +7471,8 @@ CONFIG_SENSORS_SMPRO=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -7566,6 +7650,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -7587,13 +7672,16 @@ CONFIG_SMARTJOYPLUS_FF=y # CONFIG_SMB_SERVER is not set CONFIG_SMC91X=m # CONFIG_SM_CAMCC_6350 is not set +CONFIG_SM_CAMCC_7150=m CONFIG_SM_CAMCC_8250=m # CONFIG_SM_CAMCC_8450 is not set # CONFIG_SM_CAMCC_8550 is not set +CONFIG_SM_CAMCC_8650=m CONFIG_SMC_DIAG=m # CONFIG_SMC_LO is not set CONFIG_SMC=m CONFIG_SM_DISPCC_6115=m +CONFIG_SM_DISPCC_7150=m CONFIG_SM_DISPCC_8250=m CONFIG_SM_DISPCC_8450=m # CONFIG_SM_DISPCC_8550 is not set @@ -7604,7 +7692,7 @@ CONFIG_SM_GCC_6115=m # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_6375 is not set -# CONFIG_SM_GCC_7150 is not set +CONFIG_SM_GCC_7150=m CONFIG_SM_GCC_8150=y CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m @@ -7635,6 +7723,7 @@ CONFIG_SMS_SIANO_RC=y CONFIG_SMS_USB_DRV=m # CONFIG_SM_TCSRCC_8550 is not set CONFIG_SM_TCSRCC_8650=m +CONFIG_SM_VIDEOCC_7150=m # CONFIG_SM_VIDEOCC_8150 is not set CONFIG_SM_VIDEOCC_8250=m CONFIG_SM_VIDEOCC_8350=m @@ -7718,6 +7807,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -7837,6 +7927,7 @@ CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -7883,6 +7974,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set @@ -7901,6 +7993,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -7909,6 +8002,7 @@ CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -8092,6 +8186,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_RT5631=m CONFIG_SND_SOC_RT5659=m @@ -8247,6 +8342,7 @@ CONFIG_SND_SOC_TSCS42XX=m CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m CONFIG_SND_SOC_WCD938X_SDW=m CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -8382,6 +8478,7 @@ CONFIG_SPI_BITBANG=m CONFIG_SPI_CADENCE=m CONFIG_SPI_CADENCE_QUADSPI=m CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set CONFIG_SPI_DESIGNWARE=m @@ -8707,6 +8804,7 @@ CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_VDE=m CONFIG_TEGRA_WATCHDOG=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -8792,6 +8890,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8810,6 +8909,7 @@ CONFIG_TI_DAC7311=m # CONFIG_TI_DAC7612 is not set CONFIG_TI_DAVINCI_MDIO=m CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m CONFIG_TIFM_7XX1=m CONFIG_TIFM_CORE=m CONFIG_TIGON3_HWMON=y @@ -9073,6 +9173,7 @@ CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UCSI_ACPI=m CONFIG_UCSI_CCG=m +CONFIG_UCSI_LENOVO_YOGA_C630=m CONFIG_UCSI_PMIC_GLINK=m CONFIG_UCSI_STM32G0=m CONFIG_UDF_FS=m @@ -9529,6 +9630,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -9555,6 +9657,7 @@ CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VDSO=y CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set CONFIG_VEML6070=m # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -9654,6 +9757,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -9663,6 +9767,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -9685,6 +9791,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -9712,6 +9819,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set CONFIG_VIDEO_MESON_GE2D=m CONFIG_VIDEO_MESON_VDEC=m @@ -9769,6 +9878,7 @@ CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m # CONFIG_VIDEO_RCAR_CSI2 is not set # CONFIG_VIDEO_RCAR_ISP is not set # CONFIG_VIDEO_RCAR_VIN is not set @@ -9859,6 +9969,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -10166,7 +10277,6 @@ CONFIG_ZYNQMP_POWER=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-debug-rhel.config b/SOURCES/kernel-aarch64-debug-rhel.config index 7dba0fe..8fa9205 100644 --- a/SOURCES/kernel-aarch64-debug-rhel.config +++ b/SOURCES/kernel-aarch64-debug-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -399,7 +400,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -514,6 +518,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -527,6 +532,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -551,6 +557,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -626,6 +633,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1036,6 +1044,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1209,7 +1218,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1321,6 +1330,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1438,6 +1448,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1453,7 +1464,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1514,6 +1525,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1529,7 +1541,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1546,6 +1558,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1585,6 +1598,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1634,11 +1648,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1654,6 +1670,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1890,6 +1907,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m CONFIG_EDAC_DEBUG=y @@ -1935,10 +1953,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1946,10 +1967,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2042,6 +2067,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2103,11 +2129,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2284,6 +2309,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2293,6 +2319,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2659,12 +2686,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2677,6 +2704,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2874,6 +2902,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2906,6 +2935,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3204,6 +3234,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3225,8 +3256,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3285,14 +3316,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 CONFIG_KVM_PROVE_MMU=y CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3303,6 +3329,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3361,6 +3390,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3371,6 +3401,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3384,6 +3415,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3436,7 +3468,7 @@ CONFIG_LOCKD=m CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y CONFIG_LOCKD_V4=y CONFIG_LOCK_EVENT_COUNTS=y -# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_STAT=y CONFIG_LOCK_TORTURE_TEST=m CONFIG_LOCKUP_DETECTOR=y CONFIG_LOG_BUF_SHIFT=20 @@ -3516,6 +3548,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3612,9 +3645,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3624,6 +3654,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3649,6 +3680,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3662,6 +3694,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3724,6 +3758,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4232,8 +4267,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4243,8 +4280,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4330,8 +4366,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4622,6 +4659,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4640,6 +4678,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4812,6 +4851,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4854,6 +4894,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4910,9 +4951,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -4997,6 +5040,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5100,6 +5145,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5116,14 +5162,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5144,6 +5191,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5158,6 +5206,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5204,6 +5254,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5262,7 +5313,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5301,13 +5352,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5352,6 +5403,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5366,7 +5418,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5404,6 +5456,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5464,7 +5517,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5500,10 +5553,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5515,7 +5568,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5539,6 +5592,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5578,6 +5632,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5929,9 +5990,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5977,6 +6042,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6123,6 +6189,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6228,6 +6295,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6332,6 +6400,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6394,6 +6463,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6402,6 +6472,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6574,6 +6645,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6710,6 +6782,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6832,6 +6905,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set CONFIG_SPI_DEBUG=y # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7145,6 +7219,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7201,7 +7276,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7683,6 +7758,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7694,6 +7770,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7704,6 +7781,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7800,6 +7878,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7815,6 +7895,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7834,6 +7915,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7950,6 +8033,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8126,7 +8210,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8183,7 +8267,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-fedora.config b/SOURCES/kernel-aarch64-fedora.config index 3c67f6a..8062fcd 100644 --- a/SOURCES/kernel-aarch64-fedora.config +++ b/SOURCES/kernel-aarch64-fedora.config @@ -125,6 +125,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -198,7 +199,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set # CONFIG_AFFS_FS is not set @@ -673,6 +674,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_AXI_DMAC=m CONFIG_AXP20X_ADC=m CONFIG_AXP20X_POWER=m @@ -716,6 +718,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m CONFIG_BACKLIGHT_LM3630A=m # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -752,8 +755,10 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_DS2782 is not set CONFIG_BATTERY_GAUGE_LTC2941=m # CONFIG_BATTERY_GOLDFISH is not set +CONFIG_BATTERY_LENOVO_YOGA_C630=m CONFIG_BATTERY_MAX17040=m CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set # CONFIG_BATTERY_PM8916_BMS_VM is not set CONFIG_BATTERY_QCOM_BATTMGR=m @@ -806,6 +811,7 @@ CONFIG_BCM_SBA_RAID=m CONFIG_BCM_VIDEOCORE=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -861,6 +867,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -1174,6 +1181,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set CONFIG_CHARGER_BQ25980=m +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1254,6 +1262,7 @@ CONFIG_CLK_IMX95_BLK_CTL=m CONFIG_CLK_KUNIT_TEST=m CONFIG_CLK_LS1028A_PLLDIG=y CONFIG_CLK_PX30=y +CONFIG_CLK_QCM2290_GPUCC=m CONFIG_CLK_QORIQ=y CONFIG_CLK_RASPBERRYPI=y # CONFIG_CLK_RCAR_USB2_CLOCK_SEL is not set @@ -1319,6 +1328,8 @@ CONFIG_COMMON_CLK_AXG_AUDIO=y CONFIG_COMMON_CLK_AXG=y CONFIG_COMMON_CLK_AXI_CLKGEN=m CONFIG_COMMON_CLK_BD718XX=m +CONFIG_COMMON_CLK_C3_PERIPHERALS=y +CONFIG_COMMON_CLK_C3_PLL=y # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CDCE925 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set @@ -1373,6 +1384,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_VDSO is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1713,6 +1725,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1913,6 +1926,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1947,6 +1961,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -2071,11 +2086,13 @@ CONFIG_DRM_PANEL_EDP=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set CONFIG_DRM_PANEL_HIMAX_HX8394=m CONFIG_DRM_PANEL_ILITEK_IL9322=m CONFIG_DRM_PANEL_ILITEK_ILI9341=m # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m CONFIG_DRM_PANEL_ILITEK_ILI9881C=m CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -2091,6 +2108,7 @@ CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set CONFIG_DRM_PANEL_LG_LG4573=m # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2372,6 +2390,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set CONFIG_EC_ACER_ASPIRE1=m CONFIG_ECHO=m +CONFIG_EC_LENOVO_YOGA_C630=m CONFIG_ECRYPT_FS=m # CONFIG_ECRYPT_FS_MESSAGING is not set CONFIG_EDAC_BLUEFIELD=m @@ -2426,6 +2445,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2580,7 +2600,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2626,7 +2648,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2761,6 +2782,7 @@ CONFIG_GPIO_AGGREGATOR=m # CONFIG_GPIO_AMDPT is not set # CONFIG_GPIO_BCM_XGS_IPROC is not set CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BRCMSTB=m CONFIG_GPIO_BT8XX=m CONFIG_GPIO_CADENCE=m CONFIG_GPIO_CDEV_V1=y @@ -2817,6 +2839,7 @@ CONFIG_GPIO_ROCKCHIP=y # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set CONFIG_GPIO_STMPE=y CONFIG_GPIO_SYSCON=m # CONFIG_GPIO_SYSFS is not set @@ -2831,6 +2854,7 @@ CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_VF610=y # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m CONFIG_GPIO_WATCHDOG=m CONFIG_GPIO_WCD934X=m # CONFIG_GPIO_WINBOND is not set @@ -3250,6 +3274,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -3430,6 +3455,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -3442,6 +3468,7 @@ CONFIG_INPUT_BBNSM_PWRKEY=m # CONFIG_INPUT_CM109 is not set CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3536,6 +3563,7 @@ CONFIG_INTERCONNECT_QCOM_BCM_VOTER=y # CONFIG_INTERCONNECT_QCOM_MSM8909 is not set CONFIG_INTERCONNECT_QCOM_MSM8916=m # CONFIG_INTERCONNECT_QCOM_MSM8939 is not set +CONFIG_INTERCONNECT_QCOM_MSM8953=m # CONFIG_INTERCONNECT_QCOM_MSM8974 is not set CONFIG_INTERCONNECT_QCOM_MSM8996=m CONFIG_INTERCONNECT_QCOM_OSM_L3=m @@ -3668,6 +3696,7 @@ CONFIG_IPQ_GCC_5018=m # CONFIG_IPQ_GCC_8074 is not set # CONFIG_IPQ_GCC_9574 is not set # CONFIG_IPQ_LCC_806X is not set +CONFIG_IPQ_NSSCC_QCA8K=m CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_SCTP=m @@ -3897,6 +3926,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -4009,6 +4039,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -4047,6 +4078,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -4092,6 +4124,7 @@ CONFIG_LEDS_REGULATOR=m CONFIG_LEDS_SGM3140=m # CONFIG_LEDS_SPI_BYTE is not set # CONFIG_LEDS_SUN50I_A100 is not set +CONFIG_LEDS_SY7802=m CONFIG_LEDS_SYSCON=y # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -4105,6 +4138,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -4243,6 +4277,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m CONFIG_MARVELL_88X2222_PHY=m CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -4367,6 +4402,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -4407,6 +4443,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set CONFIG_MFD_AC100=m # CONFIG_MFD_ACT8945A is not set @@ -4425,6 +4462,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -4492,6 +4531,7 @@ CONFIG_MFD_RK8XX_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set CONFIG_MFD_ROHM_BD718XX=y # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4664,6 +4704,7 @@ CONFIG_MMC_REALTEK_USB=m CONFIG_MMC_RICOH_MMC=y CONFIG_MMC_SDHCI_ACPI=m CONFIG_MMC_SDHCI_AM654=m +CONFIG_MMC_SDHCI_BRCMSTB=m CONFIG_MMC_SDHCI_CADENCE=m CONFIG_MMC_SDHCI_ESDHC_IMX=m CONFIG_MMC_SDHCI_F_SDH30=m @@ -5042,6 +5083,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -5146,8 +5188,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -5256,6 +5300,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5584,6 +5629,7 @@ CONFIG_NVMEM=y CONFIG_NVMEM_ZYNQMP=m CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5607,6 +5653,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -5810,6 +5857,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5849,6 +5897,7 @@ CONFIG_PHY_CAN_TRANSCEIVER=m # CONFIG_PHY_DM816X_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +CONFIG_PHY_FSL_IMX8QM_HSIO=m CONFIG_PHY_FSL_LYNX_28G=m CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY=m CONFIG_PHY_HI3660_USB=m @@ -5959,9 +6008,11 @@ CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QM=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +CONFIG_PINCTRL_IMX91=y CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +CONFIG_PINCTRL_IMX_SCMI=y # CONFIG_PINCTRL_IPQ4019 is not set # CONFIG_PINCTRL_IPQ5018 is not set # CONFIG_PINCTRL_IPQ5332 is not set @@ -6021,6 +6072,7 @@ CONFIG_PINCTRL_SDM845=m # CONFIG_PINCTRL_SDX65 is not set # CONFIG_PINCTRL_SDX75 is not set CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_SM4250_LPASS_LPI=m # CONFIG_PINCTRL_SM4450 is not set CONFIG_PINCTRL_SM6115_LPASS_LPI=m CONFIG_PINCTRL_SM6115=m @@ -6130,6 +6182,8 @@ CONFIG_POWER_RESET_VERSATILE=y CONFIG_POWER_RESET_VEXPRESS=y CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -6234,12 +6288,14 @@ CONFIG_PVPANIC_PCI=m CONFIG_PVPANIC=y CONFIG_PWM_APPLE=m # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m CONFIG_PWM_BCM2835=m CONFIG_PWM_CLK=m CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -6287,6 +6343,7 @@ CONFIG_QCOM_CLK_SMD_RPM=m CONFIG_QCOM_COINCELL=m CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_CPR=m +CONFIG_QCOM_CPUCP_MBOX=m # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_EMAC is not set # CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set @@ -6313,6 +6370,7 @@ CONFIG_QCOM_MPM=m CONFIG_QCOM_OCMEM=m CONFIG_QCOM_PBS=m CONFIG_QCOM_PDC=y +CONFIG_QCOM_PD_MAPPER=m CONFIG_QCOM_PIL_INFO=m CONFIG_QCOM_PMIC_GLINK=m CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m @@ -6350,6 +6408,8 @@ CONFIG_QCOM_SSC_BLOCK_BUS=y CONFIG_QCOM_STATS=m CONFIG_QCOM_SYSMON=m CONFIG_QCOM_TSENS=m +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set CONFIG_QCOM_WCNSS_CTRL=m CONFIG_QCOM_WCNSS_PIL=m CONFIG_QCOM_WDT=m @@ -6482,6 +6542,7 @@ CONFIG_REGMAP_MMIO=y CONFIG_REGMAP_SPMI=y CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m CONFIG_REGULATOR_ACT8865=m # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ANATOP=m @@ -6491,6 +6552,7 @@ CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_AXP20X=m CONFIG_REGULATOR_BD718XX=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m CONFIG_REGULATOR_CROS_EC=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set @@ -6546,6 +6608,7 @@ CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88090 is not set CONFIG_REGULATOR_PWM=y CONFIG_REGULATOR_QCOM_LABIBB=m +CONFIG_REGULATOR_QCOM_PM8008=m CONFIG_REGULATOR_QCOM_REFGEN=m CONFIG_REGULATOR_QCOM_RPMH=y # CONFIG_REGULATOR_QCOM_RPM is not set @@ -6569,6 +6632,7 @@ CONFIG_REGULATOR_RTMV20=m CONFIG_REGULATOR_RTQ2134=m CONFIG_REGULATOR_RTQ2208=m CONFIG_REGULATOR_RTQ6752=m +CONFIG_REGULATOR_RZG2L_VBCTRL=m # CONFIG_REGULATOR_SLG51000 is not set # CONFIG_REGULATOR_SUN20I is not set CONFIG_REGULATOR_SY7636A=m @@ -6621,6 +6685,7 @@ CONFIG_RESET_CONTROLLER=y CONFIG_RESET_GPIO=m CONFIG_RESET_HISI=y CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=m # CONFIG_RESET_INTEL_GW is not set CONFIG_RESET_MESON_AUDIO_ARB=m CONFIG_RESET_MESON=m @@ -6639,7 +6704,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -6708,6 +6775,7 @@ CONFIG_RPMSG_TTY=m CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_WWAN_CTRL=m CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -6860,8 +6928,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6880,6 +6949,7 @@ CONFIG_RTLLIB=m # CONFIG_RTLWIFI_DEBUG is not set CONFIG_RTLWIFI=m # CONFIG_RTS5208 is not set +CONFIG_RTSN=m CONFIG_RTW88_8723CS=m CONFIG_RTW88_8723DE=m CONFIG_RTW88_8723DS=m @@ -6905,6 +6975,13 @@ CONFIG_RTW89_8922AE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -7196,6 +7273,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -7311,10 +7389,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -7362,6 +7444,8 @@ CONFIG_SENSORS_SMPRO=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -7539,6 +7623,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -7560,13 +7645,16 @@ CONFIG_SMARTJOYPLUS_FF=y # CONFIG_SMB_SERVER is not set CONFIG_SMC91X=m # CONFIG_SM_CAMCC_6350 is not set +CONFIG_SM_CAMCC_7150=m CONFIG_SM_CAMCC_8250=m # CONFIG_SM_CAMCC_8450 is not set # CONFIG_SM_CAMCC_8550 is not set +CONFIG_SM_CAMCC_8650=m CONFIG_SMC_DIAG=m # CONFIG_SMC_LO is not set CONFIG_SMC=m CONFIG_SM_DISPCC_6115=m +CONFIG_SM_DISPCC_7150=m CONFIG_SM_DISPCC_8250=m CONFIG_SM_DISPCC_8450=m # CONFIG_SM_DISPCC_8550 is not set @@ -7577,7 +7665,7 @@ CONFIG_SM_GCC_6115=m # CONFIG_SM_GCC_6125 is not set # CONFIG_SM_GCC_6350 is not set # CONFIG_SM_GCC_6375 is not set -# CONFIG_SM_GCC_7150 is not set +CONFIG_SM_GCC_7150=m CONFIG_SM_GCC_8150=y CONFIG_SM_GCC_8250=m CONFIG_SM_GCC_8350=m @@ -7608,6 +7696,7 @@ CONFIG_SMS_SIANO_RC=y CONFIG_SMS_USB_DRV=m # CONFIG_SM_TCSRCC_8550 is not set CONFIG_SM_TCSRCC_8650=m +CONFIG_SM_VIDEOCC_7150=m # CONFIG_SM_VIDEOCC_8150 is not set CONFIG_SM_VIDEOCC_8250=m CONFIG_SM_VIDEOCC_8350=m @@ -7691,6 +7780,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -7809,6 +7899,7 @@ CONFIG_SND_SOC_ADI=m CONFIG_SND_SOC_AK4458=m # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -7855,6 +7946,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m CONFIG_SND_SOC_CS4265=m # CONFIG_SND_SOC_CS4270 is not set @@ -7873,6 +7965,7 @@ CONFIG_SND_SOC_CS42XX8_I2C=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -7881,6 +7974,7 @@ CONFIG_SND_SOC_DAVINCI_MCASP=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -8064,6 +8158,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set CONFIG_SND_SOC_RT5631=m CONFIG_SND_SOC_RT5659=m @@ -8218,6 +8313,7 @@ CONFIG_SND_SOC_TSCS42XX=m CONFIG_SND_SOC_UTILS_KUNIT_TEST=m CONFIG_SND_SOC_WCD9335=m CONFIG_SND_SOC_WCD934X=m +CONFIG_SND_SOC_WCD937X_SDW=m CONFIG_SND_SOC_WCD938X_SDW=m CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -8353,6 +8449,7 @@ CONFIG_SPI_BITBANG=m CONFIG_SPI_CADENCE=m CONFIG_SPI_CADENCE_QUADSPI=m CONFIG_SPI_CADENCE_XSPI=m +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set CONFIG_SPI_DESIGNWARE=m @@ -8678,6 +8775,7 @@ CONFIG_TEGRA_SOCTHERM=m CONFIG_TEGRA_VDE=m CONFIG_TEGRA_WATCHDOG=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -8763,6 +8861,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8781,6 +8880,7 @@ CONFIG_TI_DAC7311=m # CONFIG_TI_DAC7612 is not set CONFIG_TI_DAVINCI_MDIO=m CONFIG_TI_ECAP_CAPTURE=m +CONFIG_TI_EQEP=m CONFIG_TIFM_7XX1=m CONFIG_TIFM_CORE=m CONFIG_TIGON3_HWMON=y @@ -9044,6 +9144,7 @@ CONFIG_UCLAMP_TASK_GROUP=y CONFIG_UCLAMP_TASK=y CONFIG_UCSI_ACPI=m CONFIG_UCSI_CCG=m +CONFIG_UCSI_LENOVO_YOGA_C630=m CONFIG_UCSI_PMIC_GLINK=m CONFIG_UCSI_STM32G0=m CONFIG_UDF_FS=m @@ -9500,6 +9601,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -9526,6 +9628,7 @@ CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VDSO=y CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set CONFIG_VEML6070=m # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -9625,6 +9728,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -9634,6 +9738,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -9656,6 +9762,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -9683,6 +9790,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m CONFIG_VIDEO_MAX96712=m +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set CONFIG_VIDEO_MESON_GE2D=m CONFIG_VIDEO_MESON_VDEC=m @@ -9740,6 +9849,7 @@ CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y CONFIG_VIDEO_QCOM_CAMSS=m CONFIG_VIDEO_QCOM_VENUS=m +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m # CONFIG_VIDEO_RCAR_CSI2 is not set # CONFIG_VIDEO_RCAR_ISP is not set # CONFIG_VIDEO_RCAR_VIN is not set @@ -9830,6 +9940,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -10137,7 +10248,6 @@ CONFIG_ZYNQMP_POWER=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-rhel.config b/SOURCES/kernel-aarch64-rhel.config index 4450f4a..cf241fc 100644 --- a/SOURCES/kernel-aarch64-rhel.config +++ b/SOURCES/kernel-aarch64-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -399,7 +400,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -514,6 +518,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -527,6 +532,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -551,6 +557,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -626,6 +633,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1036,6 +1044,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1209,7 +1218,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1321,6 +1330,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1430,6 +1440,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1445,7 +1456,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1506,6 +1517,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1521,7 +1533,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1538,6 +1550,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1577,6 +1590,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1626,11 +1640,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1646,6 +1662,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1882,6 +1899,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m # CONFIG_EDAC_DEBUG is not set @@ -1927,10 +1945,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1938,10 +1959,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2026,6 +2051,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2087,11 +2113,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2268,6 +2293,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2277,6 +2303,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2643,12 +2670,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2661,6 +2688,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2858,6 +2886,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2890,6 +2919,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3183,6 +3213,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3204,8 +3235,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3264,14 +3295,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3282,6 +3308,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3340,6 +3369,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3350,6 +3380,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3363,6 +3394,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3495,6 +3527,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3591,9 +3624,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3603,6 +3633,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3628,6 +3659,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3641,6 +3673,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3703,6 +3737,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4211,8 +4246,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4222,8 +4259,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4309,8 +4345,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4601,6 +4638,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4619,6 +4657,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4789,6 +4828,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4831,6 +4871,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4887,9 +4928,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -4974,6 +5017,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5077,6 +5122,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5093,14 +5139,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5121,6 +5168,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5135,6 +5183,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5181,6 +5231,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5239,7 +5290,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5278,13 +5329,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5329,6 +5380,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5343,7 +5395,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5381,6 +5433,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5441,7 +5494,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5477,10 +5530,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5492,7 +5545,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5516,6 +5569,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5555,6 +5609,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5906,9 +5967,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5954,6 +6019,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6100,6 +6166,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6205,6 +6272,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6308,6 +6376,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6370,6 +6439,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6378,6 +6448,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6550,6 +6621,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6685,6 +6757,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6807,6 +6880,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7120,6 +7194,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7176,7 +7251,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7658,6 +7733,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7669,6 +7745,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7679,6 +7756,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7775,6 +7853,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7790,6 +7870,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7809,6 +7890,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7925,6 +8008,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8101,7 +8185,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8158,7 +8242,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-rt-debug-rhel.config b/SOURCES/kernel-aarch64-rt-debug-rhel.config index 673311a..fdcbdbe 100644 --- a/SOURCES/kernel-aarch64-rt-debug-rhel.config +++ b/SOURCES/kernel-aarch64-rt-debug-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -399,7 +400,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -514,6 +518,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -527,6 +532,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -551,6 +557,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -626,6 +633,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1036,6 +1044,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1210,7 +1219,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1322,6 +1331,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1440,6 +1450,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1455,7 +1466,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1516,6 +1527,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1531,7 +1543,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1548,6 +1560,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1587,6 +1600,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1636,11 +1650,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1656,6 +1672,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1928,6 +1945,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m CONFIG_EDAC_DEBUG=y @@ -1973,10 +1991,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1984,10 +2005,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2080,6 +2105,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2141,11 +2167,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2323,6 +2348,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2332,6 +2358,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2699,12 +2726,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2717,6 +2744,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2914,6 +2942,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2946,6 +2975,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3244,6 +3274,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3265,8 +3296,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3325,14 +3356,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 CONFIG_KVM_PROVE_MMU=y CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3343,6 +3369,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3401,6 +3430,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3411,6 +3441,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3424,6 +3455,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3464,7 +3496,7 @@ CONFIG_LLC=m CONFIG_LOAD_UEFI_KEYS=y CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_LOCKDEP_BITS=16 +CONFIG_LOCKDEP_BITS=17 CONFIG_LOCKDEP_CHAINS_BITS=18 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 @@ -3476,7 +3508,7 @@ CONFIG_LOCKD=m CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y CONFIG_LOCKD_V4=y CONFIG_LOCK_EVENT_COUNTS=y -# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_STAT=y CONFIG_LOCK_TORTURE_TEST=m CONFIG_LOCKUP_DETECTOR=y CONFIG_LOG_BUF_SHIFT=20 @@ -3556,6 +3588,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3652,14 +3685,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_MSI001 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m -# CONFIG_MEDIA_TUNER_TDA18250 is not set CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3669,6 +3694,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3694,6 +3720,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3707,6 +3734,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3769,6 +3798,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4277,8 +4307,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4288,8 +4320,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4375,8 +4406,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4667,6 +4699,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4685,6 +4718,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4857,6 +4891,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4899,6 +4934,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4955,9 +4991,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -5042,6 +5080,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5149,6 +5189,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5165,14 +5206,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5193,6 +5235,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5207,6 +5250,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5253,6 +5298,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set # CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5314,7 +5360,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5353,13 +5399,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5404,6 +5450,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5418,7 +5465,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5456,6 +5503,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5516,7 +5564,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5552,10 +5600,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5567,7 +5615,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5591,6 +5639,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5630,6 +5679,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5981,9 +6037,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -6029,6 +6089,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6175,6 +6236,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6281,6 +6343,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6385,6 +6448,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6447,6 +6511,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6455,6 +6520,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6627,6 +6693,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6763,6 +6830,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6885,6 +6953,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set CONFIG_SPI_DEBUG=y # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7198,6 +7267,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7254,7 +7324,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7737,6 +7807,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7748,6 +7819,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7758,6 +7830,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7854,6 +7927,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7869,6 +7944,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7888,6 +7964,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -8004,6 +8082,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8181,7 +8260,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8243,7 +8322,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-aarch64-rt-rhel.config b/SOURCES/kernel-aarch64-rt-rhel.config index a932510..ddd8998 100644 --- a/SOURCES/kernel-aarch64-rt-rhel.config +++ b/SOURCES/kernel-aarch64-rt-rhel.config @@ -105,6 +105,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -399,7 +400,10 @@ CONFIG_ARM_MHU=m # CONFIG_ARM_PL172_MPMC is not set CONFIG_ARM_PMU=y # CONFIG_ARM_PSCI_CHECKER is not set -# CONFIG_ARM_PSCI_CPUIDLE is not set +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_PSCI=y # CONFIG_ARM_QCOM_CPUFREQ_HW is not set CONFIG_ARM_SBSA_WATCHDOG=m CONFIG_ARM_SCMI_CPUFREQ=m @@ -514,6 +518,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -527,6 +532,7 @@ CONFIG_BACKLIGHT_GPIO=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -551,6 +557,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -626,6 +633,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -1036,6 +1044,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1210,7 +1219,7 @@ CONFIG_CRYPTO_DEV_SA2UL=m # CONFIG_CRYPTO_DEV_SAHARA is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set +CONFIG_CRYPTO_DEV_TEGRA=m # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1322,6 +1331,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1432,6 +1442,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1447,7 +1458,7 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set # CONFIG_DLM_DEPRECATED_API is not set # CONFIG_DLM is not set @@ -1508,6 +1519,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1523,7 +1535,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m CONFIG_DPAA2_CONSOLE=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set @@ -1540,6 +1552,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1579,6 +1592,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set CONFIG_DRM_I2C_NXP_TDA998X=m # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1628,11 +1642,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1648,6 +1664,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1920,6 +1937,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_BLUEFIELD=m # CONFIG_EDAC_DEBUG is not set @@ -1965,10 +1983,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set # CONFIG_EPIC100 is not set CONFIG_EPOLL=y @@ -1976,10 +1997,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -2064,6 +2089,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2125,11 +2151,10 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_BMAN_TEST is not set CONFIG_FSL_DPAA2_ETH_DCB=y @@ -2307,6 +2332,7 @@ CONFIG_GPIO_PL061=y # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set CONFIG_GPIO_TEGRA186=y @@ -2316,6 +2342,7 @@ CONFIG_GPIO_TEGRA=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set CONFIG_GPIO_WATCHDOG=m # CONFIG_GPIO_WINBOND is not set @@ -2683,12 +2710,12 @@ CONFIG_I3C=m # CONFIG_I40E_DCB is not set CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_ICE_HWMON=y @@ -2701,6 +2728,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2898,6 +2926,7 @@ CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_PWM_BEEPER is not set # CONFIG_INPUT_PWM_VIBRA is not set # CONFIG_INPUT_REGULATOR_HAPTIC is not set +# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set CONFIG_INPUT_SPARSEKMAP=m # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set @@ -2930,6 +2959,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -3223,6 +3253,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3244,8 +3275,8 @@ CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_CAP11XX is not set # CONFIG_KEYBOARD_CYPRESS_SF is not set # CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_GPIO is not set -# CONFIG_KEYBOARD_GPIO_POLLED is not set +CONFIG_KEYBOARD_GPIO=m +CONFIG_KEYBOARD_GPIO_POLLED=m # CONFIG_KEYBOARD_IMX is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_LM8323 is not set @@ -3304,14 +3335,9 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM=y @@ -3322,6 +3348,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3380,6 +3409,7 @@ CONFIG_LEDS_LT3593=m CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_NIC78BX is not set +CONFIG_LEDS_PCA9532_GPIO=y # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3390,6 +3420,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3403,6 +3434,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3535,6 +3567,7 @@ CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set CONFIG_MARVELL_CN10K_DDR_PMU=m +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_CN10K_TAD_PMU=m CONFIG_MARVELL_GTI_WDT=y CONFIG_MARVELL_PHY=m @@ -3631,14 +3664,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_MSI001 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m -# CONFIG_MEDIA_TUNER_TDA18250 is not set CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3648,6 +3673,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3673,6 +3699,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3686,6 +3713,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3748,6 +3777,7 @@ CONFIG_MFD_MAX77620=y # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4256,8 +4286,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4267,8 +4299,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4354,8 +4385,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4646,6 +4678,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4664,6 +4697,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCTEONTX2_AF=m CONFIG_OCTEONTX2_MBOX=m @@ -4834,6 +4868,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4876,6 +4911,7 @@ CONFIG_PHY_BRCM_SATA=y # CONFIG_PHY_CPCAP_USB is not set CONFIG_PHY_FSL_IMX8M_PCIE=y CONFIG_PHY_FSL_IMX8MQ_USB=m +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4932,9 +4968,11 @@ CONFIG_PINCTRL_IMX8MP=y CONFIG_PINCTRL_IMX8MQ=y CONFIG_PINCTRL_IMX8QXP=y CONFIG_PINCTRL_IMX8ULP=y +# CONFIG_PINCTRL_IMX91 is not set CONFIG_PINCTRL_IMX93=y # CONFIG_PINCTRL_IMXRT1050 is not set # CONFIG_PINCTRL_IMXRT1170 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set CONFIG_PINCTRL_IPROC_GPIO=y @@ -5019,6 +5057,8 @@ CONFIG_POWER_RESET_SYSCON=y # CONFIG_POWER_RESET_VEXPRESS is not set # CONFIG_POWER_RESET_XGENE is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5126,6 +5166,7 @@ CONFIG_PWM_BCM_IPROC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_IMX1 is not set CONFIG_PWM_IMX27=m @@ -5142,14 +5183,15 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_BAM_DMA is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set CONFIG_QCOM_EMAC=m CONFIG_QCOM_FALKOR_ERRATUM_1003=y @@ -5170,6 +5212,7 @@ CONFIG_QCOM_L3_PMU=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set CONFIG_QCOM_QDF2400_ERRATUM_0065=y # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_QSEECOM is not set @@ -5184,6 +5227,8 @@ CONFIG_QCOM_SCM=y # CONFIG_QCOM_SPM is not set # CONFIG_QCOM_SPMI_VADC is not set # CONFIG_QCOM_SSC_BLOCK_BUS is not set +CONFIG_QCOM_TZMEM_MODE_GENERIC=y +# CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE is not set # CONFIG_QCOM_WDT is not set CONFIG_QEDE=m CONFIG_QED_FCOE=y @@ -5230,6 +5275,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set # CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5291,7 +5337,7 @@ CONFIG_REGMAP=y # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set # CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_ARM_SCMI is not set +CONFIG_REGULATOR_ARM_SCMI=m # CONFIG_REGULATOR_AW37503 is not set CONFIG_REGULATOR_BD718XX=m # CONFIG_REGULATOR_DA9121 is not set @@ -5330,13 +5376,13 @@ CONFIG_REGULATOR_MAX77686=m # CONFIG_REGULATOR_MPQ7920 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set -# CONFIG_REGULATOR_PCA9450 is not set -# CONFIG_REGULATOR_PF8X00 is not set +CONFIG_REGULATOR_PCA9450=m +CONFIG_REGULATOR_PF8X00=m CONFIG_REGULATOR_PFUZE100=m # CONFIG_REGULATOR_PV88060 is not set # CONFIG_REGULATOR_PV88080 is not set # CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set +CONFIG_REGULATOR_PWM=y # CONFIG_REGULATOR_QCOM_REFGEN is not set # CONFIG_REGULATOR_RAA215300 is not set # CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set @@ -5381,6 +5427,7 @@ CONFIG_RENESAS_PHY=m CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set CONFIG_RESET_IMX7=y +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_AOSS is not set # CONFIG_RESET_QCOM_PDC is not set @@ -5395,7 +5442,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5433,6 +5480,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5493,7 +5541,7 @@ CONFIG_RTC_DRV_FSL_FTM_ALARM=m # CONFIG_RTC_DRV_FTRTC010 is not set # CONFIG_RTC_DRV_GOLDFISH is not set # CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_HYM8563=m # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_DRV_ISL12022=m # CONFIG_RTC_DRV_ISL12026 is not set @@ -5529,10 +5577,10 @@ CONFIG_RTC_DRV_R9701=m CONFIG_RTC_DRV_RP5C01=m CONFIG_RTC_DRV_RS5C348=m CONFIG_RTC_DRV_RS5C372=m -# CONFIG_RTC_DRV_RV3028 is not set +CONFIG_RTC_DRV_RV3028=m CONFIG_RTC_DRV_RV3029C2=m # CONFIG_RTC_DRV_RV3029_HWMON is not set -# CONFIG_RTC_DRV_RV3032 is not set +CONFIG_RTC_DRV_RV3032=m CONFIG_RTC_DRV_RV8803=m CONFIG_RTC_DRV_RX4581=m # CONFIG_RTC_DRV_RX6110 is not set @@ -5544,7 +5592,7 @@ CONFIG_RTC_DRV_RX8581=m # CONFIG_RTC_DRV_SD3078 is not set # CONFIG_RTC_DRV_SNVS is not set CONFIG_RTC_DRV_STK17TA8=m -# CONFIG_RTC_DRV_TEGRA is not set +CONFIG_RTC_DRV_TEGRA=m # CONFIG_RTC_DRV_TEST is not set CONFIG_RTC_DRV_TI_K3=m CONFIG_RTC_DRV_V3020=m @@ -5568,6 +5616,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5607,6 +5656,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5958,9 +6014,13 @@ CONFIG_SENSORS_MAX31790=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -6006,6 +6066,7 @@ CONFIG_SENSORS_SMPRO=m # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -6152,6 +6213,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6258,6 +6320,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6361,6 +6424,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6423,6 +6487,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6431,6 +6496,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6603,6 +6669,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6738,6 +6805,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6860,6 +6928,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_DSPI=y @@ -7173,6 +7242,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7229,7 +7299,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7712,6 +7782,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7723,6 +7794,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7733,6 +7805,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7829,6 +7902,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7844,6 +7919,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7863,6 +7939,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7979,6 +8057,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8156,7 +8235,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8218,7 +8297,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-ppc64le-debug-fedora.config b/SOURCES/kernel-ppc64le-debug-fedora.config index 0cd84a4..b93da2a 100644 --- a/SOURCES/kernel-ppc64le-debug-fedora.config +++ b/SOURCES/kernel-ppc64le-debug-fedora.config @@ -116,6 +116,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -189,7 +190,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -301,7 +302,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PTDUMP_DEBUGFS=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set @@ -413,6 +413,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_BCMA=y CONFIG_B43_BUSES_BCMA_AND_SSB=y @@ -450,6 +451,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -484,6 +486,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -525,6 +528,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -578,6 +582,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m CONFIG_BLK_DEV_RSXX=m +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SX8=m @@ -868,6 +873,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1102,6 +1108,7 @@ CONFIG_CRYPTO_CRCT10DIF_VPMSUM=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_PPC64=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set @@ -1232,8 +1239,8 @@ CONFIG_CXD2880_SPI_DRV=m # CONFIG_CX_ECAT is not set CONFIG_CXL_ACPI=m CONFIG_CXL_BUS=m -CONFIG_CXLFLASH=m -CONFIG_CXL=m +# CONFIG_CXLFLASH is not set +# CONFIG_CXL is not set CONFIG_CXL_MEM=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set CONFIG_CXL_PCI=m @@ -1241,6 +1248,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1438,6 +1446,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1471,6 +1480,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1551,11 +1561,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1571,6 +1583,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1861,6 +1874,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2020,7 +2034,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2064,7 +2080,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2215,7 +2230,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2226,6 +2241,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2233,6 +2249,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2597,6 +2614,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2746,6 +2764,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -2756,6 +2775,7 @@ CONFIG_INPUT_ATLAS_BTNS=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3156,6 +3176,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -3261,6 +3282,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3301,9 +3323,10 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set -CONFIG_LEDS_GPIO=m +# CONFIG_LEDS_GPIO is not set CONFIG_LEDS_GROUP_MULTICOLOR=m # CONFIG_LEDS_IS31FL319X is not set CONFIG_LEDS_IS31FL32XX=m @@ -3331,8 +3354,7 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m +# CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3344,6 +3366,7 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3357,6 +3380,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3608,6 +3632,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3632,6 +3657,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3647,6 +3673,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=m # CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3710,6 +3738,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4183,6 +4212,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4287,8 +4317,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4395,6 +4427,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4700,6 +4733,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4723,6 +4757,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m CONFIG_OF_FPGA_REGION=m @@ -4875,6 +4910,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5010,6 +5046,8 @@ CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5151,10 +5189,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m CONFIG_PWM_OMAP_DMTIMER=m # CONFIG_PWM_PCA9685 is not set @@ -5179,6 +5219,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5294,10 +5335,12 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5404,7 +5447,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5448,6 +5493,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5583,8 +5629,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5628,6 +5675,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5876,6 +5930,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -5992,10 +6047,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6042,6 +6101,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6183,6 +6244,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6290,6 +6352,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6401,6 +6464,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6445,6 +6509,7 @@ CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6463,6 +6528,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6471,6 +6537,7 @@ CONFIG_SND_SOC_CX2072X=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6640,6 +6707,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -6777,6 +6845,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6898,6 +6967,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -7126,6 +7196,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7207,6 +7278,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7830,6 +7902,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7854,6 +7927,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7941,6 +8015,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -7950,6 +8025,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -7968,6 +8045,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -7987,6 +8065,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -8039,6 +8119,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8104,6 +8185,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -8398,7 +8480,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-ppc64le-debug-rhel.config b/SOURCES/kernel-ppc64le-debug-rhel.config index f1fd5f1..18e2aa7 100644 --- a/SOURCES/kernel-ppc64le-debug-rhel.config +++ b/SOURCES/kernel-ppc64le-debug-rhel.config @@ -99,6 +99,7 @@ CONFIG_ACPI_VIDEO=m # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -375,6 +376,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -388,6 +390,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -412,6 +415,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -481,6 +485,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RSXX=m +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -857,6 +862,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -959,6 +965,7 @@ CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_PPC64=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set @@ -993,7 +1000,6 @@ CONFIG_CRYPTO_DEV_NX=y # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DEV_VMX_ENCRYPT=m CONFIG_CRYPTO_DEV_VMX=y @@ -1089,8 +1095,8 @@ CONFIG_CUSE=m # CONFIG_CX_ECAT is not set CONFIG_CXL_ACPI=m CONFIG_CXL_BUS=m -CONFIG_CXLFLASH=m -CONFIG_CXL=m +# CONFIG_CXLFLASH is not set +# CONFIG_CXL is not set CONFIG_CXL_MEM=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set CONFIG_CXL_PCI=m @@ -1098,6 +1104,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1217,6 +1224,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1232,11 +1240,10 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_API_DEBUG=y @@ -1294,6 +1301,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1309,7 +1317,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1325,6 +1333,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1364,6 +1373,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1410,11 +1420,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1429,6 +1441,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1655,6 +1668,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_CPC925=m CONFIG_EDAC_DEBUG=y @@ -1693,10 +1707,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set # CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1704,10 +1721,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1801,6 +1822,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1861,17 +1883,17 @@ CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_LBC is not set # CONFIG_FSL_PQ_MDIO is not set @@ -1944,8 +1966,7 @@ CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=1 -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2014,6 +2035,7 @@ CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2021,6 +2043,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2360,12 +2383,12 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_IBM_BSR=m @@ -2382,6 +2405,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2593,6 +2617,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -2885,6 +2910,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -2964,7 +2990,6 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y CONFIG_KVM_BOOK3S_64_HV=m CONFIG_KVM_BOOK3S_64=m # CONFIG_KVM_BOOK3S_64_PR is not set @@ -2974,11 +2999,9 @@ CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND=y # CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_BOOK3S_PR_POSSIBLE=y CONFIG_KVM_GUEST=y -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 CONFIG_KVM_PROVE_MMU=y CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM_XICS=y @@ -2989,6 +3012,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3059,6 +3085,7 @@ CONFIG_LEDS_POWERNV=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3072,6 +3099,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3202,6 +3230,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3291,9 +3320,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3303,6 +3329,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3328,6 +3355,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3341,6 +3369,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3402,6 +3432,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3885,8 +3916,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -3896,8 +3929,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -3982,8 +4014,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4261,6 +4294,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4279,6 +4313,7 @@ CONFIG_NVRAM=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m CONFIG_OF_KUNIT_TEST=m @@ -4424,6 +4459,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4456,6 +4492,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4493,6 +4530,8 @@ CONFIG_PID_NS=y # CONFIG_PINCTRL_CS42L43 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set # CONFIG_PINCTRL is not set @@ -4563,6 +4602,8 @@ CONFIG_POWER_RESET_GPIO=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4705,6 +4746,7 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_XILINX is not set @@ -4714,13 +4756,14 @@ CONFIG_PWM=y # CONFIG_PWRSEQ_SIMPLE is not set # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4733,6 +4776,7 @@ CONFIG_PWM=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4787,6 +4831,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m CONFIG_RANDOM32_SELFTEST=y CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -4870,6 +4915,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -4903,6 +4949,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_RESET_CONTROLLER is not set # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -4914,7 +4961,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -4952,6 +4999,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5079,6 +5127,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5118,6 +5167,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5471,9 +5527,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5518,6 +5578,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5658,6 +5719,7 @@ CONFIG_SIGNATURE=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5758,6 +5820,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -5862,6 +5925,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5924,6 +5988,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -5932,6 +5997,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6104,6 +6170,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6240,6 +6307,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6358,6 +6426,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6630,6 +6699,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6677,7 +6747,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7151,6 +7221,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7161,6 +7232,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7171,6 +7243,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7264,6 +7337,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7279,6 +7354,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7298,6 +7374,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7414,6 +7492,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7589,7 +7668,7 @@ CONFIG_XMON=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7645,7 +7724,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-ppc64le-fedora.config b/SOURCES/kernel-ppc64le-fedora.config index d0470d8..d29030e 100644 --- a/SOURCES/kernel-ppc64le-fedora.config +++ b/SOURCES/kernel-ppc64le-fedora.config @@ -116,6 +116,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -189,7 +190,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -301,7 +302,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set @@ -411,6 +411,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_BCMA=y CONFIG_B43_BUSES_BCMA_AND_SSB=y @@ -448,6 +449,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -482,6 +484,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -523,6 +526,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -576,6 +580,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m CONFIG_BLK_DEV_RSXX=m +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SX8=m @@ -866,6 +871,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1100,6 +1106,7 @@ CONFIG_CRYPTO_CRCT10DIF_VPMSUM=m CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_PPC64=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set @@ -1230,8 +1237,8 @@ CONFIG_CXD2880_SPI_DRV=m # CONFIG_CX_ECAT is not set CONFIG_CXL_ACPI=m CONFIG_CXL_BUS=m -CONFIG_CXLFLASH=m -CONFIG_CXL=m +# CONFIG_CXLFLASH is not set +# CONFIG_CXL is not set CONFIG_CXL_MEM=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set CONFIG_CXL_PCI=m @@ -1239,6 +1246,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1427,6 +1435,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1460,6 +1469,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1540,11 +1550,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1560,6 +1572,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1850,6 +1863,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2001,7 +2015,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2045,7 +2061,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2196,7 +2211,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2207,6 +2222,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2214,6 +2230,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2577,6 +2594,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2726,6 +2744,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -2736,6 +2755,7 @@ CONFIG_INPUT_ATLAS_BTNS=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3130,6 +3150,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_LZ4 is not set @@ -3235,6 +3256,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3275,9 +3297,10 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set -CONFIG_LEDS_GPIO=m +# CONFIG_LEDS_GPIO is not set CONFIG_LEDS_GROUP_MULTICOLOR=m # CONFIG_LEDS_IS31FL319X is not set CONFIG_LEDS_IS31FL32XX=m @@ -3305,8 +3328,7 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m +# CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3318,6 +3340,7 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3331,6 +3354,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3581,6 +3605,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3605,6 +3630,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3620,6 +3646,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=m # CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3683,6 +3711,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4155,6 +4184,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4259,8 +4289,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4367,6 +4399,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4672,6 +4705,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4695,6 +4729,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m CONFIG_OF_FPGA_REGION=m @@ -4846,6 +4881,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4981,6 +5017,8 @@ CONFIG_POWER_RESET_GPIO=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5122,10 +5160,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m CONFIG_PWM_OMAP_DMTIMER=m # CONFIG_PWM_PCA9685 is not set @@ -5150,6 +5190,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5265,10 +5306,12 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5375,7 +5418,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5419,6 +5464,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5554,8 +5600,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5599,6 +5646,13 @@ CONFIG_RTW89_8922AE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5847,6 +5901,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -5963,10 +6018,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6013,6 +6072,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6154,6 +6215,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6261,6 +6323,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6371,6 +6434,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6415,6 +6479,7 @@ CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6433,6 +6498,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6441,6 +6507,7 @@ CONFIG_SND_SOC_CX2072X=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6610,6 +6677,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -6746,6 +6814,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6867,6 +6936,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -7095,6 +7165,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7176,6 +7247,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7799,6 +7871,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7823,6 +7896,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7910,6 +7984,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -7919,6 +7994,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -7937,6 +8014,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -7956,6 +8034,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -8008,6 +8088,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8073,6 +8154,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -8367,7 +8449,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-ppc64le-rhel.config b/SOURCES/kernel-ppc64le-rhel.config index 5fd266b..326ae90 100644 --- a/SOURCES/kernel-ppc64le-rhel.config +++ b/SOURCES/kernel-ppc64le-rhel.config @@ -99,6 +99,7 @@ CONFIG_ACPI_VIDEO=m # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -375,6 +376,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -388,6 +390,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -412,6 +415,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -481,6 +485,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RSXX=m +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -857,6 +862,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -959,6 +965,7 @@ CONFIG_CRYPTO_CRYPTD=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_CTS=y CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_CURVE25519_PPC64=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set @@ -993,7 +1000,6 @@ CONFIG_CRYPTO_DEV_NX=y # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DEV_VMX_ENCRYPT=m CONFIG_CRYPTO_DEV_VMX=y @@ -1089,8 +1095,8 @@ CONFIG_CUSE=m # CONFIG_CX_ECAT is not set CONFIG_CXL_ACPI=m CONFIG_CXL_BUS=m -CONFIG_CXLFLASH=m -CONFIG_CXL=m +# CONFIG_CXLFLASH is not set +# CONFIG_CXL is not set CONFIG_CXL_MEM=m # CONFIG_CXL_MEM_RAW_COMMANDS is not set CONFIG_CXL_PCI=m @@ -1098,6 +1104,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1209,6 +1216,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1224,11 +1232,10 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_API_DEBUG_SG is not set @@ -1286,6 +1293,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1301,7 +1309,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1317,6 +1325,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1356,6 +1365,7 @@ CONFIG_DRM_I2C_CH7006=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1402,11 +1412,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1421,6 +1433,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1647,6 +1660,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_CPC925=m # CONFIG_EDAC_DEBUG is not set @@ -1685,10 +1699,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set # CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1696,10 +1713,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1785,6 +1806,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1845,17 +1867,17 @@ CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_LBC is not set # CONFIG_FSL_PQ_MDIO is not set @@ -1928,8 +1950,7 @@ CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=1 -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -1998,6 +2019,7 @@ CONFIG_GPIO_PCF857X=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2005,6 +2027,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2344,12 +2367,12 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_IBM_BSR=m @@ -2366,6 +2389,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2577,6 +2601,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -2865,6 +2890,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -2944,7 +2970,6 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y CONFIG_KVM_BOOK3S_64_HV=m CONFIG_KVM_BOOK3S_64=m # CONFIG_KVM_BOOK3S_64_PR is not set @@ -2954,11 +2979,9 @@ CONFIG_KVM_BOOK3S_HV_NESTED_PMU_WORKAROUND=y # CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_BOOK3S_PR_POSSIBLE=y CONFIG_KVM_GUEST=y -CONFIG_KVM_HYPERV=y CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set CONFIG_KVM_XICS=y @@ -2969,6 +2992,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3039,6 +3065,7 @@ CONFIG_LEDS_POWERNV=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3052,6 +3079,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3182,6 +3210,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3271,9 +3300,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3283,6 +3309,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3308,6 +3335,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3321,6 +3349,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3382,6 +3412,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3865,8 +3896,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -3876,8 +3909,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -3962,8 +3994,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4241,6 +4274,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4259,6 +4293,7 @@ CONFIG_NVRAM=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m CONFIG_OF_KUNIT_TEST=m @@ -4403,6 +4438,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4435,6 +4471,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4472,6 +4509,8 @@ CONFIG_PID_NS=y # CONFIG_PINCTRL_CS42L43 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set # CONFIG_PINCTRL is not set @@ -4542,6 +4581,8 @@ CONFIG_POWER_RESET_GPIO=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4684,6 +4725,7 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM_PCA9685 is not set # CONFIG_PWM_XILINX is not set @@ -4693,13 +4735,14 @@ CONFIG_PWM=y # CONFIG_PWRSEQ_SIMPLE is not set # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4712,6 +4755,7 @@ CONFIG_PWM=y # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4766,6 +4810,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -4849,6 +4894,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -4882,6 +4928,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_RESET_CONTROLLER is not set # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -4893,7 +4940,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -4931,6 +4978,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5058,6 +5106,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5097,6 +5146,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5450,9 +5506,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5497,6 +5557,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5637,6 +5698,7 @@ CONFIG_SIGNATURE=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5737,6 +5799,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -5840,6 +5903,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5902,6 +5966,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -5910,6 +5975,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6082,6 +6148,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6217,6 +6284,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6335,6 +6403,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6607,6 +6676,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6654,7 +6724,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7128,6 +7198,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7138,6 +7209,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7148,6 +7220,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7241,6 +7314,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7256,6 +7331,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7275,6 +7351,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7391,6 +7469,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7566,7 +7645,7 @@ CONFIG_XMON=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7622,7 +7701,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-riscv64-debug-fedora.config b/SOURCES/kernel-riscv64-debug-fedora.config new file mode 100644 index 0000000..51b92ad --- /dev/null +++ b/SOURCES/kernel-riscv64-debug-fedora.config @@ -0,0 +1,8607 @@ +# riscv +# CONFIG_60XX_WDT is not set +CONFIG_6LOWPAN_DEBUGFS=y +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6PACK=m +CONFIG_8139CP=m +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_8139TOO_8129=y +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_ABP060MG=m +CONFIG_ACCESSIBILITY=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI_AC=y +CONFIG_ACPI_ALS=m +CONFIG_ACPI_APEI_EINJ_CXL=y +CONFIG_ACPI_APEI_EINJ=m +CONFIG_ACPI_APEI_ERST_DEBUG=m +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_BUTTON=y +# CONFIG_ACPI_CMPC is not set +CONFIG_ACPI_CONFIGFS=m +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_CPUFREQ=m +CONFIG_ACPI_CUSTOM_METHOD=m +CONFIG_ACPI_DEBUGGER_USER=m +CONFIG_ACPI_DEBUGGER=y +CONFIG_ACPI_DEBUG=y +# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +# CONFIG_ACPI_FPDT is not set +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IPMI=m +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PLATFORM_PROFILE=m +CONFIG_ACPI_PRMT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI=y +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +CONFIG_AD3552R=m +CONFIG_AD4130=m +# CONFIG_AD5064 is not set +CONFIG_AD5110=m +# CONFIG_AD525X_DPOT is not set +CONFIG_AD5272=m +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +CONFIG_AD5766=m +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7091R5 is not set +CONFIG_AD7091R8=m +CONFIG_AD7124=m +# CONFIG_AD7150 is not set +# CONFIG_AD7173 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +CONFIG_AD7293=m +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +CONFIG_AD7380=m +CONFIG_AD74115=m +CONFIG_AD74413R=m +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7746 is not set +CONFIG_AD7766=m +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7944 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD8801 is not set +CONFIG_AD9467=m +# CONFIG_AD9523 is not set +# CONFIG_AD9739A is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_ADA4250 is not set +CONFIG_ADAPTEC_STARFIRE=m +# CONFIG_ADDRESS_MASKING is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +CONFIG_ADF4377=m +# CONFIG_ADFS_FS is not set +# CONFIG_ADI_AXI_ADC is not set +# CONFIG_ADI_AXI_DAC is not set +# CONFIG_ADIN1100_PHY is not set +CONFIG_ADIN1110=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADMFM2000 is not set +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV1014 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADMV8818 is not set +# CONFIG_ADRF6780 is not set +# CONFIG_ADT7316 is not set +CONFIG_ADUX1020=m +# CONFIG_ADVANTECH_WDT is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_ADV_SWBUTTON is not set +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +CONFIG_AF8133J=m +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +CONFIG_AFFS_FS=m +CONFIG_AF_KCM=m +CONFIG_AF_RXRPC_DEBUG=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_RXRPC=m +# CONFIG_AFS_DEBUG_CURSOR is not set +CONFIG_AFS_DEBUG=y +CONFIG_AFS_FSCACHE=y +CONFIG_AFS_FS=m +# CONFIG_AHCI_CEVA is not set +CONFIG_AHCI_DWC=m +# CONFIG_AHCI_QORIQ is not set +CONFIG_AIC79XX_CMDS_PER_DEVICE=4 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +CONFIG_AIO=y +CONFIG_AIR_EN8811H_PHY=m +CONFIG_AIX_PARTITION=y +# CONFIG_AK09911 is not set +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_AL_FIC is not set +# CONFIG_ALIBABA_ENI_VDPA is not set +CONFIG_ALIM1535_WDT=m +CONFIG_ALIM7101_WDT=m +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_FREEZE_BRIDGE is not set +# CONFIG_ALTERA_MBOX is not set +CONFIG_ALTERA_MSGDMA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_ALTERA_STAPL=m +CONFIG_ALTERA_TSE=m +CONFIG_ALX=m +# CONFIG_AM2315 is not set +# CONFIG_AMBA_PL08X is not set +CONFIG_AMD8111_ETH=m +CONFIG_AMD_ATL=m +# CONFIG_AMD_IOMMU_DEBUGFS is not set +CONFIG_AMD_PHY=m +CONFIG_AMD_PMC=m +# CONFIG_AMD_PTDMA is not set +# CONFIG_AMDTEE is not set +# CONFIG_AMD_XGBE_DCB is not set +# CONFIG_AMIGA_PARTITION is not set +CONFIG_AMT=m +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDERFS=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# CONFIG_ANON_VMA_NAME is not set +# CONFIG_AOSONG_AGS02MA is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9306=m +CONFIG_APDS9802ALS=m +# CONFIG_APDS9960 is not set +CONFIG_APPLE_MFI_FASTCHARGE=m +# CONFIG_APPLE_PROPERTIES is not set +# CONFIG_APPLICOM is not set +CONFIG_AQTION=m +CONFIG_AQUANTIA_PHY=m +CONFIG_AR5523=m +# CONFIG_ARCH_APPLE is not set +# CONFIG_ARCH_BCM4908 is not set +CONFIG_ARCH_CANAAN=y +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEEMBAY is not set +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_R9A07G043 is not set +CONFIG_ARCH_RANDOM=y +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SA1100 is not set +CONFIG_ARCH_SIFIVE=y +CONFIG_ARCH_SOPHGO=y +# CONFIG_ARCH_SPARX5 is not set +CONFIG_ARCH_STARFIVE=y +# CONFIG_ARCH_SUNXI is not set +CONFIG_ARCH_THEAD=y +CONFIG_ARCH_VIRT=y +# CONFIG_ARCNET is not set +CONFIG_ARM64_AMU_EXTN=y +CONFIG_ARM64_E0PD=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2119858=y +CONFIG_ARM64_ERRATUM_2139208=y +CONFIG_ARM64_ERRATUM_2224489=y +CONFIG_ARM64_ERRATUM_2253138=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +CONFIG_ARM_CMN=m +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set +CONFIG_ARM_PTDUMP_DEBUGFS=y +# CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set +# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set +# CONFIG_ARM_SCMI_TRANSPORT_SMC is not set +# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set +CONFIG_ARM_SMCCC_SOC_ID=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +# CONFIG_AS3935 is not set +# CONFIG_AS73211 is not set +# CONFIG_ASUS_TF103C_DOCK is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_AT803X_PHY=m +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATALK=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA=y +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_DEBUGFS=y +CONFIG_ATH10K_DEBUG=y +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SDIO=m +# CONFIG_ATH10K_SPECTRAL is not set +CONFIG_ATH10K_TRACING=y +CONFIG_ATH10K_USB=m +# CONFIG_ATH11K_AHB is not set +CONFIG_ATH11K_DEBUGFS=y +CONFIG_ATH11K_DEBUG=y +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m +CONFIG_ATH11K_SPECTRAL=y +CONFIG_ATH11K_TRACING=y +CONFIG_ATH12K_DEBUGFS=y +CONFIG_ATH12K_DEBUG=y +CONFIG_ATH12K=m +CONFIG_ATH12K_TRACING=y +CONFIG_ATH5K_DEBUG=y +CONFIG_ATH5K=m +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH6KL_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +# CONFIG_ATH6KL_TRACING is not set +CONFIG_ATH6KL_USB=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_BTCOEX_SUPPORT=y +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +CONFIG_ATH9K_DEBUGFS=y +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HWRNG is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_RFKILL=y +# CONFIG_ATH9K_STATION_STATISTICS is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH_COMMON=m +CONFIG_ATH_DEBUG=y +# CONFIG_ATH_TRACEPOINTS is not set +CONFIG_ATL1C=m +CONFIG_ATL1E=m +CONFIG_ATL1=m +CONFIG_ATL2=m +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_ATM_BR2684=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_TUNE_BURST is not set +# CONFIG_ATM_FORE200E is not set +CONFIG_ATM_HE=m +# CONFIG_ATM_HE_USE_SUNI is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +CONFIG_ATM_LANE=m +CONFIG_ATM=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +CONFIG_ATM_SOLOS=m +CONFIG_ATM_TCP=m +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_ATP=m +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_AX25=m +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y +CONFIG_AXP20X_ADC=m +CONFIG_AXP20X_POWER=m +CONFIG_AXP288_ADC=m +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_BCMA=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +CONFIG_B43_DEBUG=y +CONFIG_B43LEGACY_DEBUG=y +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_B43LEGACY_PIO=y +CONFIG_B43=m +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_N=y +CONFIG_B43_SDIO=y +CONFIG_B44=m +CONFIG_B44_PCI=y +CONFIG_B53=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +CONFIG_BACKLIGHT_ARCXCNN=m +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GPIO is not set +CONFIG_BACKLIGHT_KTD253=m +# CONFIG_BACKLIGHT_KTD2801 is not set +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +CONFIG_BACKLIGHT_MP3309C=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BACKLIGHT_RT4831=m +# CONFIG_BACKLIGHT_SAHARA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BARCO_P50_GPIO is not set +CONFIG_BAREUDP=m +CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_TRACING=y +CONFIG_BATTERY_AXP20X=m +# CONFIG_BATTERY_BQ27XXX is not set +CONFIG_BATTERY_CW2015=m +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m +# CONFIG_BATTERY_MAX1721X is not set +CONFIG_BATTERY_RT5033=m +CONFIG_BATTERY_SAMSUNG_SDI=y +# CONFIG_BATTERY_SBS is not set +CONFIG_BATTERY_SURFACE=m +CONFIG_BATTERY_UG3105=m +CONFIG_BAYCOM_EPP=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_DEBUG is not set +CONFIG_BCACHEFS_DEBUG_TRANSACTIONS=y +CONFIG_BCACHEFS_DEBUG=y +# CONFIG_BCACHEFS_ERASURE_CODING is not set +CONFIG_BCACHEFS_FS=m +CONFIG_BCACHEFS_LOCK_TIME_STATS=y +# CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set +CONFIG_BCACHEFS_POSIX_ACL=y +CONFIG_BCACHEFS_QUOTA=y +CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y +# CONFIG_BCACHEFS_TESTS is not set +CONFIG_BCACHE=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA=m +CONFIG_BCMGENET=m +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYPTP=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m +CONFIG_BE2ISCSI=m +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +# CONFIG_BE2NET_HWMON is not set +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET=m +CONFIG_BE2NET_SKYHAWK=y +# CONFIG_BEFS_DEBUG is not set +CONFIG_BEFS_FS=m +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +CONFIG_BH1750=m +# CONFIG_BH1780 is not set +CONFIG_BIG_KEYS=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITFIELD_KUNIT=m +CONFIG_BITS_TEST=m +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_CGROUP=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_DM=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_DEV_FD_RAWCMD is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION=y +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +# CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SX8=m +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLKDEV_UBLK_LEGACY_OPCODES=y +CONFIG_BLK_DEV_UBLK=m +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_WBT=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_BME680=m +# CONFIG_BMG160 is not set +# CONFIG_BMI088_ACCEL is not set +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BMI323_I2C=m +CONFIG_BMI323_SPI=m +CONFIG_BMP280=m +CONFIG_BNA=m +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_HWMON=y +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOUNCE=y +# CONFIG_BPFILTER is not set +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT=y +CONFIG_BPF_KPROBE_OVERRIDE=y +CONFIG_BPF_LIRC_MODE2=y +CONFIG_BPF_LSM=y +CONFIG_BPF_PRELOAD_UMD=m +CONFIG_BPF_PRELOAD=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPQETHER=m +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +CONFIG_BRCMDBG=y +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMSMAC=m +CONFIG_BRCM_TRACING=y +CONFIG_BRIDGE_CFM=y +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_AOSPEXT=y +CONFIG_BT_ATH3K=m +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_BREDR=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_QCA=y +# CONFIG_BT_HCIUART_RTL is not set +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIVHCI=m +CONFIG_BT_HIDP=m +# CONFIG_BT_HS is not set +CONFIG_BT_INTEL_PCIE=m +CONFIG_BT_LEDS=y +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_LE=y +CONFIG_BT=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_MSFTEXT=y +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_NXPUART=m +CONFIG_BT_QCA=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BTRFS_ASSERT=y +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_REF_VERIFY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTRFS_FS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BTT is not set +CONFIG_BT_VIRTIO=m +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_BUG=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +CONFIG_CACHEFILES=m +CONFIG_CACHEFILES_ONDEMAND=y +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_CAN327=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_C_CAN is not set +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +CONFIG_CAN_DEBUG_DEVICES=y +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_ESD_USB=m +# CONFIG_CAN_ETAS_ES58X is not set +CONFIG_CAN_F81604=m +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_GS_USB=m +CONFIG_CAN_GW=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_J1939=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +# CONFIG_CAN_M_CAN_PLATFORM is not set +# CONFIG_CAN_M_CAN_TCAN4X5X is not set +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +CONFIG_CAN_MCP251X=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_SJA1000 is not set +CONFIG_CAN_SLCAN=m +# CONFIG_CAN_SOFTING is not set +CONFIG_CAN_SUN4I=m +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +# CONFIG_CARDBUS is not set +CONFIG_CARL9170_DEBUGFS=y +# CONFIG_CARL9170_HWRNG is not set +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170=m +CONFIG_CASSINI=m +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +# CONFIG_CC10001_ADC is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CCS811 is not set +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD=m +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_CDX_CONTROLLER=m +CONFIG_CEC_CH7322=m +CONFIG_CEC_GPIO=m +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_CEC_PIN=y +# CONFIG_CEC_SECO is not set +CONFIG_CEC_SECO_RC=y +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CEPH_LIB=m +CONFIG_CEPH_LIB_PRETTYDEBUG=y +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_CFAG12864B=m +CONFIG_CFAG12864B_RATE=20 +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_KUNIT_TEST=m +CONFIG_CFG80211=m +# CONFIG_CFI_CLANG is not set +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUPS=y +# CONFIG_CHARGER_ADP5061 is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_CHARGER_BD99954=m +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ256XX=m +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m +CONFIG_CHARGER_CROS_PCHG=m +# CONFIG_CHARGER_CROS_USBPD is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +# CONFIG_CHARGER_MAX8903 is not set +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_RT9455 is not set +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +CONFIG_CHARGER_SURFACE=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECKSUM_KUNIT=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4_DCB=y +# CONFIG_CHELSIO_T4_FCOE is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHROMEOS_ACPI=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m +CONFIG_CHROMEOS_TBMC=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHT_DC_TI_PMIC_OPREGION=y +CONFIG_CICADA_PHY=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DEBUG=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS=m +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIO2_BRIDGE=y +CONFIG_CLEANCACHE=y +CONFIG_CLK_FD_KUNIT_TEST=m +CONFIG_CLK_GATE_KUNIT_TEST=m +# CONFIG_CLK_ICST is not set +CONFIG_CLK_KUNIT_TEST=m +# CONFIG_CLK_QORIQ is not set +# CONFIG_CLK_RASPBERRYPI is not set +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SOPHGO_CV1800=y +# CONFIG_CLK_SOPHGO_SG2042_PLL is not set +# CONFIG_CLK_SP810 is not set +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_CLK_STARFIVE_JH71X0=y +# CONFIG_CLK_SUNXI_CLOCKS is not set +# CONFIG_CLK_SUNXI is not set +# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CM32181=m +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMDLINE_KUNIT_TEST=m +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +CONFIG_CODA_FS=m +# CONFIG_COMEDI is not set +CONFIG_COMMAND_LINE_SIZE=4096 +CONFIG_COMMON_CLK_AXG_AUDIO=y +CONFIG_COMMON_CLK_AXI_CLKGEN=m +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set +# CONFIG_COMMON_CLK_FSL_SAI is not set +# CONFIG_COMMON_CLK_LAN966X is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_MMP2_AUDIO is not set +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +# CONFIG_COMMON_CLK_SI514 is not set +CONFIG_COMMON_CLK_SI521XX=y +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_VC3=m +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_COMMON_CLK_VC7=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACTION=y +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPAT is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CORDIC=m +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_COREDUMP=y +# CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON is not set +CONFIG_CORTINA_PHY=m +# CONFIG_COUNTER is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +# CONFIG_CPU_IDLE_GOV_LADDER is not set +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPUMASK_KUNIT_TEST=m +CONFIG_CPUMASK_OFFSTACK=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPUSETS=y +# CONFIG_CPU_THERMAL is not set +# CONFIG_CRAMFS is not set +# CONFIG_CRAMFS_MTD is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_HOTPLUG=y +CONFIG_CRASH_MAX_MEMORY_RANGES=8192 +CONFIG_CRC16=y +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC32=y +CONFIG_CRC4=m +CONFIG_CRC64=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_T10DIF=y +# CONFIG_CROS_EC_DEBUGFS is not set +# CONFIG_CROS_EC is not set +# CONFIG_CROS_EC_LIGHTBAR is not set +CONFIG_CROS_EC_MKBP_PROXIMITY=m +CONFIG_CROS_EC_RPMSG=m +CONFIG_CROS_EC_SENSORHUB=m +CONFIG_CROS_EC_TYPEC=m +CONFIG_CROS_EC_UART=m +CONFIG_CROS_EC_WATCHDOG=m +CONFIG_CROS_HPS_I2C=m +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_CROS_KUNIT_EC_PROTO_TEST=m +CONFIG_CROS_KUNIT=m +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CROS_TYPEC_SWITCH=m +CONFIG_CROS_USBPD_LOGGER=m +CONFIG_CROS_USBPD_NOTIFY=m +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_AEGIS128=m +# CONFIG_CRYPTO_AES_ARM64 is not set +CONFIG_CRYPTO_AES_RISCV64=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CHACHA_RISCV64=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C_VPMSUM=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +CONFIG_CRYPTO_DEV_CCP_DEBUGFS=y +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_HIFN_795X=m +CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_HISI_TRNG is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set +CONFIG_CRYPTO_DEV_QAT_420XX=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +# CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SP_CCP is not set +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +# CONFIG_CRYPTO_FIPS_CUSTOM_VERSION is not set +CONFIG_CRYPTO_FIPS_NAME="Linux Kernel Cryptographic API" +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GHASH_RISCV64=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_1024 is not set +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_128 is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_2=y +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_8192 is not set +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256_RISCV64=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512_RISCV64=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_SM3_RISCV64 is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_SM4_RISCV64 is not set +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_USER_API_AEAD=y +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +CONFIG_CRYPTO_USER_API_HASH=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ZSTD=m +# CONFIG_CSD_LOCK_WAIT_DEBUG_DEFAULT is not set +CONFIG_CSD_LOCK_WAIT_DEBUG=y +CONFIG_CUSE=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_CXD2880_SPI_DRV=m +# CONFIG_CX_ECAT is not set +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=m +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=m +CONFIG_CXL_PMEM=m +CONFIG_CXL_PMU=m +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DA9063_WATCHDOG=m +# CONFIG_DAMON_DBGFS_DEPRECATED is not set +CONFIG_DAMON_DBGFS=y +# CONFIG_DAMON_LRU_SORT is not set +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCB=y +# CONFIG_DDR is not set +CONFIG_DE2104X_DSL=0 +CONFIG_DE2104X=m +CONFIG_DEBUG_ATOMIC_SLEEP=y +CONFIG_DEBUG_BOOT_PARAMS=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +CONFIG_DEBUG_CREDENTIALS=y +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_DEBUG_HIGHMEM=y +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_BTF=y +# CONFIG_DEBUG_INFO_COMPRESSED is not set +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_IRQFLAGS=y +# CONFIG_DEBUG_KERNEL_DC is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_KMAP_LOCAL=y +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=40000 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +CONFIG_DEBUG_LIST=y +CONFIG_DEBUG_LOCK_ALLOC=y +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +CONFIG_DEBUG_MISC=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_NET=y +CONFIG_DEBUG_NOTIFIERS=y +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=1 +CONFIG_DEBUG_OBJECTS_FREE=y +CONFIG_DEBUG_OBJECTS_PERCPU_COUNTER=y +CONFIG_DEBUG_OBJECTS_RCU_HEAD=y +# CONFIG_DEBUG_OBJECTS_SELFTEST is not set +CONFIG_DEBUG_OBJECTS_TIMERS=y +CONFIG_DEBUG_OBJECTS_WORK=y +CONFIG_DEBUG_OBJECTS=y +# CONFIG_DEBUG_PAGEALLOC_ENABLE_DEFAULT is not set +CONFIG_DEBUG_PAGEALLOC=y +CONFIG_DEBUG_PAGE_REF=y +CONFIG_DEBUG_PER_CPU_MAPS=y +CONFIG_DEBUG_PERF_USE_VMALLOC=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_RWSEMS=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_SG=y +CONFIG_DEBUG_SHIRQ=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_STACK_USAGE=y +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM_MAPLE_TREE is not set +CONFIG_DEBUG_VM_PGFLAGS=y +CONFIG_DEBUG_VM_PGTABLE=y +# CONFIG_DEBUG_VM_RB is not set +CONFIG_DEBUG_VM_SHOOT_LAZIES=y +# CONFIG_DEBUG_VM_VMACACHE is not set +CONFIG_DEBUG_VM=y +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +CONFIG_DEBUG_WX=y +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +# CONFIG_DEV_DAX_KMEM is not set +CONFIG_DEV_DAX=m +# CONFIG_DEV_DAX_PMEM_COMPAT is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_DEVTMPFS=y +CONFIG_DHT11=m +CONFIG_DL2K=m +# CONFIG_DLHL60D is not set +CONFIG_DLM_DEBUG=y +# CONFIG_DLM_DEPRECATED_API is not set +CONFIG_DLM=m +CONFIG_DLN2_ADC=m +CONFIG_DM9051=m +CONFIG_DM9102=m +CONFIG_DMA_API_DEBUG_SG=y +CONFIG_DMA_API_DEBUG=y +CONFIG_DMABUF_DEBUG=y +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# CONFIG_DMA_CMA is not set +CONFIG_DMADEVICES_DEBUG=y +CONFIG_DMADEVICES_VDEBUG=y +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +# CONFIG_DMA_NUMA_CMA is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +CONFIG_DMARD10=m +# CONFIG_DMA_RESTRICTED_POOL is not set +# CONFIG_DMATEST is not set +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_CLONE=m +CONFIG_DM_CRYPT=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set +CONFIG_DM_DEBUG=y +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +CONFIG_DMIID=y +CONFIG_DM_INIT=y +CONFIG_DM_INTEGRITY=m +CONFIG_DMI_SYSFS=y +CONFIG_DMI=y +# CONFIG_DM_KUNIT_TEST is not set +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=y +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_VDO=m +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ZERO=y +CONFIG_DM_ZONED=m +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=m +CONFIG_DP83640_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +CONFIG_DP83TG720_PHY=m +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DPOT_DAC=m +# CONFIG_DPS310 is not set +CONFIG_DRAGONRISE_FF=y +CONFIG_DRBD_FAULT_INJECTION=y +CONFIG_DRIVER_PE_KUNIT_TEST=m +# CONFIG_DRM_ACCEL_QAIC is not set +CONFIG_DRM_ACCEL=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC_HDCP=y +CONFIG_DRM_AMD_DC_SI=y +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y +CONFIG_DRM_AMD_SECURE_DISPLAY=y +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_CIRRUS_QEMU=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE is not set +CONFIG_DRM_DISPLAY_DP_AUX_CEC=y +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y +# CONFIG_DRM_DISPLAY_DP_TUNNEL_STATE_DEBUG is not set +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FSL_LDB is not set +CONFIG_DRM_GM12U320=m +CONFIG_DRM_GUD=m +# CONFIG_DRM_HISI_HIBMC is not set +CONFIG_DRM_HYPERV=m +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_CH7006=m +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_IMX_LCDIF is not set +CONFIG_DRM_ITE_IT6505=m +# CONFIG_DRM_ITE_IT66121 is not set +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_KUNIT_TEST=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +CONFIG_DRM_LONTIUM_LT9611UXC=m +# CONFIG_DRM_LOONGSON is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +# CONFIG_DRM_MSM_GPU_SUDO is not set +# CONFIG_DRM_MSM_VALIDATE_XML is not set +# CONFIG_DRM_MXSFB is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y +CONFIG_DRM_NOUVEAU=m +# CONFIG_DRM_NOUVEAU_SVM is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_DSI_CM=m +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +CONFIG_DRM_PANEL_ILITEK_ILI9882T=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LPM102A188A=m +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +CONFIG_DRM_PANEL_JDI_R63452=m +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m +# CONFIG_DRM_PANEL_LVDS is not set +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_MIPI_DBI=m +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m +CONFIG_DRM_PANEL_RAYDIUM_RM69380=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +CONFIG_DRM_PANEL_VISIONOX_R66451=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PARADE_PS8622 is not set +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set +CONFIG_DRM_SAMSUNG_DSIM=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_SIMPLEDRM=y +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_SPI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +CONFIG_DRM_TI_DLPC3433=m +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +# CONFIG_DRM_TOSHIBA_TC358767 is not set +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +# CONFIG_DRM_TTM_KUNIT_TEST is not set +CONFIG_DRM_UDL=m +CONFIG_DRM_USE_DYNAMIC_DEBUG=y +# CONFIG_DRM_VBOXVIDEO is not set +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VKMS=m +CONFIG_DRM_VMWGFX_FBCON=y +CONFIG_DRM_VMWGFX=m +# CONFIG_DRM_VMWGFX_MKSSTATS is not set +CONFIG_DRM_WERROR=y +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +# CONFIG_DRM_XE_KUNIT_TEST is not set +# CONFIG_DRM_XE_LARGE_GUC_BUFFER is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XEN_FRONTEND is not set +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +# CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE is not set +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +CONFIG_DRM=y +# CONFIG_DS1682 is not set +# CONFIG_DS1803 is not set +# CONFIG_DS4424 is not set +CONFIG_DTPM_CPU=y +CONFIG_DTPM_DEVFREQ=y +CONFIG_DTPM=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_DUMMY_CONSOLE=y +# CONFIG_DUMMY_IRQ is not set +CONFIG_DUMMY=m +CONFIG_DVB_AS102=m +# CONFIG_DVB_AV7110 is not set +CONFIG_DVB_B2C2_FLEXCOP=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_BT8XX=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CXD2099=m +# CONFIG_DVB_CXD2880 is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_DIB9000 is not set +CONFIG_DVB_DM1105=m +# CONFIG_DVB_DUMMY_FE is not set +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_HOPPER=m +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LNBH29 is not set +CONFIG_DVB_MANTIS=m +CONFIG_DVB_MAX_ADAPTERS=16 +# CONFIG_DVB_MMAP is not set +# CONFIG_DVB_MN88443X is not set +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NET=y +CONFIG_DVB_NGENE=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +# CONFIG_DVB_PT3 is not set +# CONFIG_DVB_S5H1432 is not set +CONFIG_DVB_SMIPCIE=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +# CONFIG_DVB_ULE_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB0700=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DW_AXI_DMAC=m +CONFIG_DWC_PCIE_PMU=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +# CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_DWMAC_LOONGSON is not set +CONFIG_DWMAC_STARFIVE=m +# CONFIG_DW_WATCHDOG is not set +CONFIG_DW_XDATA_PCIE=m +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_E1000E=m +CONFIG_E1000=m +CONFIG_E100=m +CONFIG_EARLY_PRINTK_DBGP=y +CONFIG_EARLY_PRINTK_USB_XDBC=y +CONFIG_EARLY_PRINTK=y +# CONFIG_EBC_C384_WDT is not set +CONFIG_ECHO=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +CONFIG_EDAC_DEBUG=y +CONFIG_EDAC_DMC520=m +CONFIG_EDAC_GHES=y +CONFIG_EDAC_IGEN6=m +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SIFIVE=y +# CONFIG_EDAC_SYNOPSYS is not set +CONFIG_EDAC=y +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_EE1004=m +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_MAX6875=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +CONFIG_EFI_COCO_SECRET=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_HANDOVER_PROTOCOL=y +CONFIG_EFI_PARTITION=y +CONFIG_EFI_PGT_DUMP=y +# CONFIG_EFI_RCI2_TABLE is not set +CONFIG_EFI_SECRET=m +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +CONFIG_EFI_TEST=m +CONFIG_EFIVAR_FS=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI=y +CONFIG_EFI_ZBOOT=y +# CONFIG_EFS_FS is not set +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +# CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set +CONFIG_ENERGY_MODEL=y +CONFIG_ENIC=m +# CONFIG_ENS160 is not set +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EQUALIZER=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_ONDEMAND=y +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP_DEFLATE=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_ZSTD=y +CONFIG_ERRATA_ANDES_CMO=y +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE=y +# CONFIG_ERRATA_STARFIVE_JH7100 is not set +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ERRATA_THEAD=y +CONFIG_ET131X=m +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +# CONFIG_EUROTECH_WDT is not set +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +# CONFIG_EVM_LOAD_X509 is not set +CONFIG_EVM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=m +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_DEBUG=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_KUNIT_TESTS=m +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_QCOM_SPMI_MISC is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +CONFIG_EXTCON_USBC_TUSB320=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +CONFIG_FAIL_FUNCTION=y +# CONFIG_FAIL_FUTEX is not set +CONFIG_FAIL_IO_TIMEOUT=y +CONFIG_FAIL_MAKE_REQUEST=y +CONFIG_FAIL_MMC_REQUEST=y +CONFIG_FAILOVER=m +CONFIG_FAIL_PAGE_ALLOC=y +CONFIG_FAILSLAB=y +CONFIG_FAIL_SUNRPC=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_FANOTIFY=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=m +CONFIG_FAT_KUNIT_TEST=m +# CONFIG_FAULT_INJECTION_CONFIGFS is not set +CONFIG_FAULT_INJECTION_DEBUG_FS=y +CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y +# CONFIG_FAULT_INJECTION_USERCOPY is not set +CONFIG_FAULT_INJECTION=y +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DEVICE is not set +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_HYPERV is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_I810 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX_G is not set +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MATROX_MILLENIUM is not set +# CONFIG_FB_MATROX_MYSTIQUE is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +CONFIG_FB_SIMPLE=y +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM501 is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SM750 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +# CONFIG_FB_TFT is not set +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +CONFIG_FB_VESA=y +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XILINX is not set +CONFIG_FB=y +CONFIG_FCOE=m +# CONFIG_FDDI is not set +CONFIG_FEALNX=m +CONFIG_FHANDLE=y +# CONFIG_FIELDBUS_DEV is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIXED_PHY=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FORCEDETH=m +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_FORTIFY_KUNIT_TEST=m +CONFIG_FORTIFY_SOURCE=y +CONFIG_FPGA_BRIDGE=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set +CONFIG_FPGA_MGR_XILINX_SELECTMAP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ZYNQ_FPGA=m +CONFIG_FPGA_REGION=m +CONFIG_FPROBE_EVENTS=y +CONFIG_FPROBE=y +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FRONTSWAP=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE=y +CONFIG_FS_DAX=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_ENCRYPTION=y +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_ENETC_IERB is not set +# CONFIG_FSL_ENETC is not set +# CONFIG_FSL_ENETC_MDIO is not set +# CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_PQ_MDIO is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_FSL_RCPM is not set +CONFIG_FS_MBCACHE=y +CONFIG_FSNOTIFY=y +CONFIG_FS_PID=y +# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set +# CONFIG_FS_VERITY_DEBUG is not set +CONFIG_FS_VERITY=y +# CONFIG_FTL is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +CONFIG_FTRACE=y +CONFIG_FUEL_GAUGE_MM8013=m +# CONFIG_FUJITSU_ES is not set +# CONFIG_FUNCTION_ERROR_INJECTION is not set +CONFIG_FUNCTION_GRAPH_RETVAL=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUN_ETH=m +CONFIG_FUSE_DAX=y +CONFIG_FUSE_FS=m +CONFIG_FUSE_PASSTHROUGH=y +CONFIG_FUSION_CTL=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_SAS=m +CONFIG_FUSION_SPI=m +CONFIG_FUSION=y +CONFIG_FUTEX=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER=y +CONFIG_FW_UPLOAD=y +CONFIG_FXAS21002C=m +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_GACT_PROB=y +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# CONFIG_GCC_PLUGINS is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_GENERIC_ADC_THERMAL is not set +# CONFIG_GENERIC_CPU is not set +CONFIG_GENERIC_IRQ_DEBUGFS=y +CONFIG_GENERIC_PHY=y +CONFIG_GENEVE=m +# CONFIG_GEN_RTC is not set +# CONFIG_GENWQE is not set +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_GFS2_FS=m +# CONFIG_GIGABYTE_WMI is not set +# CONFIG_GLOB_SELFTEST is not set +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +# CONFIG_GOLDFISH_AUDIO is not set +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +CONFIG_GOLDFISH=y +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +CONFIG_GPIO_AGGREGATOR=m +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_BCM_XGS_IPROC is not set +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BT8XX=m +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CROS_EC=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_DS4520=m +# CONFIG_GPIO_DWAPB is not set +CONFIG_GPIO_EXAR=m +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_FXL6408=m +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_IT87 is not set +# CONFIG_GPIO_LATCH is not set +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB=y +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_MAX77650=m +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_MLXBF2=m +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_MXC=m +# CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +CONFIG_GPIO_PCI_IDIO_16=m +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SCH311X is not set +CONFIG_GPIO_SIFIVE=y +CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SYSCON=m +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TPIC2810 is not set +CONFIG_GPIO_TPS65219=m +# CONFIG_GPIO_TS4900 is not set +# CONFIG_GPIO_VIPERBOARD is not set +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WINBOND is not set +CONFIG_GPIO_WM8994=m +# CONFIG_GPIO_WS16C48 is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +CONFIG_GP_PCI1XXXX=m +CONFIG_GREENASIA_FF=y +# CONFIG_GREYBUS is not set +# CONFIG_GS_FPGABOOT is not set +CONFIG_GTP=m +CONFIG_GUP_TEST=y +CONFIG_GVE=m +# CONFIG_HABANA_AI is not set +CONFIG_HAMACHI=m +CONFIG_HAMRADIO=y +CONFIG_HANGCHECK_TIMER=m +CONFIG_HAPPYMEAL=m +CONFIG_HARDENED_USERCOPY=y +# CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY is not set +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_HASH_KUNIT_TEST=m +CONFIG_HASHTABLE_KUNIT_TEST=m +CONFIG_HD44780=m +# CONFIG_HDC100X is not set +CONFIG_HDC2010=m +# CONFIG_HDC3020 is not set +CONFIG_HEADERS_INSTALL=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_HI6421V600_IRQ=m +# CONFIG_HI8435 is not set +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBERNATION=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_ACRUX=m +CONFIG_HID_ALPS=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_APPLE=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_BPF=y +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +# CONFIG_HID_GOOGLE_HAMMER is not set +CONFIG_HID_GOOGLE_STADIA_FF=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_HYPERV_MOUSE=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KUNIT_TEST=m +CONFIG_HID_KYE=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_MACALLY=m +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +# CONFIG_HID_MCP2200 is not set +CONFIG_HID_MCP2221=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=y +CONFIG_HID_NVIDIA_SHIELD=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD=m +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_PXRC=m +CONFIG_HIDRAW=y +CONFIG_HID_RAZER=m +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_RETRODE=m +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_HID_SENSOR_PRESS is not set +# CONFIG_HID_SENSOR_PROX is not set +CONFIG_HID_SENSOR_TEMP=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPRE=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VIVALDI=m +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WINWING=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_XINMO=m +CONFIG_HID=y +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_DMA is not set +CONFIG_HISI_HIKEY_USB=m +# CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HIST_TRIGGERS_DEBUG is not set +CONFIG_HIST_TRIGGERS=y +CONFIG_HMC425=m +# CONFIG_HMC6352 is not set +CONFIG_HOLTEK_FF=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_ACPI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +CONFIG_HOTPLUG_PCI_PCIE=y +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HOTPLUG_PCI=y +# CONFIG_HP03 is not set +# CONFIG_HP206C is not set +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD_SVM=y +CONFIG_HSA_AMD=y +# CONFIG_HSC030PA is not set +# CONFIG_HSI is not set +CONFIG_HSR=m +# CONFIG_HSU_DMA is not set +CONFIG_HT16K33=m +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTE is not set +CONFIG_HTS221=m +# CONFIG_HTU21 is not set +CONFIG_HUGETLBFS=y +# CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON is not set +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PAGE=y +# CONFIG_HVC_RISCV_SBI is not set +CONFIG_HW_CONSOLE=y +CONFIG_HWLAT_TRACER=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON=y +CONFIG_HWPOISON_INJECT=m +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +CONFIG_HW_RANDOM_JH7110=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM=y +CONFIG_HWSPINLOCK=y +# CONFIG_HX711 is not set +CONFIG_HYPERV_BALLOON=m +CONFIG_HYPERV_IOMMU=y +CONFIG_HYPERV_KEYBOARD=m +CONFIG_HYPERV=m +CONFIG_HYPERV_NET=m +CONFIG_HYPERV_STORAGE=m +# CONFIG_HYPERV_TESTING is not set +CONFIG_HYPERV_UTILS=m +CONFIG_HYPERV_VSOCKETS=m +CONFIG_HZ_1000=y +# CONFIG_HZ_100 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_ALGOPCF=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD756_S4882 is not set +# CONFIG_I2C_AMD8111 is not set +CONFIG_I2C_AMD_MP2=m +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_ATR=m +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CP2615=m +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_FSI is not set +CONFIG_I2C_GPIO_FAULT_INJECTOR=y +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF_ELAN=m +# CONFIG_I2C_HID_OF_GOODIX is not set +# CONFIG_I2C_HID_OF is not set +CONFIG_I2C_HID=y +# CONFIG_I2C_HISI is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_MICROCHIP_CORE is not set +CONFIG_I2C_MLXBF=m +CONFIG_I2C_MLXCPLD=m +# CONFIG_I2C_MUX_GPIO is not set +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_NFORCE2_S4985 is not set +# CONFIG_I2C_NOMADIK is not set +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_OCORES=y +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_PCI1XXXX=m +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_QCOM_CCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +CONFIG_I2C_SCMI=m +CONFIG_I2C_SI470X=m +# CONFIG_I2C_SI4713 is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIPERBOARD is not set +CONFIG_I2C_VIRTIO=m +# CONFIG_I2C_XILINX is not set +CONFIG_I2C=y +CONFIG_I2C_ZHAOXIN=m +# CONFIG_I3C is not set +# CONFIG_I40E_DCB is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +CONFIG_I6300ESB_WDT=m +# CONFIG_I8K is not set +# CONFIG_IAQCORE is not set +CONFIG_ICE_HWMON=y +CONFIG_ICE_HWTS=y +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICP10100=m +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +# CONFIG_IDLE_INJECT is not set +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_ADF7242=m +# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_ATUSB=m +# CONFIG_IEEE802154_CA8210_DEBUGFS is not set +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_HWSIM is not set +CONFIG_IEEE802154=m +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_MRF24J40=m +# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set +CONFIG_IEEE802154_SOCKET=m +CONFIG_IFB=m +CONFIG_IFCVF=m +CONFIG_IGB_DCA=y +CONFIG_IGB_HWMON=y +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGC=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m +CONFIG_IIO_FORMAT_KUNIT_TEST=m +CONFIG_IIO_GTS_KUNIT_TEST=m +# CONFIG_IIO_HRTIMER_TRIGGER is not set +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_KX022A_I2C=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO=m +CONFIG_IIO_MUX=m +CONFIG_IIO_RESCALE_KUNIT_TEST=m +CONFIG_IIO_RESCALE=m +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_SPI_3AXIS=m +CONFIG_IIO_ST_LSM6DSX=m +# CONFIG_IIO_ST_LSM9DS0 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_IIO_ST_PRESS is not set +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IIO_TRIGGER=y +# CONFIG_IKCONFIG is not set +CONFIG_IKHEADERS=m +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +CONFIG_IMA_APPRAISE_MODSIG=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_ARCH_POLICY=y +# CONFIG_IMA_BLACKLIST_KEYRING is not set +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DISABLE_HTABLE is not set +CONFIG_IMA_KEXEC=y +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y +# CONFIG_IMA_LOAD_X509 is not set +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_TEMPLATE is not set +CONFIG_IMA_WRITE_POLICY=y +CONFIG_IMA=y +# CONFIG_IMG_ASCII_LCD is not set +# CONFIG_INA2XX_ADC is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_INET_DIAG=y +CONFIG_INET_ESPINTCP=y +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=y +CONFIG_INET_RAW_DIAG=y +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=y +CONFIG_INET=y +CONFIG_INFINIBAND_ADDR_TRANS=y +# CONFIG_INFINIBAND_BNXT_RE is not set +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_QIB_DCA=y +CONFIG_INFINIBAND_QIB=m +CONFIG_INFINIBAND_RDMAVT=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USNIC=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +# CONFIG_INFTL is not set +# CONFIG_INIT_MLOCKED_ON_FREE_DEFAULT_ON is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INITRAMFS_PRESERVE_MTIME is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INIT_STACK_ALL_PATTERN is not set +CONFIG_INIT_STACK_ALL_ZERO=y +# CONFIG_INIT_STACK_NONE is not set +CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +CONFIG_INPUT_APANEL=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_ATLAS_BTNS=m +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +CONFIG_INPUT_AXP20X_PEK=m +# CONFIG_INPUT_BMA150 is not set +CONFIG_INPUT_CM109=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m +# CONFIG_INPUT_DA7280_HAPTICS is not set +CONFIG_INPUT_DA9063_ONKEY=m +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +CONFIG_INPUT_E3X0_BUTTON=m +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_GPIO_VIBRA=m +# CONFIG_INPUT_IBM_PANEL is not set +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m +# CONFIG_INPUT_IMS_PCU is not set +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KUNIT_TEST=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSE=y +# CONFIG_INPUT_PCF8574 is not set +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_PMIC8XXX_PWRKEY=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_PWM_BEEPER=m +# CONFIG_INPUT_PWM_VIBRA is not set +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_WISTRON_BTNS=m +CONFIG_INPUT=y +CONFIG_INPUT_YEALINK=m +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +CONFIG_INTEGRITY_CA_MACHINE_KEYRING_MAX=y +CONFIG_INTEGRITY_CA_MACHINE_KEYRING=y +CONFIG_INTEGRITY_MACHINE_KEYRING=y +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +CONFIG_INTEGRITY=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD_COMPAT is not set +CONFIG_INTEL_IDXD=m +# CONFIG_INTEL_IDXD_PERFMON is not set +# CONFIG_INTEL_IOMMU_DEBUGFS is not set +# CONFIG_INTEL_ISHTP_ECLITE is not set +# CONFIG_INTEL_LDMA is not set +# CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_PMT_CLASS is not set +# CONFIG_INTEL_PMT_CRASHLOG is not set +# CONFIG_INTEL_PMT_TELEMETRY is not set +# CONFIG_INTEL_SAR_INT1092 is not set +# CONFIG_INTEL_SCU_PCI is not set +# CONFIG_INTEL_SCU_PLATFORM is not set +CONFIG_INTEL_SOC_PMIC_CHTDC_TI=y +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTEL_TCC_COOLING is not set +# CONFIG_INTEL_TH is not set +CONFIG_INTEL_UNCORE_FREQ_CONTROL=m +# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set +CONFIG_INTEL_XWAY_PHY=m +# CONFIG_INTERCONNECT_QCOM_SM6350 is not set +CONFIG_INTERCONNECT=y +# CONFIG_INTERVAL_TREE_TEST is not set +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_INV_MPU6050_SPI is not set +CONFIG_IO_DELAY_0X80=y +# CONFIG_IO_DELAY_0XED is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_IO_DELAY_UDELAY is not set +CONFIG_IOMMU_DEBUGFS=y +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMUFD_TEST=y +CONFIG_IOMMUFD=y +CONFIG_IOMMU_SUPPORT=y +CONFIG_IONIC=m +CONFIG_IOSCHED_BFQ=y +CONFIG_IOSM=m +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IPC_NS=y +# CONFIG_IP_DCCP is not set +CONFIG_IP_FIB_TRIE_STATS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_IPMB=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IPU_BRIDGE=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6=y +CONFIG_IPVLAN=m +CONFIG_IP_VS_DEBUG=y +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IPVTAP=m +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_PWM_TX=m +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SANYO_DECODER=m +# CONFIG_IRSD200 is not set +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_XMP_DECODER=m +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +# CONFIG_ISA is not set +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +# CONFIG_ISL29125 is not set +# CONFIG_ISL29501 is not set +# CONFIG_ISL76682 is not set +CONFIG_ISO9660_FS=m +CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m +CONFIG_IT8712F_WDT=m +CONFIG_IT87_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +CONFIG_ITCO_WDT=m +# CONFIG_ITG3200 is not set +CONFIG_IWL3945=m +CONFIG_IWL4965=m +CONFIG_IWLDVM=m +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLEGACY_DEBUG=y +CONFIG_IWLEGACY=m +# CONFIG_IWLMEI is not set +CONFIG_IWLMVM=m +# CONFIG_IWLWIFI_BCAST_FILTERING is not set +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_IWLWIFI_DEBUG=y +CONFIG_IWLWIFI_DEVICE_TRACING=y +CONFIG_IWLWIFI=m +CONFIG_IXGBE_DCA=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGB=m +CONFIG_JBD2_DEBUG=y +CONFIG_JBD2=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_STATISTICS is not set +CONFIG_JH71XX_PMU=y +CONFIG_JME=m +CONFIG_JOLIET=y +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_ANALOG=m +# CONFIG_JOYSTICK_AS5011 is not set +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_DB9=m +# CONFIG_JOYSTICK_FSIA6B is not set +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_JOYDUMP=m +# CONFIG_JOYSTICK_MAGELLAN is not set +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +# CONFIG_JOYSTICK_SEESAW is not set +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_JOYSTICK_SIDEWINDER=m +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_STINGER is not set +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_TURBOGRAFX=m +# CONFIG_JOYSTICK_TWIDJOY is not set +CONFIG_JOYSTICK_WALKERA0701=m +# CONFIG_JOYSTICK_WARRIOR is not set +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_XPAD=m +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JSA1212 is not set +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KASAN_EXTRA_INFO is not set +CONFIG_KASAN_GENERIC=y +CONFIG_KASAN_INLINE=y +CONFIG_KASAN_KUNIT_TEST=m +# CONFIG_KASAN_MODULE_TEST is not set +# CONFIG_KASAN_OUTLINE is not set +CONFIG_KASAN_VMALLOC=y +CONFIG_KASAN=y +# CONFIG_KCOV is not set +# CONFIG_KCSAN is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KDB_DEFAULT_ENABLE=0x0 +CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_UNCOMPRESSED is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_KEXEC_SIG=y +CONFIG_KEXEC=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_APPLESPI is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +CONFIG_KEYBOARD_PMIC8XXX=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_KEYS=y +# CONFIG_KFENCE_DEFERRABLE is not set +# CONFIG_KFENCE is not set +CONFIG_KFENCE_KUNIT_TEST=m +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_KDB=y +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KGDB_TESTS=y +CONFIG_KGDB=y +# CONFIG_KMX61 is not set +CONFIG_KPROBE_EVENT_GEN_TEST=m +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_KPROBE_EVENTS=y +CONFIG_KPROBES_SANITY_TEST=m +CONFIG_KPROBES=y +# CONFIG_KS7010 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_KSM=y +CONFIG_KSZ884X_PCI=m +CONFIG_KUNIT_ALL_TESTS=m +CONFIG_KUNIT_DEBUGFS=y +# CONFIG_KUNIT_DEFAULT_ENABLED is not set +CONFIG_KUNIT_EXAMPLE_TEST=m +# CONFIG_KUNIT_FAULT_TEST is not set +CONFIG_KUNIT=m +CONFIG_KUNIT_TEST=m +CONFIG_KVM_MAX_NR_VCPUS=4096 +CONFIG_KVM_PROVE_MMU=y +CONFIG_KVM_SMM=y +# CONFIG_KVM_WERROR is not set +CONFIG_KVM_XEN=y +CONFIG_KVM=y +CONFIG_KXCJK1013=m +# CONFIG_KXSD9 is not set +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m +CONFIG_LAN966X_SWITCH=m +# CONFIG_LAPB is not set +CONFIG_LATENCYTOP=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_DEBUG is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AN30259A=m +# CONFIG_LEDS_ARIEL is not set +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_AW200XX=m +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLEVO_MAIL=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GROUP_MULTICOLOR=m +# CONFIG_LEDS_IS31FL319X is not set +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_KTD202X=m +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LGM is not set +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +# CONFIG_LEDS_LM355x is not set +CONFIG_LEDS_LM3601X=m +# CONFIG_LEDS_LM36274 is not set +# CONFIG_LEDS_LM3642 is not set +CONFIG_LEDS_LM3692X=m +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MAX5970=m +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_MLXCPLD=m +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_NCP5623=m +CONFIG_LEDS_NIC78BX=m +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_REGULATOR=m +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m +CONFIG_LEDS_SYSCON=y +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_LEDS_USER=m +CONFIG_LED_TRIGGER_PHY=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +CONFIG_LIB80211_CRYPT_WEP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_LIB80211=m +CONFIG_LIBCRC32C=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBNVDIMM=m +# CONFIG_LIDAR_LITE_V2 is not set +CONFIG_LINEAR_RANGES_TEST=m +CONFIG_LIRC=y +CONFIG_LIST_KUNIT_TEST=m +CONFIG_LITEX_LITEETH=y +CONFIG_LITEX_SOC_CONTROLLER=y +CONFIG_LIVEPATCH=y +# CONFIG_LKDTM is not set +# CONFIG_LLC2 is not set +CONFIG_LLC=m +# CONFIG_LMK04832 is not set +CONFIG_LMP91000=m +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKDEP_BITS=16 +CONFIG_LOCKDEP_CHAINS_BITS=19 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKD=m +# CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +CONFIG_LOCKD_V4=y +CONFIG_LOCK_EVENT_COUNTS=y +CONFIG_LOCK_STAT=y +CONFIG_LOCK_TORTURE_TEST=m +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOGIG940_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO=y +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +CONFIG_LP_CONSOLE=y +# CONFIG_LPC_SCH is not set +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,integrity,selinux,bpf,landlock" +CONFIG_LSM_MMAP_MIN_ADDR=65535 +CONFIG_LTC1660=m +# CONFIG_LTC2309 is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2497 is not set +# CONFIG_LTC2632 is not set +CONFIG_LTC2688=m +CONFIG_LTC2983=m +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTO_CLANG_FULL is not set +# CONFIG_LTO_CLANG_THIN is not set +CONFIG_LTO_NONE=y +# CONFIG_LTR390 is not set +CONFIG_LTR501=m +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL_BPF=y +CONFIG_LWTUNNEL=y +CONFIG_LXT_PHY=m +CONFIG_LZ4_COMPRESS=m +# CONFIG_M62332 is not set +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HWSIM=m +CONFIG_MAC80211_KUNIT_TEST=m +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC802154=m +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MAC_EMUMOUSEBTN=y +CONFIG_MACHZ_WDT=m +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_MAC_PARTITION=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAG3110 is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MAILBOX=y +# CONFIG_MANAGER_SBS is not set +CONFIG_MANTIS_CORE=m +# CONFIG_MARCH_Z16 is not set +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88Q2XXX_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MARVELL_PHY=m +# CONFIG_MATOM is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX30100=m +# CONFIG_MAX30102 is not set +CONFIG_MAX30208=m +CONFIG_MAX31827=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_MAX34408=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +# CONFIG_MAX517 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +CONFIG_MAX5522=m +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +CONFIG_MAX77620_WATCHDOG=m +# CONFIG_MAX9611 is not set +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MAXPHYSMEM_128GB=y +# CONFIG_MAXPHYSMEM_2GB is not set +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_MAXSMP=y +CONFIG_MB1232=m +# CONFIG_MC3230 is not set +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCORE2 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3564 is not set +CONFIG_MCP3911=m +CONFIG_MCP4018=m +CONFIG_MCP41010=m +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP4725 is not set +CONFIG_MCP4728=m +CONFIG_MCP4821=m +# CONFIG_MCP4922 is not set +CONFIG_MCP9600=m +CONFIG_MCTP_SERIAL=m +# CONFIG_MCTP_TRANSPORT_I2C is not set +# CONFIG_MCTP_TRANSPORT_I3C is not set +CONFIG_MCTP=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_CLUSTER is not set +CONFIG_MD_FAULTY=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_DEVICE=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_MDIO_MVUSB=m +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_MD_LINEAR=m +CONFIG_MDM_GCC_9607=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID456=m +CONFIG_MD=y +CONFIG_MEAN_AND_VARIANCE_UNIT_TEST=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MEDIA_TEST_SUPPORT=y +# CONFIG_MEDIA_TUNER_MSI001 is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEFFICEON is not set +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_SAS=m +# CONFIG_MELAN is not set +CONFIG_MELLANOX_PLATFORM=y +# CONFIG_MEM_ALLOC_PROFILING is not set +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y +CONFIG_MEMCG=y +CONFIG_MEMCPY_KUNIT_TEST=m +CONFIG_MEMCPY_SLOW_KUNIT_TEST=y +CONFIG_MEMORY_FAILURE=y +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY is not set +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MEMTEST=y +# CONFIG_MEN_A21_WDT is not set +# CONFIG_MERAKI_MX100 is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_AXP20X=y +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m +CONFIG_MFD_CS42L43_I2C=m +CONFIG_MFD_CS42L43_SDW=m +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_ENE_KB3930=m +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_INTEL_M10_BMC=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +# CONFIG_MFD_INTEL_PMC_BXT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX5970=m +CONFIG_MFD_MAX597X=m +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +CONFIG_MFD_MAX77714=m +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SL28CPLD is not set +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SM501=m +# CONFIG_MFD_SMPRO is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +CONFIG_MFD_SY7636A=m +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_SPI is not set +CONFIG_MFD_TPS6594_I2C=m +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +CONFIG_MFD_VX855=m +CONFIG_MFD_WL1273_CORE=m +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MGEODEGX1 is not set +# CONFIG_MGEODE_LX is not set +# CONFIG_MHI_BUS_DEBUG is not set +# CONFIG_MHI_BUS_EP is not set +CONFIG_MHI_BUS=m +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_NET=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_PIT64B is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MICROSOFT_MANA=m +CONFIG_MIGRATION=y +CONFIG_MII=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_SUBPARTITION=y +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_FILESYSTEMS=y +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MKISS=m +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_ACCEL=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_DPLL=m +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_MACSEC=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA_IPSEC is not set +# CONFIG_MLX5_FPGA_TLS is not set +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_INFINIBAND=m +CONFIG_MLX5_IPSEC=y +CONFIG_MLX5_MACSEC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_TLS=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VFIO_PCI=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +# CONFIG_MLX90635 is not set +# CONFIG_MLXBF_BOOTCTL is not set +# CONFIG_MLXBF_GIGE is not set +# CONFIG_MLXBF_TMFIFO is not set +CONFIG_MLXFW=m +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_MLXREG_LC=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLX_WDT=m +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MMC35240 is not set +CONFIG_MMC_ALCOR=m +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_CRYPTO is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +CONFIG_MMC_DW_HI3798MV200=m +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +# CONFIG_MMC_GOLDFISH is not set +CONFIG_MMC_HSQ=m +CONFIG_MMC_LITEX=y +# CONFIG_MMC_MTK is not set +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_ACPI=m +# CONFIG_MMC_SDHCI_AM654 is not set +CONFIG_MMC_SDHCI_CADENCE=m +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_SPI=y +# CONFIG_MMC_STM32_SDMMC is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_WBSD=m +CONFIG_MMC=y +CONFIG_MMIOTRACE=y +CONFIG_MMU=y +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_MODPROBE_PATH="/usr/sbin/modprobe" +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOST is not set +CONFIG_MOTORCOMM_PHY=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +# CONFIG_MOUSE_PS2_SENTELIC is not set +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPL115_I2C=m +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +CONFIG_MPLS_IPTUNNEL=m +CONFIG_MPLS_ROUTING=m +# CONFIG_MPRLS0025PA is not set +CONFIG_MPTCP_IPV6=y +CONFIG_MPTCP_KUNIT_TEST=m +CONFIG_MPTCP=y +CONFIG_MPU3050_I2C=m +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +CONFIG_MSA311=m +# CONFIG_MS_BLOCK is not set +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MSE102X=m +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8953 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_MMCC_8998 is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MT7601U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663S=m +CONFIG_MT7663U=m +CONFIG_MT76x0E=m +CONFIG_MT76x0U=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7915E=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7925E=m +CONFIG_MT7925U=m +CONFIG_MT7996E=m +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_STAA=m +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD=m +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MCHP23K256 is not set +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_MTDRAM=m +# CONFIG_MTD_NAND_ARASAN is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +CONFIG_MTD_NAND_CADENCE=m +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DENALI_DT is not set +# CONFIG_MTD_NAND_DENALI_PCI is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_ECC_MXIC=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_HISI504 is not set +# CONFIG_MTD_NAND_INTEL_LGM is not set +# CONFIG_MTD_NAND_MESON is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_MXIC is not set +CONFIG_MTD_NAND_NANDSIM=m +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_PL35X is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_QCOM is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_ROCKCHIP is not set +# CONFIG_MTD_NAND_SUNXI is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +CONFIG_MTDRAM_ERASE_SIZE=128 +# CONFIG_MTD_RAM is not set +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTD_RAW_NAND=m +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SHARPSL_PARTS is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_FAULT_INJECTION is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_NVMEM=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTK_T7XX=m +CONFIG_MULTIPLEXER=m +CONFIG_MULTIUSER=y +CONFIG_MUX_ADG792A=m +# CONFIG_MUX_ADGS1408 is not set +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# CONFIG_MVIAC7 is not set +CONFIG_MVMDIO=m +CONFIG_MWAVE=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_MYRI10GE_DCA=y +CONFIG_MYRI10GE=m +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +CONFIG_NATSEMI=m +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +CONFIG_NCN26000_PHY=m +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_NCSI_OEM_CMD_KEEP_PHY=y +# CONFIG_NDC_DIS_DYNAMIC_CACHING is not set +CONFIG_NE2K_PCI=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +CONFIG_NET_9P=m +CONFIG_NET_9P_RDMA=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CALXEDA_XGMAC=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS=y +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETCONSOLE=m +CONFIG_NET_CORE=y +CONFIG_NETDEV_ADDR_LIST_TEST=m +CONFIG_NETDEVICES=y +CONFIG_NET_DEVLINK=y +CONFIG_NET_DEV_REFCNT_TRACKER=y +CONFIG_NETDEVSIM=m +CONFIG_NET_DROP_MONITOR=y +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA=m +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set +CONFIG_NET_DSA_MICROCHIP_KSZ9477=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +# CONFIG_NET_DSA_MV88E6060 is not set +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_REALTEK=m +# CONFIG_NET_DSA_REALTEK_MDIO is not set +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +# CONFIG_NET_DSA_REALTEK_SMI is not set +# CONFIG_NET_DSA_SJA1105 is not set +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +# CONFIG_NET_DSA_TAG_AR9331 is not set +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set +CONFIG_NET_DSA_TAG_XRS700X=m +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH=y +CONFIG_NET_FAILOVER=m +CONFIG_NET_FC=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK_ACCT=m +# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +# CONFIG_NETFILTER_XTABLES_COMPAT is not set +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=m +CONFIG_NET_HANDSHAKE_KUNIT_TEST=m +CONFIG_NET_IFE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NETKIT=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NET_MPLS_GSO=m +CONFIG_NET_NCSI=y +CONFIG_NET_NSH=m +CONFIG_NET_NS_REFCNT_TRACKER=y +CONFIG_NET_NS=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NETROM=m +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +# CONFIG_NET_SCH_DEFAULT is not set +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEST=m +CONFIG_NET_TULIP=y +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_ADI=y +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_NET_VENDOR_CAVIUM is not set +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_NET_VENDOR_MICROSEMI is not set +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETERION=y +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +# CONFIG_NET_VENDOR_SYNOPSYS is not set +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_NET_VENDOR_VIA=y +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_NET_VRF=m +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETXEN_NIC=m +CONFIG_NET=y +CONFIG_NEW_LEDS=y +CONFIG_NFC_DIGITAL=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_HCI=m +CONFIG_NFC=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MICROREAD=m +# CONFIG_NFC_MRVL_I2C is not set +CONFIG_NFC_MRVL=m +# CONFIG_NFC_MRVL_SPI is not set +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +# CONFIG_NFC_NCI_UART is not set +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PORT100=m +# CONFIG_NFC_S3FWRN5_I2C is not set +# CONFIG_NFC_S3FWRN82_UART is not set +CONFIG_NFC_SHDLC=y +CONFIG_NFC_SIM=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST21NFCA=m +# CONFIG_NFC_ST95HF is not set +# CONFIG_NFC_ST_NCI_I2C is not set +# CONFIG_NFC_ST_NCI_SPI is not set +CONFIG_NF_CT_NETLINK=m +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NFC_TRF7970A=m +# CONFIG_NFC_VIRTUAL_NCI is not set +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_SNMP_BASIC=m +# CONFIG_NFP_APP_ABM_NIC is not set +CONFIG_NFP_APP_FLOWER=y +CONFIG_NFP_DEBUG=y +CONFIG_NFP=m +CONFIG_NFP_NET_IPSEC=y +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set +CONFIG_NFSD=m +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFSD_V4=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFS_FS=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NFS_SWAP=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V3=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_1=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2=y +CONFIG_NFS_V4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +# CONFIG_NFTL is not set +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_OBJREF=m +# CONFIG_NFT_OSF is not set +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_XFRM=m +CONFIG_NGBE=m +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_NI903X_WDT is not set +CONFIG_NILFS2_FS=m +CONFIG_NINTENDO_FF=y +CONFIG_NITRO_ENCLAVES=m +# CONFIG_NITRO_ENCLAVES_MISC_DEV_TEST is not set +CONFIG_NIU=m +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLMON=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NLS=y +# CONFIG_NMI_CHECK_CPU is not set +# CONFIG_NOA1305 is not set +CONFIG_NODES_SHIFT=2 +CONFIG_NO_HZ_FULL=y +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ=y +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_USB_XCEIV=m +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +CONFIG_NOUVEAU_DEBUG_MMU=y +CONFIG_NOUVEAU_DEBUG_PUSH=y +# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set +CONFIG_NOZOMI=m +CONFIG_NR_CPUS=32 +CONFIG_NS83820=m +CONFIG_NSM=m +CONFIG_NTB_EPF=m +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS_FS is not set +CONFIG_NULL_TTY=m +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +# CONFIG_NVHE_EL2_DEBUG is not set +CONFIG_NVIDIA_SHIELD_FF=y +# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set +CONFIG_NVME_AUTH=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVMEM_LAYOUT_ONIE_TLV=m +CONFIG_NVMEM_LAYOUT_SL28_VPD=m +# CONFIG_NVMEM_QCOM_QFPROM is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_U_BOOT_ENV=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVMEM=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_TCP_TLS=y +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NVRAM is not set +# CONFIG_NVSW_SN2201 is not set +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_CBTX_PHY=m +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m +CONFIG_OCTEON_EP_VF=m +CONFIG_OF_FPGA_REGION=m +CONFIG_OF_GPIO=y +CONFIG_OF_KUNIT_TEST=m +CONFIG_OF_OVERLAY=y +CONFIG_OF_PMEM=m +# CONFIG_OF_UNITTEST is not set +CONFIG_OF=y +# CONFIG_OMFS_FS is not set +# CONFIG_OPAL_CORE is not set +# CONFIG_OPEN_DICE is not set +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPT3001=m +CONFIG_OPT4001=m +CONFIG_OPTPROBES=y +CONFIG_ORANGEFS_FS=m +CONFIG_OSF_PARTITION=y +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERFLOW_KUNIT_TEST=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PA12203001=m +CONFIG_PAC1934=m +CONFIG_PACKET_DIAG=y +CONFIG_PACKET=y +CONFIG_PACKING=y +CONFIG_PAGE_EXTENSION=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SIZE_4KB=y +CONFIG_PAGE_TABLE_CHECK_ENFORCED=y +CONFIG_PAGE_TABLE_CHECK=y +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PANTHERLORD_FF=y +CONFIG_PARAVIRT_TIME_ACCOUNTING=y +CONFIG_PARAVIRT=y +CONFIG_PARMAN=m +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +# CONFIG_PATA_ATIIXP is not set +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CS5520=m +CONFIG_PATA_CS5530=m +CONFIG_PATA_CS5535=m +CONFIG_PATA_CS5536=m +# CONFIG_PATA_CYPRESS is not set +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +# CONFIG_PATA_LEGACY is not set +CONFIG_PATA_MARVELL=m +# CONFIG_PATA_MPIIX is not set +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_NS87415=m +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_OPTI=m +# CONFIG_PATA_PARPORT is not set +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PC104 is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEAER=y +# CONFIG_PCIE_ALTERA is not set +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEASPM=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +CONFIG_PCIE_ECRC=y +CONFIG_PCIE_EDR=y +CONFIG_PCIE_FU740=y +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +CONFIG_PCIE_MICROCHIP_HOST=y +# CONFIG_PCIE_MOBIVEIL is not set +# CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_STARFIVE_HOST is not set +CONFIG_PCIE_XILINX_CPM=y +CONFIG_PCIE_XILINX=y +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_GOOLPC is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_HYPERV=m +CONFIG_PCI_IOV=y +CONFIG_PCI_J721E_HOST=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_MSI=y +CONFIG_PCI_P2PDMA=y +CONFIG_PCI_PASID=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_PCI=y +CONFIG_PCNET32=m +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PCS_XPCS=m +# CONFIG_PDA_POWER is not set +CONFIG_PDC_ADMA=m +CONFIG_PDS_CORE=m +CONFIG_PDS_VDPA=m +CONFIG_PDS_VFIO_PCI=m +# CONFIG_PECI is not set +CONFIG_PERCPU_STATS=y +# CONFIG_PERCPU_TEST is not set +CONFIG_PERF_EVENTS_AMD_UNCORE=y +CONFIG_PERF_EVENTS=y +CONFIG_PERSISTENT_KEYRINGS=y +CONFIG_PER_VMA_LOCK_STATS=y +CONFIG_PFCP=m +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_TORRENT=m +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_HI3670_PCIE is not set +# CONFIG_PHY_HI3670_USB is not set +# CONFIG_PHY_LAN966X_SERDES is not set +CONFIG_PHYLIB=y +CONFIG_PHYLINK=m +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PHY_RTK_RTD_USB2PHY=m +CONFIG_PHY_RTK_RTD_USB3PHY=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHYS_RAM_BASE_FIXED is not set +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +# CONFIG_PHY_STARFIVE_JH7110_DPHY_TX is not set +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_TUSB1210 is not set +# CONFIG_PI433 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CS42L43=m +CONFIG_PINCTRL_CY8C95X0=m +# CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +# CONFIG_PINCTRL_LPASS_LPI is not set +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_MESON=y +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8953 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_MSM is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_QCS404 is not set +CONFIG_PINCTRL_RK805=m +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SC8180X is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM8250 is not set +# CONFIG_PINCTRL_SM8350 is not set +CONFIG_PINCTRL_SM8350_LPASS_LPI=m +# CONFIG_PINCTRL_SM8450 is not set +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TPS6594=m +CONFIG_PINCTRL=y +# CONFIG_PING is not set +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PLATFORM_SI4713 is not set +CONFIG_PLAYSTATION_FF=y +# CONFIG_PLFXLC is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_DMA is not set +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PMBUS=m +CONFIG_PM_DEBUG=y +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_OPREGION is not set +CONFIG_PM_OPP=y +CONFIG_PMS7003=m +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_TRACE_RTC=y +CONFIG_PM_TRACE=y +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PMU_SYSFS is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +CONFIG_PNFS_BLOCK=m +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_TIMERS=y +CONFIG_POWERCAP=y +# CONFIG_POWER_RESET_BRCMKONA is not set +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_LINKSTATION is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_TPS65086=y +# CONFIG_POWER_RESET_VEXPRESS is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_POWER_SUPPLY=y +# CONFIG_PPC_PROT_SAO_LPAR is not set +CONFIG_PPC_QUEUED_SPINLOCKS=y +CONFIG_PPC_RTAS_FILTER=y +CONFIG_PPDEV=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP=m +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +CONFIG_PPS=y +CONFIG_PPTP=m +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRIME_NUMBERS=m +CONFIG_PRINTER=m +# CONFIG_PRINTK_CALLER is not set +CONFIG_PRINTK_INDEX=y +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12 +CONFIG_PRINTK_TIME=y +CONFIG_PRINTK=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_PRISM2_USB is not set +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +# CONFIG_PROCESSOR_SELECT is not set +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +CONFIG_PROVE_CXL_LOCKING=y +CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_NVDIMM_LOCKING is not set +# CONFIG_PROVE_RAW_LOCK_NESTING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +# CONFIG_PSI_DEFAULT_DISABLED is not set +CONFIG_PSI=y +# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_842_COMPRESS=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZ4_COMPRESS=m +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZO_COMPRESS=m +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE=y +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PTDUMP_DEBUGFS=y +CONFIG_PTE_MARKER_UFFD_WP=y +CONFIG_PTP_1588_CLOCK_FC3W=m +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +# CONFIG_PTP_1588_CLOCK_INES is not set +CONFIG_PTP_1588_CLOCK_KVM=m +CONFIG_PTP_1588_CLOCK_MOCK=m +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_PCH=m +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_DFL_TOD=m +# CONFIG_PVPANIC_MMIO is not set +# CONFIG_PVPANIC_PCI is not set +CONFIG_PVPANIC=y +# CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m +CONFIG_PWM_HIBVT=m +# CONFIG_PWM_MICROCHIP_CORE is not set +CONFIG_PWM_OMAP_DMTIMER=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_XILINX is not set +CONFIG_PWM=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_QAT_VFIO_PCI=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m +# CONFIG_QCOM_A7PLL is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GPI_DMA is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_QCOM_LMH is not set +# CONFIG_QCOM_OCMEM is not set +CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +# CONFIG_QCOM_SCM is not set +# CONFIG_QCOM_SPM is not set +# CONFIG_QCS_TURING_404 is not set +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED=m +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLGE=m +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_QRTR=m +CONFIG_QRTR_MHI=m +# CONFIG_QRTR_SMD is not set +# CONFIG_QRTR_TUN is not set +CONFIG_QSEMI_PHY=m +CONFIG_QTNFMAC_PCIE=m +# CONFIG_QUICC_ENGINE is not set +CONFIG_QUOTACTL=y +CONFIG_QUOTA_DEBUG=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA=y +CONFIG_R6040=m +CONFIG_R8169=m +CONFIG_R8712U=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RADIO_WL1273=m +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_RAID_ATTRS=m +CONFIG_RANDOM32_SELFTEST=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_RANDOM_KMALLOC_CACHES=y +CONFIG_RANDOM_TRUST_BOOTLOADER=y +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDSTRUCT_FULL is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_PERFORMANCE is not set +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_CPS_XX=m +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_RAPIDIO_TSI568=m +CONFIG_RAPIDIO_TSI57X=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAS_FMPM=m +CONFIG_RATIONAL_KUNIT_TEST=m +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_RBTREE_TEST is not set +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_CORE=y +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_EXPERT is not set +# CONFIG_RCU_LAZY is not set +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +CONFIG_RCU_NOCB_CPU=y +CONFIG_RCU_REF_SCALE_TEST=m +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +CONFIG_RCU_TRACE=y +CONFIG_RC_XBOX_DVD=m +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +# CONFIG_RDS_DEBUG is not set +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=m +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_REGMAP_BUILD is not set +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_KUNIT=m +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP=y +# CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ANATOP=m +CONFIG_REGULATOR_AW37503=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m +CONFIG_REGULATOR_DA9063=m +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +CONFIG_REGULATOR_MAX20411=m +CONFIG_REGULATOR_MAX5970=m +CONFIG_REGULATOR_MAX597X=m +CONFIG_REGULATOR_MAX77503=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MAX77857=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MCP16502 is not set +CONFIG_REGULATOR_MP5416=m +# CONFIG_REGULATOR_MP8859 is not set +CONFIG_REGULATOR_MP886X=m +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6370=m +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RAA215300=m +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTQ2208=m +CONFIG_REGULATOR_RTQ6752=m +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SUN20I is not set +CONFIG_REGULATOR_SY7636A=m +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +CONFIG_REGULATOR_TPS6286X=m +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_TPS6594=m +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_VCTRL=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR=y +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_PROC_INFO=y +CONFIG_RELAY=y +# CONFIG_RELOCATABLE_TEST is not set +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC_CDEV is not set +CONFIG_REMOTEPROC=y +CONFIG_REMOTE_TARGET=m +# CONFIG_RENESAS_PHY is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_GPIO=m +# CONFIG_RESET_INTEL_GW is not set +CONFIG_RESET_POLARFIRE_SOC=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +# CONFIG_RESET_TI_SYSCON is not set +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESOURCE_KUNIT_TEST=m +# CONFIG_RFD77402 is not set +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y +# CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set +CONFIG_RICHTEK_RTQ6056=m +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RIONET=m +CONFIG_RIONET_RX_SIZE=128 +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_BASE_PMU=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +# CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +# CONFIG_RISCV_MODULE_LINKING_KUNIT is not set +CONFIG_RISCV_PLIC=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_SBI_CPUIDLE=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SBI=y +CONFIG_RISCV_TIMER=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +CONFIG_RMI4_F55=y +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +CONFIG_RMNET=m +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROHM_BM1390 is not set +# CONFIG_ROHM_BU27008 is not set +CONFIG_ROHM_BU27034=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_FS=m +CONFIG_ROSE=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set +CONFIG_RPCSEC_GSS_KRB5_KUNIT_TEST=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG=m +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_TTY=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_RPR0521=m +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RSI_91X=m +CONFIG_RSI_COEX=y +CONFIG_RSI_DEBUGFS=y +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT2500USB=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB_DEBUGFS=y +CONFIG_RT2X00=m +CONFIG_RT61PCI=m +CONFIG_RT73USB=m +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +# CONFIG_RTC_DRV_DS3232_HWMON is not set +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_EFI=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_MAX31335=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PM8XXX is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV3029_HWMON=y +CONFIG_RTC_DRV_RV3032=m +# CONFIG_RTC_DRV_RV8803 is not set +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SA1100 is not set +CONFIG_RTC_DRV_SD3078=m +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_TPS6594=m +CONFIG_RTC_DRV_V3020=m +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_HCTOSYS=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB_KUNIT_TEST=m +CONFIG_RTC_NVMEM=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +# CONFIG_RTL8192CU is not set +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192E=m +CONFIG_RTL8192SE=m +# CONFIG_RTL8192U is not set +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723BS=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTL_CARDS=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTLLIB=m +CONFIG_RTLWIFI_DEBUG=y +CONFIG_RTLWIFI=m +# CONFIG_RTS5208 is not set +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +CONFIG_RTW88_DEBUGFS=y +CONFIG_RTW88_DEBUG=y +CONFIG_RTW88=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922AE=m +CONFIG_RTW89_DEBUGFS=y +CONFIG_RTW89_DEBUGMSG=y +CONFIG_RTW89=m +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +# CONFIG_RUST is not set +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RV_MON_WWNR=y +CONFIG_RV_REACTORS=y +CONFIG_RV_REACT_PANIC=y +CONFIG_RV_REACT_PRINTK=y +CONFIG_RV=y +CONFIG_RXKAD=y +# CONFIG_RXPERF is not set +CONFIG_S2IO=m +# CONFIG_S390_KPROBES_SANITY_TEST is not set +# CONFIG_S390_MODULES_SANITY_TEST is not set +# CONFIG_SAMPLE_FPROBE is not set +# CONFIG_SAMPLES is not set +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_SATA_AHCI=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_HIGHBANK is not set +CONFIG_SATA_INIC162X=m +CONFIG_SATA_MOBILE_LPM_POLICY=3 +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PMP=y +CONFIG_SATA_PROMISE=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_SX4=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +# CONFIG_SATA_ZPODD is not set +# CONFIG_SBC7240_WDT is not set +# CONFIG_SBC8360_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +CONFIG_SBP_TARGET=m +# CONFIG_SC1200_WDT is not set +CONFIG_SC92031=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +# CONFIG_SCD4X is not set +CONFIG_SCF_TORTURE_TEST=m +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_CLUSTER=y +CONFIG_SCHED_CORE=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHED_MC_PRIO is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_SCHED_TRACER=y +CONFIG_SC_LPASS_CORECC_7180=m +# CONFIG_SCR24X is not set +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_ACARD=m +# CONFIG_SCSI_ADVANSYS is not set +CONFIG_SCSI_AIC79XX=m +CONFIG_SCSI_AIC7XXX=m +# CONFIG_SCSI_AIC94XX is not set +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DMX3191D=m +# CONFIG_SCSI_DPT_I2O is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_ESAS2R=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_FLASHPOINT=y +# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set +# CONFIG_SCSI_HISI_SAS is not set +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_HPTIOP=m +# CONFIG_SCSI_IMM is not set +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LIB_KUNIT_TEST=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS=m +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +# CONFIG_SCSI_NSP32 is not set +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_PMCRAID=m +# CONFIG_SCSI_PPA is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_PROTO_TEST=m +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_SNIC=m +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +# CONFIG_SCSI_UFS_FAULT_INJECTION is not set +# CONFIG_SCSI_UFSHCD is not set +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI=y +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +# CONFIG_SD_ADC_MODULATOR is not set +CONFIG_SDIO_UART=m +# CONFIG_SDX_GCC_55 is not set +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECONDARY_TRUSTED_KEYRING=y +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_SECURITY_APPARMOR is not set +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_INFINIBAND=y +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_LOCKDOWN_LSM_EARLY is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +# CONFIG_SECURITY_SELINUX_DISABLE is not set +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +# CONFIG_SENSEAIR_SUNRISE_CO2 is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +# CONFIG_SENSORS_ACBEL_FSG032 is not set +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADP1050=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ASUS_ROG_RYUJIN=m +# CONFIG_SENSORS_ASUS_WMI_EC is not set +# CONFIG_SENSORS_ASUS_WMI is not set +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_CHIPCAP2=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GIGABYTE_WATERFORCE=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_HP_WMI=m +CONFIG_SENSORS_HS3001=m +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +# CONFIG_SENSORS_INSPUR_IPSPS is not set +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LIS3LV02D=m +# CONFIG_SENSORS_LIS3_SPI is not set +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2991=m +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31722=m +# CONFIG_SENSORS_MAX31730 is not set +CONFIG_SENSORS_MAX31760=m +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX6620=m +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MLXREG_FAN=m +# CONFIG_SENSORS_MP2856 is not set +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m +# CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ8785=m +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_KRAKEN3=m +CONFIG_SENSORS_NZXT_SMART2=m +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_POWERZ=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_PT5161L=m +CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_PXE1610 is not set +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +# CONFIG_SENSORS_SBRMI is not set +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SFCTEMP=y +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +# CONFIG_SENSORS_SMM665 is not set +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +CONFIG_SENSORS_SURFACE_FAN=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +# CONFIG_SENSORS_TPS23861 is not set +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_TSL2550=m +# CONFIG_SENSORS_TSL2563 is not set +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_XDP710=m +# CONFIG_SENSORS_XDPE122 is not set +CONFIG_SENSORS_XDPE152=m +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_CS=m +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +# CONFIG_SERIAL_8250_MID is not set +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI1XXXX=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_SERIAL_EARLYCON_RISCV_SBI is not set +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_IMX_EARLYCON is not set +CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_LANTIQ is not set +CONFIG_SERIAL_LITEUART_CONSOLE=y +CONFIG_SERIAL_LITEUART_MAX_PORTS=1 +CONFIG_SERIAL_LITEUART=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +CONFIG_SERIAL_SC16IS7XX_I2C=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=m +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC is not set +CONFIG_SF_PDMA=y +CONFIG_SFP=m +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SGI_PARTITION=y +# CONFIG_SHADOW_CALL_STACK is not set +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# CONFIG_SIEMENS_SIMATIC_IPC is not set +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SIPHASH_KUNIT_TEST=m +CONFIG_SIS190=m +CONFIG_SIS900=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKGE=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP=m +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_SLUB_DEBUG=y +CONFIG_SLUB_KUNIT_TEST=m +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SLUB=y +CONFIG_SMARTJOYPLUS_FF=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMC_DIAG=m +# CONFIG_SMC_LO is not set +CONFIG_SMC=m +# CONFIG_SM_FTL is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_SMS_SDIO_DRV=m +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_SMS_USB_DRV=m +# CONFIG_SM_VIDEOCC_8150 is not set +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_AC97_POWER_SAVE=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALI5451 is not set +CONFIG_SND_ALOOP=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +# CONFIG_SND_AW2 is not set +CONFIG_SND_AZT3328=m +CONFIG_SND_BCD2000=m +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +CONFIG_SND_BEBOB=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_CORE_TEST=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CS5530=m +CONFIG_SND_CS5535AUDIO=m +CONFIG_SND_CTL_DEBUG=y +CONFIG_SND_CTL_FAST_LOOKUP=y +CONFIG_SND_CTL_INPUT_VALIDATION=y +CONFIG_SND_CTL_VALIDATION=y +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_DARLA24=m +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_DEBUG=y +CONFIG_SND_DESIGNWARE_I2S=m +# CONFIG_SND_DESIGNWARE_PCM is not set +CONFIG_SND_DICE=m +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_ECHO3G=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FIREFACE=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_GINA20=m +CONFIG_SND_GINA24=m +CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_PREALLOC_SIZE=2048 +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m +CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m +# CONFIG_SND_HDA_TEGRA is not set +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_HRTIMER=m +# CONFIG_SND_I2S_HI6210_I2S is not set +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +# CONFIG_SND_IMX_SOC is not set +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGO=m +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTEL_BYT_PREFER_SOF is not set +CONFIG_SND_ISIGHT=m +CONFIG_SND_JACK_INJECTION_DEBUG=y +CONFIG_SND_JACK=y +# CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +CONFIG_SND_KORG1212=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_MESON_AIU is not set +# CONFIG_SND_MESON_G12A_TOACODEC is not set +# CONFIG_SND_MESON_G12A_TOHDMITX is not set +# CONFIG_SND_MESON_GX_SOUND_CARD is not set +CONFIG_SND_MIA=m +CONFIG_SND_MIXART=m +CONFIG_SND_MIXER_OSS=m +# CONFIG_SND_MMP_SOC_SSPA is not set +CONFIG_SND_MONA=m +CONFIG_SND_MPU401=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_NM256=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_OXFW=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_PCI=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCMTEST=m +CONFIG_SND_PCM_TIMER=y +CONFIG_SND_PCM_XRUN_DEBUG=y +# CONFIG_SND_PCSP is not set +CONFIG_SND_PCXHR=m +CONFIG_SND_PORTMAN2X4=m +# CONFIG_SND_PPC is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME9652=m +CONFIG_SND_RME96=m +# CONFIG_SND_SAMSUNG_PCM is not set +# CONFIG_SND_SAMSUNG_SPDIF is not set +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SIMPLE_CARD_UTILS=m +# CONFIG_SND_SIS7019 is not set +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AC97_CODEC=m +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_ADI=m +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +CONFIG_SND_SOC_AK5558=m +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP3x is not set +# CONFIG_SND_SOC_AMD_ACP5x is not set +# CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set +# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set +# CONFIG_SND_SOC_AMD_PS is not set +# CONFIG_SND_SOC_AMD_PS_MACH is not set +# CONFIG_SND_SOC_AMD_RENOIR is not set +# CONFIG_SND_SOC_AMD_RENOIR_MACH is not set +# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set +# CONFIG_SND_SOC_AMD_RV_RT5682_MACH is not set +# CONFIG_SND_SOC_AMD_VANGOGH_MACH is not set +# CONFIG_SND_SOC_AMD_YC_MACH is not set +# CONFIG_SND_SOC_APQ8016_SBC is not set +# CONFIG_SND_SOC_ARNDALE is not set +CONFIG_SND_SOC_AUDIO_IIO_AUX=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_AW87390=m +CONFIG_SND_SOC_AW88261=m +CONFIG_SND_SOC_AW88395=m +CONFIG_SND_SOC_AW88399=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CARD_KUNIT_TEST=m +CONFIG_SND_SOC_CHV3_CODEC=m +CONFIG_SND_SOC_CHV3_I2S=m +# CONFIG_SND_SOC_CROS_EC_CODEC is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m +CONFIG_SND_SOC_CS4234=m +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L43=m +CONFIG_SND_SOC_CS42L43_SDW=m +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +CONFIG_SND_SOC_CS42L83=m +# CONFIG_SND_SOC_CS42XX8_I2C is not set +CONFIG_SND_SOC_CS43130=m +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m +# CONFIG_SND_SOC_CS53L30 is not set +CONFIG_SND_SOC_CS_AMP_LIB_TEST=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +# CONFIG_SND_SOC_DAVINCI_MCASP is not set +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +# CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m +# CONFIG_SND_SOC_ES8316 is not set +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_SPI=m +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUD2HTX is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_EASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_MQS is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDAC_HDMI=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_HDMI_CODEC=m +# CONFIG_SND_SOC_ICS43432 is not set +CONFIG_SND_SOC_IDT821034=m +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_IMX_AUDIO_RPMSG is not set +# CONFIG_SND_SOC_IMX_AUDMIX is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_IMX_CARD is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_HDMI is not set +# CONFIG_SND_SOC_IMX_PCM_RPMSG is not set +# CONFIG_SND_SOC_IMX_RPMSG is not set +# CONFIG_SND_SOC_IMX_SGTL5000 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_INTEL_AVS is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT286 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 is not set +# CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH is not set +# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set +# CONFIG_SND_SOC_INTEL_BROADWELL_MACH is not set +# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH is not set +# CONFIG_SND_SOC_INTEL_CATPT is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set +# CONFIG_SND_SOC_INTEL_CML_H is not set +# CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_CML_LP is not set +# CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH is not set +# CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_HASWELL_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set +# CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC is not set +# CONFIG_SND_SOC_INTEL_SKYLAKE is not set +# CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH is not set +# CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_INTEL_SST_TOPLEVEL is not set +# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set +CONFIG_SND_SOC_JH7110_PWMDAC=m +CONFIG_SND_SOC_JH7110_TDM=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MAX98088=m +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98388=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +# CONFIG_SND_SOC_MAX98504 is not set +CONFIG_SND_SOC_MAX98520=m +# CONFIG_SND_SOC_MAX9860 is not set +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +# CONFIG_SND_SOC_MESON_T9015 is not set +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MSM8996 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +CONFIG_SND_SOC_NAU8824=m +# CONFIG_SND_SOC_NAU8825 is not set +# CONFIG_SND_SOC_ODROID is not set +# CONFIG_SND_SOC_OMAP_ABE_TWL6040 is not set +# CONFIG_SND_SOC_OMAP_DMIC is not set +# CONFIG_SND_SOC_OMAP_HDMI is not set +# CONFIG_SND_SOC_OMAP_MCBSP is not set +# CONFIG_SND_SOC_OMAP_MCPDM is not set +# CONFIG_SND_SOC_PCM1681 is not set +CONFIG_SND_SOC_PCM1789_I2C=m +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +CONFIG_SND_SOC_PCM6240=m +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_QDSP6 is not set +# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +# CONFIG_SND_SOC_RK817 is not set +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1017_SDCA_SDW=m +# CONFIG_SND_SOC_RT1308 is not set +# CONFIG_SND_SOC_RT1308_SDW is not set +# CONFIG_SND_SOC_RT1316_SDW is not set +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5660=m +# CONFIG_SND_SOC_RT5663 is not set +# CONFIG_SND_SOC_RT5677 is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +# CONFIG_SND_SOC_RT712_SDCA_SDW is not set +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT722_SDCA_SDW=m +# CONFIG_SND_SOC_RT9120 is not set +CONFIG_SND_SOC_RTQ9128=m +# CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994 is not set +# CONFIG_SND_SOC_SAMSUNG is not set +# CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811 is not set +# CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF is not set +# CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994 is not set +# CONFIG_SND_SOC_SC7180 is not set +# CONFIG_SND_SOC_SDM845 is not set +# CONFIG_SND_SOC_SDW_MOCKUP is not set +# CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +# CONFIG_SND_SOC_SM8250 is not set +CONFIG_SND_SOC_SMA1303=m +# CONFIG_SND_SOC_SMDK_WM8994_PCM is not set +# CONFIG_SND_SOC_SNOW is not set +CONFIG_SND_SOC_SOF_ACPI=m +# CONFIG_SND_SOC_SOF_ALDERLAKE is not set +# CONFIG_SND_SOC_SOF_AMD_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_APOLLOLAKE is not set +# CONFIG_SND_SOC_SOF_BAYTRAIL is not set +# CONFIG_SND_SOC_SOF_BROADWELL is not set +# CONFIG_SND_SOC_SOF_CANNONLAKE is not set +# CONFIG_SND_SOC_SOF_COFFEELAKE is not set +# CONFIG_SND_SOC_SOF_COMETLAKE is not set +# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set +# CONFIG_SND_SOC_SOF_ELKHARTLAKE is not set +# CONFIG_SND_SOC_SOF_GEMINILAKE is not set +# CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SOF_HDA_LINK is not set +CONFIG_SND_SOC_SOF_HDA_PROBES=m +# CONFIG_SND_SOC_SOF_ICELAKE is not set +# CONFIG_SND_SOC_SOF_IMX8M_SUPPORT is not set +# CONFIG_SND_SOC_SOF_IMX8_SUPPORT is not set +# CONFIG_SND_SOC_SOF_IMX_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE is not set +# CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_JASPERLAKE is not set +# CONFIG_SND_SOC_SOF_KABYLAKE is not set +# CONFIG_SND_SOC_SOF_MERRIFIELD is not set +# CONFIG_SND_SOC_SOF_METEORLAKE is not set +# CONFIG_SND_SOC_SOF_MT8195 is not set +# CONFIG_SND_SOC_SOF_OF is not set +CONFIG_SND_SOC_SOF_PCI=m +# CONFIG_SND_SOC_SOF_SKYLAKE is not set +# CONFIG_SND_SOC_SOF_TIGERLAKE is not set +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +CONFIG_SND_SOC_SSM3515=m +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +CONFIG_SND_SOC_STARFIVE=m +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_STM32_DFSDM is not set +# CONFIG_SND_SOC_STM32_I2S is not set +# CONFIG_SND_SOC_STM32_SAI is not set +# CONFIG_SND_SOC_STM32_SPDIFRX is not set +# CONFIG_SND_SOC_STORM is not set +# CONFIG_SND_SOC_TAS2552 is not set +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS2781_I2C=m +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +# CONFIG_SND_SOC_TEGRA186_DSPK is not set +# CONFIG_SND_SOC_TEGRA20_AC97 is not set +# CONFIG_SND_SOC_TEGRA20_DAS is not set +# CONFIG_SND_SOC_TEGRA20_I2S is not set +# CONFIG_SND_SOC_TEGRA20_SPDIF is not set +# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set +# CONFIG_SND_SOC_TEGRA210_AHUB is not set +# CONFIG_SND_SOC_TEGRA210_DMIC is not set +# CONFIG_SND_SOC_TEGRA210_I2S is not set +# CONFIG_SND_SOC_TEGRA30_AHUB is not set +# CONFIG_SND_SOC_TEGRA30_I2S is not set +# CONFIG_SND_SOC_TEGRA_ALC5632 is not set +# CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_SOC_TEGRA is not set +# CONFIG_SND_SOC_TEGRA_MACHINE_DRV is not set +# CONFIG_SND_SOC_TEGRA_MAX98090 is not set +# CONFIG_SND_SOC_TEGRA_RT5640 is not set +# CONFIG_SND_SOC_TEGRA_RT5677 is not set +# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set +# CONFIG_SND_SOC_TEGRA_TRIMSLICE is not set +# CONFIG_SND_SOC_TEGRA_WM8753 is not set +# CONFIG_SND_SOC_TEGRA_WM8903 is not set +# CONFIG_SND_SOC_TEGRA_WM9712 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320ADCX140=m +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23 is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TOPOLOGY_BUILD is not set +CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +CONFIG_SND_SOC_TSCS42XX=m +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +CONFIG_SND_SOC_UTILS_KUNIT_TEST=m +# CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m +# CONFIG_SND_SOC_WCD938X_SDW is not set +CONFIG_SND_SOC_WCD939X_SDW=m +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +CONFIG_SND_SOC_WM8524=m +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_SPI=m +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804=m +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +CONFIG_SND_SOC_WM8940=m +# CONFIG_SND_SOC_WM8960 is not set +CONFIG_SND_SOC_WM8961=m +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_WSA881X is not set +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_WSA884X=m +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SONICVIBES=m +# CONFIG_SND_SPI is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_CODEC_ANALOG is not set +# CONFIG_SND_SUN8I_CODEC_ANALOG is not set +# CONFIG_SND_SUN8I_CODEC is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TRIDENT=m +CONFIG_SND_UMP_LEGACY_RAWMIDI=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_US122L=m +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_USB=y +CONFIG_SND_VERBOSE_PRINTK=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +CONFIG_SND_VIRMIDI=m +CONFIG_SND_VIRTIO=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +# CONFIG_SND_X86 is not set +# CONFIG_SND_XEN_FRONTEND is not set +CONFIG_SND_YMFPCI=m +CONFIG_SNET_VDPA=m +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SONYPI is not set +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +# CONFIG_SOUNDWIRE_AMD is not set +# CONFIG_SOUNDWIRE_CADENCE is not set +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m +# CONFIG_SOUNDWIRE_INTEL is not set +# CONFIG_SOUNDWIRE is not set +# CONFIG_SOUNDWIRE_QCOM is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +# CONFIG_SPEAKUP_SYNTH_DECEXT is not set +CONFIG_SPEAKUP_SYNTH_DECTLK=m +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_AMD=y +CONFIG_SPI_AX88796C_COMPRESSION=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +CONFIG_SPI_CADENCE_QUADSPI=m +# CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m +# CONFIG_SPI_CS42L43 is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_DLN2=m +CONFIG_SPI_FSL_LPSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_HISI_KUNPENG is not set +# CONFIG_SPI_HISI_SFC_V3XX is not set +# CONFIG_SPI_LANTIQ_SSC is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_MUX=m +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_PCI1XXXX=m +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI=y +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SPMI is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SRAM is not set +# CONFIG_SRF04 is not set +# CONFIG_SRF08 is not set +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB=m +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_SDIOHOST=y +# CONFIG_SSFDC is not set +CONFIG_SSIF_IPMI_BMC=m +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACK_HASH_ORDER=20 +CONFIG_STACKINIT_KUNIT_TEST=m +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKPROTECTOR=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACK_TRACER=y +CONFIG_STACK_VALIDATION=y +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +CONFIG_STAGING_MEDIA=y +CONFIG_STAGING=y +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_CALL_SELFTEST is not set +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +CONFIG_STEAM_FF=y +CONFIG_STK3310=m +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# CONFIG_STM_DUMMY is not set +CONFIG_STM=m +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_PCI is not set +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +# CONFIG_STM_PROTO_BASIC is not set +# CONFIG_STM_PROTO_SYS_T is not set +# CONFIG_STM_SOURCE_CONSOLE is not set +# CONFIG_STM_SOURCE_FTRACE is not set +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STRCAT_KUNIT_TEST=m +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRING_HELPERS_KUNIT_TEST=m +CONFIG_STRING_KUNIT_TEST=m +# CONFIG_STRING_SELFTEST is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_STRSCPY_KUNIT_TEST=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_SPI=m +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_SUNGEM=m +CONFIG_SUN_PARTITION=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC=m +CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SURFACE_3_POWER_OPREGION is not set +CONFIG_SURFACE_ACPI_NOTIFY=m +CONFIG_SURFACE_AGGREGATOR_BUS=y +CONFIG_SURFACE_AGGREGATOR_CDEV=m +# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set +CONFIG_SURFACE_AGGREGATOR_HUB=m +CONFIG_SURFACE_AGGREGATOR=m +CONFIG_SURFACE_AGGREGATOR_REGISTRY=m +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m +CONFIG_SURFACE_DTX=m +CONFIG_SURFACE_GPE=m +CONFIG_SURFACE_HID=m +CONFIG_SURFACE_HOTPLUG=m +CONFIG_SURFACE_KBD=m +CONFIG_SURFACE_PLATFORM_PROFILE=m +CONFIG_SURFACE_PLATFORMS=y +CONFIG_SURFACE_PRO3_BUTTON=m +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SUSPEND=y +CONFIG_SWAP=y +# CONFIG_SWIOTLB_DYNAMIC is not set +# CONFIG_SW_SYNC is not set +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +# CONFIG_SX9500 is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNCLINK_GT=m +CONFIG_SYN_COOKIES=y +CONFIG_SYNTH_EVENT_GEN_TEST=m +CONFIG_SYNTH_EVENTS=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_SYSCTL_KUNIT_TEST=m +CONFIG_SYSCTL=y +CONFIG_SYSFB_SIMPLEFB=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEM76_ACPI is not set +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 +CONFIG_SYSTEM_EXTRA_CERTIFICATE=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_REVOCATION_LIST is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSV_FS=m +CONFIG_SYSVIPC=y +# CONFIG_T5403 is not set +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TARGET_CORE=m +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASKS_RCU=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_NSC=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_SPI=m +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TPM2_HMAC=y +CONFIG_TCG_TPM=y +CONFIG_TCG_VTPM_PROXY=m +# CONFIG_TCG_XEN is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_TCM_QLA2XXX=m +CONFIG_TCM_USER2=m +CONFIG_TCP_AO=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +CONFIG_TDX_GUEST_DRIVER=m +CONFIG_TEE=m +CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m +CONFIG_TELCLOCK=m +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +CONFIG_TEST_BPF=m +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +CONFIG_TEST_CPUMASK=m +# CONFIG_TEST_DHRY is not set +# CONFIG_TEST_DIV64 is not set +CONFIG_TEST_DYNAMIC_DEBUG=m +# CONFIG_TEST_FIRMWARE is not set +CONFIG_TEST_FPU=m +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_HEXDUMP is not set +CONFIG_TEST_HMM=m +# CONFIG_TEST_IDA is not set +CONFIG_TEST_IOV_ITER=m +# CONFIG_TEST_KMOD is not set +CONFIG_TEST_KSTRTOX=y +CONFIG_TEST_LIST_SORT=m +# CONFIG_TEST_LKM is not set +CONFIG_TEST_LOCKUP=m +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +CONFIG_TEST_MIN_HEAP=m +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_OBJPOOL is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_SIPHASH is not set +CONFIG_TEST_SORT=m +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_STATIC_KEYS is not set +CONFIG_TEST_STRING_HELPERS=m +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UBSAN is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_UUID is not set +CONFIG_TEST_VMALLOC=m +# CONFIG_TEST_XARRAY is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +CONFIG_THERMAL_NETLINK=y +# CONFIG_THERMAL_OF is not set +CONFIG_THERMAL_STATISTICS=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL=y +CONFIG_THREAD_SIZE_ORDER=3 +CONFIG_THRUSTMASTER_FF=y +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set +CONFIG_TI_ADC128S052=m +# CONFIG_TI_ADC161S626 is not set +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS1298 is not set +CONFIG_TI_ADS131E08=m +CONFIG_TI_ADS7924=m +# CONFIG_TI_ADS7950 is not set +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +CONFIG_TI_DAC7311=m +# CONFIG_TI_DAC7612 is not set +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIGON3=m +CONFIG_TI_LMP92064=m +CONFIG_TIME_KUNIT_TEST=m +CONFIG_TIME_NS=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +# CONFIG_TINYDRM_HX8357D is not set +CONFIG_TINYDRM_ILI9163=m +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +CONFIG_TINYDRM_ILI9486=m +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_ST is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TMAG5273 is not set +CONFIG_TI_TSC2046=m +CONFIG_TLAN=m +CONFIG_TLS_DEVICE=y +CONFIG_TLS=m +# CONFIG_TLS_TOE is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +CONFIG_TMP117=m +CONFIG_TMPFS_INODE64=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_QUOTA=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS=y +CONFIG_TORTURE_TEST=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +CONFIG_TOUCHSCREEN_CYTTSP5=m +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DMI is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +CONFIG_TOUCHSCREEN_ELAN=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_IQS7211=m +# CONFIG_TOUCHSCREEN_MAX11801 is not set +CONFIG_TOUCHSCREEN_MCS5000=m +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MSG2638=m +# CONFIG_TOUCHSCREEN_MTOUCH is not set +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_RM_TS=m +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_TOUCHSCREEN_TS4800=m +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_WACOM_I2C=m +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ZINITIX=m +# CONFIG_TPL0102 is not set +CONFIG_TPM_KEY_PARSER=m +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TPS6594_ESM=m +CONFIG_TPS6594_PFSM=m +# CONFIG_TPS68470_PMIC_OPREGION is not set +CONFIG_TRACE_EVAL_MAP_FILE=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_MMIO_ACCESS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS_TEE=y +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TRUSTED_KEYS=y +# CONFIG_TS4800_IRQ is not set +# CONFIG_TS4800_WATCHDOG is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_TTY=y +CONFIG_TULIP=m +CONFIG_TULIP_MMIO=y +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_TUNE_GENERIC=y +CONFIG_TUN=m +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_IT5205=m +CONFIG_TYPEC_MUX_NB7VPQ904M=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_PTN36502=m +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# CONFIG_TYPEC_QCOM_PMIC is not set +# CONFIG_TYPEC_RT1711H is not set +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPHOON=m +CONFIG_UACCE=m +CONFIG_UAPI_HEADER_TEST=y +CONFIG_UBIFS_ATIME_SUPPORT=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_XATTR=y +# CONFIG_UBSAN_ALIGNMENT is not set +# CONFIG_UBSAN_BOOL is not set +CONFIG_UBSAN_BOUNDS=y +# CONFIG_UBSAN_DIV_ZERO is not set +# CONFIG_UBSAN_ENUM is not set +CONFIG_UBSAN_SANITIZE_ALL=y +CONFIG_UBSAN_SHIFT=y +# CONFIG_UBSAN_SIGNED_WRAP is not set +# CONFIG_UBSAN_TRAP is not set +# CONFIG_UBSAN_UNREACHABLE is not set +CONFIG_UBSAN=y +CONFIG_UCLAMP_BUCKETS_COUNT=5 +CONFIG_UCLAMP_TASK_GROUP=y +CONFIG_UCLAMP_TASK=y +CONFIG_UCSI_ACPI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UDF_FS=m +CONFIG_UDMABUF=y +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +CONFIG_UHID=m +CONFIG_UID16=y +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_CIF is not set +CONFIG_UIO_DFL=m +# CONFIG_UIO_DMEM_GENIRQ is not set +CONFIG_UIO_HV_GENERIC=m +CONFIG_UIO=m +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_SERCOS3 is not set +CONFIG_ULI526X=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_UNICODE_UTF8_DATA=y +CONFIG_UNICODE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX_DIAG=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX=y +CONFIG_UNUSED_KSYMS_WHITELIST="" +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UPROBE_EVENTS=y +# CONFIG_US5182D is not set +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +# CONFIG_USB4_KUNIT_TEST is not set +CONFIG_USB4_NET=m +CONFIG_USB4=y +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARMLINUX=y +CONFIG_USB_ATM=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_BDC_UDC is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_USB_CDNS2_UDC=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_PCI_WRAP=m +CONFIG_USB_CDNS3_STARFIVE=m +# CONFIG_USB_CDNSP_GADGET is not set +# CONFIG_USB_CDNSP_HOST is not set +CONFIG_USB_CDNSP_PCI=m +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_IMX=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_NPCM=m +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_EEM=y +# CONFIG_USB_CONFIGFS_F_FS is not set +CONFIG_USB_CONFIGFS_F_HID=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +CONFIG_USB_CONFIGFS_F_MIDI2=y +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +CONFIG_USB_CONFIGFS_F_TCM=y +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +# CONFIG_USB_CONFIGFS_F_UVC is not set +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_OBEX=y +# CONFIG_USB_CONFIGFS_RNDIS is not set +CONFIG_USB_CONFIGFS_SERIAL=y +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_CXACRU=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DSBR=m +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2_DEBUG is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_HOST is not set +CONFIG_USB_DWC2=m +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_HAPS is not set +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +# CONFIG_USB_ETH is not set +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_GADGET=m +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_GADGET_TARGET is not set +CONFIG_USB_GADGET_VBUS_DRAW=100 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +CONFIG_USB_GL860=m +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GOKU is not set +CONFIG_USB_GPIO_VBUS=m +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_GR_UDC is not set +CONFIG_USB_G_SERIAL=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HIDDEV=y +CONFIG_USB_HID=y +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_HSO=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USBIP_CORE=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USB_IPHETH=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_VUDC=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_ISP1760_DUAL_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_HOST_ROLE is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +CONFIG_USB_KEENE=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +CONFIG_USB_M5602=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_MA901=m +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_MON=y +CONFIG_USB_MR800=m +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +CONFIG_USB_NET_AQC111=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ONBOARD_DEV=m +CONFIG_USB_ONBOARD_HUB=m +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +# CONFIG_USB_OTG_PRODUCTLIST is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI_AMD=y +CONFIG_USB_PCI=y +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_PHY=y +CONFIG_USB_PRINTER=m +CONFIG_USB_PULSE8_CEC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_PWC=m +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_RAINSHADOW_CEC=m +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_RAW_GADGET=m +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_USB_S2255=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL=y +CONFIG_USB_SEVSEG=m +CONFIG_USB_SI470X=m +# CONFIG_USB_SI4713 is not set +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_CS is not set +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SNP_UDC_PLAT=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STV06XX=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_UAS=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +CONFIG_USB_XEN_HCD=m +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_HISTB is not set +CONFIG_USB_XHCI_PCI_RENESAS=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XUSBATM=m +CONFIG_USB=y +CONFIG_USB_YUREX=m +# CONFIG_USB_ZERO is not set +CONFIG_USB_ZR364XX=m +# CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USERFAULTFD=y +CONFIG_U_SERIAL_CONSOLE=y +# CONFIG_USERIO is not set +CONFIG_USER_NS=y +CONFIG_UTS_NS=y +# CONFIG_UV_SYSFS is not set +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_VCAP=y +CONFIG_VCHIQ_CDEV=y +CONFIG_VCNL3020=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_USER=m +CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VEML6075 is not set +CONFIG_VETH=m +# CONFIG_VF610_ADC is not set +# CONFIG_VF610_DAC is not set +CONFIG_VFAT_FS=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +# CONFIG_VFIO_DEVICE_CDEV is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO=m +CONFIG_VFIO_MDEV=m +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI=m +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_ARB=y +CONFIG_VGA_CONSOLE=y +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VDPA=m +CONFIG_VHOST_VSOCK=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_VIDEO_AD5820=m +# CONFIG_VIDEO_AD9389B is not set +CONFIG_VIDEO_ADP1653=m +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604_CEC is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842_CEC is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_AK7375=m +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_AU0828=m +# CONFIG_VIDEO_AU0828_RC is not set +CONFIG_VIDEO_AU0828_V4L2=y +# CONFIG_VIDEO_BT819 is not set +CONFIG_VIDEO_BT848=m +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +CONFIG_VIDEO_CADENCE_CSI2TX=m +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_VIDEO_CAMERA_SENSOR=y +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX23885=m +# CONFIG_VIDEO_CX25821 is not set +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_DS90UB913=m +CONFIG_VIDEO_DS90UB953=m +CONFIG_VIDEO_DS90UB960=m +# CONFIG_VIDEO_DT3155 is not set +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9719=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_RC=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_FB_IVTV=m +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GS1662=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +# CONFIG_VIDEO_I2C is not set +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +# CONFIG_VIDEO_IPU3_CIO2 is not set +CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_IVTV_ALSA is not set +CONFIG_VIDEO_IVTV=m +# CONFIG_VIDEO_KS0127 is not set +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_M52790=m +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_MGB4 is not set +# CONFIG_VIDEO_ML86V7667 is not set +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_MT9M001=m +# CONFIG_VIDEO_MT9M111 is not set +CONFIG_VIDEO_MT9M114=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV01A10=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_PVRUSB2_DVB=y +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m +CONFIG_VIDEO_RDACM20=m +# CONFIG_VIDEO_RDACM21 is not set +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K4ECGX=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_SAA6588=m +# CONFIG_VIDEO_SAA7110 is not set +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_SAA7164=m +CONFIG_VIDEO_SAA717X=m +# CONFIG_VIDEO_SAA7185 is not set +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_STKWEBCAM is not set +CONFIG_VIDEO_STM32_DMA2D=m +# CONFIG_VIDEO_ST_MIPID02 is not set +CONFIG_VIDEO_ST_VGXY61=m +CONFIG_VIDEO_TC358743_CEC=y +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +# CONFIG_VIDEO_TEGRA_TPG is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_TVAUDIO=m +# CONFIG_VIDEO_TVP514X is not set +CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set +CONFIG_VIDEO_TW2804=m +# CONFIG_VIDEO_TW5864 is not set +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_TW68 is not set +# CONFIG_VIDEO_TW9900 is not set +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +# CONFIG_VIDEO_TW9910 is not set +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VISL=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VP27SMPX=m +# CONFIG_VIDEO_VPX3220 is not set +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_XILINX is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_BLK=m +CONFIG_VIRTIO_CONSOLE=m +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_FS=m +# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set +CONFIG_VIRTIO_INPUT=m +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_NET=m +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI=y +# CONFIG_VIRTIO_PMEM is not set +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_VFIO_PCI=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO=y +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_WIFI=m +# CONFIG_VISL_DEBUGFS is not set +CONFIG_VITESSE_PHY=m +CONFIG_VL53L0X_I2C=m +CONFIG_VL6180=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_STACK=y +# CONFIG_VME_BUS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_3G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMXNET3 is not set +CONFIG_VORTEX=m +CONFIG_VP_VDPA=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKMON=m +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VT=y +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set +CONFIG_VXGE=m +CONFIG_VXLAN=m +# CONFIG_VZ89X is not set +CONFIG_W1_CON=y +CONFIG_W1=m +# CONFIG_W1_MASTER_AMD_AXI is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS2490=m +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_MASTER_SGI is not set +CONFIG_W1_MASTER_UART=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +# CONFIG_W1_SLAVE_DS250X is not set +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS28E04=m +# CONFIG_W1_SLAVE_DS28E17 is not set +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W83627HF_WDT=m +CONFIG_W83877F_WDT=m +CONFIG_W83977F_WDT=m +# CONFIG_WAFER_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_WATCH_QUEUE=y +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WCN36XX=m +CONFIG_WDAT_WDT=m +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +# CONFIG_WFX is not set +CONFIG_WIL6210_DEBUGFS=y +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210=m +# CONFIG_WIL6210_TRACING is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WILINK_PLATFORM_DATA=y +CONFIG_WINBOND_840=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIREGUARD=m +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_HOTKEY=m +CONFIG_WIRELESS=y +CONFIG_WIZNET_BUS_ANY=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_WIZNET_W5300=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL1251_SPI=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_WLAN_VENDOR_CISCO is not set +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_WLAN_VENDOR_INTERSIL is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WLAN_VENDOR_PURELIFI is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_WLAN_VENDOR_SILABS is not set +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN=y +CONFIG_WLCORE=m +CONFIG_WLCORE_SDIO=m +CONFIG_WLCORE_SPI=m +CONFIG_WPCM450_SOC=m +CONFIG_WQ_CPU_INTENSIVE_REPORT=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_WQ_WATCHDOG=y +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_WWAN=y +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X9250=m +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XDP_SOCKETS=y +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT=512 +CONFIG_XEN_PRIVCMD_EVENTFD=y +CONFIG_XEN_PRIVCMD_IRQFD=y +CONFIG_XEN_PRIVCMD=m +# CONFIG_XEN_PVCALLS_FRONTEND is not set +CONFIG_XEN_PVHVM_GUEST=y +CONFIG_XEN_UNPOPULATED_ALLOC=y +# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set +CONFIG_XEN_VIRTIO=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +# CONFIG_XFRM_USER_COMPAT is not set +CONFIG_XFRM_USER=y +CONFIG_XFRM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_ONLINE_REPAIR is not set +# CONFIG_XFS_ONLINE_SCRUB_STATS is not set +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +CONFIG_XFS_SUPPORT_ASCII_CI=y +CONFIG_XFS_SUPPORT_V4=y +CONFIG_XFS_WARN=y +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_DMA is not set +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_GMII2RGMII=m +# CONFIG_XILINX_INTC is not set +CONFIG_XILINX_LL_TEMAC=m +CONFIG_XILINX_PR_DECOUPLER=m +# CONFIG_XILINX_SDFEC is not set +CONFIG_XILINX_VCU=m +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XADC is not set +CONFIG_XILINX_XDMA=m +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +CONFIG_XILLYBUS=m +# CONFIG_XILLYBUS_OF is not set +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +# CONFIG_XIP_KERNEL is not set +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC=y +# CONFIG_YAMAHA_YAS530 is not set +CONFIG_YAM=m +CONFIG_YELLOWFIN=m +# CONFIG_YENTA is not set +# CONFIG_YOGABOOK_WMI is not set +CONFIG_Z3FOLD=y +CONFIG_ZBUD=y +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_ZD1211RW=m +# CONFIG_ZERO_CALL_USED_REGS is not set +CONFIG_ZEROPLUS_FF=y +# CONFIG_ZIIRAVE_WATCHDOG is not set +CONFIG_ZISOFS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_DFLTCC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA=y +CONFIG_ZONEFS_FS=m +CONFIG_ZOPT2201=m +# CONFIG_ZPA2326 is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +CONFIG_ZRAM=m +CONFIG_ZRAM_MEMORY_TRACKING=y +CONFIG_ZRAM_MULTI_COMP=y +CONFIG_ZRAM_TRACK_ENTRY_ACTIME=y +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON=y +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_I2C_NCT6775=m +CONFIG_ZENIFY=y +CONFIG_NTSYNC=y +CONFIG_TCP_CONG_BBR2=m +CONFIG_SND_SOC_AW87XXX=m +CONFIG_SCHED_BORE=y +CONFIG_MIN_BASE_SLICE_NS=1000000 +CONFIG_SCHED_CLASS_EXT=y +CONFIG_HID_IPTS=m +CONFIG_HID_ITHC=m +CONFIG_SURFACE_BOOK1_DGPU_SWITCH=m +CONFIG_IPC_CLASSES=y +CONFIG_LEDS_TPS68470=m +CONFIG_SENSORS_SURFACE_TEMP=m +CONFIG_AMD_PRIVATE_COLOR=y +CONFIG_DRM_APPLETBDRM=m +CONFIG_HID_APPLETB_BL=m +CONFIG_HID_APPLETB_KBD=m +CONFIG_HID_APPLE_MAGIC_BACKLIGHT=m +CONFIG_APPLE_BCE=m +CONFIG_HID_ASUS_ALLY=m +CONFIG_ASUS_ARMOURY=m diff --git a/SOURCES/kernel-riscv64-fedora.config b/SOURCES/kernel-riscv64-fedora.config new file mode 100644 index 0000000..8237444 --- /dev/null +++ b/SOURCES/kernel-riscv64-fedora.config @@ -0,0 +1,8576 @@ +# riscv +# CONFIG_60XX_WDT is not set +CONFIG_6LOWPAN_DEBUGFS=y +CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m +CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m +CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m +CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m +CONFIG_6LOWPAN_GHC_ICMPV6=m +CONFIG_6LOWPAN_GHC_UDP=m +CONFIG_6LOWPAN=m +CONFIG_6LOWPAN_NHC_DEST=m +CONFIG_6LOWPAN_NHC_FRAGMENT=m +CONFIG_6LOWPAN_NHC_HOP=m +CONFIG_6LOWPAN_NHC_IPV6=m +CONFIG_6LOWPAN_NHC=m +CONFIG_6LOWPAN_NHC_MOBILITY=m +CONFIG_6LOWPAN_NHC_ROUTING=m +CONFIG_6LOWPAN_NHC_UDP=m +CONFIG_6PACK=m +CONFIG_8139CP=m +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_8139TOO_8129=y +CONFIG_8139TOO=m +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +CONFIG_9P_FSCACHE=y +CONFIG_9P_FS=m +CONFIG_9P_FS_POSIX_ACL=y +CONFIG_9P_FS_SECURITY=y +CONFIG_A11Y_BRAILLE_CONSOLE=y +CONFIG_ABP060MG=m +CONFIG_ACCESSIBILITY=y +CONFIG_ACENIC=m +# CONFIG_ACENIC_OMIT_TIGON_I is not set +# CONFIG_ACORN_PARTITION is not set +CONFIG_ACPI_AC=y +CONFIG_ACPI_ALS=m +CONFIG_ACPI_APEI_EINJ_CXL=y +CONFIG_ACPI_APEI_EINJ=m +# CONFIG_ACPI_APEI_ERST_DEBUG is not set +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BGRT=y +CONFIG_ACPI_BUTTON=y +# CONFIG_ACPI_CMPC is not set +# CONFIG_ACPI_CONFIGFS is not set +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_CPPC_CPUFREQ_FIE=y +CONFIG_ACPI_CPPC_CPUFREQ=m +# CONFIG_ACPI_CUSTOM_METHOD is not set +# CONFIG_ACPI_DEBUGGER is not set +# CONFIG_ACPI_DEBUGGER_USER is not set +# CONFIG_ACPI_DEBUG is not set +# CONFIG_ACPI_DOCK is not set +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_FAN=y +CONFIG_ACPI_FFH=y +# CONFIG_ACPI_FPDT is not set +CONFIG_ACPI_HED=y +CONFIG_ACPI_HMAT=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_ACPI_IPMI=m +CONFIG_ACPI_NFIT=m +CONFIG_ACPI_NUMA=y +CONFIG_ACPI_PCC=y +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_PFRUT=m +CONFIG_ACPI_PLATFORM_PROFILE=m +CONFIG_ACPI_PRMT=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TAD=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI=y +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set +# CONFIG_AD2S90 is not set +CONFIG_AD3552R=m +CONFIG_AD4130=m +# CONFIG_AD5064 is not set +CONFIG_AD5110=m +# CONFIG_AD525X_DPOT is not set +CONFIG_AD5272=m +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5592R is not set +# CONFIG_AD5593R is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5686_SPI is not set +# CONFIG_AD5696_I2C is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5758 is not set +# CONFIG_AD5761 is not set +# CONFIG_AD5764 is not set +CONFIG_AD5766=m +CONFIG_AD5770R=m +# CONFIG_AD5791 is not set +# CONFIG_AD5933 is not set +# CONFIG_AD7091R5 is not set +CONFIG_AD7091R8=m +CONFIG_AD7124=m +# CONFIG_AD7150 is not set +# CONFIG_AD7173 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7266 is not set +# CONFIG_AD7280 is not set +# CONFIG_AD7291 is not set +CONFIG_AD7292=m +CONFIG_AD7293=m +# CONFIG_AD7298 is not set +# CONFIG_AD7303 is not set +CONFIG_AD7380=m +CONFIG_AD74115=m +CONFIG_AD74413R=m +# CONFIG_AD7476 is not set +# CONFIG_AD7606_IFACE_PARALLEL is not set +# CONFIG_AD7606_IFACE_SPI is not set +# CONFIG_AD7746 is not set +CONFIG_AD7766=m +# CONFIG_AD7768_1 is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7887 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7944 is not set +CONFIG_AD7949=m +# CONFIG_AD799X is not set +# CONFIG_AD8366 is not set +# CONFIG_AD8801 is not set +CONFIG_AD9467=m +# CONFIG_AD9523 is not set +# CONFIG_AD9739A is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_ADA4250 is not set +CONFIG_ADAPTEC_STARFIRE=m +# CONFIG_ADDRESS_MASKING is not set +# CONFIG_ADE7854 is not set +# CONFIG_ADF4350 is not set +# CONFIG_ADF4371 is not set +CONFIG_ADF4377=m +# CONFIG_ADFS_FS is not set +# CONFIG_ADI_AXI_ADC is not set +# CONFIG_ADI_AXI_DAC is not set +# CONFIG_ADIN1100_PHY is not set +CONFIG_ADIN1110=m +CONFIG_ADIN_PHY=m +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_ADIS16260 is not set +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16460 is not set +CONFIG_ADIS16475=m +# CONFIG_ADIS16480 is not set +# CONFIG_ADJD_S311 is not set +# CONFIG_ADMFM2000 is not set +# CONFIG_ADMV1013 is not set +# CONFIG_ADMV1014 is not set +# CONFIG_ADMV4420 is not set +# CONFIG_ADMV8818 is not set +# CONFIG_ADRF6780 is not set +# CONFIG_ADT7316 is not set +CONFIG_ADUX1020=m +# CONFIG_ADVANTECH_WDT is not set +CONFIG_ADVISE_SYSCALLS=y +# CONFIG_ADV_SWBUTTON is not set +CONFIG_ADXL313_I2C=m +CONFIG_ADXL313_SPI=m +# CONFIG_ADXL345_I2C is not set +# CONFIG_ADXL345_SPI is not set +CONFIG_ADXL355_I2C=m +CONFIG_ADXL355_SPI=m +CONFIG_ADXL367_I2C=m +CONFIG_ADXL367_SPI=m +CONFIG_ADXL372_I2C=m +CONFIG_ADXL372_SPI=m +CONFIG_ADXRS290=m +# CONFIG_ADXRS450 is not set +CONFIG_AF8133J=m +# CONFIG_AFE4403 is not set +# CONFIG_AFE4404 is not set +CONFIG_AFFS_FS=m +CONFIG_AF_KCM=m +CONFIG_AF_RXRPC_DEBUG=y +# CONFIG_AF_RXRPC_INJECT_LOSS is not set +# CONFIG_AF_RXRPC_INJECT_RX_DELAY is not set +CONFIG_AF_RXRPC_IPV6=y +CONFIG_AF_RXRPC=m +# CONFIG_AFS_DEBUG_CURSOR is not set +CONFIG_AFS_DEBUG=y +CONFIG_AFS_FSCACHE=y +CONFIG_AFS_FS=m +# CONFIG_AHCI_CEVA is not set +CONFIG_AHCI_DWC=m +# CONFIG_AHCI_QORIQ is not set +CONFIG_AIC79XX_CMDS_PER_DEVICE=4 +# CONFIG_AIC79XX_DEBUG_ENABLE is not set +CONFIG_AIC79XX_DEBUG_MASK=0 +# CONFIG_AIC79XX_REG_PRETTY_PRINT is not set +CONFIG_AIC79XX_RESET_DELAY_MS=15000 +CONFIG_AIC7XXX_CMDS_PER_DEVICE=4 +# CONFIG_AIC7XXX_DEBUG_ENABLE is not set +CONFIG_AIC7XXX_DEBUG_MASK=0 +# CONFIG_AIC7XXX_REG_PRETTY_PRINT is not set +CONFIG_AIC7XXX_RESET_DELAY_MS=15000 +CONFIG_AIO=y +CONFIG_AIR_EN8811H_PHY=m +CONFIG_AIX_PARTITION=y +# CONFIG_AK09911 is not set +# CONFIG_AK8974 is not set +# CONFIG_AK8975 is not set +CONFIG_AL3010=m +# CONFIG_AL3320A is not set +# CONFIG_AL_FIC is not set +# CONFIG_ALIBABA_ENI_VDPA is not set +CONFIG_ALIM1535_WDT=m +CONFIG_ALIM7101_WDT=m +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_ALTERA_FREEZE_BRIDGE is not set +# CONFIG_ALTERA_MBOX is not set +CONFIG_ALTERA_MSGDMA=m +CONFIG_ALTERA_PR_IP_CORE=m +CONFIG_ALTERA_PR_IP_CORE_PLAT=m +CONFIG_ALTERA_STAPL=m +CONFIG_ALTERA_TSE=m +CONFIG_ALX=m +# CONFIG_AM2315 is not set +# CONFIG_AMBA_PL08X is not set +CONFIG_AMD8111_ETH=m +CONFIG_AMD_ATL=m +# CONFIG_AMD_IOMMU_DEBUGFS is not set +CONFIG_AMD_PHY=m +CONFIG_AMD_PMC=m +# CONFIG_AMD_PTDMA is not set +# CONFIG_AMDTEE is not set +# CONFIG_AMD_XGBE_DCB is not set +# CONFIG_AMIGA_PARTITION is not set +CONFIG_AMT=m +CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" +CONFIG_ANDROID_BINDERFS=y +# CONFIG_ANDROID_BINDER_IPC is not set +# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set +# CONFIG_ANON_VMA_NAME is not set +# CONFIG_AOSONG_AGS02MA is not set +# CONFIG_APDS9300 is not set +CONFIG_APDS9306=m +CONFIG_APDS9802ALS=m +# CONFIG_APDS9960 is not set +CONFIG_APPLE_MFI_FASTCHARGE=m +# CONFIG_APPLE_PROPERTIES is not set +# CONFIG_APPLICOM is not set +CONFIG_AQTION=m +CONFIG_AQUANTIA_PHY=m +CONFIG_AR5523=m +# CONFIG_ARCH_APPLE is not set +# CONFIG_ARCH_BCM4908 is not set +CONFIG_ARCH_CANAAN=y +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_KEEMBAY is not set +CONFIG_ARCH_MICROCHIP_POLARFIRE=y +CONFIG_ARCH_MICROCHIP=y +CONFIG_ARCH_MMAP_RND_BITS=18 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_OMAP1 is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_R9A07G043 is not set +CONFIG_ARCH_RANDOM=y +# CONFIG_ARCH_REALTEK is not set +# CONFIG_ARCH_RENESAS is not set +# CONFIG_ARCH_RV32I is not set +CONFIG_ARCH_RV64I=y +# CONFIG_ARCH_S32 is not set +# CONFIG_ARCH_SA1100 is not set +CONFIG_ARCH_SIFIVE=y +CONFIG_ARCH_SOPHGO=y +# CONFIG_ARCH_SPARX5 is not set +CONFIG_ARCH_STARFIVE=y +# CONFIG_ARCH_SUNXI is not set +CONFIG_ARCH_THEAD=y +CONFIG_ARCH_VIRT=y +# CONFIG_ARCNET is not set +CONFIG_ARM64_AMU_EXTN=y +CONFIG_ARM64_E0PD=y +CONFIG_ARM64_EPAN=y +CONFIG_ARM64_ERRATUM_1319367=y +CONFIG_ARM64_ERRATUM_1530923=y +CONFIG_ARM64_ERRATUM_1542419=y +CONFIG_ARM64_ERRATUM_2054223=y +CONFIG_ARM64_ERRATUM_2067961=y +CONFIG_ARM64_ERRATUM_2119858=y +CONFIG_ARM64_ERRATUM_2139208=y +CONFIG_ARM64_ERRATUM_2224489=y +CONFIG_ARM64_ERRATUM_2253138=y +CONFIG_ARM64_USE_LSE_ATOMICS=y +CONFIG_ARM_CMN=m +# CONFIG_ARM_MHU is not set +# CONFIG_ARM_MHU_V2 is not set +# CONFIG_ARM_MHU_V3 is not set +# CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set +# CONFIG_ARM_SCMI_TRANSPORT_SMC is not set +# CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set +CONFIG_ARM_SMCCC_SOC_ID=y +# CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS is not set +# CONFIG_AS3935 is not set +# CONFIG_AS73211 is not set +# CONFIG_ASUS_TF103C_DOCK is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_TPM_KEY_SUBTYPE=m +CONFIG_ASYNC_RAID6_TEST=m +CONFIG_ASYNC_TX_DMA=y +CONFIG_AT803X_PHY=m +CONFIG_ATA_ACPI=y +CONFIG_ATA_BMDMA=y +CONFIG_ATA_FORCE=y +CONFIG_ATA_GENERIC=m +CONFIG_ATALK=m +CONFIG_ATA_OVER_ETH=m +CONFIG_ATA_PIIX=y +# CONFIG_ATARI_PARTITION is not set +CONFIG_ATA_SFF=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA=y +CONFIG_ATH10K_AHB=y +CONFIG_ATH10K_DEBUGFS=y +# CONFIG_ATH10K_DEBUG is not set +CONFIG_ATH10K=m +CONFIG_ATH10K_PCI=m +CONFIG_ATH10K_SDIO=m +# CONFIG_ATH10K_SPECTRAL is not set +# CONFIG_ATH10K_TRACING is not set +CONFIG_ATH10K_USB=m +# CONFIG_ATH11K_AHB is not set +# CONFIG_ATH11K_DEBUGFS is not set +# CONFIG_ATH11K_DEBUG is not set +CONFIG_ATH11K=m +CONFIG_ATH11K_PCI=m +# CONFIG_ATH11K_SPECTRAL is not set +# CONFIG_ATH11K_TRACING is not set +# CONFIG_ATH12K_DEBUGFS is not set +# CONFIG_ATH12K_DEBUG is not set +CONFIG_ATH12K=m +# CONFIG_ATH12K_TRACING is not set +CONFIG_ATH5K_DEBUG=y +CONFIG_ATH5K=m +# CONFIG_ATH5K_TRACER is not set +CONFIG_ATH6KL_DEBUG=y +CONFIG_ATH6KL=m +CONFIG_ATH6KL_SDIO=m +# CONFIG_ATH6KL_TRACING is not set +CONFIG_ATH6KL_USB=m +CONFIG_ATH9K_AHB=y +CONFIG_ATH9K_BTCOEX_SUPPORT=y +# CONFIG_ATH9K_CHANNEL_CONTEXT is not set +# CONFIG_ATH9K_COMMON_SPECTRAL is not set +CONFIG_ATH9K_DEBUGFS=y +# CONFIG_ATH9K_DYNACK is not set +# CONFIG_ATH9K_HTC_DEBUGFS is not set +CONFIG_ATH9K_HTC=m +# CONFIG_ATH9K_HWRNG is not set +CONFIG_ATH9K=m +CONFIG_ATH9K_PCI_NO_EEPROM=m +CONFIG_ATH9K_PCI=y +CONFIG_ATH9K_PCOEM=y +CONFIG_ATH9K_RFKILL=y +# CONFIG_ATH9K_STATION_STATISTICS is not set +# CONFIG_ATH9K_WOW is not set +CONFIG_ATH_COMMON=m +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH_TRACEPOINTS is not set +CONFIG_ATL1C=m +CONFIG_ATL1E=m +CONFIG_ATL1=m +CONFIG_ATL2=m +# CONFIG_ATLAS_EZO_SENSOR is not set +# CONFIG_ATLAS_PH_SENSOR is not set +# CONFIG_ATM_BR2684_IPFILTER is not set +CONFIG_ATM_BR2684=m +CONFIG_ATM_CLIP=m +# CONFIG_ATM_CLIP_NO_ICMP is not set +CONFIG_ATM_DRIVERS=y +# CONFIG_ATM_DUMMY is not set +# CONFIG_ATM_ENI_DEBUG is not set +CONFIG_ATM_ENI=m +# CONFIG_ATM_ENI_TUNE_BURST is not set +# CONFIG_ATM_FORE200E is not set +CONFIG_ATM_HE=m +# CONFIG_ATM_HE_USE_SUNI is not set +# CONFIG_ATM_IA is not set +# CONFIG_ATM_IDT77252 is not set +# CONFIG_ATM_LANAI is not set +CONFIG_ATM_LANE=m +CONFIG_ATM=m +# CONFIG_ATM_MPOA is not set +CONFIG_ATM_NICSTAR=m +# CONFIG_ATM_NICSTAR_USE_IDT77105 is not set +# CONFIG_ATM_NICSTAR_USE_SUNI is not set +CONFIG_ATM_SOLOS=m +CONFIG_ATM_TCP=m +CONFIG_ATOMIC64_SELFTEST=y +CONFIG_ATP=m +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT=y +CONFIG_AUTOFS_FS=y +CONFIG_AUXDISPLAY=y +CONFIG_AX25_DAMA_SLAVE=y +CONFIG_AX25=m +# CONFIG_AX45MP_L2_CACHE is not set +CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y +CONFIG_AXP20X_ADC=m +CONFIG_AXP20X_POWER=m +CONFIG_AXP288_ADC=m +CONFIG_B43_BCMA_PIO=y +CONFIG_B43_BCMA=y +CONFIG_B43_BUSES_BCMA_AND_SSB=y +# CONFIG_B43_BUSES_BCMA is not set +# CONFIG_B43_BUSES_SSB is not set +# CONFIG_B43_DEBUG is not set +# CONFIG_B43LEGACY_DEBUG is not set +CONFIG_B43LEGACY_DMA_AND_PIO_MODE=y +# CONFIG_B43LEGACY_DMA_MODE is not set +CONFIG_B43LEGACY_DMA=y +CONFIG_B43LEGACY=m +# CONFIG_B43LEGACY_PIO_MODE is not set +CONFIG_B43LEGACY_PIO=y +CONFIG_B43=m +CONFIG_B43_PHY_G=y +CONFIG_B43_PHY_HT=y +CONFIG_B43_PHY_LP=y +CONFIG_B43_PHY_N=y +CONFIG_B43_SDIO=y +CONFIG_B44=m +CONFIG_B44_PCI=y +CONFIG_B53=m +CONFIG_B53_MDIO_DRIVER=m +CONFIG_B53_MMAP_DRIVER=m +CONFIG_B53_SERDES=m +CONFIG_B53_SPI_DRIVER=m +CONFIG_B53_SRAB_DRIVER=m +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +CONFIG_BACKLIGHT_ARCXCNN=m +# CONFIG_BACKLIGHT_BD6107 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GPIO is not set +CONFIG_BACKLIGHT_KTD253=m +# CONFIG_BACKLIGHT_KTD2801 is not set +CONFIG_BACKLIGHT_KTZ8866=m +CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m +# CONFIG_BACKLIGHT_LM3630A is not set +# CONFIG_BACKLIGHT_LM3639 is not set +CONFIG_BACKLIGHT_LP855X=m +# CONFIG_BACKLIGHT_LV5207LP is not set +CONFIG_BACKLIGHT_MP3309C=m +CONFIG_BACKLIGHT_MT6370=m +CONFIG_BACKLIGHT_PWM=m +# CONFIG_BACKLIGHT_QCOM_WLED is not set +CONFIG_BACKLIGHT_RT4831=m +# CONFIG_BACKLIGHT_SAHARA is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +CONFIG_BALLOON_COMPACTION=y +# CONFIG_BARCO_P50_GPIO is not set +CONFIG_BAREUDP=m +CONFIG_BASE_FULL=y +# CONFIG_BASE_SMALL is not set +CONFIG_BATMAN_ADV_BATMAN_V=y +CONFIG_BATMAN_ADV_BLA=y +CONFIG_BATMAN_ADV_DAT=y +# CONFIG_BATMAN_ADV_DEBUG is not set +CONFIG_BATMAN_ADV=m +CONFIG_BATMAN_ADV_MCAST=y +CONFIG_BATMAN_ADV_NC=y +CONFIG_BATMAN_ADV_TRACING=y +CONFIG_BATTERY_AXP20X=m +# CONFIG_BATTERY_BQ27XXX is not set +CONFIG_BATTERY_CW2015=m +# CONFIG_BATTERY_DS2760 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m +# CONFIG_BATTERY_MAX1721X is not set +CONFIG_BATTERY_RT5033=m +CONFIG_BATTERY_SAMSUNG_SDI=y +# CONFIG_BATTERY_SBS is not set +CONFIG_BATTERY_SURFACE=m +CONFIG_BATTERY_UG3105=m +CONFIG_BAYCOM_EPP=m +CONFIG_BAYCOM_PAR=m +CONFIG_BAYCOM_SER_FDX=m +CONFIG_BAYCOM_SER_HDX=m +# CONFIG_BCACHE_ASYNC_REGISTRATION is not set +# CONFIG_BCACHE_CLOSURES_DEBUG is not set +# CONFIG_BCACHE_DEBUG is not set +# CONFIG_BCACHEFS_DEBUG is not set +# CONFIG_BCACHEFS_DEBUG_TRANSACTIONS is not set +# CONFIG_BCACHEFS_ERASURE_CODING is not set +CONFIG_BCACHEFS_FS=m +# CONFIG_BCACHEFS_LOCK_TIME_STATS is not set +# CONFIG_BCACHEFS_NO_LATENCY_ACCT is not set +CONFIG_BCACHEFS_POSIX_ACL=y +CONFIG_BCACHEFS_QUOTA=y +CONFIG_BCACHEFS_SIX_OPTIMISTIC_SPIN=y +# CONFIG_BCACHEFS_TESTS is not set +CONFIG_BCACHE=m +CONFIG_BCM54140_PHY=m +CONFIG_BCM7XXX_PHY=m +# CONFIG_BCM84881_PHY is not set +CONFIG_BCM87XX_PHY=m +CONFIG_BCMA_BLOCKIO=y +# CONFIG_BCMA_DEBUG is not set +CONFIG_BCMA_DRIVER_GMAC_CMN=y +CONFIG_BCMA_DRIVER_GPIO=y +CONFIG_BCMA_HOST_PCI_POSSIBLE=y +CONFIG_BCMA_HOST_PCI=y +# CONFIG_BCMA_HOST_SOC is not set +CONFIG_BCMA=m +CONFIG_BCMGENET=m +# CONFIG_BCM_KONA_USB2_PHY is not set +CONFIG_BCM_NET_PHYPTP=m +CONFIG_BCM_VK=m +CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m +CONFIG_BE2ISCSI=m +CONFIG_BE2NET_BE2=y +CONFIG_BE2NET_BE3=y +# CONFIG_BE2NET_HWMON is not set +CONFIG_BE2NET_LANCER=y +CONFIG_BE2NET=m +CONFIG_BE2NET_SKYHAWK=y +# CONFIG_BEFS_DEBUG is not set +CONFIG_BEFS_FS=m +# CONFIG_BFQ_CGROUP_DEBUG is not set +CONFIG_BFQ_GROUP_IOSCHED=y +# CONFIG_BFS_FS is not set +CONFIG_BH1750=m +# CONFIG_BH1780 is not set +CONFIG_BIG_KEYS=y +CONFIG_BINFMT_ELF=y +# CONFIG_BINFMT_FLAT is not set +CONFIG_BINFMT_MISC=m +CONFIG_BINFMT_SCRIPT=y +CONFIG_BITFIELD_KUNIT=m +CONFIG_BITS_TEST=m +CONFIG_BLK_CGROUP_FC_APPID=y +CONFIG_BLK_CGROUP_IOCOST=y +CONFIG_BLK_CGROUP_IOLATENCY=y +CONFIG_BLK_CGROUP_IOPRIO=y +CONFIG_BLK_CGROUP=y +CONFIG_BLK_DEBUG_FS=y +CONFIG_BLK_DEV_3W_XXXX_RAID=m +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_DM=y +CONFIG_BLK_DEV_DRBD=m +CONFIG_BLK_DEV_FD=m +# CONFIG_BLK_DEV_FD_RAWCMD is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_BLK_DEV_LOOP=m +CONFIG_BLK_DEV_LOOP_MIN_COUNT=0 +CONFIG_BLK_DEV_MD=y +CONFIG_BLK_DEV_NBD=m +# CONFIG_BLK_DEV_NULL_BLK_FAULT_INJECTION is not set +CONFIG_BLK_DEV_NULL_BLK=m +CONFIG_BLK_DEV_NVME=m +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +CONFIG_BLK_DEV_PMEM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_BLK_DEV_RBD=m +CONFIG_BLK_DEV_RNBD_CLIENT=m +CONFIG_BLK_DEV_RNBD_SERVER=m +# CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SX8=m +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_DEV_THROTTLING=y +CONFIG_BLKDEV_UBLK_LEGACY_OPCODES=y +CONFIG_BLK_DEV_UBLK=m +CONFIG_BLK_DEV_WRITE_MOUNTED=y +CONFIG_BLK_DEV=y +CONFIG_BLK_DEV_ZONED=y +# CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK is not set +CONFIG_BLK_INLINE_ENCRYPTION=y +CONFIG_BLK_SED_OPAL=y +CONFIG_BLK_WBT_MQ=y +CONFIG_BLK_WBT=y +CONFIG_BLOCK_LEGACY_AUTOLOAD=y +CONFIG_BLOCK=y +# CONFIG_BMA180 is not set +# CONFIG_BMA220 is not set +# CONFIG_BMA400 is not set +CONFIG_BMC150_ACCEL=m +CONFIG_BMC150_MAGN_I2C=m +CONFIG_BMC150_MAGN_SPI=m +CONFIG_BME680=m +# CONFIG_BMG160 is not set +# CONFIG_BMI088_ACCEL is not set +CONFIG_BMI160_I2C=m +CONFIG_BMI160_SPI=m +CONFIG_BMI323_I2C=m +CONFIG_BMI323_SPI=m +CONFIG_BMP280=m +CONFIG_BNA=m +CONFIG_BNX2=m +CONFIG_BNX2X=m +CONFIG_BNX2X_SRIOV=y +CONFIG_BNXT_DCB=y +CONFIG_BNXT_FLOWER_OFFLOAD=y +CONFIG_BNXT_HWMON=y +CONFIG_BNXT=m +CONFIG_BNXT_SRIOV=y +CONFIG_BONDING=m +# CONFIG_BOOT_CONFIG_EMBED is not set +# CONFIG_BOOT_CONFIG_FORCE is not set +CONFIG_BOOT_CONFIG=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOT_PRINTK_DELAY=y +CONFIG_BOOTTIME_TRACING=y +CONFIG_BOSCH_BNO055_I2C=m +CONFIG_BOSCH_BNO055_SERIAL=m +CONFIG_BOUNCE=y +# CONFIG_BPFILTER is not set +CONFIG_BPF_JIT_ALWAYS_ON=y +CONFIG_BPF_JIT=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_BPF_LIRC_MODE2=y +CONFIG_BPF_LSM=y +CONFIG_BPF_PRELOAD_UMD=m +CONFIG_BPF_PRELOAD=y +CONFIG_BPF_STREAM_PARSER=y +CONFIG_BPF_SYSCALL=y +CONFIG_BPF_UNPRIV_DEFAULT_OFF=y +CONFIG_BPQETHER=m +CONFIG_BQL=y +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_BRCMDBG is not set +CONFIG_BRCMFMAC=m +CONFIG_BRCMFMAC_PCIE=y +CONFIG_BRCMFMAC_SDIO=y +CONFIG_BRCMFMAC_USB=y +CONFIG_BRCMSMAC=m +# CONFIG_BRCM_TRACING is not set +CONFIG_BRIDGE_CFM=y +CONFIG_BRIDGE_EBT_802_3=m +CONFIG_BRIDGE_EBT_AMONG=m +CONFIG_BRIDGE_EBT_ARP=m +CONFIG_BRIDGE_EBT_ARPREPLY=m +CONFIG_BRIDGE_EBT_BROUTE=m +CONFIG_BRIDGE_EBT_DNAT=m +CONFIG_BRIDGE_EBT_IP6=m +CONFIG_BRIDGE_EBT_IP=m +CONFIG_BRIDGE_EBT_LIMIT=m +CONFIG_BRIDGE_EBT_LOG=m +CONFIG_BRIDGE_EBT_MARK=m +CONFIG_BRIDGE_EBT_MARK_T=m +CONFIG_BRIDGE_EBT_NFLOG=m +CONFIG_BRIDGE_EBT_PKTTYPE=m +CONFIG_BRIDGE_EBT_REDIRECT=m +CONFIG_BRIDGE_EBT_SNAT=m +CONFIG_BRIDGE_EBT_STP=m +CONFIG_BRIDGE_EBT_T_FILTER=m +CONFIG_BRIDGE_EBT_T_NAT=m +CONFIG_BRIDGE_EBT_VLAN=m +CONFIG_BRIDGE_IGMP_SNOOPING=y +CONFIG_BRIDGE=m +CONFIG_BRIDGE_MRP=y +CONFIG_BRIDGE_NETFILTER=m +CONFIG_BRIDGE_NF_EBTABLES=m +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_BROADCOM_PHY=m +CONFIG_BSD_DISKLABEL=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BT_6LOWPAN=m +CONFIG_BT_AOSPEXT=y +CONFIG_BT_ATH3K=m +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_BREDR=y +# CONFIG_BT_DEBUGFS is not set +CONFIG_BT_HCIBCM203X=m +CONFIG_BT_HCIBCM4377=m +CONFIG_BT_HCIBFUSB=m +CONFIG_BT_HCIBLUECARD=m +CONFIG_BT_HCIBPA10X=m +CONFIG_BT_HCIBT3C=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y +CONFIG_BT_HCIBTUSB_BCM=y +CONFIG_BT_HCIBTUSB=m +CONFIG_BT_HCIBTUSB_MTK=y +CONFIG_BT_HCIBTUSB_POLL_SYNC=y +CONFIG_BT_HCIBTUSB_RTL=y +CONFIG_BT_HCIDTL1=m +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_AG6XX=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_BCM=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_H4=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_HCIUART_NOKIA=m +CONFIG_BT_HCIUART_QCA=y +# CONFIG_BT_HCIUART_RTL is not set +CONFIG_BT_HCIUART_SERDEV=y +CONFIG_BT_HCIVHCI=m +CONFIG_BT_HIDP=m +# CONFIG_BT_HS is not set +CONFIG_BT_INTEL_PCIE=m +CONFIG_BT_LEDS=y +CONFIG_BT_LE_L2CAP_ECRED=y +CONFIG_BT_LE=y +CONFIG_BT=m +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_BT_MSFTEXT=y +CONFIG_BT_MTKSDIO=m +CONFIG_BT_MTKUART=m +CONFIG_BT_NXPUART=m +CONFIG_BT_QCA=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +# CONFIG_BTRFS_ASSERT is not set +# CONFIG_BTRFS_DEBUG is not set +# CONFIG_BTRFS_FS_CHECK_INTEGRITY is not set +CONFIG_BTRFS_FS_POSIX_ACL=y +# CONFIG_BTRFS_FS_REF_VERIFY is not set +# CONFIG_BTRFS_FS_RUN_SANITY_TESTS is not set +CONFIG_BTRFS_FS=y +# CONFIG_BT_SELFTEST is not set +# CONFIG_BTT is not set +CONFIG_BT_VIRTIO=m +CONFIG_BUG_ON_DATA_CORRUPTION=y +CONFIG_BUG=y +CONFIG_BUILD_SALT="" +# CONFIG_C2PORT is not set +# CONFIG_CACHEFILES_DEBUG is not set +# CONFIG_CACHEFILES_ERROR_INJECTION is not set +CONFIG_CACHEFILES=m +CONFIG_CACHEFILES_ONDEMAND=y +CONFIG_CACHESTAT_SYSCALL=y +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_CAIF is not set +CONFIG_CAN_8DEV_USB=m +CONFIG_CAN_BCM=m +CONFIG_CAN_CALC_BITTIMING=y +CONFIG_CAN_CAN327=m +# CONFIG_CAN_CC770 is not set +# CONFIG_CAN_C_CAN is not set +CONFIG_CAN_CTUCANFD_PCI=m +CONFIG_CAN_CTUCANFD_PLATFORM=m +# CONFIG_CAN_DEBUG_DEVICES is not set +CONFIG_CAN_DEV=m +CONFIG_CAN_EMS_USB=m +# CONFIG_CAN_ESD_402_PCI is not set +CONFIG_CAN_ESD_USB2=m +CONFIG_CAN_ESD_USB=m +# CONFIG_CAN_ETAS_ES58X is not set +CONFIG_CAN_F81604=m +# CONFIG_CAN_FLEXCAN is not set +# CONFIG_CAN_GRCAN is not set +CONFIG_CAN_GS_USB=m +CONFIG_CAN_GW=m +CONFIG_CAN_HI311X=m +CONFIG_CAN_IFI_CANFD=m +CONFIG_CAN_ISOTP=m +CONFIG_CAN_J1939=m +# CONFIG_CAN_KVASER_PCIEFD is not set +CONFIG_CAN_KVASER_USB=m +CONFIG_CAN=m +CONFIG_CAN_M_CAN=m +CONFIG_CAN_M_CAN_PCI=m +# CONFIG_CAN_M_CAN_PLATFORM is not set +# CONFIG_CAN_M_CAN_TCAN4X5X is not set +CONFIG_CAN_MCBA_USB=m +CONFIG_CAN_MCP251XFD=m +# CONFIG_CAN_MCP251XFD_SANITY is not set +CONFIG_CAN_MCP251X=m +CONFIG_CAN_NETLINK=y +CONFIG_CAN_PEAK_PCIEFD=m +CONFIG_CAN_PEAK_USB=m +CONFIG_CAN_RAW=m +# CONFIG_CAN_SJA1000 is not set +CONFIG_CAN_SLCAN=m +# CONFIG_CAN_SOFTING is not set +CONFIG_CAN_SUN4I=m +# CONFIG_CAN_UCAN is not set +CONFIG_CAN_VCAN=m +CONFIG_CAN_VXCAN=m +# CONFIG_CARDBUS is not set +# CONFIG_CARL9170_DEBUGFS is not set +# CONFIG_CARL9170_HWRNG is not set +CONFIG_CARL9170_LEDS=y +CONFIG_CARL9170=m +CONFIG_CASSINI=m +CONFIG_CB710_CORE=m +# CONFIG_CB710_DEBUG is not set +# CONFIG_CC10001_ADC is not set +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_CCS811 is not set +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +CONFIG_CDROM_PKTCDVD=m +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_CDX_CONTROLLER=m +CONFIG_CEC_CH7322=m +CONFIG_CEC_GPIO=m +# CONFIG_CEC_PIN_ERROR_INJ is not set +CONFIG_CEC_PIN=y +# CONFIG_CEC_SECO is not set +CONFIG_CEC_SECO_RC=y +CONFIG_CEPH_FSCACHE=y +CONFIG_CEPH_FS=m +CONFIG_CEPH_FS_POSIX_ACL=y +CONFIG_CEPH_FS_SECURITY_LABEL=y +CONFIG_CEPH_LIB=m +# CONFIG_CEPH_LIB_PRETTYDEBUG is not set +# CONFIG_CEPH_LIB_USE_DNS_RESOLVER is not set +CONFIG_CFAG12864B=m +CONFIG_CFAG12864B_RATE=20 +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_CRDA_SUPPORT=y +CONFIG_CFG80211_DEBUGFS=y +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +CONFIG_CFG80211_KUNIT_TEST=m +CONFIG_CFG80211=m +# CONFIG_CFI_CLANG is not set +CONFIG_CFS_BANDWIDTH=y +CONFIG_CGROUP_BPF=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_DEVICE=y +# CONFIG_CGROUP_FAVOR_DYNMODS is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CGROUP_MISC=y +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_CGROUP_NET_PRIO=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_RDMA=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUPS=y +# CONFIG_CHARGER_ADP5061 is not set +CONFIG_CHARGER_AXP20X=m +CONFIG_CHARGER_BD99954=m +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_BQ24190 is not set +# CONFIG_CHARGER_BQ24257 is not set +# CONFIG_CHARGER_BQ24735 is not set +CONFIG_CHARGER_BQ2515X=m +CONFIG_CHARGER_BQ256XX=m +# CONFIG_CHARGER_BQ25890 is not set +# CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m +CONFIG_CHARGER_CROS_PCHG=m +# CONFIG_CHARGER_CROS_USBPD is not set +# CONFIG_CHARGER_DETECTOR_MAX14656 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_LP8727 is not set +CONFIG_CHARGER_LT3651=m +CONFIG_CHARGER_LTC4162L=m +# CONFIG_CHARGER_MANAGER is not set +CONFIG_CHARGER_MAX77650=m +CONFIG_CHARGER_MAX77976=m +# CONFIG_CHARGER_MAX8903 is not set +CONFIG_CHARGER_MT6370=m +# CONFIG_CHARGER_RT9455 is not set +CONFIG_CHARGER_RT9467=m +CONFIG_CHARGER_RT9471=m +# CONFIG_CHARGER_SBS is not set +CONFIG_CHARGER_SMB347=m +CONFIG_CHARGER_SURFACE=m +CONFIG_CHARGER_UCS1002=m +CONFIG_CHARLCD_BL_FLASH=y +# CONFIG_CHARLCD_BL_OFF is not set +# CONFIG_CHARLCD_BL_ON is not set +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_CHECKSUM_KUNIT=m +CONFIG_CHELSIO_INLINE_CRYPTO=y +CONFIG_CHELSIO_IPSEC_INLINE=m +CONFIG_CHELSIO_T1_1G=y +CONFIG_CHELSIO_T1=m +CONFIG_CHELSIO_T3=m +CONFIG_CHELSIO_T4_DCB=y +# CONFIG_CHELSIO_T4_FCOE is not set +CONFIG_CHELSIO_T4=m +CONFIG_CHELSIO_T4VF=m +CONFIG_CHELSIO_TLS_DEVICE=m +CONFIG_CHR_DEV_SCH=m +CONFIG_CHR_DEV_SG=y +CONFIG_CHR_DEV_ST=m +CONFIG_CHROMEOS_ACPI=m +CONFIG_CHROMEOS_PRIVACY_SCREEN=m +CONFIG_CHROMEOS_TBMC=y +CONFIG_CHROME_PLATFORMS=y +CONFIG_CHT_DC_TI_PMIC_OPREGION=y +CONFIG_CICADA_PHY=m +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +CONFIG_CIFS_DEBUG=y +CONFIG_CIFS_DFS_UPCALL=y +CONFIG_CIFS_FSCACHE=y +CONFIG_CIFS=m +CONFIG_CIFS_POSIX=y +# CONFIG_CIFS_SMB_DIRECT is not set +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_SWN_UPCALL=y +CONFIG_CIFS_UPCALL=y +CONFIG_CIFS_XATTR=y +CONFIG_CIO2_BRIDGE=y +CONFIG_CLEANCACHE=y +CONFIG_CLK_FD_KUNIT_TEST=m +CONFIG_CLK_GATE_KUNIT_TEST=m +# CONFIG_CLK_ICST is not set +CONFIG_CLK_KUNIT_TEST=m +# CONFIG_CLK_QORIQ is not set +# CONFIG_CLK_RASPBERRYPI is not set +CONFIG_CLK_SIFIVE_PRCI=y +CONFIG_CLK_SIFIVE=y +CONFIG_CLK_SOPHGO_CV1800=y +# CONFIG_CLK_SOPHGO_SG2042_PLL is not set +# CONFIG_CLK_SP810 is not set +CONFIG_CLK_STARFIVE_JH7100_AUDIO=m +CONFIG_CLK_STARFIVE_JH7100=y +CONFIG_CLK_STARFIVE_JH7110_AON=y +CONFIG_CLK_STARFIVE_JH7110_ISP=y +CONFIG_CLK_STARFIVE_JH7110_PLL=y +CONFIG_CLK_STARFIVE_JH7110_STG=y +CONFIG_CLK_STARFIVE_JH7110_SYS=y +CONFIG_CLK_STARFIVE_JH7110_VOUT=y +CONFIG_CLK_STARFIVE_JH71X0=y +# CONFIG_CLK_SUNXI_CLOCKS is not set +# CONFIG_CLK_SUNXI is not set +# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set +# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set +CONFIG_CLK_THEAD_TH1520_AP=y +CONFIG_CLOCKSOURCE_WATCHDOG_MAX_SKEW_US=100 +CONFIG_CLS_U32_MARK=y +CONFIG_CLS_U32_PERF=y +CONFIG_CM32181=m +# CONFIG_CM3232 is not set +# CONFIG_CM3323 is not set +CONFIG_CM3605=m +# CONFIG_CM36651 is not set +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA is not set +CONFIG_CMA_SYSFS=y +CONFIG_CMDLINE="" +# CONFIG_CMDLINE_BOOL is not set +CONFIG_CMDLINE_FROM_BOOTLOADER=y +CONFIG_CMDLINE_KUNIT_TEST=m +# CONFIG_CMDLINE_PARTITION is not set +CONFIG_CMODEL_MEDANY=y +# CONFIG_CMODEL_MEDLOW is not set +CONFIG_CNIC=m +CONFIG_CODA_FS=m +# CONFIG_COMEDI is not set +CONFIG_COMMAND_LINE_SIZE=4096 +CONFIG_COMMON_CLK_AXG_AUDIO=y +CONFIG_COMMON_CLK_AXI_CLKGEN=m +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CDCE925 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_COMMON_CLK_FIXED_MMIO is not set +# CONFIG_COMMON_CLK_FSL_FLEXSPI is not set +# CONFIG_COMMON_CLK_FSL_SAI is not set +# CONFIG_COMMON_CLK_LAN966X is not set +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_MMP2_AUDIO is not set +CONFIG_COMMON_CLK_PWM=m +CONFIG_COMMON_CLK_RS9_PCIE=m +# CONFIG_COMMON_CLK_SI514 is not set +CONFIG_COMMON_CLK_SI521XX=y +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +CONFIG_COMMON_CLK_SI544=m +# CONFIG_COMMON_CLK_SI570 is not set +CONFIG_COMMON_CLK_VC3=m +# CONFIG_COMMON_CLK_VC5 is not set +CONFIG_COMMON_CLK_VC7=m +# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set +CONFIG_COMMON_CLK=y +CONFIG_COMPACTION=y +CONFIG_COMPAT_32BIT_TIME=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_COMPAT is not set +# CONFIG_COMPILE_TEST is not set +CONFIG_CONFIGFS_FS=y +CONFIG_CONNECTOR=y +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=3 +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set +CONFIG_CORDIC=m +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_COREDUMP=y +# CONFIG_CORESIGHT_CPU_DEBUG_DEFAULT_ON is not set +CONFIG_CORTINA_PHY=m +# CONFIG_COUNTER is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=m +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_THERMAL=y +CONFIG_CPU_FREQ=y +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +# CONFIG_CPU_IDLE_GOV_LADDER is not set +# CONFIG_CPU_IDLE_GOV_TEO is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPUMASK_KUNIT_TEST=m +CONFIG_CPUMASK_OFFSTACK=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPUSETS=y +# CONFIG_CPU_THERMAL is not set +# CONFIG_CRAMFS is not set +# CONFIG_CRAMFS_MTD is not set +CONFIG_CRASH_DUMP=y +CONFIG_CRASH_HOTPLUG=y +CONFIG_CRASH_MAX_MEMORY_RANGES=8192 +CONFIG_CRC16=y +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_SELFTEST is not set +# CONFIG_CRC32_SLICEBY4 is not set +CONFIG_CRC32_SLICEBY8=y +CONFIG_CRC32=y +CONFIG_CRC4=m +CONFIG_CRC64=y +CONFIG_CRC7=y +CONFIG_CRC8=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC_T10DIF=y +# CONFIG_CROS_EC_DEBUGFS is not set +# CONFIG_CROS_EC is not set +# CONFIG_CROS_EC_LIGHTBAR is not set +CONFIG_CROS_EC_MKBP_PROXIMITY=m +CONFIG_CROS_EC_RPMSG=m +CONFIG_CROS_EC_SENSORHUB=m +CONFIG_CROS_EC_TYPEC=m +CONFIG_CROS_EC_UART=m +CONFIG_CROS_EC_WATCHDOG=m +CONFIG_CROS_HPS_I2C=m +CONFIG_CROS_KBD_LED_BACKLIGHT=m +CONFIG_CROS_KUNIT_EC_PROTO_TEST=m +CONFIG_CROS_KUNIT=m +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CROS_TYPEC_SWITCH=m +CONFIG_CROS_USBPD_LOGGER=m +CONFIG_CROS_USBPD_NOTIFY=m +CONFIG_CRYPTO_842=y +CONFIG_CRYPTO_ADIANTUM=m +CONFIG_CRYPTO_AEGIS128=m +# CONFIG_CRYPTO_AES_ARM64 is not set +CONFIG_CRYPTO_AES_RISCV64=y +CONFIG_CRYPTO_AES_TI=m +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_ARIA is not set +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_BLAKE2B=y +CONFIG_CRYPTO_BLAKE2S=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_CHACHA20=m +CONFIG_CRYPTO_CHACHA20POLY1305=m +CONFIG_CRYPTO_CHACHA_RISCV64=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_CRC32C_VPMSUM=m +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_CRC32=m +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_CURVE25519=m +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set +CONFIG_CRYPTO_DEV_ATMEL_ECC=m +CONFIG_CRYPTO_DEV_ATMEL_SHA204A=m +# CONFIG_CRYPTO_DEV_CCP_DEBUGFS is not set +# CONFIG_CRYPTO_DEV_CCREE is not set +CONFIG_CRYPTO_DEV_CHELSIO=m +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_HIFN_795X=m +CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y +# CONFIG_CRYPTO_DEV_HISI_HPRE is not set +# CONFIG_CRYPTO_DEV_HISI_SEC2 is not set +# CONFIG_CRYPTO_DEV_HISI_SEC is not set +# CONFIG_CRYPTO_DEV_HISI_TRNG is not set +CONFIG_CRYPTO_DEV_JH7110=m +CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m +# CONFIG_CRYPTO_DEV_OCTEONTX_CPT is not set +CONFIG_CRYPTO_DEV_QAT_420XX=m +CONFIG_CRYPTO_DEV_QAT_4XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXX=m +CONFIG_CRYPTO_DEV_QAT_C3XXXVF=m +CONFIG_CRYPTO_DEV_QAT_C62X=m +CONFIG_CRYPTO_DEV_QAT_C62XVF=m +CONFIG_CRYPTO_DEV_QAT_DH895xCC=m +CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m +# CONFIG_CRYPTO_DEV_QAT_ERROR_INJECTION is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_SP_CCP is not set +CONFIG_CRYPTO_DEV_VIRTIO=m +CONFIG_CRYPTO_DH_RFC7919_GROUPS=y +CONFIG_CRYPTO_DH=y +CONFIG_CRYPTO_DRBG_CTR=y +CONFIG_CRYPTO_DRBG_HASH=y +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_ECDSA=y +CONFIG_CRYPTO_ECHAINIV=m +CONFIG_CRYPTO_ECRDSA=m +CONFIG_CRYPTO_ESSIV=m +CONFIG_CRYPTO_FCRYPT=m +# CONFIG_CRYPTO_FIPS_CUSTOM_VERSION is not set +CONFIG_CRYPTO_FIPS_NAME="Linux Kernel Cryptographic API" +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_GHASH_RISCV64=y +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_HCTR2=m +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_1024 is not set +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_128 is not set +CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_2=y +# CONFIG_CRYPTO_JITTERENTROPY_MEMSIZE_8192 is not set +CONFIG_CRYPTO_JITTERENTROPY_OSR=1 +# CONFIG_CRYPTO_JITTERENTROPY_TESTINTERFACE is not set +CONFIG_CRYPTO_KEYWRAP=m +CONFIG_CRYPTO_LIB_BLAKE2S=m +CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y +CONFIG_CRYPTO_LIB_CHACHA=y +CONFIG_CRYPTO_LIB_CURVE25519=m +CONFIG_CRYPTO_LIB_POLY1305=y +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_LZ4HC=m +CONFIG_CRYPTO_LZ4=m +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +# CONFIG_CRYPTO_MANAGER_EXTRA_TESTS is not set +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_PCRYPT=m +CONFIG_CRYPTO_POLY1305=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA256_RISCV64=y +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA3=y +CONFIG_CRYPTO_SHA512_RISCV64=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_SIMD=y +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_SM3_GENERIC is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_SM3_RISCV64 is not set +# CONFIG_CRYPTO_SM4_ARM64_CE_BLK is not set +# CONFIG_CRYPTO_SM4_ARM64_NEON_BLK is not set +# CONFIG_CRYPTO_SM4_GENERIC is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_SM4_RISCV64 is not set +# CONFIG_CRYPTO_STATS is not set +CONFIG_CRYPTO_STREEBOG=m +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_USER_API_AEAD=y +# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set +CONFIG_CRYPTO_USER_API_HASH=y +# CONFIG_CRYPTO_USER_API_RNG_CAVP is not set +CONFIG_CRYPTO_USER_API_RNG=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_USER=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_XCBC=m +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_XXHASH=y +CONFIG_CRYPTO=y +CONFIG_CRYPTO_ZSTD=m +# CONFIG_CSD_LOCK_WAIT_DEBUG_DEFAULT is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set +CONFIG_CUSE=m +CONFIG_CW1200=m +CONFIG_CW1200_WLAN_SDIO=m +CONFIG_CW1200_WLAN_SPI=m +CONFIG_CXD2880_SPI_DRV=m +# CONFIG_CX_ECAT is not set +CONFIG_CXL_ACPI=m +CONFIG_CXL_BUS=m +CONFIG_CXL_MEM=m +# CONFIG_CXL_MEM_RAW_COMMANDS is not set +CONFIG_CXL_PCI=m +CONFIG_CXL_PMEM=m +CONFIG_CXL_PMU=m +# CONFIG_CXL_REGION_INVALIDATION_TEST is not set +CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set +CONFIG_DA280=m +CONFIG_DA311=m +CONFIG_DA9063_WATCHDOG=m +# CONFIG_DAMON_DBGFS_DEPRECATED is not set +CONFIG_DAMON_DBGFS=y +# CONFIG_DAMON_LRU_SORT is not set +CONFIG_DAMON_PADDR=y +CONFIG_DAMON_RECLAIM=y +CONFIG_DAMON_SYSFS=y +CONFIG_DAMON_VADDR=y +CONFIG_DAMON=y +CONFIG_DAVICOM_PHY=m +CONFIG_DAX=y +CONFIG_DCB=y +# CONFIG_DDR is not set +CONFIG_DE2104X_DSL=0 +CONFIG_DE2104X=m +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +CONFIG_DEBUG_BOOT_PARAMS=y +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_CGROUP_REF is not set +# CONFIG_DEBUG_CLOSURES is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_64B is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +CONFIG_DEBUG_FS=y +# CONFIG_DEBUG_GPIO is not set +# CONFIG_DEBUG_HIGHMEM is not set +CONFIG_DEBUG_INFO_BTF_MODULES=y +CONFIG_DEBUG_INFO_BTF=y +# CONFIG_DEBUG_INFO_COMPRESSED is not set +CONFIG_DEBUG_INFO_COMPRESSED_NONE=y +# CONFIG_DEBUG_INFO_COMPRESSED_ZLIB is not set +# CONFIG_DEBUG_INFO_COMPRESSED_ZSTD is not set +# CONFIG_DEBUG_INFO_DWARF4 is not set +# CONFIG_DEBUG_INFO_DWARF5 is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y +# CONFIG_DEBUG_INFO_NONE is not set +# CONFIG_DEBUG_INFO_REDUCED is not set +# CONFIG_DEBUG_INFO_SPLIT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_IRQFLAGS is not set +# CONFIG_DEBUG_KERNEL_DC is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_KMAP_LOCAL is not set +# CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN is not set +# CONFIG_DEBUG_KMEMLEAK is not set +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_KOBJECT_RELEASE is not set +CONFIG_DEBUG_LIST=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_DEBUG_LOCKDEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_MAPLE_TREE is not set +CONFIG_DEBUG_MEMORY_INIT=y +# CONFIG_DEBUG_MISC is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_NET is not set +# CONFIG_DEBUG_NOTIFIERS is not set +CONFIG_DEBUG_OBJECTS_ENABLE_DEFAULT=0 +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_OBJECTS_SELFTEST is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_DEBUG_PAGE_REF is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RODATA_TEST is not set +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_DEBUG_RWSEMS is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +# CONFIG_DEBUG_SG is not set +CONFIG_DEBUG_SHIRQ=y +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_DEBUG_TIMEKEEPING is not set +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_MAPLE_TREE is not set +# CONFIG_DEBUG_VM_PGFLAGS is not set +# CONFIG_DEBUG_VM_PGTABLE is not set +# CONFIG_DEBUG_VM_RB is not set +# CONFIG_DEBUG_VM_SHOOT_LAZIES is not set +# CONFIG_DEBUG_VM_VMACACHE is not set +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set +CONFIG_DEBUG_WX=y +# CONFIG_DECNET is not set +CONFIG_DEFAULT_CUBIC=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +CONFIG_DEFAULT_INIT="" +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +# CONFIG_DEFAULT_RENO is not set +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_DETECT_HUNG_TASK is not set +CONFIG_DEV_DAX_CXL=m +CONFIG_DEV_DAX_HMEM=m +# CONFIG_DEV_DAX_KMEM is not set +CONFIG_DEV_DAX=m +# CONFIG_DEV_DAX_PMEM_COMPAT is not set +CONFIG_DEVMEM=y +CONFIG_DEVPORT=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_DEVTMPFS_SAFE=y +CONFIG_DEVTMPFS=y +CONFIG_DHT11=m +CONFIG_DL2K=m +# CONFIG_DLHL60D is not set +CONFIG_DLM_DEBUG=y +# CONFIG_DLM_DEPRECATED_API is not set +CONFIG_DLM=m +CONFIG_DLN2_ADC=m +CONFIG_DM9051=m +CONFIG_DM9102=m +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_API_DEBUG_SG is not set +# CONFIG_DMABUF_DEBUG is not set +CONFIG_DMABUF_HEAPS_CMA=y +CONFIG_DMABUF_HEAPS_SYSTEM=y +CONFIG_DMABUF_HEAPS=y +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_SYSFS_STATS is not set +# CONFIG_DMA_CMA is not set +# CONFIG_DMADEVICES_DEBUG is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_ENGINE=y +# CONFIG_DMA_FENCE_TRACE is not set +# CONFIG_DMA_MAP_BENCHMARK is not set +# CONFIG_DMA_NUMA_CMA is not set +# CONFIG_DMAPOOL_TEST is not set +# CONFIG_DMARD06 is not set +# CONFIG_DMARD09 is not set +CONFIG_DMARD10=m +# CONFIG_DMA_RESTRICTED_POOL is not set +# CONFIG_DMATEST is not set +CONFIG_DM_CACHE=m +CONFIG_DM_CACHE_SMQ=m +CONFIG_DM_CLONE=m +CONFIG_DM_CRYPT=m +# CONFIG_DM_DEBUG_BLOCK_MANAGER_LOCKING is not set +# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set +CONFIG_DM_DEBUG=y +CONFIG_DM_DELAY=m +CONFIG_DM_DUST=m +CONFIG_DM_EBS=m +CONFIG_DM_ERA=m +CONFIG_DM_FLAKEY=m +CONFIG_DMIID=y +CONFIG_DM_INIT=y +CONFIG_DM_INTEGRITY=m +CONFIG_DMI_SYSFS=y +CONFIG_DMI=y +# CONFIG_DM_KUNIT_TEST is not set +CONFIG_DM_LOG_USERSPACE=m +CONFIG_DM_LOG_WRITES=m +CONFIG_DM_MIRROR=y +CONFIG_DM_MULTIPATH_HST=m +CONFIG_DM_MULTIPATH_IOA=m +CONFIG_DM_MULTIPATH=m +CONFIG_DM_MULTIPATH_QL=m +CONFIG_DM_MULTIPATH_ST=m +CONFIG_DM_RAID=m +CONFIG_DM_SNAPSHOT=y +CONFIG_DM_SWITCH=m +CONFIG_DM_THIN_PROVISIONING=m +CONFIG_DM_UEVENT=y +CONFIG_DM_UNSTRIPED=m +CONFIG_DM_VDO=m +CONFIG_DM_VERITY_FEC=y +CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y +CONFIG_DM_WRITECACHE=m +CONFIG_DM_ZERO=y +CONFIG_DM_ZONED=m +CONFIG_DNET=m +CONFIG_DNOTIFY=y +CONFIG_DNS_RESOLVER=m +CONFIG_DP83640_PHY=m +CONFIG_DP83822_PHY=m +CONFIG_DP83848_PHY=m +CONFIG_DP83867_PHY=m +CONFIG_DP83869_PHY=m +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83TD510_PHY is not set +CONFIG_DP83TG720_PHY=m +# CONFIG_DPM_WATCHDOG is not set +CONFIG_DPOT_DAC=m +# CONFIG_DPS310 is not set +CONFIG_DRAGONRISE_FF=y +# CONFIG_DRBD_FAULT_INJECTION is not set +CONFIG_DRIVER_PE_KUNIT_TEST=m +# CONFIG_DRM_ACCEL_QAIC is not set +CONFIG_DRM_ACCEL=y +CONFIG_DRM_AMD_ACP=y +CONFIG_DRM_AMD_DC_HDCP=y +CONFIG_DRM_AMD_DC_SI=y +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y +CONFIG_DRM_AMD_SECURE_DISPLAY=y +CONFIG_DRM_ANALOGIX_ANX6345=m +CONFIG_DRM_ANALOGIX_ANX7625=m +CONFIG_DRM_ANALOGIX_ANX78XX=m +# CONFIG_DRM_ARCPGU is not set +CONFIG_DRM_AST=m +CONFIG_DRM_BOCHS=m +# CONFIG_DRM_CDNS_DSI is not set +# CONFIG_DRM_CDNS_MHDP8546 is not set +CONFIG_DRM_CHIPONE_ICN6211=m +CONFIG_DRM_CHRONTEL_CH7033=m +CONFIG_DRM_CIRRUS_QEMU=m +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_MODESET_LOCK is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_DISPLAY_CONNECTOR=m +# CONFIG_DRM_DISPLAY_DEBUG_DP_TUNNEL_STATE is not set +CONFIG_DRM_DISPLAY_DP_AUX_CEC=y +CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y +# CONFIG_DRM_DISPLAY_DP_TUNNEL_STATE_DEBUG is not set +CONFIG_DRM_DP_AUX_CHARDEV=y +CONFIG_DRM_DP_CEC=y +# CONFIG_DRM_DW_HDMI_AHB_AUDIO is not set +# CONFIG_DRM_DW_HDMI_I2S_AUDIO is not set +# CONFIG_DRM_ETNAVIV is not set +CONFIG_DRM_FBDEV_EMULATION=y +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FSL_LDB is not set +CONFIG_DRM_GM12U320=m +CONFIG_DRM_GUD=m +# CONFIG_DRM_HISI_HIBMC is not set +CONFIG_DRM_HYPERV=m +# CONFIG_DRM_I2C_ADV7511 is not set +CONFIG_DRM_I2C_CH7006=m +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +CONFIG_DRM_I2C_SIL164=m +# CONFIG_DRM_IMX_LCDIF is not set +CONFIG_DRM_ITE_IT6505=m +# CONFIG_DRM_ITE_IT66121 is not set +# CONFIG_DRM_KOMEDA is not set +CONFIG_DRM_KUNIT_TEST=m +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_LOAD_EDID_FIRMWARE=y +# CONFIG_DRM_LOGICVC is not set +CONFIG_DRM_LONTIUM_LT8912B=m +# CONFIG_DRM_LONTIUM_LT9211 is not set +# CONFIG_DRM_LONTIUM_LT9611 is not set +CONFIG_DRM_LONTIUM_LT9611UXC=m +# CONFIG_DRM_LOONGSON is not set +# CONFIG_DRM_LVDS_CODEC is not set +# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set +CONFIG_DRM_MGAG200=m +# CONFIG_DRM_MSM_GPU_SUDO is not set +# CONFIG_DRM_MSM_VALIDATE_XML is not set +# CONFIG_DRM_MXSFB is not set +CONFIG_DRM_NOUVEAU_BACKLIGHT=y +CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y +CONFIG_DRM_NOUVEAU=m +# CONFIG_DRM_NOUVEAU_SVM is not set +# CONFIG_DRM_NWL_MIPI_DSI is not set +# CONFIG_DRM_NXP_PTN3460 is not set +# CONFIG_DRM_PANEL_ABT_Y030XX067A is not set +# CONFIG_DRM_PANEL_ARM_VERSATILE is not set +# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set +# CONFIG_DRM_PANEL_AUO_A030JTN01 is not set +CONFIG_DRM_PANEL_BOE_BF060Y8M_AJ0=m +# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set +# CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A is not set +CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m +CONFIG_DRM_PANEL_BRIDGE=y +CONFIG_DRM_PANEL_DSI_CM=m +# CONFIG_DRM_PANEL_EBBG_FT8719 is not set +# CONFIG_DRM_PANEL_EDP is not set +CONFIG_DRM_PANEL_ELIDA_KD35T133=m +CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m +CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m +# CONFIG_DRM_PANEL_HIMAX_HX83112A is not set +# CONFIG_DRM_PANEL_HIMAX_HX8394 is not set +# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m +# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set +CONFIG_DRM_PANEL_ILITEK_ILI9882T=m +CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m +# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set +CONFIG_DRM_PANEL_JADARD_JD9365DA_H3=m +CONFIG_DRM_PANEL_JDI_LPM102A188A=m +# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set +CONFIG_DRM_PANEL_JDI_R63452=m +# CONFIG_DRM_PANEL_KHADAS_TS050 is not set +# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set +# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set +# CONFIG_DRM_PANEL_LG_LB035Q02 is not set +# CONFIG_DRM_PANEL_LG_LG4573 is not set +# CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m +# CONFIG_DRM_PANEL_LVDS is not set +CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m +CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m +CONFIG_DRM_PANEL_MIPI_DBI=m +# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set +CONFIG_DRM_PANEL_NEWVISION_NV3051D=m +# CONFIG_DRM_PANEL_NEWVISION_NV3052C is not set +CONFIG_DRM_PANEL_NOVATEK_NT35510=m +CONFIG_DRM_PANEL_NOVATEK_NT35560=m +CONFIG_DRM_PANEL_NOVATEK_NT35950=m +# CONFIG_DRM_PANEL_NOVATEK_NT36523 is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672A is not set +# CONFIG_DRM_PANEL_NOVATEK_NT36672E is not set +# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set +# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set +# CONFIG_DRM_PANEL_ORISETECH_OTA5601A is not set +CONFIG_DRM_PANEL_ORISETECH_OTM8009A=m +# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set +# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set +# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set +# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set +CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m +CONFIG_DRM_PANEL_RAYDIUM_RM69380=m +CONFIG_DRM_PANEL_RONBO_RB070D30=m +CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m +CONFIG_DRM_PANEL_SAMSUNG_DB7430=m +# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D27A1 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6D7AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3FA7 is not set +# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03=m +# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set +CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01=m +# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set +# CONFIG_DRM_PANEL_SAMSUNG_SOFEF00 is not set +CONFIG_DRM_PANEL_SEIKO_43WVF1G=m +# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set +# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set +# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set +# CONFIG_DRM_PANEL_SHARP_LS060T1SX01 is not set +# CONFIG_DRM_PANEL_SIMPLE is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set +# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set +# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set +# CONFIG_DRM_PANEL_SONY_TD4353_JDI is not set +CONFIG_DRM_PANEL_SONY_TULIP_TRULY_NT35521=m +CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m +# CONFIG_DRM_PANEL_SYNAPTICS_R63353 is not set +# CONFIG_DRM_PANEL_TDO_TL070WSH30 is not set +# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set +# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set +# CONFIG_DRM_PANEL_TPO_TPG110 is not set +# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set +CONFIG_DRM_PANEL_VISIONOX_R66451=m +CONFIG_DRM_PANEL_VISIONOX_RM69299=m +# CONFIG_DRM_PANEL_VISIONOX_VTDR6130 is not set +CONFIG_DRM_PANEL_WIDECHIPS_WS2401=m +# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set +CONFIG_DRM_PANEL=y +# CONFIG_DRM_PARADE_PS8622 is not set +CONFIG_DRM_PARADE_PS8640=m +CONFIG_DRM_QXL=m +CONFIG_DRM_RADEON=m +CONFIG_DRM_RADEON_USERPTR=y +# CONFIG_DRM_RCAR_DW_HDMI is not set +# CONFIG_DRM_RCAR_LVDS is not set +# CONFIG_DRM_RCAR_MIPI_DSI is not set +# CONFIG_DRM_RCAR_USE_LVDS is not set +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set +CONFIG_DRM_SAMSUNG_DSIM=m +CONFIG_DRM_SII902X=m +CONFIG_DRM_SII9234=m +# CONFIG_DRM_SIL_SII8620 is not set +CONFIG_DRM_SIMPLE_BRIDGE=m +CONFIG_DRM_SIMPLEDRM=y +CONFIG_DRM_SSD130X_I2C=m +CONFIG_DRM_SSD130X=m +CONFIG_DRM_SSD130X_SPI=m +# CONFIG_DRM_THINE_THC63LVD1024 is not set +CONFIG_DRM_TI_DLPC3433=m +# CONFIG_DRM_TIDSS is not set +# CONFIG_DRM_TI_SN65DSI83 is not set +CONFIG_DRM_TI_SN65DSI86=m +CONFIG_DRM_TI_TFP410=m +CONFIG_DRM_TI_TPD12S015=m +CONFIG_DRM_TOSHIBA_TC358762=m +CONFIG_DRM_TOSHIBA_TC358764=m +# CONFIG_DRM_TOSHIBA_TC358767 is not set +CONFIG_DRM_TOSHIBA_TC358768=m +CONFIG_DRM_TOSHIBA_TC358775=m +# CONFIG_DRM_TTM_KUNIT_TEST is not set +CONFIG_DRM_UDL=m +CONFIG_DRM_USE_DYNAMIC_DEBUG=y +# CONFIG_DRM_VBOXVIDEO is not set +CONFIG_DRM_VGEM=m +CONFIG_DRM_VIRTIO_GPU_KMS=y +CONFIG_DRM_VIRTIO_GPU=m +CONFIG_DRM_VKMS=m +CONFIG_DRM_VMWGFX_FBCON=y +CONFIG_DRM_VMWGFX=m +# CONFIG_DRM_VMWGFX_MKSSTATS is not set +CONFIG_DRM_WERROR=y +# CONFIG_DRM_XE_DEBUG is not set +# CONFIG_DRM_XE_DEBUG_MEM is not set +# CONFIG_DRM_XE_DEBUG_SRIOV is not set +# CONFIG_DRM_XE_DEBUG_VM is not set +CONFIG_DRM_XE_DISPLAY=y +CONFIG_DRM_XE_ENABLE_SCHEDTIMEOUT_LIMIT=y +CONFIG_DRM_XE_FORCE_PROBE="" +CONFIG_DRM_XE_JOB_TIMEOUT_MAX=10000 +CONFIG_DRM_XE_JOB_TIMEOUT_MIN=1 +# CONFIG_DRM_XE_KUNIT_TEST is not set +# CONFIG_DRM_XE_LARGE_GUC_BUFFER is not set +CONFIG_DRM_XE=m +# CONFIG_DRM_XEN_FRONTEND is not set +CONFIG_DRM_XE_PREEMPT_TIMEOUT=640000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MAX=10000000 +CONFIG_DRM_XE_PREEMPT_TIMEOUT_MIN=1 +# CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE is not set +CONFIG_DRM_XE_TIMESLICE_MAX=10000000 +CONFIG_DRM_XE_TIMESLICE_MIN=1 +# CONFIG_DRM_XE_USERPTR_INVAL_INJECT is not set +# CONFIG_DRM_XE_WERROR is not set +CONFIG_DRM=y +# CONFIG_DS1682 is not set +# CONFIG_DS1803 is not set +# CONFIG_DS4424 is not set +CONFIG_DTPM_CPU=y +CONFIG_DTPM_DEVFREQ=y +CONFIG_DTPM=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_DUMMY_CONSOLE=y +# CONFIG_DUMMY_IRQ is not set +CONFIG_DUMMY=m +CONFIG_DVB_AS102=m +# CONFIG_DVB_AV7110 is not set +CONFIG_DVB_B2C2_FLEXCOP=m +# CONFIG_DVB_B2C2_FLEXCOP_PCI_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_PCI=m +# CONFIG_DVB_B2C2_FLEXCOP_USB_DEBUG is not set +CONFIG_DVB_B2C2_FLEXCOP_USB=m +CONFIG_DVB_BT8XX=m +CONFIG_DVB_BUDGET_AV=m +CONFIG_DVB_BUDGET_CI=m +CONFIG_DVB_BUDGET_CORE=m +CONFIG_DVB_BUDGET=m +CONFIG_DVB_CORE=m +CONFIG_DVB_CXD2099=m +# CONFIG_DVB_CXD2880 is not set +CONFIG_DVB_DDBRIDGE=m +# CONFIG_DVB_DDBRIDGE_MSIENABLE is not set +# CONFIG_DVB_DEMUX_SECTION_LOSS_LOG is not set +# CONFIG_DVB_DIB9000 is not set +CONFIG_DVB_DM1105=m +# CONFIG_DVB_DUMMY_FE is not set +CONFIG_DVB_DYNAMIC_MINORS=y +CONFIG_DVB_FIREDTV=m +CONFIG_DVB_HOPPER=m +# CONFIG_DVB_LGS8GL5 is not set +# CONFIG_DVB_LNBH29 is not set +CONFIG_DVB_MANTIS=m +CONFIG_DVB_MAX_ADAPTERS=16 +# CONFIG_DVB_MMAP is not set +# CONFIG_DVB_MN88443X is not set +CONFIG_DVB_MN88472=m +CONFIG_DVB_MN88473=m +CONFIG_DVB_NETUP_UNIDVB=m +CONFIG_DVB_NET=y +CONFIG_DVB_NGENE=m +# CONFIG_DVB_PLATFORM_DRIVERS is not set +CONFIG_DVB_PLUTO2=m +CONFIG_DVB_PT1=m +# CONFIG_DVB_PT3 is not set +# CONFIG_DVB_S5H1432 is not set +CONFIG_DVB_SMIPCIE=m +# CONFIG_DVB_TEST_DRIVERS is not set +CONFIG_DVB_TTUSB_BUDGET=m +CONFIG_DVB_TTUSB_DEC=m +# CONFIG_DVB_ULE_DEBUG is not set +CONFIG_DVB_USB_A800=m +CONFIG_DVB_USB_AF9005=m +CONFIG_DVB_USB_AF9005_REMOTE=m +CONFIG_DVB_USB_AF9015=m +CONFIG_DVB_USB_AF9035=m +CONFIG_DVB_USB_ANYSEE=m +CONFIG_DVB_USB_AU6610=m +CONFIG_DVB_USB_AZ6007=m +CONFIG_DVB_USB_AZ6027=m +CONFIG_DVB_USB_CE6230=m +CONFIG_DVB_USB_CINERGY_T2=m +CONFIG_DVB_USB_CXUSB_ANALOG=y +CONFIG_DVB_USB_CXUSB=m +# CONFIG_DVB_USB_DEBUG is not set +CONFIG_DVB_USB_DIB0700=m +# CONFIG_DVB_USB_DIBUSB_MB_FAULTY is not set +CONFIG_DVB_USB_DIBUSB_MB=m +CONFIG_DVB_USB_DIBUSB_MC=m +CONFIG_DVB_USB_DIGITV=m +CONFIG_DVB_USB_DTT200U=m +CONFIG_DVB_USB_DTV5100=m +CONFIG_DVB_USB_DVBSKY=m +CONFIG_DVB_USB_DW2102=m +CONFIG_DVB_USB_EC168=m +CONFIG_DVB_USB_GL861=m +CONFIG_DVB_USB_GP8PSK=m +CONFIG_DVB_USB_LME2510=m +CONFIG_DVB_USB=m +CONFIG_DVB_USB_M920X=m +CONFIG_DVB_USB_MXL111SF=m +CONFIG_DVB_USB_NOVA_T_USB2=m +CONFIG_DVB_USB_OPERA1=m +CONFIG_DVB_USB_PCTV452E=m +CONFIG_DVB_USB_RTL28XXU=m +CONFIG_DVB_USB_TECHNISAT_USB2=m +CONFIG_DVB_USB_TTUSB2=m +CONFIG_DVB_USB_UMT_010=m +CONFIG_DVB_USB_V2=m +CONFIG_DVB_USB_VP702X=m +CONFIG_DVB_USB_VP7045=m +CONFIG_DVB_USB_ZD1301=m +CONFIG_DW_AXI_DMAC=m +CONFIG_DWC_PCIE_PMU=m +CONFIG_DW_DMAC_CORE=m +CONFIG_DW_DMAC=m +CONFIG_DW_DMAC_PCI=m +CONFIG_DW_EDMA=m +CONFIG_DW_EDMA_PCIE=m +CONFIG_DWMAC_DWC_QOS_ETH=m +CONFIG_DWMAC_GENERIC=m +# CONFIG_DWMAC_INTEL_PLAT is not set +# CONFIG_DWMAC_LOONGSON is not set +CONFIG_DWMAC_STARFIVE=m +# CONFIG_DW_WATCHDOG is not set +CONFIG_DW_XDATA_PCIE=m +CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_E1000E=m +CONFIG_E1000=m +CONFIG_E100=m +CONFIG_EARLY_PRINTK_DBGP=y +CONFIG_EARLY_PRINTK_USB_XDBC=y +CONFIG_EARLY_PRINTK=y +# CONFIG_EBC_C384_WDT is not set +CONFIG_ECHO=m +CONFIG_ECRYPT_FS=m +# CONFIG_ECRYPT_FS_MESSAGING is not set +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_DMC520=m +CONFIG_EDAC_GHES=y +CONFIG_EDAC_IGEN6=m +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SIFIVE=y +# CONFIG_EDAC_SYNOPSYS is not set +CONFIG_EDAC=y +CONFIG_EEPROM_93CX6=m +# CONFIG_EEPROM_93XX46 is not set +CONFIG_EEPROM_AT24=m +# CONFIG_EEPROM_AT25 is not set +CONFIG_EEPROM_EE1004=m +CONFIG_EEPROM_IDT_89HPESX=m +CONFIG_EEPROM_MAX6875=m +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +CONFIG_EFI_COCO_SECRET=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y +# CONFIG_EFI_DISABLE_PCI_DMA is not set +# CONFIG_EFI_DISABLE_RUNTIME is not set +CONFIG_EFI_HANDOVER_PROTOCOL=y +CONFIG_EFI_PARTITION=y +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_EFI_RCI2_TABLE is not set +CONFIG_EFI_SECRET=m +CONFIG_EFI_SOFT_RESERVE=y +CONFIG_EFI_STUB=y +CONFIG_EFI_TEST=m +CONFIG_EFIVAR_FS=y +CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y +CONFIG_EFI_VARS_PSTORE=y +CONFIG_EFI=y +CONFIG_EFI_ZBOOT=y +# CONFIG_EFS_FS is not set +CONFIG_ELF_CORE=y +# CONFIG_EMBEDDED is not set +# CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set +CONFIG_ENCLOSURE_SERVICES=m +CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set +CONFIG_ENERGY_MODEL=y +CONFIG_ENIC=m +# CONFIG_ENS160 is not set +CONFIG_ENVELOPE_DETECTOR=m +CONFIG_EPIC100=m +CONFIG_EPOLL=y +CONFIG_EQUALIZER=m +# CONFIG_EROFS_FS_DEBUG is not set +CONFIG_EROFS_FS=m +CONFIG_EROFS_FS_ONDEMAND=y +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set +CONFIG_EROFS_FS_POSIX_ACL=y +CONFIG_EROFS_FS_SECURITY=y +CONFIG_EROFS_FS_XATTR=y +CONFIG_EROFS_FS_ZIP_DEFLATE=y +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +CONFIG_EROFS_FS_ZIP_ZSTD=y +CONFIG_ERRATA_ANDES_CMO=y +CONFIG_ERRATA_ANDES=y +CONFIG_ERRATA_SIFIVE_CIP_1200=y +CONFIG_ERRATA_SIFIVE_CIP_453=y +CONFIG_ERRATA_SIFIVE=y +# CONFIG_ERRATA_STARFIVE_JH7100 is not set +CONFIG_ERRATA_THEAD_CMO=y +CONFIG_ERRATA_THEAD_MAE=y +CONFIG_ERRATA_THEAD_PMU=y +CONFIG_ERRATA_THEAD=y +CONFIG_ET131X=m +CONFIG_ETHERNET=y +CONFIG_ETHOC=m +CONFIG_ETHTOOL_NETLINK=y +# CONFIG_EUROTECH_WDT is not set +# CONFIG_EVM_ADD_XATTRS is not set +CONFIG_EVM_ATTR_FSUUID=y +# CONFIG_EVM_LOAD_X509 is not set +CONFIG_EVM=y +CONFIG_EXFAT_DEFAULT_IOCHARSET="utf8" +CONFIG_EXFAT_FS=m +CONFIG_EXPERT=y +CONFIG_EXPORTFS=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_DEBUG is not set +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_KUNIT_TESTS=m +CONFIG_EXT4_USE_FOR_EXT2=y +# CONFIG_EXTCON_ADC_JACK is not set +# CONFIG_EXTCON_FSA9480 is not set +# CONFIG_EXTCON_GPIO is not set +# CONFIG_EXTCON_MAX3355 is not set +# CONFIG_EXTCON_PTN5150 is not set +# CONFIG_EXTCON_QCOM_SPMI_MISC is not set +# CONFIG_EXTCON_RT8973A is not set +# CONFIG_EXTCON_SM5502 is not set +CONFIG_EXTCON_USBC_TUSB320=m +# CONFIG_EXTCON_USB_GPIO is not set +CONFIG_EXTCON=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_EZX_PCAP is not set +# CONFIG_F2FS_CHECK_FS is not set +# CONFIG_F2FS_FAULT_INJECTION is not set +CONFIG_F2FS_FS_COMPRESSION=y +CONFIG_F2FS_FS_LZ4HC=y +CONFIG_F2FS_FS_LZ4=y +CONFIG_F2FS_FS_LZORLE=y +CONFIG_F2FS_FS_LZO=y +CONFIG_F2FS_FS=m +CONFIG_F2FS_FS_POSIX_ACL=y +CONFIG_F2FS_FS_SECURITY=y +CONFIG_F2FS_FS_XATTR=y +CONFIG_F2FS_FS_ZSTD=y +CONFIG_F2FS_IOSTAT=y +CONFIG_F2FS_STAT_FS=y +CONFIG_F2FS_UNFAIR_RWSEM=y +# CONFIG_FAIL_FUTEX is not set +CONFIG_FAILOVER=m +# CONFIG_FAIL_SUNRPC is not set +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y +CONFIG_FANOTIFY=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_FAT_FS=m +CONFIG_FAT_KUNIT_TEST=m +# CONFIG_FAULT_INJECTION_CONFIGFS is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_FAULT_INJECTION_USERCOPY is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_DA8XX is not set +# CONFIG_FB_DEVICE is not set +CONFIG_FB_EFI=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_GEODE is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_HYPERV is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_I810 is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_IMX is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_MATROX_G is not set +# CONFIG_FB_MATROX_I2C is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_MATROX_MILLENIUM is not set +# CONFIG_FB_MATROX_MYSTIQUE is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_METRONOME is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_OF is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +CONFIG_FB_SIMPLE=y +# CONFIG_FB_SIS is not set +# CONFIG_FB_SM501 is not set +# CONFIG_FB_SM712 is not set +# CONFIG_FB_SM750 is not set +# CONFIG_FB_SMSCUFX is not set +CONFIG_FB_SSD1307=m +# CONFIG_FB_TFT is not set +CONFIG_FB_TILEBLITTING=y +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_UVESA is not set +CONFIG_FB_VESA=y +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_XILINX is not set +CONFIG_FB=y +CONFIG_FCOE=m +# CONFIG_FDDI is not set +CONFIG_FEALNX=m +CONFIG_FHANDLE=y +# CONFIG_FIELDBUS_DEV is not set +CONFIG_FILE_LOCKING=y +# CONFIG_FIND_BIT_BENCHMARK is not set +# CONFIG_FIPS_SIGNATURE_SELFTEST is not set +# CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FIRMWARE_MEMMAP is not set +CONFIG_FIXED_PHY=y +# CONFIG_FLATMEM_MANUAL is not set +CONFIG_FM10K=m +# CONFIG_FONTS is not set +CONFIG_FORCEDETH=m +# CONFIG_FORCE_NR_CPUS is not set +CONFIG_FORTIFY_KUNIT_TEST=m +CONFIG_FORTIFY_SOURCE=y +CONFIG_FPGA_BRIDGE=m +CONFIG_FPGA_DFL_AFU=m +CONFIG_FPGA_DFL_EMIF=m +CONFIG_FPGA_DFL_FME_BRIDGE=m +CONFIG_FPGA_DFL_FME=m +CONFIG_FPGA_DFL_FME_MGR=m +CONFIG_FPGA_DFL_FME_REGION=m +CONFIG_FPGA_DFL=m +CONFIG_FPGA_DFL_NIOS_INTEL_PAC_N3000=m +CONFIG_FPGA_DFL_PCI=m +CONFIG_FPGA=m +CONFIG_FPGA_M10_BMC_SEC_UPDATE=m +CONFIG_FPGA_MGR_ALTERA_CVP=m +CONFIG_FPGA_MGR_ALTERA_PS_SPI=m +CONFIG_FPGA_MGR_ICE40_SPI=m +CONFIG_FPGA_MGR_LATTICE_SYSCONFIG_SPI=m +CONFIG_FPGA_MGR_MACHXO2_SPI=m +# CONFIG_FPGA_MGR_MICROCHIP_SPI is not set +CONFIG_FPGA_MGR_XILINX_SELECTMAP=m +CONFIG_FPGA_MGR_XILINX_SPI=m +CONFIG_FPGA_MGR_ZYNQ_FPGA=m +CONFIG_FPGA_REGION=m +CONFIG_FPROBE_EVENTS=y +CONFIG_FPROBE=y +CONFIG_FPU=y +CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_LEGACY_ACCELERATION is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAME_POINTER=y +CONFIG_FRAME_WARN=2048 +CONFIG_FRONTSWAP=y +CONFIG_FSCACHE_STATS=y +CONFIG_FSCACHE=y +CONFIG_FS_DAX=y +CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y +CONFIG_FS_ENCRYPTION=y +# CONFIG_FSI is not set +# CONFIG_FSL_EDMA is not set +# CONFIG_FSL_ENETC_IERB is not set +# CONFIG_FSL_ENETC is not set +# CONFIG_FSL_ENETC_MDIO is not set +# CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_PQ_MDIO is not set +# CONFIG_FSL_QDMA is not set +# CONFIG_FSL_RCPM is not set +CONFIG_FS_MBCACHE=y +CONFIG_FSNOTIFY=y +CONFIG_FS_PID=y +# CONFIG_FS_VERITY_BUILTIN_SIGNATURES is not set +# CONFIG_FS_VERITY_DEBUG is not set +CONFIG_FS_VERITY=y +# CONFIG_FTL is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_SORT_STARTUP_TEST is not set +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_FTRACE_SYSCALLS=y +# CONFIG_FTRACE_VALIDATE_RCU_IS_WATCHING is not set +CONFIG_FTRACE=y +CONFIG_FUEL_GAUGE_MM8013=m +# CONFIG_FUJITSU_ES is not set +# CONFIG_FUNCTION_ERROR_INJECTION is not set +CONFIG_FUNCTION_GRAPH_RETVAL=y +CONFIG_FUNCTION_GRAPH_TRACER=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUN_ETH=m +CONFIG_FUSE_DAX=y +CONFIG_FUSE_FS=m +CONFIG_FUSE_PASSTHROUGH=y +CONFIG_FUSION_CTL=m +CONFIG_FUSION_FC=m +CONFIG_FUSION_LAN=m +CONFIG_FUSION_LOGGING=y +CONFIG_FUSION_MAX_SGE=128 +CONFIG_FUSION_SAS=m +CONFIG_FUSION_SPI=m +CONFIG_FUSION=y +CONFIG_FUTEX=y +CONFIG_FW_CACHE=y +# CONFIG_FW_CFG_SYSFS_CMDLINE is not set +CONFIG_FW_CFG_SYSFS=m +# CONFIG_FW_DEVLINK_SYNC_STATE_TIMEOUT is not set +CONFIG_FW_LOADER_COMPRESS_XZ=y +CONFIG_FW_LOADER_COMPRESS=y +CONFIG_FW_LOADER_COMPRESS_ZSTD=y +CONFIG_FW_LOADER_DEBUG=y +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_FW_LOADER_USER_HELPER=y +CONFIG_FW_LOADER=y +CONFIG_FW_UPLOAD=y +CONFIG_FXAS21002C=m +# CONFIG_FXLS8962AF_I2C is not set +# CONFIG_FXLS8962AF_SPI is not set +CONFIG_FXOS8700_I2C=m +CONFIG_FXOS8700_SPI=m +CONFIG_GACT_PROB=y +CONFIG_GAMEPORT_EMU10K1=m +CONFIG_GAMEPORT_FM801=m +CONFIG_GAMEPORT_L4=m +CONFIG_GAMEPORT=m +CONFIG_GAMEPORT_NS558=m +# CONFIG_GCC_PLUGIN_LATENT_ENTROPY is not set +# CONFIG_GCC_PLUGIN_RANDSTRUCT is not set +# CONFIG_GCC_PLUGINS is not set +# CONFIG_GCC_PLUGIN_STACKLEAK is not set +# CONFIG_GCOV_KERNEL is not set +# CONFIG_GDB_SCRIPTS is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_GENERIC_ADC_THERMAL is not set +# CONFIG_GENERIC_CPU is not set +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +CONFIG_GENERIC_PHY=y +CONFIG_GENEVE=m +# CONFIG_GEN_RTC is not set +# CONFIG_GENWQE is not set +CONFIG_GFS2_FS_LOCKING_DLM=y +CONFIG_GFS2_FS=m +# CONFIG_GIGABYTE_WMI is not set +# CONFIG_GLOB_SELFTEST is not set +CONFIG_GNSS=m +CONFIG_GNSS_MTK_SERIAL=m +CONFIG_GNSS_SIRF_SERIAL=m +CONFIG_GNSS_UBX_SERIAL=m +CONFIG_GNSS_USB=m +# CONFIG_GOLDFISH_AUDIO is not set +# CONFIG_GOLDFISH_PIPE is not set +# CONFIG_GOLDFISH_TTY is not set +CONFIG_GOLDFISH=y +# CONFIG_GOOGLE_FIRMWARE is not set +CONFIG_GP2AP002=m +# CONFIG_GP2AP020A00F is not set +# CONFIG_GPIO_74X164 is not set +# CONFIG_GPIO_74XX_MMIO is not set +# CONFIG_GPIO_ADNP is not set +# CONFIG_GPIO_ADP5588 is not set +CONFIG_GPIO_AGGREGATOR=m +# CONFIG_GPIO_ALTERA is not set +# CONFIG_GPIO_AMD_FCH is not set +# CONFIG_GPIO_AMDPT is not set +# CONFIG_GPIO_BCM_XGS_IPROC is not set +CONFIG_GPIO_BD9571MWV=m +CONFIG_GPIO_BT8XX=m +CONFIG_GPIO_CADENCE=m +CONFIG_GPIO_CDEV_V1=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_CROS_EC=m +CONFIG_GPIO_DLN2=m +CONFIG_GPIO_DS4520=m +# CONFIG_GPIO_DWAPB is not set +CONFIG_GPIO_EXAR=m +# CONFIG_GPIO_FTGPIO010 is not set +CONFIG_GPIO_FXL6408=m +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_GRGPIO is not set +# CONFIG_GPIO_GW_PLD is not set +# CONFIG_GPIO_HLWD is not set +# CONFIG_GPIO_IT87 is not set +# CONFIG_GPIO_LATCH is not set +CONFIG_GPIOLIB_FASTPATH_LIMIT=512 +CONFIG_GPIOLIB=y +# CONFIG_GPIO_LOGICVC is not set +# CONFIG_GPIO_MAX3191X is not set +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MAX732X is not set +CONFIG_GPIO_MAX77650=m +# CONFIG_GPIO_MB86S7X is not set +# CONFIG_GPIO_MC33880 is not set +CONFIG_GPIO_MLXBF2=m +# CONFIG_GPIO_MOCKUP is not set +CONFIG_GPIO_MXC=m +# CONFIG_GPIO_PCA953X_IRQ is not set +CONFIG_GPIO_PCA953X=m +# CONFIG_GPIO_PCA9570 is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_PCH is not set +# CONFIG_GPIO_PCIE_IDIO_24 is not set +CONFIG_GPIO_PCI_IDIO_16=m +# CONFIG_GPIO_PISOSR is not set +# CONFIG_GPIO_PL061 is not set +# CONFIG_GPIO_RDC321X is not set +# CONFIG_GPIO_SAMA5D2_PIOBU is not set +# CONFIG_GPIO_SCH311X is not set +CONFIG_GPIO_SIFIVE=y +CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set +CONFIG_GPIO_SYSCON=m +# CONFIG_GPIO_SYSFS is not set +# CONFIG_GPIO_TPIC2810 is not set +CONFIG_GPIO_TPS65219=m +# CONFIG_GPIO_TS4900 is not set +# CONFIG_GPIO_VIPERBOARD is not set +CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m +# CONFIG_GPIO_WATCHDOG is not set +# CONFIG_GPIO_WINBOND is not set +CONFIG_GPIO_WM8994=m +# CONFIG_GPIO_WS16C48 is not set +# CONFIG_GPIO_XILINX is not set +# CONFIG_GPIO_XRA1403 is not set +CONFIG_GP_PCI1XXXX=m +CONFIG_GREENASIA_FF=y +# CONFIG_GREYBUS is not set +# CONFIG_GS_FPGABOOT is not set +CONFIG_GTP=m +# CONFIG_GUP_TEST is not set +CONFIG_GVE=m +# CONFIG_HABANA_AI is not set +CONFIG_HAMACHI=m +CONFIG_HAMRADIO=y +CONFIG_HANGCHECK_TIMER=m +CONFIG_HAPPYMEAL=m +CONFIG_HARDENED_USERCOPY=y +# CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY is not set +CONFIG_HARDLOCKUP_DETECTOR=y +CONFIG_HASH_KUNIT_TEST=m +CONFIG_HASHTABLE_KUNIT_TEST=m +CONFIG_HD44780=m +# CONFIG_HDC100X is not set +CONFIG_HDC2010=m +# CONFIG_HDC3020 is not set +CONFIG_HEADERS_INSTALL=y +CONFIG_HFS_FS=m +CONFIG_HFSPLUS_FS=m +CONFIG_HI6421V600_IRQ=m +# CONFIG_HI8435 is not set +# CONFIG_HIBERNATION_COMP_LZ4 is not set +CONFIG_HIBERNATION_COMP_LZO=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y +CONFIG_HIBERNATION=y +CONFIG_HID_A4TECH=m +CONFIG_HID_ACCUTOUCH=m +CONFIG_HID_ACRUX_FF=y +CONFIG_HID_ACRUX=m +CONFIG_HID_ALPS=m +CONFIG_HID_APPLEIR=m +CONFIG_HID_APPLE=m +# CONFIG_HID_ASUS is not set +CONFIG_HID_AUREAL=m +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HID_BELKIN=m +CONFIG_HID_BETOP_FF=m +CONFIG_HID_BIGBEN_FF=m +CONFIG_HID_BPF=y +CONFIG_HID_CHERRY=m +CONFIG_HID_CHICONY=m +CONFIG_HID_CMEDIA=m +CONFIG_HID_CORSAIR=m +CONFIG_HID_COUGAR=m +CONFIG_HID_CP2112=m +CONFIG_HID_CREATIVE_SB0540=m +CONFIG_HID_CYPRESS=m +CONFIG_HID_DRAGONRISE=m +CONFIG_HID_ELAN=m +CONFIG_HID_ELECOM=m +CONFIG_HID_ELO=m +CONFIG_HID_EMS_FF=m +CONFIG_HID_EVISION=m +CONFIG_HID_EZKEY=m +CONFIG_HID_FT260=m +CONFIG_HID_GEMBIRD=m +CONFIG_HID_GENERIC=y +CONFIG_HID_GFRM=m +CONFIG_HID_GLORIOUS=m +# CONFIG_HID_GOOGLE_HAMMER is not set +CONFIG_HID_GOOGLE_STADIA_FF=m +CONFIG_HID_GREENASIA=m +CONFIG_HID_GT683R=m +CONFIG_HID_GYRATION=m +CONFIG_HID_HOLTEK=m +CONFIG_HID_HYPERV_MOUSE=m +CONFIG_HID_ICADE=m +CONFIG_HID_ITE=m +CONFIG_HID_JABRA=m +CONFIG_HID_KENSINGTON=m +CONFIG_HID_KEYTOUCH=m +CONFIG_HID_KUNIT_TEST=m +CONFIG_HID_KYE=m +CONFIG_HID_LCPOWER=m +CONFIG_HID_LED=m +CONFIG_HID_LENOVO=m +CONFIG_HID_LETSKETCH=m +CONFIG_HID_LOGITECH_DJ=m +CONFIG_HID_LOGITECH_HIDPP=m +CONFIG_HID_LOGITECH=m +CONFIG_HID_MACALLY=m +CONFIG_HID_MAGICMOUSE=y +CONFIG_HID_MALTRON=m +CONFIG_HID_MAYFLASH=m +# CONFIG_HID_MCP2200 is not set +CONFIG_HID_MCP2221=m +CONFIG_HID_MEGAWORLD_FF=m +CONFIG_HID_MICROSOFT=m +CONFIG_HID_MONTEREY=m +CONFIG_HID_MULTITOUCH=m +CONFIG_HID_NINTENDO=m +CONFIG_HID_NTI=m +CONFIG_HID_NTRIG=y +CONFIG_HID_NVIDIA_SHIELD=m +CONFIG_HID_ORTEK=m +CONFIG_HID_PANTHERLORD=m +CONFIG_HID_PENMOUNT=m +CONFIG_HID_PETALYNX=m +CONFIG_HID_PICOLCD_BACKLIGHT=y +CONFIG_HID_PICOLCD_CIR=y +CONFIG_HID_PICOLCD_FB=y +CONFIG_HID_PICOLCD_LCD=y +CONFIG_HID_PICOLCD_LEDS=y +CONFIG_HID_PICOLCD=m +CONFIG_HID_PID=y +CONFIG_HID_PLANTRONICS=m +CONFIG_HID_PLAYSTATION=m +CONFIG_HID_PRIMAX=m +CONFIG_HID_PRODIKEYS=m +CONFIG_HID_PXRC=m +CONFIG_HIDRAW=y +CONFIG_HID_RAZER=m +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_RETRODE=m +CONFIG_HID_RMI=m +CONFIG_HID_ROCCAT=m +CONFIG_HID_SAITEK=m +CONFIG_HID_SAMSUNG=m +CONFIG_HID_SEMITEK=m +CONFIG_HID_SENSOR_ACCEL_3D=m +CONFIG_HID_SENSOR_ALS=m +CONFIG_HID_SENSOR_CUSTOM_INTEL_HINGE=m +# CONFIG_HID_SENSOR_CUSTOM_SENSOR is not set +CONFIG_HID_SENSOR_DEVICE_ROTATION=m +CONFIG_HID_SENSOR_GYRO_3D=m +CONFIG_HID_SENSOR_HUB=m +CONFIG_HID_SENSOR_HUMIDITY=m +CONFIG_HID_SENSOR_IIO_COMMON=m +CONFIG_HID_SENSOR_IIO_TRIGGER=m +CONFIG_HID_SENSOR_INCLINOMETER_3D=m +CONFIG_HID_SENSOR_MAGNETOMETER_3D=m +# CONFIG_HID_SENSOR_PRESS is not set +# CONFIG_HID_SENSOR_PROX is not set +CONFIG_HID_SENSOR_TEMP=m +CONFIG_HID_SIGMAMICRO=m +CONFIG_HID_SMARTJOYPLUS=m +CONFIG_HID_SONY=m +CONFIG_HID_SPEEDLINK=m +CONFIG_HID_STEAM=m +CONFIG_HID_STEELSERIES=m +CONFIG_HID_SUNPLUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID_THINGM=m +CONFIG_HID_THRUSTMASTER=m +CONFIG_HID_TIVO=m +CONFIG_HID_TOPRE=m +CONFIG_HID_TOPSEED=m +CONFIG_HID_TWINHAN=m +CONFIG_HID_U2FZERO=m +CONFIG_HID_UCLOGIC=m +CONFIG_HID_UDRAW_PS3=m +CONFIG_HID_VIEWSONIC=m +CONFIG_HID_VIVALDI=m +# CONFIG_HID_VRC2 is not set +CONFIG_HID_WACOM=m +CONFIG_HID_WALTOP=m +CONFIG_HID_WIIMOTE=m +CONFIG_HID_WINWING=m +CONFIG_HID_XIAOMI=m +CONFIG_HID_XINMO=m +CONFIG_HID=y +CONFIG_HID_ZEROPLUS=m +CONFIG_HID_ZYDACRON=m +CONFIG_HIGH_RES_TIMERS=y +# CONFIG_HIPPI is not set +# CONFIG_HISI_DMA is not set +CONFIG_HISI_HIKEY_USB=m +# CONFIG_HISI_PCIE_PMU is not set +# CONFIG_HIST_TRIGGERS_DEBUG is not set +CONFIG_HIST_TRIGGERS=y +CONFIG_HMC425=m +# CONFIG_HMC6352 is not set +CONFIG_HOLTEK_FF=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HOTPLUG_PCI_ACPI_IBM=m +CONFIG_HOTPLUG_PCI_ACPI=y +# CONFIG_HOTPLUG_PCI_CPCI is not set +CONFIG_HOTPLUG_PCI_PCIE=y +# CONFIG_HOTPLUG_PCI_SHPC is not set +CONFIG_HOTPLUG_PCI=y +# CONFIG_HP03 is not set +# CONFIG_HP206C is not set +# CONFIG_HPFS_FS is not set +# CONFIG_HP_ILO is not set +CONFIG_HSA_AMD_SVM=y +CONFIG_HSA_AMD=y +# CONFIG_HSC030PA is not set +# CONFIG_HSI is not set +CONFIG_HSR=m +# CONFIG_HSU_DMA is not set +CONFIG_HT16K33=m +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTE is not set +CONFIG_HTS221=m +# CONFIG_HTU21 is not set +CONFIG_HUGETLBFS=y +# CONFIG_HUGETLB_PAGE_FREE_VMEMMAP_DEFAULT_ON is not set +# CONFIG_HUGETLB_PAGE_OPTIMIZE_VMEMMAP_DEFAULT_ON is not set +CONFIG_HUGETLB_PAGE=y +# CONFIG_HVC_RISCV_SBI is not set +CONFIG_HW_CONSOLE=y +CONFIG_HWLAT_TRACER=y +# CONFIG_HWMON_DEBUG_CHIP is not set +CONFIG_HWMON=y +CONFIG_HWPOISON_INJECT=m +CONFIG_HW_RANDOM_ARM_SMCCC_TRNG=y +# CONFIG_HW_RANDOM_BA431 is not set +# CONFIG_HW_RANDOM_CCTRNG is not set +CONFIG_HW_RANDOM_JH7110=y +CONFIG_HW_RANDOM_TIMERIOMEM=m +CONFIG_HW_RANDOM_TPM=y +CONFIG_HW_RANDOM_VIRTIO=y +CONFIG_HW_RANDOM_XIPHERA=m +CONFIG_HW_RANDOM=y +CONFIG_HWSPINLOCK=y +# CONFIG_HX711 is not set +CONFIG_HYPERV_BALLOON=m +CONFIG_HYPERV_IOMMU=y +CONFIG_HYPERV_KEYBOARD=m +CONFIG_HYPERV=m +CONFIG_HYPERV_NET=m +CONFIG_HYPERV_STORAGE=m +# CONFIG_HYPERV_TESTING is not set +CONFIG_HYPERV_UTILS=m +CONFIG_HYPERV_VSOCKETS=m +CONFIG_HZ_1000=y +# CONFIG_HZ_100 is not set +# CONFIG_HZ_200 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_300 is not set +# CONFIG_HZ_500 is not set +# CONFIG_HZ_PERIODIC is not set +CONFIG_I2C_ALGOBIT=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_ALGOPCF=m +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD756_S4882 is not set +# CONFIG_I2C_AMD8111 is not set +CONFIG_I2C_AMD_MP2=m +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_ATR=m +# CONFIG_I2C_CADENCE is not set +# CONFIG_I2C_CBUS_GPIO is not set +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_COMPAT=y +CONFIG_I2C_CP2615=m +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEMUX_PINCTRL is not set +CONFIG_I2C_DESIGNWARE_PCI=m +CONFIG_I2C_DESIGNWARE_PLATFORM=y +CONFIG_I2C_DESIGNWARE_SLAVE=y +CONFIG_I2C_DIOLAN_U2C=m +CONFIG_I2C_DLN2=m +# CONFIG_I2C_EG20T is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_FSI is not set +# CONFIG_I2C_GPIO is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_HID_ACPI=m +CONFIG_I2C_HID_OF_ELAN=m +# CONFIG_I2C_HID_OF_GOODIX is not set +# CONFIG_I2C_HID_OF is not set +CONFIG_I2C_HID=y +# CONFIG_I2C_HISI is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_MICROCHIP_CORE is not set +CONFIG_I2C_MLXBF=m +CONFIG_I2C_MLXCPLD=m +# CONFIG_I2C_MUX_GPIO is not set +CONFIG_I2C_MUX_GPMUX=m +CONFIG_I2C_MUX_LTC4306=m +CONFIG_I2C_MUX=m +CONFIG_I2C_MUX_MLXCPLD=m +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_MUX_REG is not set +CONFIG_I2C_NFORCE2=m +# CONFIG_I2C_NFORCE2_S4985 is not set +# CONFIG_I2C_NOMADIK is not set +CONFIG_I2C_NVIDIA_GPU=m +CONFIG_I2C_OCORES=y +CONFIG_I2C_PCA_PLATFORM=m +CONFIG_I2C_PCI1XXXX=m +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_QCOM_CCI is not set +# CONFIG_I2C_RK3X is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +CONFIG_I2C_SCMI=m +CONFIG_I2C_SI470X=m +# CONFIG_I2C_SI4713 is not set +CONFIG_I2C_SIMTEC=m +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +CONFIG_I2C_SLAVE_EEPROM=m +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SLAVE=y +CONFIG_I2C_SMBUS=m +CONFIG_I2C_STUB=m +# CONFIG_I2C_TAOS_EVM is not set +CONFIG_I2C_TINY_USB=m +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set +# CONFIG_I2C_VIPERBOARD is not set +CONFIG_I2C_VIRTIO=m +# CONFIG_I2C_XILINX is not set +CONFIG_I2C=y +CONFIG_I2C_ZHAOXIN=m +# CONFIG_I3C is not set +# CONFIG_I40E_DCB is not set +CONFIG_I40E=m +CONFIG_I40EVF=m +CONFIG_I6300ESB_WDT=m +# CONFIG_I8K is not set +# CONFIG_IAQCORE is not set +CONFIG_ICE_HWMON=y +CONFIG_ICE_HWTS=y +CONFIG_ICE=m +CONFIG_ICE_SWITCHDEV=y +CONFIG_ICP10100=m +CONFIG_ICPLUS_PHY=m +# CONFIG_ICS932S401 is not set +# CONFIG_IDLE_INJECT is not set +CONFIG_IDLE_PAGE_TRACKING=y +CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y +CONFIG_IEEE802154_6LOWPAN=m +CONFIG_IEEE802154_ADF7242=m +# CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set +CONFIG_IEEE802154_AT86RF230=m +CONFIG_IEEE802154_ATUSB=m +# CONFIG_IEEE802154_CA8210_DEBUGFS is not set +CONFIG_IEEE802154_CA8210=m +CONFIG_IEEE802154_CC2520=m +CONFIG_IEEE802154_DRIVERS=m +CONFIG_IEEE802154_FAKELB=m +# CONFIG_IEEE802154_HWSIM is not set +CONFIG_IEEE802154=m +CONFIG_IEEE802154_MCR20A=m +CONFIG_IEEE802154_MRF24J40=m +# CONFIG_IEEE802154_NL802154_EXPERIMENTAL is not set +CONFIG_IEEE802154_SOCKET=m +CONFIG_IFB=m +CONFIG_IFCVF=m +CONFIG_IGB_DCA=y +CONFIG_IGB_HWMON=y +CONFIG_IGB=m +CONFIG_IGBVF=m +CONFIG_IGC=m +CONFIG_IIO_BUFFER_CB=m +CONFIG_IIO_BUFFER_DMAENGINE=m +CONFIG_IIO_BUFFER_DMA=m +CONFIG_IIO_BUFFER_HW_CONSUMER=m +CONFIG_IIO_BUFFER=y +CONFIG_IIO_CONFIGFS=m +CONFIG_IIO_CONSUMERS_PER_TRIGGER=2 +CONFIG_IIO_CROS_EC_ACCEL_LEGACY=m +CONFIG_IIO_CROS_EC_SENSORS_LID_ANGLE=m +CONFIG_IIO_FORMAT_KUNIT_TEST=m +CONFIG_IIO_GTS_KUNIT_TEST=m +# CONFIG_IIO_HRTIMER_TRIGGER is not set +CONFIG_IIO_INTERRUPT_TRIGGER=m +CONFIG_IIO_KFIFO_BUF=m +CONFIG_IIO_KX022A_I2C=m +CONFIG_IIO_KX022A_SPI=m +CONFIG_IIO=m +CONFIG_IIO_MUX=m +CONFIG_IIO_RESCALE_KUNIT_TEST=m +CONFIG_IIO_RESCALE=m +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_IIO_SSP_SENSORHUB is not set +CONFIG_IIO_ST_ACCEL_3AXIS=m +CONFIG_IIO_ST_ACCEL_I2C_3AXIS=m +CONFIG_IIO_ST_ACCEL_SPI_3AXIS=m +CONFIG_IIO_ST_GYRO_3AXIS=m +CONFIG_IIO_ST_GYRO_I2C_3AXIS=m +CONFIG_IIO_ST_GYRO_SPI_3AXIS=m +CONFIG_IIO_ST_LSM6DSX=m +# CONFIG_IIO_ST_LSM9DS0 is not set +CONFIG_IIO_ST_MAGN_3AXIS=m +CONFIG_IIO_ST_MAGN_I2C_3AXIS=m +CONFIG_IIO_ST_MAGN_SPI_3AXIS=m +# CONFIG_IIO_ST_PRESS is not set +CONFIG_IIO_SW_DEVICE=m +CONFIG_IIO_SW_TRIGGER=m +# CONFIG_IIO_SYSFS_TRIGGER is not set +CONFIG_IIO_TIGHTLOOP_TRIGGER=m +CONFIG_IIO_TRIGGERED_BUFFER=m +CONFIG_IIO_TRIGGERED_EVENT=m +CONFIG_IIO_TRIGGER=y +# CONFIG_IKCONFIG is not set +CONFIG_IKHEADERS=m +CONFIG_IMA_APPRAISE_BOOTPARAM=y +# CONFIG_IMA_APPRAISE_BUILD_POLICY is not set +CONFIG_IMA_APPRAISE_MODSIG=y +CONFIG_IMA_APPRAISE=y +CONFIG_IMA_ARCH_POLICY=y +# CONFIG_IMA_BLACKLIST_KEYRING is not set +# CONFIG_IMA_DEFAULT_HASH_SHA1 is not set +CONFIG_IMA_DEFAULT_HASH="sha256" +CONFIG_IMA_DEFAULT_HASH_SHA256=y +# CONFIG_IMA_DEFAULT_HASH_SHA512 is not set +# CONFIG_IMA_DISABLE_HTABLE is not set +CONFIG_IMA_KEXEC=y +CONFIG_IMA_KEYRINGS_PERMIT_SIGNED_BY_BUILTIN_OR_SECONDARY=y +# CONFIG_IMA_LOAD_X509 is not set +CONFIG_IMA_LSM_RULES=y +CONFIG_IMA_MEASURE_PCR_IDX=10 +CONFIG_IMA_NG_TEMPLATE=y +CONFIG_IMA_READ_POLICY=y +# CONFIG_IMA_SIG_TEMPLATE is not set +# CONFIG_IMA_TEMPLATE is not set +CONFIG_IMA_WRITE_POLICY=y +CONFIG_IMA=y +# CONFIG_IMG_ASCII_LCD is not set +# CONFIG_INA2XX_ADC is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESPINTCP=y +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_INET_AH=m +CONFIG_INET_DIAG_DESTROY=y +CONFIG_INET_DIAG=y +CONFIG_INET_ESPINTCP=y +CONFIG_INET_ESP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_MPTCP_DIAG=y +CONFIG_INET_RAW_DIAG=y +CONFIG_INET_TABLE_PERTURB_ORDER=16 +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_TUNNEL=m +CONFIG_INET_UDP_DIAG=y +CONFIG_INET=y +CONFIG_INFINIBAND_ADDR_TRANS=y +# CONFIG_INFINIBAND_BNXT_RE is not set +CONFIG_INFINIBAND_CXGB4=m +CONFIG_INFINIBAND_EFA=m +CONFIG_INFINIBAND_ERDMA=m +CONFIG_INFINIBAND_IPOIB_CM=y +CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y +CONFIG_INFINIBAND_IPOIB_DEBUG=y +CONFIG_INFINIBAND_IPOIB=m +CONFIG_INFINIBAND_IRDMA=m +CONFIG_INFINIBAND_ISER=m +CONFIG_INFINIBAND_ISERT=m +CONFIG_INFINIBAND=m +CONFIG_INFINIBAND_MTHCA_DEBUG=y +CONFIG_INFINIBAND_MTHCA=m +CONFIG_INFINIBAND_OCRDMA=m +CONFIG_INFINIBAND_ON_DEMAND_PAGING=y +CONFIG_INFINIBAND_QEDR=m +CONFIG_INFINIBAND_QIB_DCA=y +CONFIG_INFINIBAND_QIB=m +CONFIG_INFINIBAND_RDMAVT=m +CONFIG_INFINIBAND_RTRS_CLIENT=m +CONFIG_INFINIBAND_RTRS_SERVER=m +CONFIG_INFINIBAND_SRP=m +CONFIG_INFINIBAND_SRPT=m +CONFIG_INFINIBAND_USER_ACCESS=m +CONFIG_INFINIBAND_USER_MAD=m +CONFIG_INFINIBAND_USNIC=m +# CONFIG_INFINIBAND_VMWARE_PVRDMA is not set +# CONFIG_INFTL is not set +# CONFIG_INIT_MLOCKED_ON_FREE_DEFAULT_ON is not set +CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# CONFIG_INITRAMFS_PRESERVE_MTIME is not set +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_INIT_STACK_ALL_PATTERN is not set +CONFIG_INIT_STACK_ALL_ZERO=y +# CONFIG_INIT_STACK_NONE is not set +CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_ADXL34X is not set +CONFIG_INPUT_APANEL=m +CONFIG_INPUT_ATI_REMOTE2=m +CONFIG_INPUT_ATLAS_BTNS=m +# CONFIG_INPUT_ATMEL_CAPTOUCH is not set +CONFIG_INPUT_AXP20X_PEK=m +# CONFIG_INPUT_BMA150 is not set +CONFIG_INPUT_CM109=m +CONFIG_INPUT_CMA3000_I2C=m +CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m +# CONFIG_INPUT_DA7280_HAPTICS is not set +CONFIG_INPUT_DA9063_ONKEY=m +# CONFIG_INPUT_DRV260X_HAPTICS is not set +# CONFIG_INPUT_DRV2665_HAPTICS is not set +# CONFIG_INPUT_DRV2667_HAPTICS is not set +CONFIG_INPUT_E3X0_BUTTON=m +# CONFIG_INPUT_EVBUG is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_FF_MEMLESS=m +# CONFIG_INPUT_GPIO_BEEPER is not set +# CONFIG_INPUT_GPIO_DECODER is not set +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m +CONFIG_INPUT_GPIO_VIBRA=m +# CONFIG_INPUT_IBM_PANEL is not set +CONFIG_INPUT_IDEAPAD_SLIDEBAR=m +# CONFIG_INPUT_IMS_PCU is not set +CONFIG_INPUT_IQS269A=m +CONFIG_INPUT_IQS626A=m +CONFIG_INPUT_IQS7222=m +CONFIG_INPUT_JOYDEV=m +CONFIG_INPUT_JOYSTICK=y +CONFIG_INPUT_KEYBOARD=y +CONFIG_INPUT_KEYSPAN_REMOTE=m +CONFIG_INPUT_KUNIT_TEST=m +CONFIG_INPUT_KXTJ9=m +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_MATRIXKMAP=m +CONFIG_INPUT_MAX77650_ONKEY=m +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSE=y +# CONFIG_INPUT_PCF8574 is not set +CONFIG_INPUT_PCSPKR=m +CONFIG_INPUT_PM8XXX_VIBRATOR=m +CONFIG_INPUT_PMIC8XXX_PWRKEY=m +CONFIG_INPUT_POWERMATE=m +CONFIG_INPUT_PWM_BEEPER=m +# CONFIG_INPUT_PWM_VIBRA is not set +CONFIG_INPUT_REGULATOR_HAPTIC=m +CONFIG_INPUT_RK805_PWRKEY=m +CONFIG_INPUT_RT5120_PWRKEY=m +CONFIG_INPUT_SPARSEKMAP=m +CONFIG_INPUT_TABLET=y +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_INPUT_UINPUT=m +CONFIG_INPUT_WISTRON_BTNS=m +CONFIG_INPUT=y +CONFIG_INPUT_YEALINK=m +CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y +CONFIG_INTEGRITY_AUDIT=y +CONFIG_INTEGRITY_CA_MACHINE_KEYRING_MAX=y +CONFIG_INTEGRITY_CA_MACHINE_KEYRING=y +CONFIG_INTEGRITY_MACHINE_KEYRING=y +CONFIG_INTEGRITY_PLATFORM_KEYRING=y +CONFIG_INTEGRITY_SIGNATURE=y +CONFIG_INTEGRITY_TRUSTED_KEYRING=y +CONFIG_INTEGRITY=y +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD_COMPAT is not set +CONFIG_INTEL_IDXD=m +# CONFIG_INTEL_IDXD_PERFMON is not set +# CONFIG_INTEL_IOMMU_DEBUGFS is not set +# CONFIG_INTEL_ISHTP_ECLITE is not set +# CONFIG_INTEL_LDMA is not set +# CONFIG_INTEL_MEI_PXP is not set +# CONFIG_INTEL_PMT_CLASS is not set +# CONFIG_INTEL_PMT_CRASHLOG is not set +# CONFIG_INTEL_PMT_TELEMETRY is not set +# CONFIG_INTEL_SAR_INT1092 is not set +# CONFIG_INTEL_SCU_PCI is not set +# CONFIG_INTEL_SCU_PLATFORM is not set +CONFIG_INTEL_SOC_PMIC_CHTDC_TI=y +# CONFIG_INTEL_SOC_PMIC is not set +# CONFIG_INTEL_TCC_COOLING is not set +# CONFIG_INTEL_TH is not set +CONFIG_INTEL_UNCORE_FREQ_CONTROL=m +# CONFIG_INTEL_WMI_SBL_FW_UPDATE is not set +CONFIG_INTEL_XWAY_PHY=m +# CONFIG_INTERCONNECT_QCOM_SM6350 is not set +CONFIG_INTERCONNECT=y +# CONFIG_INTERVAL_TREE_TEST is not set +CONFIG_INV_ICM42600_I2C=m +CONFIG_INV_ICM42600_SPI=m +# CONFIG_INV_MPU6050_I2C is not set +# CONFIG_INV_MPU6050_IIO is not set +# CONFIG_INV_MPU6050_SPI is not set +CONFIG_IO_DELAY_0X80=y +# CONFIG_IO_DELAY_0XED is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_DEFAULT_DMA_LAZY=y +# CONFIG_IOMMU_DEFAULT_DMA_STRICT is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMUFD=m +# CONFIG_IOMMUFD_TEST is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IONIC=m +CONFIG_IOSCHED_BFQ=y +CONFIG_IOSM=m +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_IO_URING=y +# CONFIG_IP5XXX_POWER is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_IPTABLES=m +CONFIG_IP6_NF_MANGLE=m +CONFIG_IP6_NF_MATCH_AH=m +CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_HL=m +CONFIG_IP6_NF_MATCH_IPV6HEADER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_RAW=m +CONFIG_IP6_NF_SECURITY=m +CONFIG_IP6_NF_TARGET_HL=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +CONFIG_IP6_NF_TARGET_NPT=m +CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m +# CONFIG_IPACK_BUS is not set +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IPC_NS=y +# CONFIG_IP_DCCP is not set +CONFIG_IP_FIB_TRIE_STATS=y +# CONFIG_IPMB_DEVICE_INTERFACE is not set +CONFIG_IPMI_DEVICE_INTERFACE=m +CONFIG_IPMI_HANDLER=m +CONFIG_IPMI_IPMB=m +# CONFIG_IPMI_PANIC_EVENT is not set +CONFIG_IPMI_POWEROFF=m +CONFIG_IPMI_SI=m +CONFIG_IPMI_SSIF=m +CONFIG_IPMI_WATCHDOG=m +CONFIG_IP_MROUTE_MULTIPLE_TABLES=y +CONFIG_IP_MROUTE=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_IP_PNP is not set +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_SCTP=m +CONFIG_IP_SET_BITMAP_IP=m +CONFIG_IP_SET_BITMAP_IPMAC=m +CONFIG_IP_SET_BITMAP_PORT=m +CONFIG_IP_SET_HASH_IP=m +CONFIG_IP_SET_HASH_IPMAC=m +CONFIG_IP_SET_HASH_IPMARK=m +CONFIG_IP_SET_HASH_IPPORTIP=m +CONFIG_IP_SET_HASH_IPPORT=m +CONFIG_IP_SET_HASH_IPPORTNET=m +CONFIG_IP_SET_HASH_MAC=m +CONFIG_IP_SET_HASH_NETIFACE=m +CONFIG_IP_SET_HASH_NET=m +CONFIG_IP_SET_HASH_NETNET=m +CONFIG_IP_SET_HASH_NETPORT=m +CONFIG_IP_SET_HASH_NETPORTNET=m +CONFIG_IP_SET_LIST_SET=m +CONFIG_IP_SET=m +CONFIG_IP_SET_MAX=256 +CONFIG_IPU_BRIDGE=m +CONFIG_IPV6_GRE=m +CONFIG_IPV6_ILA=m +CONFIG_IPV6_IOAM6_LWTUNNEL=y +CONFIG_IPV6_MIP6=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_RPL_LWTUNNEL=y +CONFIG_IPV6_SEG6_HMAC=y +CONFIG_IPV6_SEG6_LWTUNNEL=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_SIT=m +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_TUNNEL=m +CONFIG_IPV6_VTI=m +CONFIG_IPV6=y +CONFIG_IPVLAN=m +# CONFIG_IP_VS_DEBUG is not set +CONFIG_IP_VS_DH=m +CONFIG_IP_VS_FO=m +CONFIG_IP_VS_FTP=m +CONFIG_IP_VS_IPV6=y +CONFIG_IP_VS_LBLC=m +CONFIG_IP_VS_LBLCR=m +CONFIG_IP_VS_LC=m +CONFIG_IP_VS=m +CONFIG_IP_VS_MH=m +CONFIG_IP_VS_MH_TAB_INDEX=12 +CONFIG_IP_VS_NQ=m +CONFIG_IP_VS_OVF=m +CONFIG_IP_VS_PE_SIP=m +CONFIG_IP_VS_PROTO_AH=y +CONFIG_IP_VS_PROTO_ESP=y +CONFIG_IP_VS_PROTO_SCTP=y +CONFIG_IP_VS_PROTO_TCP=y +CONFIG_IP_VS_PROTO_UDP=y +CONFIG_IP_VS_RR=m +CONFIG_IP_VS_SED=m +CONFIG_IP_VS_SH=m +CONFIG_IP_VS_SH_TAB_BITS=8 +CONFIG_IP_VS_TAB_BITS=12 +CONFIG_IP_VS_TWOS=m +CONFIG_IP_VS_WLC=m +CONFIG_IP_VS_WRR=m +CONFIG_IPVTAP=m +# CONFIG_IPW2100 is not set +# CONFIG_IPW2200 is not set +CONFIG_IR_ENE=m +CONFIG_IR_FINTEK=m +CONFIG_IR_GPIO_CIR=m +CONFIG_IR_GPIO_TX=m +CONFIG_IR_HIX5HD2=m +CONFIG_IR_IGORPLUGUSB=m +CONFIG_IR_IGUANA=m +CONFIG_IR_IMON_DECODER=m +CONFIG_IR_IMON=m +CONFIG_IR_IMON_RAW=m +CONFIG_IR_ITE_CIR=m +CONFIG_IR_JVC_DECODER=m +CONFIG_IR_MCE_KBD_DECODER=m +CONFIG_IR_MCEUSB=m +CONFIG_IR_NEC_DECODER=m +CONFIG_IR_NUVOTON=m +CONFIG_IR_PWM_TX=m +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_IRQ_STACKS=y +CONFIG_IRQ_TIME_ACCOUNTING=y +CONFIG_IR_RC5_DECODER=m +CONFIG_IR_RC6_DECODER=m +CONFIG_IR_RCMM_DECODER=m +CONFIG_IR_REDRAT3=m +CONFIG_IR_SANYO_DECODER=m +# CONFIG_IRSD200 is not set +CONFIG_IR_SERIAL=m +CONFIG_IR_SERIAL_TRANSMITTER=y +CONFIG_IR_SHARP_DECODER=m +CONFIG_IR_SONY_DECODER=m +CONFIG_IR_SPI=m +CONFIG_IR_STREAMZAP=m +CONFIG_IR_TOY=m +CONFIG_IR_TTUSBIR=m +CONFIG_IR_WINBOND_CIR=m +CONFIG_IR_XMP_DECODER=m +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +# CONFIG_ISA is not set +CONFIG_ISCSI_BOOT_SYSFS=m +# CONFIG_ISCSI_IBFT is not set +CONFIG_ISCSI_TARGET_CXGB4=m +CONFIG_ISCSI_TARGET=m +CONFIG_ISCSI_TCP=m +# CONFIG_ISDN is not set +CONFIG_ISL29003=m +CONFIG_ISL29020=m +# CONFIG_ISL29125 is not set +# CONFIG_ISL29501 is not set +# CONFIG_ISL76682 is not set +CONFIG_ISO9660_FS=m +CONFIG_IS_SIGNED_TYPE_KUNIT_TEST=m +CONFIG_IT8712F_WDT=m +CONFIG_IT87_WDT=m +CONFIG_ITCO_VENDOR_SUPPORT=y +CONFIG_ITCO_WDT=m +# CONFIG_ITG3200 is not set +CONFIG_IWL3945=m +CONFIG_IWL4965=m +CONFIG_IWLDVM=m +CONFIG_IWLEGACY_DEBUGFS=y +CONFIG_IWLEGACY_DEBUG=y +CONFIG_IWLEGACY=m +# CONFIG_IWLMEI is not set +CONFIG_IWLMVM=m +# CONFIG_IWLWIFI_BCAST_FILTERING is not set +CONFIG_IWLWIFI_DEBUGFS=y +CONFIG_IWLWIFI_DEBUG=y +# CONFIG_IWLWIFI_DEVICE_TRACING is not set +CONFIG_IWLWIFI=m +CONFIG_IXGBE_DCA=y +CONFIG_IXGBE_DCB=y +CONFIG_IXGBE_HWMON=y +CONFIG_IXGBE_IPSEC=y +CONFIG_IXGBE=m +CONFIG_IXGBEVF_IPSEC=y +CONFIG_IXGBEVF=m +CONFIG_IXGB=m +# CONFIG_JBD2_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS=m +CONFIG_JFFS2_FS_POSIX_ACL=y +CONFIG_JFFS2_FS_SECURITY=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_FS_WRITEBUFFER=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_RTIME=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFS_DEBUG is not set +CONFIG_JFS_FS=m +CONFIG_JFS_POSIX_ACL=y +CONFIG_JFS_SECURITY=y +# CONFIG_JFS_STATISTICS is not set +CONFIG_JH71XX_PMU=y +CONFIG_JME=m +CONFIG_JOLIET=y +CONFIG_JOYSTICK_A3D=m +CONFIG_JOYSTICK_ADC=m +CONFIG_JOYSTICK_ADI=m +CONFIG_JOYSTICK_ANALOG=m +# CONFIG_JOYSTICK_AS5011 is not set +CONFIG_JOYSTICK_COBRA=m +CONFIG_JOYSTICK_DB9=m +# CONFIG_JOYSTICK_FSIA6B is not set +CONFIG_JOYSTICK_GAMECON=m +CONFIG_JOYSTICK_GF2K=m +CONFIG_JOYSTICK_GRIP=m +CONFIG_JOYSTICK_GRIP_MP=m +CONFIG_JOYSTICK_GUILLEMOT=m +CONFIG_JOYSTICK_IFORCE_232=m +CONFIG_JOYSTICK_IFORCE=m +CONFIG_JOYSTICK_IFORCE_USB=m +CONFIG_JOYSTICK_INTERACT=m +CONFIG_JOYSTICK_JOYDUMP=m +# CONFIG_JOYSTICK_MAGELLAN is not set +CONFIG_JOYSTICK_PSXPAD_SPI_FF=y +CONFIG_JOYSTICK_PSXPAD_SPI=m +CONFIG_JOYSTICK_PXRC=m +CONFIG_JOYSTICK_QWIIC=m +# CONFIG_JOYSTICK_SEESAW is not set +# CONFIG_JOYSTICK_SENSEHAT is not set +CONFIG_JOYSTICK_SIDEWINDER=m +# CONFIG_JOYSTICK_SPACEBALL is not set +# CONFIG_JOYSTICK_SPACEORB is not set +# CONFIG_JOYSTICK_STINGER is not set +CONFIG_JOYSTICK_TMDC=m +CONFIG_JOYSTICK_TURBOGRAFX=m +# CONFIG_JOYSTICK_TWIDJOY is not set +CONFIG_JOYSTICK_WALKERA0701=m +# CONFIG_JOYSTICK_WARRIOR is not set +CONFIG_JOYSTICK_XPAD_FF=y +CONFIG_JOYSTICK_XPAD_LEDS=y +CONFIG_JOYSTICK_XPAD=m +# CONFIG_JOYSTICK_ZHENHUA is not set +# CONFIG_JSA1212 is not set +CONFIG_JUMP_LABEL=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_SELFTEST is not set +CONFIG_KALLSYMS=y +# CONFIG_KARMA_PARTITION is not set +# CONFIG_KASAN_EXTRA_INFO is not set +# CONFIG_KASAN is not set +# CONFIG_KASAN_MODULE_TEST is not set +# CONFIG_KASAN_VMALLOC is not set +# CONFIG_KCOV is not set +# CONFIG_KCSAN is not set +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_UNCOMPRESSED is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_KEXEC_FILE=y +CONFIG_KEXEC_IMAGE_VERIFY_SIG=y +CONFIG_KEXEC_SIG=y +CONFIG_KEXEC=y +# CONFIG_KEYBOARD_ADC is not set +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +# CONFIG_KEYBOARD_APPLESPI is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_KEYBOARD_BCM is not set +# CONFIG_KEYBOARD_CAP11XX is not set +CONFIG_KEYBOARD_CYPRESS_SF=m +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_GOLDFISH_EVENTS is not set +# CONFIG_KEYBOARD_GPIO is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OMAP4 is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_PINEPHONE is not set +CONFIG_KEYBOARD_PMIC8XXX=m +CONFIG_KEYBOARD_QT1050=m +CONFIG_KEYBOARD_QT1070=m +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +CONFIG_KEYBOARD_TM2_TOUCHKEY=m +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_KEY_DH_OPERATIONS=y +CONFIG_KEY_NOTIFICATIONS=y +CONFIG_KEYS_REQUEST_CACHE=y +CONFIG_KEYS=y +# CONFIG_KFENCE_DEFERRABLE is not set +CONFIG_KFENCE_KUNIT_TEST=m +CONFIG_KFENCE_NUM_OBJECTS=255 +CONFIG_KFENCE_SAMPLE_INTERVAL=100 +# CONFIG_KFENCE_STATIC_KEYS is not set +CONFIG_KFENCE_STRESS_TEST_FAULTS=0 +CONFIG_KFENCE=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +# CONFIG_KGDB_KDB is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS_ON_BOOT is not set +CONFIG_KGDB_TESTS=y +CONFIG_KGDB=y +# CONFIG_KMX61 is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_KPROBE_EVENTS=y +CONFIG_KPROBES_SANITY_TEST=m +CONFIG_KPROBES=y +# CONFIG_KS7010 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +CONFIG_KSM=y +CONFIG_KSZ884X_PCI=m +CONFIG_KUNIT_ALL_TESTS=m +CONFIG_KUNIT_DEBUGFS=y +# CONFIG_KUNIT_DEFAULT_ENABLED is not set +CONFIG_KUNIT_EXAMPLE_TEST=m +# CONFIG_KUNIT_FAULT_TEST is not set +CONFIG_KUNIT=m +CONFIG_KUNIT_TEST=m +CONFIG_KVM_MAX_NR_VCPUS=4096 +# CONFIG_KVM_PROVE_MMU is not set +CONFIG_KVM_SMM=y +# CONFIG_KVM_WERROR is not set +CONFIG_KVM_XEN=y +CONFIG_KVM=y +CONFIG_KXCJK1013=m +# CONFIG_KXSD9 is not set +CONFIG_L2TP_DEBUGFS=m +CONFIG_L2TP_ETH=m +CONFIG_L2TP_IP=m +CONFIG_L2TP=m +CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m +CONFIG_LAN966X_SWITCH=m +# CONFIG_LAPB is not set +CONFIG_LATENCYTOP=y +# CONFIG_LATTICE_ECP3_CONFIG is not set +# CONFIG_LCD2S is not set +# CONFIG_LCD_AMS369FG06 is not set +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_HX8357 is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_L4F00242T03 is not set +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_OTM3225A is not set +CONFIG_LCD_PLATFORM=m +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +# CONFIG_LD_DEAD_CODE_DATA_ELIMINATION is not set +CONFIG_LDISC_AUTOLOAD=y +# CONFIG_LDM_DEBUG is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LEDS_AAT1290 is not set +CONFIG_LEDS_AN30259A=m +# CONFIG_LEDS_ARIEL is not set +CONFIG_LEDS_AS3645A=m +CONFIG_LEDS_AW200XX=m +# CONFIG_LEDS_AW2013 is not set +# CONFIG_LEDS_BCM6328 is not set +# CONFIG_LEDS_BCM6358 is not set +# CONFIG_LEDS_BD2606MVV is not set +# CONFIG_LEDS_BD2802 is not set +CONFIG_LEDS_BLINKM=m +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_CLASS_FLASH=m +CONFIG_LEDS_CLASS_MULTICOLOR=m +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_CLEVO_MAIL=m +CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_EL15203000 is not set +# CONFIG_LEDS_GPIO is not set +CONFIG_LEDS_GROUP_MULTICOLOR=m +# CONFIG_LEDS_IS31FL319X is not set +CONFIG_LEDS_IS31FL32XX=m +CONFIG_LEDS_KTD202X=m +# CONFIG_LEDS_KTD2692 is not set +# CONFIG_LEDS_LGM is not set +CONFIG_LEDS_LM3530=m +CONFIG_LEDS_LM3532=m +# CONFIG_LEDS_LM355x is not set +CONFIG_LEDS_LM3601X=m +# CONFIG_LEDS_LM36274 is not set +# CONFIG_LEDS_LM3642 is not set +CONFIG_LEDS_LM3692X=m +# CONFIG_LEDS_LM3697 is not set +CONFIG_LEDS_LP3944=m +CONFIG_LEDS_LP3952=m +CONFIG_LEDS_LP50XX=m +# CONFIG_LEDS_LP55XX_COMMON is not set +# CONFIG_LEDS_LP8860 is not set +CONFIG_LEDS_LT3593=m +CONFIG_LEDS_MAX5970=m +CONFIG_LEDS_MAX77650=m +CONFIG_LEDS_MLXCPLD=m +CONFIG_LEDS_MLXREG=m +CONFIG_LEDS_NCP5623=m +CONFIG_LEDS_NIC78BX=m +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +CONFIG_LEDS_PCA995X=m +CONFIG_LEDS_PWM=m +CONFIG_LEDS_PWM_MULTICOLOR=m +CONFIG_LEDS_REGULATOR=m +# CONFIG_LEDS_RT4505 is not set +# CONFIG_LEDS_RT8515 is not set +# CONFIG_LEDS_SGM3140 is not set +# CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m +CONFIG_LEDS_SYSCON=y +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set +# CONFIG_LEDS_TLC591XX is not set +CONFIG_LEDS_TRIGGER_ACTIVITY=m +CONFIG_LEDS_TRIGGER_AUDIO=m +CONFIG_LEDS_TRIGGER_BACKLIGHT=m +CONFIG_LEDS_TRIGGER_CAMERA=m +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m +CONFIG_LEDS_TRIGGER_DISK=y +CONFIG_LEDS_TRIGGER_GPIO=m +CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m +CONFIG_LEDS_TRIGGER_MTD=y +CONFIG_LEDS_TRIGGER_NETDEV=m +CONFIG_LEDS_TRIGGER_ONESHOT=m +CONFIG_LEDS_TRIGGER_PANIC=y +CONFIG_LEDS_TRIGGER_PATTERN=m +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=m +CONFIG_LEDS_TRIGGER_TRANSIENT=m +CONFIG_LEDS_TRIGGER_TTY=m +CONFIG_LEDS_USER=m +CONFIG_LED_TRIGGER_PHY=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_LIB80211_CRYPT_CCMP=m +CONFIG_LIB80211_CRYPT_TKIP=m +CONFIG_LIB80211_CRYPT_WEP=m +# CONFIG_LIB80211_DEBUG is not set +CONFIG_LIB80211=m +CONFIG_LIBCRC32C=y +# CONFIG_LIBERTAS is not set +# CONFIG_LIBERTAS_THINFIRM_DEBUG is not set +CONFIG_LIBERTAS_THINFIRM=m +CONFIG_LIBERTAS_THINFIRM_USB=m +CONFIG_LIBFC=m +CONFIG_LIBFCOE=m +CONFIG_LIBNVDIMM=m +# CONFIG_LIDAR_LITE_V2 is not set +CONFIG_LINEAR_RANGES_TEST=m +CONFIG_LIRC=y +CONFIG_LIST_KUNIT_TEST=m +CONFIG_LITEX_LITEETH=y +CONFIG_LITEX_SOC_CONTROLLER=y +CONFIG_LIVEPATCH=y +# CONFIG_LKDTM is not set +# CONFIG_LLC2 is not set +CONFIG_LLC=m +# CONFIG_LMK04832 is not set +CONFIG_LMP91000=m +CONFIG_LOAD_UEFI_KEYS=y +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_LOCKDEP_BITS=16 +CONFIG_LOCKDEP_CHAINS_BITS=19 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKD=m +# CONFIG_LOCK_DOWN_IN_EFI_SECURE_BOOT is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_CONFIDENTIALITY is not set +# CONFIG_LOCK_DOWN_KERNEL_FORCE_INTEGRITY is not set +CONFIG_LOCK_DOWN_KERNEL_FORCE_NONE=y +CONFIG_LOCKD_V4=y +# CONFIG_LOCK_EVENT_COUNTS is not set +# CONFIG_LOCK_STAT is not set +CONFIG_LOCK_TORTURE_TEST=m +CONFIG_LOCKUP_DETECTOR=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_LOGIG940_FF=y +CONFIG_LOGIRUMBLEPAD2_FF=y +CONFIG_LOGITECH_FF=y +CONFIG_LOGIWHEELS_FF=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO=y +CONFIG_LOOPBACK_TARGET=m +# CONFIG_LPC_ICH is not set +CONFIG_LP_CONSOLE=y +# CONFIG_LPC_SCH is not set +CONFIG_LRU_GEN_ENABLED=y +# CONFIG_LRU_GEN_STATS is not set +CONFIG_LRU_GEN=y +CONFIG_LSI_ET1011C_PHY=m +CONFIG_LSM="lockdown,yama,integrity,selinux,bpf,landlock" +CONFIG_LSM_MMAP_MIN_ADDR=65535 +CONFIG_LTC1660=m +# CONFIG_LTC2309 is not set +# CONFIG_LTC2471 is not set +# CONFIG_LTC2485 is not set +# CONFIG_LTC2496 is not set +# CONFIG_LTC2497 is not set +# CONFIG_LTC2632 is not set +CONFIG_LTC2688=m +CONFIG_LTC2983=m +# CONFIG_LTE_GDM724X is not set +# CONFIG_LTO_CLANG_FULL is not set +# CONFIG_LTO_CLANG_THIN is not set +CONFIG_LTO_NONE=y +# CONFIG_LTR390 is not set +CONFIG_LTR501=m +CONFIG_LTRF216A=m +CONFIG_LV0104CS=m +# CONFIG_LWQ_TEST is not set +CONFIG_LWTUNNEL_BPF=y +CONFIG_LWTUNNEL=y +CONFIG_LXT_PHY=m +CONFIG_LZ4_COMPRESS=m +# CONFIG_M62332 is not set +CONFIG_MAC80211_DEBUGFS=y +# CONFIG_MAC80211_DEBUG_MENU is not set +CONFIG_MAC80211_HWSIM=m +CONFIG_MAC80211_KUNIT_TEST=m +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211=m +CONFIG_MAC80211_MESH=y +# CONFIG_MAC80211_MESSAGE_TRACING is not set +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC802154=m +CONFIG_MACB=m +CONFIG_MACB_PCI=m +CONFIG_MACB_USE_HWSTAMP=y +CONFIG_MAC_EMUMOUSEBTN=y +CONFIG_MACHZ_WDT=m +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_MAC_PARTITION=y +CONFIG_MACSEC=m +CONFIG_MACVLAN=m +CONFIG_MACVTAP=m +# CONFIG_MAG3110 is not set +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_MAILBOX_TEST is not set +CONFIG_MAILBOX=y +# CONFIG_MANAGER_SBS is not set +CONFIG_MANTIS_CORE=m +# CONFIG_MARCH_Z16 is not set +CONFIG_MARVELL_10G_PHY=m +CONFIG_MARVELL_88Q2XXX_PHY=m +CONFIG_MARVELL_88X2222_PHY=m +CONFIG_MARVELL_PHY=m +# CONFIG_MATOM is not set +# CONFIG_MAX1027 is not set +# CONFIG_MAX11100 is not set +# CONFIG_MAX1118 is not set +CONFIG_MAX11205=m +CONFIG_MAX11410=m +CONFIG_MAX1241=m +CONFIG_MAX1363=m +CONFIG_MAX30100=m +# CONFIG_MAX30102 is not set +CONFIG_MAX30208=m +CONFIG_MAX31827=m +CONFIG_MAX31856=m +CONFIG_MAX31865=m +CONFIG_MAX34408=m +# CONFIG_MAX44000 is not set +CONFIG_MAX44009=m +# CONFIG_MAX517 is not set +# CONFIG_MAX5432 is not set +# CONFIG_MAX5481 is not set +# CONFIG_MAX5487 is not set +CONFIG_MAX5522=m +# CONFIG_MAX5821 is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_MAX6959 is not set +CONFIG_MAX77620_WATCHDOG=m +# CONFIG_MAX9611 is not set +CONFIG_MAXIM_THERMOCOUPLE=m +CONFIG_MAXLINEAR_GPHY=m +CONFIG_MAXPHYSMEM_128GB=y +# CONFIG_MAXPHYSMEM_2GB is not set +CONFIG_MAX_SKB_FRAGS=17 +CONFIG_MB1232=m +# CONFIG_MC3230 is not set +# CONFIG_MCB is not set +CONFIG_MCHP_CLK_MPFS=y +# CONFIG_MCORE2 is not set +# CONFIG_MCP320X is not set +# CONFIG_MCP3422 is not set +# CONFIG_MCP3564 is not set +CONFIG_MCP3911=m +CONFIG_MCP4018=m +CONFIG_MCP41010=m +# CONFIG_MCP4131 is not set +# CONFIG_MCP4531 is not set +# CONFIG_MCP4725 is not set +CONFIG_MCP4728=m +CONFIG_MCP4821=m +# CONFIG_MCP4922 is not set +CONFIG_MCP9600=m +CONFIG_MCTP_SERIAL=m +# CONFIG_MCTP_TRANSPORT_I2C is not set +# CONFIG_MCTP_TRANSPORT_I3C is not set +CONFIG_MCTP=y +CONFIG_MD_AUTODETECT=y +CONFIG_MD_BITMAP_FILE=y +# CONFIG_MD_CLUSTER is not set +CONFIG_MD_FAULTY=m +CONFIG_MDIO_BCM_UNIMAC=m +CONFIG_MDIO_BITBANG=m +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MDIO_BUS_MUX_MULTIPLEXER is not set +CONFIG_MDIO_DEVICE=y +# CONFIG_MDIO_GPIO is not set +# CONFIG_MDIO_HISI_FEMAC is not set +CONFIG_MDIO_I2C=m +# CONFIG_MDIO_IPQ4019 is not set +# CONFIG_MDIO_IPQ8064 is not set +# CONFIG_MDIO_MSCC_MIIM is not set +CONFIG_MDIO_MVUSB=m +# CONFIG_MDIO_OCTEON is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_MD_LINEAR=m +CONFIG_MDM_GCC_9607=m +CONFIG_MD_MULTIPATH=m +CONFIG_MD_RAID0=m +CONFIG_MD_RAID10=m +CONFIG_MD_RAID1=m +CONFIG_MD_RAID456=m +CONFIG_MD=y +CONFIG_MEAN_AND_VARIANCE_UNIT_TEST=m +CONFIG_MEDIA_ALTERA_CI=m +CONFIG_MEDIA_ANALOG_TV_SUPPORT=y +CONFIG_MEDIA_ATTACH=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_CEC_RC=y +CONFIG_MEDIA_CEC_SUPPORT=y +CONFIG_MEDIA_CONTROLLER_DVB=y +CONFIG_MEDIA_CONTROLLER=y +CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y +CONFIG_MEDIA_PCI_SUPPORT=y +CONFIG_MEDIA_PLATFORM_DRIVERS=y +CONFIG_MEDIA_PLATFORM_SUPPORT=y +CONFIG_MEDIA_RADIO_SUPPORT=y +# CONFIG_MEDIA_SDR_SUPPORT is not set +CONFIG_MEDIA_SUBDRV_AUTOSELECT=y +CONFIG_MEDIA_SUPPORT_FILTER=y +CONFIG_MEDIA_SUPPORT=m +CONFIG_MEDIATEK_GE_PHY=m +CONFIG_MEDIATEK_MT6370_ADC=m +CONFIG_MEDIA_TEST_SUPPORT=y +# CONFIG_MEDIA_TUNER_MSI001 is not set +# CONFIG_MEDIA_TUNER_MXL301RF is not set +CONFIG_MEDIA_USB_SUPPORT=y +# CONFIG_MEFFICEON is not set +CONFIG_MEGARAID_LEGACY=m +CONFIG_MEGARAID_MAILBOX=m +CONFIG_MEGARAID_MM=m +CONFIG_MEGARAID_NEWGEN=y +CONFIG_MEGARAID_SAS=m +# CONFIG_MELAN is not set +CONFIG_MELLANOX_PLATFORM=y +# CONFIG_MEM_ALLOC_PROFILING is not set +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y +CONFIG_MEMCG=y +CONFIG_MEMCPY_KUNIT_TEST=m +CONFIG_MEMCPY_SLOW_KUNIT_TEST=y +CONFIG_MEMORY_FAILURE=y +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +# CONFIG_MEMORY_HOTPLUG is not set +# CONFIG_MEMORY is not set +# CONFIG_MEMSTICK_DEBUG is not set +CONFIG_MEMSTICK_JMICRON_38X=m +CONFIG_MEMSTICK=m +CONFIG_MEMSTICK_R592=m +CONFIG_MEMSTICK_REALTEK_PCI=m +CONFIG_MEMSTICK_REALTEK_USB=m +CONFIG_MEMSTICK_TIFM_MS=m +# CONFIG_MEMSTICK_UNSAFE_RESUME is not set +CONFIG_MEMTEST=y +# CONFIG_MEN_A21_WDT is not set +# CONFIG_MERAKI_MX100 is not set +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_ACT8945A is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_AS3711 is not set +# CONFIG_MFD_AS3722 is not set +# CONFIG_MFD_ATC260X_I2C is not set +# CONFIG_MFD_ATMEL_FLEXCOM is not set +# CONFIG_MFD_ATMEL_HLCDC is not set +CONFIG_MFD_AXP20X_I2C=y +CONFIG_MFD_AXP20X_RSB=m +CONFIG_MFD_AXP20X=y +# CONFIG_MFD_BCM590XX is not set +CONFIG_MFD_BD9571MWV=m +CONFIG_MFD_CORE=y +# CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m +CONFIG_MFD_CS42L43_I2C=m +CONFIG_MFD_CS42L43_SDW=m +# CONFIG_MFD_CS5535 is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +CONFIG_MFD_DA9063=m +# CONFIG_MFD_DA9150 is not set +CONFIG_MFD_DLN2=m +CONFIG_MFD_ENE_KB3930=m +# CONFIG_MFD_GATEWORKS_GSC is not set +# CONFIG_MFD_HI6421_PMIC is not set +# CONFIG_MFD_HI6421_SPMI is not set +CONFIG_MFD_INTEL_M10_BMC=m +CONFIG_MFD_INTEL_M10_BMC_PMCI=m +CONFIG_MFD_INTEL_M10_BMC_SPI=m +# CONFIG_MFD_INTEL_PMC_BXT is not set +# CONFIG_MFD_IQS62X is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_KHADAS_MCU is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_LOCHNAGAR is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_MFD_MAX14577 is not set +CONFIG_MFD_MAX5970=m +CONFIG_MFD_MAX597X=m +# CONFIG_MFD_MAX77541 is not set +# CONFIG_MFD_MAX77620 is not set +CONFIG_MFD_MAX77650=m +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +CONFIG_MFD_MAX77714=m +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_MP2629 is not set +# CONFIG_MFD_MT6360 is not set +# CONFIG_MFD_MT6370 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_NTXEC is not set +# CONFIG_MFD_OCELOT is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_QCOM_PM8008 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_RK808 is not set +# CONFIG_MFD_RK8XX_I2C is not set +# CONFIG_MFD_RK8XX_SPI is not set +# CONFIG_MFD_RN5T618 is not set +# CONFIG_MFD_ROHM_BD71828 is not set +# CONFIG_MFD_ROHM_BD718XX is not set +# CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m +CONFIG_MFD_RSMU_I2C=m +CONFIG_MFD_RSMU_SPI=m +CONFIG_MFD_RT4831=m +# CONFIG_MFD_RT5033 is not set +CONFIG_MFD_RT5120=m +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +CONFIG_MFD_SIMPLE_MFD_I2C=m +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SL28CPLD is not set +CONFIG_MFD_SM501_GPIO=y +CONFIG_MFD_SM501=m +# CONFIG_MFD_SMPRO is not set +# CONFIG_MFD_STMFX is not set +# CONFIG_MFD_STMPE is not set +# CONFIG_MFD_STPMIC1 is not set +CONFIG_MFD_SY7636A=m +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TI_LP87565 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS65218 is not set +# CONFIG_MFD_TPS65219 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_SPI is not set +CONFIG_MFD_TPS6594_I2C=m +# CONFIG_MFD_TPS6594_SPI is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VIPERBOARD is not set +CONFIG_MFD_VX855=m +CONFIG_MFD_WL1273_CORE=m +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8994 is not set +# CONFIG_MGEODEGX1 is not set +# CONFIG_MGEODE_LX is not set +# CONFIG_MHI_BUS_DEBUG is not set +# CONFIG_MHI_BUS_EP is not set +CONFIG_MHI_BUS=m +CONFIG_MHI_BUS_PCI_GENERIC=m +CONFIG_MHI_NET=m +CONFIG_MHI_WWAN_CTRL=m +CONFIG_MHI_WWAN_MBIM=m +# CONFIG_MICREL_KS8995MA is not set +CONFIG_MICREL_PHY=m +CONFIG_MICROCHIP_PHY=m +# CONFIG_MICROCHIP_PIT64B is not set +# CONFIG_MICROCHIP_T1_PHY is not set +CONFIG_MICROCHIP_T1S_PHY=m +CONFIG_MICROSEMI_PHY=m +CONFIG_MICROSOFT_MANA=m +CONFIG_MIGRATION=y +CONFIG_MII=m +CONFIG_MINIX_FS=m +CONFIG_MINIX_SUBPARTITION=y +CONFIG_MISC_ALCOR_PCI=m +CONFIG_MISC_FILESYSTEMS=y +CONFIG_MISC_RTSX_PCI=m +CONFIG_MISC_RTSX_USB=m +CONFIG_MKISS=m +CONFIG_MLX4_CORE_GEN2=y +CONFIG_MLX4_CORE=m +CONFIG_MLX4_DEBUG=y +CONFIG_MLX4_EN_DCB=y +CONFIG_MLX4_EN=m +CONFIG_MLX4_INFINIBAND=m +CONFIG_MLX5_ACCEL=y +CONFIG_MLX5_CLS_ACT=y +CONFIG_MLX5_CORE_EN_DCB=y +CONFIG_MLX5_CORE_EN=y +CONFIG_MLX5_CORE_IPOIB=y +CONFIG_MLX5_CORE=m +CONFIG_MLX5_DPLL=m +CONFIG_MLX5_EN_ARFS=y +CONFIG_MLX5_EN_IPSEC=y +CONFIG_MLX5_EN_MACSEC=y +CONFIG_MLX5_EN_RXNFC=y +CONFIG_MLX5_EN_TLS=y +CONFIG_MLX5_ESWITCH=y +# CONFIG_MLX5_FPGA_IPSEC is not set +# CONFIG_MLX5_FPGA_TLS is not set +CONFIG_MLX5_FPGA=y +CONFIG_MLX5_INFINIBAND=m +CONFIG_MLX5_IPSEC=y +CONFIG_MLX5_MACSEC=y +CONFIG_MLX5_MPFS=y +CONFIG_MLX5_SF=y +CONFIG_MLX5_SW_STEERING=y +CONFIG_MLX5_TC_CT=y +CONFIG_MLX5_TC_SAMPLE=y +CONFIG_MLX5_TLS=y +CONFIG_MLX5_VDPA_NET=m +# CONFIG_MLX5_VDPA_STEERING_DEBUG is not set +CONFIG_MLX5_VDPA=y +CONFIG_MLX5_VFIO_PCI=m +CONFIG_MLX90614=m +CONFIG_MLX90632=m +# CONFIG_MLX90635 is not set +# CONFIG_MLXBF_BOOTCTL is not set +# CONFIG_MLXBF_GIGE is not set +# CONFIG_MLXBF_TMFIFO is not set +CONFIG_MLXFW=m +CONFIG_MLXREG_HOTPLUG=m +CONFIG_MLXREG_IO=m +CONFIG_MLXREG_LC=m +CONFIG_MLXSW_CORE_HWMON=y +CONFIG_MLXSW_CORE=m +CONFIG_MLXSW_CORE_THERMAL=y +CONFIG_MLXSW_I2C=m +CONFIG_MLXSW_MINIMAL=m +CONFIG_MLXSW_PCI=m +CONFIG_MLXSW_SPECTRUM_DCB=y +CONFIG_MLXSW_SPECTRUM=m +CONFIG_MLX_WDT=m +# CONFIG_MMA7455_I2C is not set +# CONFIG_MMA7455_SPI is not set +CONFIG_MMA7660=m +# CONFIG_MMA8452 is not set +# CONFIG_MMA9551 is not set +# CONFIG_MMA9553 is not set +# CONFIG_MMC35240 is not set +CONFIG_MMC_ALCOR=m +# CONFIG_MMC_ARMMMCI is not set +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK=y +CONFIG_MMC_CB710=m +CONFIG_MMC_CQHCI=y +# CONFIG_MMC_CRYPTO is not set +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_DW_BLUEFIELD is not set +# CONFIG_MMC_DW_EXYNOS is not set +# CONFIG_MMC_DW_HI3798CV200 is not set +CONFIG_MMC_DW_HI3798MV200=m +# CONFIG_MMC_DW_K3 is not set +CONFIG_MMC_DW=m +CONFIG_MMC_DW_PCI=m +CONFIG_MMC_DW_PLTFM=m +CONFIG_MMC_DW_STARFIVE=m +# CONFIG_MMC_GOLDFISH is not set +CONFIG_MMC_HSQ=m +CONFIG_MMC_LITEX=y +# CONFIG_MMC_MTK is not set +CONFIG_MMC_REALTEK_PCI=m +CONFIG_MMC_REALTEK_USB=m +CONFIG_MMC_RICOH_MMC=y +CONFIG_MMC_SDHCI_ACPI=m +# CONFIG_MMC_SDHCI_AM654 is not set +CONFIG_MMC_SDHCI_CADENCE=m +# CONFIG_MMC_SDHCI_F_SDH30 is not set +# CONFIG_MMC_SDHCI_MILBEAUT is not set +# CONFIG_MMC_SDHCI_OF_ARASAN is not set +# CONFIG_MMC_SDHCI_OF_AT91 is not set +CONFIG_MMC_SDHCI_OF_DWCMSHC=m +# CONFIG_MMC_SDHCI_OF_ESDHC is not set +# CONFIG_MMC_SDHCI_OMAP is not set +CONFIG_MMC_SDHCI_PCI=m +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_XENON=m +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDRICOH_CS=m +CONFIG_MMC_SPI=y +# CONFIG_MMC_STM32_SDMMC is not set +# CONFIG_MMC_TEST is not set +CONFIG_MMC_TIFM_SD=m +# CONFIG_MMC_TOSHIBA_PCI is not set +# CONFIG_MMC_USDHI6ROL0 is not set +CONFIG_MMC_USHC=m +CONFIG_MMC_VIA_SDMMC=m +CONFIG_MMC_VUB300=m +CONFIG_MMC_WBSD=m +CONFIG_MMC=y +CONFIG_MMU=y +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_MODPROBE_PATH="/usr/sbin/modprobe" +# CONFIG_MODULE_ALLOW_BTF_MISMATCH is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_MODULE_COMPRESS_GZIP is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set +# CONFIG_MODULE_DEBUG is not set +# CONFIG_MODULE_FORCE_LOAD is not set +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +# CONFIG_MODULE_SIG_KEY_TYPE_ECDSA is not set +CONFIG_MODULE_SIG_KEY_TYPE_RSA=y +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA3_256 is not set +# CONFIG_MODULE_SIG_SHA3_384 is not set +# CONFIG_MODULE_SIG_SHA3_512 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MOST is not set +CONFIG_MOTORCOMM_PHY=m +CONFIG_MOUSE_APPLETOUCH=m +CONFIG_MOUSE_BCM5974=m +CONFIG_MOUSE_CYAPA=m +CONFIG_MOUSE_ELAN_I2C_I2C=y +CONFIG_MOUSE_ELAN_I2C=m +CONFIG_MOUSE_ELAN_I2C_SMBUS=y +# CONFIG_MOUSE_GPIO is not set +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_CYPRESS=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +CONFIG_MOUSE_PS2_ELANTECH_SMBUS=y +CONFIG_MOUSE_PS2_FOCALTECH=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +# CONFIG_MOUSE_PS2_SENTELIC is not set +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_SERIAL is not set +CONFIG_MOUSE_SYNAPTICS_I2C=m +CONFIG_MOUSE_SYNAPTICS_USB=m +CONFIG_MOUSE_VSXXXAA=m +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_MOXTET is not set +CONFIG_MPL115_I2C=m +# CONFIG_MPL115_SPI is not set +# CONFIG_MPL3115 is not set +CONFIG_MPLS_IPTUNNEL=m +CONFIG_MPLS_ROUTING=m +# CONFIG_MPRLS0025PA is not set +CONFIG_MPTCP_IPV6=y +CONFIG_MPTCP_KUNIT_TEST=m +CONFIG_MPTCP=y +CONFIG_MPU3050_I2C=m +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_MS5611 is not set +# CONFIG_MS5637 is not set +CONFIG_MSA311=m +# CONFIG_MS_BLOCK is not set +CONFIG_MSDOS_FS=m +CONFIG_MSDOS_PARTITION=y +CONFIG_MSE102X=m +# CONFIG_MSM_GCC_8939 is not set +# CONFIG_MSM_GCC_8953 is not set +# CONFIG_MSM_GPUCC_8998 is not set +# CONFIG_MSM_MMCC_8998 is not set +CONFIG_MSPRO_BLOCK=m +CONFIG_MT7601U=m +CONFIG_MT7603E=m +CONFIG_MT7615E=m +CONFIG_MT7663S=m +CONFIG_MT7663U=m +CONFIG_MT76x0E=m +CONFIG_MT76x0U=m +CONFIG_MT76x2E=m +CONFIG_MT76x2U=m +CONFIG_MT7915E=m +CONFIG_MT7921E=m +CONFIG_MT7921S=m +CONFIG_MT7921U=m +CONFIG_MT7925E=m +CONFIG_MT7925U=m +CONFIG_MT7996E=m +# CONFIG_MTD_ABSENT is not set +# CONFIG_MTD_AR7_PARTS is not set +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK2MTD=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +CONFIG_MTD_CFI_INTELEXT=m +CONFIG_MTD_CFI=m +CONFIG_MTD_CFI_STAA=m +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_HYPERBUS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_JEDECPROBE is not set +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD=m +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MCHP23K256 is not set +CONFIG_MTD_MCHP48L640=m +CONFIG_MTD_MTDRAM=m +# CONFIG_MTD_NAND_ARASAN is not set +# CONFIG_MTD_NAND_BRCMNAND is not set +CONFIG_MTD_NAND_CADENCE=m +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_CS553X is not set +# CONFIG_MTD_NAND_DENALI_DT is not set +# CONFIG_MTD_NAND_DENALI_PCI is not set +# CONFIG_MTD_NAND_DISKONCHIP is not set +CONFIG_MTD_NAND_ECC_MXIC=y +# CONFIG_MTD_NAND_ECC_SW_BCH is not set +# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set +CONFIG_MTD_NAND_ECC_SW_HAMMING=y +# CONFIG_MTD_NAND_GPIO is not set +# CONFIG_MTD_NAND_HISI504 is not set +# CONFIG_MTD_NAND_INTEL_LGM is not set +# CONFIG_MTD_NAND_MESON is not set +# CONFIG_MTD_NAND_MXC is not set +# CONFIG_MTD_NAND_MXIC is not set +CONFIG_MTD_NAND_NANDSIM=m +# CONFIG_MTD_NAND_OMAP2 is not set +# CONFIG_MTD_NAND_PL35X is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_NAND_QCOM is not set +# CONFIG_MTD_NAND_RICOH is not set +# CONFIG_MTD_NAND_ROCKCHIP is not set +# CONFIG_MTD_NAND_SUNXI is not set +CONFIG_MTD_OF_PARTS=m +# CONFIG_MTD_ONENAND is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_PARTITIONED_MASTER is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PHYSMAP_GEMINI is not set +CONFIG_MTD_PHYSMAP=m +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_PHYSMAP_VERSATILE is not set +# CONFIG_MTD_PLATRAM is not set +# CONFIG_MTD_PMC551 is not set +CONFIG_MTDRAM_ERASE_SIZE=128 +# CONFIG_MTD_RAM is not set +CONFIG_MTDRAM_TOTAL_SIZE=4096 +CONFIG_MTD_RAW_NAND=m +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_SHARPSL_PARTS is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_SPI_NAND is not set +CONFIG_MTD_SPI_NOR=m +# CONFIG_MTD_SPI_NOR_SWP_DISABLE is not set +CONFIG_MTD_SPI_NOR_SWP_DISABLE_ON_VOLATILE=y +# CONFIG_MTD_SPI_NOR_SWP_KEEP is not set +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SWAP is not set +# CONFIG_MTD_TESTS is not set +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_BLOCK is not set +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_FAULT_INJECTION is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_MTD_UBI=m +CONFIG_MTD_UBI_NVMEM=m +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTK_T7XX=m +CONFIG_MULTIPLEXER=m +CONFIG_MULTIUSER=y +CONFIG_MUX_ADG792A=m +# CONFIG_MUX_ADGS1408 is not set +CONFIG_MUX_GPIO=m +CONFIG_MUX_MMIO=m +# CONFIG_MVIAC7 is not set +CONFIG_MVMDIO=m +CONFIG_MWAVE=m +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_USB=m +CONFIG_MWL8K=m +CONFIG_MXC4005=m +CONFIG_MXC6255=m +CONFIG_MYRI10GE_DCA=y +CONFIG_MYRI10GE=m +CONFIG_NAMESPACES=y +CONFIG_NATIONAL_PHY=m +CONFIG_NATSEMI=m +# CONFIG_NAU7802 is not set +# CONFIG_NBPFAXI_DMA is not set +CONFIG_NCN26000_PHY=m +CONFIG_NCSI_OEM_CMD_GET_MAC=y +CONFIG_NCSI_OEM_CMD_KEEP_PHY=y +# CONFIG_NDC_DIS_DYNAMIC_CACHING is not set +CONFIG_NE2K_PCI=m +# CONFIG_NET_9P_DEBUG is not set +CONFIG_NET_9P_FD=m +CONFIG_NET_9P=m +CONFIG_NET_9P_RDMA=m +CONFIG_NET_9P_VIRTIO=m +CONFIG_NET_9P_XEN=m +CONFIG_NET_ACT_BPF=m +CONFIG_NET_ACT_CONNMARK=m +CONFIG_NET_ACT_CSUM=m +CONFIG_NET_ACT_CTINFO=m +CONFIG_NET_ACT_CT=m +CONFIG_NET_ACT_GACT=m +CONFIG_NET_ACT_GATE=m +CONFIG_NET_ACT_IFE=m +CONFIG_NET_ACT_MIRRED=m +CONFIG_NET_ACT_MPLS=m +CONFIG_NET_ACT_NAT=m +CONFIG_NET_ACT_PEDIT=m +CONFIG_NET_ACT_POLICE=m +CONFIG_NET_ACT_SAMPLE=m +CONFIG_NET_ACT_SIMP=m +CONFIG_NET_ACT_SKBEDIT=m +CONFIG_NET_ACT_SKBMOD=m +CONFIG_NET_ACT_TUNNEL_KEY=m +CONFIG_NET_ACT_VLAN=m +CONFIG_NET_CALXEDA_XGMAC=m +CONFIG_NET_CLS_ACT=y +CONFIG_NET_CLS_BASIC=m +CONFIG_NET_CLS_BPF=m +CONFIG_NET_CLS_CGROUP=y +CONFIG_NET_CLS_FLOWER=m +CONFIG_NET_CLS_FLOW=m +CONFIG_NET_CLS_FW=m +CONFIG_NET_CLS_MATCHALL=m +CONFIG_NET_CLS_ROUTE4=m +CONFIG_NET_CLS_U32=m +CONFIG_NET_CLS=y +CONFIG_NETCONSOLE_DYNAMIC=y +# CONFIG_NETCONSOLE_EXTENDED_LOG is not set +CONFIG_NETCONSOLE=m +CONFIG_NET_CORE=y +CONFIG_NETDEV_ADDR_LIST_TEST=m +CONFIG_NETDEVICES=y +CONFIG_NET_DEVLINK=y +# CONFIG_NET_DEV_REFCNT_TRACKER is not set +CONFIG_NETDEVSIM=m +CONFIG_NET_DROP_MONITOR=y +# CONFIG_NET_DSA_AR9331 is not set +CONFIG_NET_DSA_BCM_SF2=m +CONFIG_NET_DSA_HIRSCHMANN_HELLCREEK=m +# CONFIG_NET_DSA_LANTIQ_GSWIP is not set +CONFIG_NET_DSA_LOOP=m +CONFIG_NET_DSA=m +# CONFIG_NET_DSA_MICROCHIP_KSZ8795 is not set +# CONFIG_NET_DSA_MICROCHIP_KSZ9477_I2C is not set +CONFIG_NET_DSA_MICROCHIP_KSZ9477=m +CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m +# CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON is not set +CONFIG_NET_DSA_MT7530=m +CONFIG_NET_DSA_MT7530_MDIO=m +CONFIG_NET_DSA_MT7530_MMIO=m +# CONFIG_NET_DSA_MV88E6060 is not set +CONFIG_NET_DSA_MV88E6XXX=m +CONFIG_NET_DSA_MV88E6XXX_PTP=y +CONFIG_NET_DSA_QCA8K_LEDS_SUPPORT=y +CONFIG_NET_DSA_QCA8K=m +CONFIG_NET_DSA_REALTEK=m +# CONFIG_NET_DSA_REALTEK_MDIO is not set +CONFIG_NET_DSA_REALTEK_RTL8365MB=m +CONFIG_NET_DSA_REALTEK_RTL8366RB=m +# CONFIG_NET_DSA_REALTEK_SMI is not set +# CONFIG_NET_DSA_SJA1105 is not set +CONFIG_NET_DSA_SMSC_LAN9303_I2C=m +CONFIG_NET_DSA_SMSC_LAN9303_MDIO=m +# CONFIG_NET_DSA_TAG_AR9331 is not set +CONFIG_NET_DSA_TAG_GSWIP=m +CONFIG_NET_DSA_TAG_HELLCREEK=m +CONFIG_NET_DSA_TAG_KSZ=m +CONFIG_NET_DSA_TAG_OCELOT_8021Q=m +CONFIG_NET_DSA_TAG_OCELOT=m +CONFIG_NET_DSA_TAG_RTL4_A=m +CONFIG_NET_DSA_TAG_RTL8_4=m +# CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set +CONFIG_NET_DSA_TAG_SJA1105=m +CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set +CONFIG_NET_DSA_TAG_XRS700X=m +# CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set +# CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set +CONFIG_NET_DSA_XRS700X_I2C=m +CONFIG_NET_DSA_XRS700X_MDIO=m +CONFIG_NET_EMATCH_CANID=m +CONFIG_NET_EMATCH_CMP=m +CONFIG_NET_EMATCH_IPSET=m +CONFIG_NET_EMATCH_IPT=m +CONFIG_NET_EMATCH_META=m +CONFIG_NET_EMATCH_NBYTE=m +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_TEXT=m +CONFIG_NET_EMATCH_U32=m +CONFIG_NET_EMATCH=y +CONFIG_NET_FAILOVER=m +CONFIG_NET_FC=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_NETFILTER_EGRESS=y +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK_ACCT=m +# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set +CONFIG_NETFILTER_NETLINK_HOOK=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +# CONFIG_NETFILTER_XTABLES_COMPAT is not set +CONFIG_NETFILTER_XTABLES=y +CONFIG_NETFILTER_XT_CONNMARK=m +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_IPVS=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_SOCKET=m +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_SET=m +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_FOU_IP_TUNNELS=y +CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set +CONFIG_NETFS_STATS=y +CONFIG_NETFS_SUPPORT=m +CONFIG_NET_HANDSHAKE_KUNIT_TEST=m +CONFIG_NET_IFE=m +CONFIG_NET_IFE_SKBMARK=m +CONFIG_NET_IFE_SKBPRIO=m +CONFIG_NET_IFE_SKBTCINDEX=m +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_NET_IPGRE_DEMUX=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPIP=m +CONFIG_NET_IPVTI=m +CONFIG_NET_KEY=m +CONFIG_NET_KEY_MIGRATE=y +CONFIG_NETKIT=y +CONFIG_NET_L3_MASTER_DEV=y +CONFIG_NETLABEL=y +CONFIG_NETLINK_DIAG=y +CONFIG_NET_MPLS_GSO=m +CONFIG_NET_NCSI=y +CONFIG_NET_NSH=m +# CONFIG_NET_NS_REFCNT_TRACKER is not set +CONFIG_NET_NS=y +CONFIG_NET_PKTGEN=m +CONFIG_NET_POLL_CONTROLLER=y +CONFIG_NETROM=m +# CONFIG_NET_SB1000 is not set +CONFIG_NET_SCH_CAKE=m +CONFIG_NET_SCH_CBS=m +CONFIG_NET_SCH_CHOKE=m +CONFIG_NET_SCH_CODEL=m +# CONFIG_NET_SCH_DEFAULT is not set +CONFIG_NET_SCH_DRR=m +CONFIG_NET_SCHED=y +CONFIG_NET_SCH_ETF=m +CONFIG_NET_SCH_ETS=m +CONFIG_NET_SCH_FQ_CODEL=y +CONFIG_NET_SCH_FQ=m +CONFIG_NET_SCH_FQ_PIE=m +CONFIG_NET_SCH_GRED=m +CONFIG_NET_SCH_HFSC=m +CONFIG_NET_SCH_HHF=m +CONFIG_NET_SCH_HTB=m +CONFIG_NET_SCH_INGRESS=m +CONFIG_NET_SCH_MQPRIO=m +CONFIG_NET_SCH_MULTIQ=m +CONFIG_NET_SCH_NETEM=m +CONFIG_NET_SCH_PIE=m +CONFIG_NET_SCH_PLUG=m +CONFIG_NET_SCH_PRIO=m +CONFIG_NET_SCH_QFQ=m +CONFIG_NET_SCH_RED=m +CONFIG_NET_SCH_SFB=m +CONFIG_NET_SCH_SFQ=m +# CONFIG_NET_SCH_SKBPRIO is not set +CONFIG_NET_SCH_TAPRIO=m +CONFIG_NET_SCH_TBF=m +CONFIG_NET_SCH_TEQL=m +CONFIG_NET_SWITCHDEV=y +CONFIG_NET_TC_SKB_EXT=y +CONFIG_NET_TEAM=m +CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m +CONFIG_NET_TEAM_MODE_BROADCAST=m +CONFIG_NET_TEAM_MODE_LOADBALANCE=m +CONFIG_NET_TEAM_MODE_RANDOM=m +CONFIG_NET_TEAM_MODE_ROUNDROBIN=m +CONFIG_NET_TEST=m +CONFIG_NET_TULIP=y +CONFIG_NET_UDP_TUNNEL=m +CONFIG_NET_VENDOR_3COM=y +CONFIG_NET_VENDOR_8390=y +CONFIG_NET_VENDOR_ADAPTEC=y +CONFIG_NET_VENDOR_ADI=y +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +CONFIG_NET_VENDOR_ALTEON=y +CONFIG_NET_VENDOR_AMAZON=y +CONFIG_NET_VENDOR_AMD=y +CONFIG_NET_VENDOR_AQUANTIA=y +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ASIX=y +CONFIG_NET_VENDOR_ATHEROS=y +CONFIG_NET_VENDOR_BROADCOM=y +CONFIG_NET_VENDOR_BROCADE=y +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_NET_VENDOR_CAVIUM is not set +CONFIG_NET_VENDOR_CHELSIO=y +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_NET_VENDOR_CORTINA is not set +CONFIG_NET_VENDOR_DAVICOM=y +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_VENDOR_DLINK=y +CONFIG_NET_VENDOR_EMULEX=y +CONFIG_NET_VENDOR_ENGLEDER=y +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_FUJITSU is not set +CONFIG_NET_VENDOR_FUNGIBLE=y +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_I825XX is not set +CONFIG_NET_VENDOR_INTEL=y +CONFIG_NET_VENDOR_LITEX=y +CONFIG_NET_VENDOR_MARVELL=y +CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y +CONFIG_NET_VENDOR_MICREL=y +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_NET_VENDOR_MICROSEMI is not set +CONFIG_NET_VENDOR_MICROSOFT=y +CONFIG_NET_VENDOR_MYRI=y +CONFIG_NET_VENDOR_NATSEMI=y +CONFIG_NET_VENDOR_NETERION=y +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NET_VENDOR_NI is not set +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_NET_VENDOR_OKI=y +CONFIG_NET_VENDOR_PACKET_ENGINES=y +CONFIG_NET_VENDOR_PENSANDO=y +CONFIG_NET_VENDOR_QLOGIC=y +CONFIG_NET_VENDOR_QUALCOMM=y +CONFIG_NET_VENDOR_RDC=y +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_NET_VENDOR_RENESAS is not set +CONFIG_NET_VENDOR_ROCKER=y +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SILAN=y +CONFIG_NET_VENDOR_SIS=y +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +CONFIG_NET_VENDOR_STMICRO=y +CONFIG_NET_VENDOR_SUN=y +# CONFIG_NET_VENDOR_SYNOPSYS is not set +CONFIG_NET_VENDOR_TEHUTI=y +CONFIG_NET_VENDOR_TI=y +CONFIG_NET_VENDOR_VERTEXCOM=y +CONFIG_NET_VENDOR_VIA=y +CONFIG_NET_VENDOR_WANGXUN=y +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_NET_VENDOR_XILINX=y +CONFIG_NET_VENDOR_XIRCOM=y +CONFIG_NET_VRF=m +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NETWORK_PHY_TIMESTAMPING=y +CONFIG_NETXEN_NIC=m +CONFIG_NET=y +CONFIG_NEW_LEDS=y +CONFIG_NFC_DIGITAL=m +# CONFIG_NFC_FDP is not set +CONFIG_NFC_HCI=m +CONFIG_NFC=m +CONFIG_NFC_MICROREAD_I2C=m +CONFIG_NFC_MICROREAD=m +# CONFIG_NFC_MRVL_I2C is not set +CONFIG_NFC_MRVL=m +# CONFIG_NFC_MRVL_SPI is not set +CONFIG_NFC_MRVL_USB=m +CONFIG_NFC_NCI=m +CONFIG_NFC_NCI_SPI=m +# CONFIG_NFC_NCI_UART is not set +CONFIG_NFC_NXP_NCI_I2C=m +CONFIG_NFC_NXP_NCI=m +CONFIG_NF_CONNTRACK_AMANDA=m +CONFIG_NF_CONNTRACK_BRIDGE=m +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_FTP=m +CONFIG_NF_CONNTRACK_H323=m +CONFIG_NF_CONNTRACK_IRC=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=m +CONFIG_NF_CONNTRACK_PPTP=m +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_SANE=m +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_SIP=m +CONFIG_NF_CONNTRACK_SNMP=m +CONFIG_NF_CONNTRACK_TFTP=m +# CONFIG_NF_CONNTRACK_TIMEOUT is not set +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NFC_PN532_UART=m +CONFIG_NFC_PN533_I2C=m +CONFIG_NFC_PN533=m +CONFIG_NFC_PN533_USB=m +CONFIG_NFC_PN544_I2C=m +CONFIG_NFC_PN544=m +CONFIG_NFC_PORT100=m +# CONFIG_NFC_S3FWRN5_I2C is not set +# CONFIG_NFC_S3FWRN82_UART is not set +CONFIG_NFC_SHDLC=y +CONFIG_NFC_SIM=m +CONFIG_NFC_ST21NFCA_I2C=m +CONFIG_NFC_ST21NFCA=m +# CONFIG_NFC_ST95HF is not set +# CONFIG_NFC_ST_NCI_I2C is not set +# CONFIG_NFC_ST_NCI_SPI is not set +CONFIG_NF_CT_NETLINK=m +# CONFIG_NF_CT_PROTO_DCCP is not set +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NFC_TRF7970A=m +# CONFIG_NFC_VIRTUAL_NCI is not set +CONFIG_NF_DUP_IPV4=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_DUP_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=m +CONFIG_NF_FLOW_TABLE_IPV4=m +CONFIG_NF_FLOW_TABLE_IPV6=m +CONFIG_NF_FLOW_TABLE=m +CONFIG_NF_FLOW_TABLE_PROCFS=y +# CONFIG_NFIT_SECURITY_DEBUG is not set +CONFIG_NF_LOG_ARP=m +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_LOG_IPV6=m +CONFIG_NF_LOG_SYSLOG=m +CONFIG_NF_NAT=m +CONFIG_NF_NAT_SNMP_BASIC=m +# CONFIG_NFP_APP_ABM_NIC is not set +CONFIG_NFP_APP_FLOWER=y +# CONFIG_NFP_DEBUG is not set +CONFIG_NFP=m +CONFIG_NFP_NET_IPSEC=y +CONFIG_NF_REJECT_IPV4=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NFSD_BLOCKLAYOUT=y +CONFIG_NFSD_FLEXFILELAYOUT=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y +# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set +CONFIG_NFSD=m +CONFIG_NFSD_PNFS=y +CONFIG_NFSD_SCSILAYOUT=y +# CONFIG_NFSD_V2 is not set +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V4_2_INTER_SSC=y +CONFIG_NFSD_V4_SECURITY_LABEL=y +CONFIG_NFSD_V4=y +CONFIG_NFS_FSCACHE=y +CONFIG_NFS_FS=m +CONFIG_NF_SOCKET_IPV4=m +CONFIG_NF_SOCKET_IPV6=m +CONFIG_NFS_SWAP=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +# CONFIG_NFS_V2 is not set +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V3=m +CONFIG_NFS_V4_1_IMPLEMENTATION_ID_DOMAIN="kernel.org" +# CONFIG_NFS_V4_1_MIGRATION is not set +CONFIG_NFS_V4_1=y +# CONFIG_NFS_V4_2_READ_PLUS is not set +CONFIG_NFS_V4_2=y +CONFIG_NFS_V4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_TABLES_BRIDGE=m +CONFIG_NF_TABLES_INET=y +CONFIG_NF_TABLES_IPV4=y +CONFIG_NF_TABLES_IPV6=y +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m +CONFIG_NFT_COMPAT=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CT=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_DUP_NETDEV=m +CONFIG_NFT_FIB_INET=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NFT_FIB_NETDEV=m +CONFIG_NFT_FLOW_OFFLOAD=m +CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_HASH=m +CONFIG_NFT_LIMIT=m +# CONFIG_NFTL is not set +CONFIG_NFT_LOG=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_NAT=m +CONFIG_NFT_NUMGEN=m +CONFIG_NFT_OBJREF=m +# CONFIG_NFT_OSF is not set +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_REJECT=m +CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NFT_SOCKET=m +CONFIG_NFT_SYNPROXY=m +CONFIG_NFT_TPROXY=m +CONFIG_NFT_TUNNEL=m +CONFIG_NFT_XFRM=m +CONFIG_NGBE=m +CONFIG_N_GSM=m +CONFIG_N_HDLC=m +# CONFIG_NI903X_WDT is not set +CONFIG_NILFS2_FS=m +CONFIG_NINTENDO_FF=y +CONFIG_NITRO_ENCLAVES=m +# CONFIG_NITRO_ENCLAVES_MISC_DEV_TEST is not set +CONFIG_NIU=m +# CONFIG_NL80211_TESTMODE is not set +CONFIG_NLMON=m +CONFIG_NLS_ASCII=y +CONFIG_NLS_CODEPAGE_1250=m +CONFIG_NLS_CODEPAGE_1251=m +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_737=m +CONFIG_NLS_CODEPAGE_775=m +CONFIG_NLS_CODEPAGE_850=m +CONFIG_NLS_CODEPAGE_852=m +CONFIG_NLS_CODEPAGE_855=m +CONFIG_NLS_CODEPAGE_857=m +CONFIG_NLS_CODEPAGE_860=m +CONFIG_NLS_CODEPAGE_861=m +CONFIG_NLS_CODEPAGE_862=m +CONFIG_NLS_CODEPAGE_863=m +CONFIG_NLS_CODEPAGE_864=m +CONFIG_NLS_CODEPAGE_865=m +CONFIG_NLS_CODEPAGE_866=m +CONFIG_NLS_CODEPAGE_869=m +CONFIG_NLS_CODEPAGE_874=m +CONFIG_NLS_CODEPAGE_932=m +CONFIG_NLS_CODEPAGE_936=m +CONFIG_NLS_CODEPAGE_949=m +CONFIG_NLS_CODEPAGE_950=m +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_ISO8859_13=m +CONFIG_NLS_ISO8859_14=m +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_ISO8859_1=m +CONFIG_NLS_ISO8859_2=m +CONFIG_NLS_ISO8859_3=m +CONFIG_NLS_ISO8859_4=m +CONFIG_NLS_ISO8859_5=m +CONFIG_NLS_ISO8859_6=m +CONFIG_NLS_ISO8859_7=m +CONFIG_NLS_ISO8859_8=m +CONFIG_NLS_ISO8859_9=m +CONFIG_NLS_KOI8_R=m +CONFIG_NLS_KOI8_U=m +CONFIG_NLS_MAC_CELTIC=m +CONFIG_NLS_MAC_CENTEURO=m +CONFIG_NLS_MAC_CROATIAN=m +CONFIG_NLS_MAC_CYRILLIC=m +CONFIG_NLS_MAC_GAELIC=m +CONFIG_NLS_MAC_GREEK=m +CONFIG_NLS_MAC_ICELAND=m +CONFIG_NLS_MAC_INUIT=m +CONFIG_NLS_MAC_ROMANIAN=m +CONFIG_NLS_MAC_ROMAN=m +CONFIG_NLS_MAC_TURKISH=m +CONFIG_NLS_UCS2_UTILS=m +CONFIG_NLS_UTF8=m +CONFIG_NLS=y +# CONFIG_NMI_CHECK_CPU is not set +# CONFIG_NOA1305 is not set +CONFIG_NODES_SHIFT=2 +CONFIG_NO_HZ_FULL=y +# CONFIG_NO_HZ_IDLE is not set +CONFIG_NO_HZ=y +# CONFIG_NONPORTABLE is not set +CONFIG_NOP_USB_XCEIV=m +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_NOUVEAU_DEBUG=5 +CONFIG_NOUVEAU_DEBUG_DEFAULT=3 +# CONFIG_NOUVEAU_DEBUG_MMU is not set +# CONFIG_NOUVEAU_DEBUG_PUSH is not set +# CONFIG_NOUVEAU_LEGACY_CTX_SUPPORT is not set +CONFIG_NOZOMI=m +CONFIG_NR_CPUS=32 +CONFIG_NS83820=m +CONFIG_NSM=m +CONFIG_NTB_EPF=m +# CONFIG_NTB is not set +# CONFIG_NTFS3_64BIT_CLUSTER is not set +CONFIG_NTFS3_FS=m +CONFIG_NTFS3_FS_POSIX_ACL=y +CONFIG_NTFS3_LZX_XPRESS=y +# CONFIG_NTFS_FS is not set +CONFIG_NULL_TTY=m +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA=y +# CONFIG_NVDIMM_SECURITY_TEST is not set +# CONFIG_NVHE_EL2_DEBUG is not set +CONFIG_NVIDIA_SHIELD_FF=y +# CONFIG_NVIDIA_WMI_EC_BACKLIGHT is not set +CONFIG_NVME_AUTH=m +CONFIG_NVME_FC=m +CONFIG_NVME_HOST_AUTH=y +CONFIG_NVME_HWMON=y +CONFIG_NVMEM_LAYOUT_ONIE_TLV=m +CONFIG_NVMEM_LAYOUT_SL28_VPD=m +# CONFIG_NVMEM_QCOM_QFPROM is not set +# CONFIG_NVMEM_REBOOT_MODE is not set +CONFIG_NVMEM_RMEM=m +CONFIG_NVMEM_SYSFS=y +CONFIG_NVMEM_U_BOOT_ENV=m +CONFIG_NVME_MULTIPATH=y +CONFIG_NVMEM=y +CONFIG_NVME_RDMA=m +CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set +CONFIG_NVME_TARGET_FCLOOP=m +CONFIG_NVME_TARGET_FC=m +CONFIG_NVME_TARGET_LOOP=m +CONFIG_NVME_TARGET=m +CONFIG_NVME_TARGET_PASSTHRU=y +CONFIG_NVME_TARGET_RDMA=m +CONFIG_NVME_TARGET_TCP=m +CONFIG_NVME_TARGET_TCP_TLS=y +CONFIG_NVME_TCP=m +CONFIG_NVME_TCP_TLS=y +# CONFIG_NVME_VERBOSE_ERRORS is not set +# CONFIG_NVRAM is not set +# CONFIG_NVSW_SN2201 is not set +CONFIG_NXP_C45_TJA11XX_PHY=m +CONFIG_NXP_CBTX_PHY=m +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_OCFS2_DEBUG_FS is not set +# CONFIG_OCFS2_DEBUG_MASKLOG is not set +CONFIG_OCFS2_FS=m +CONFIG_OCFS2_FS_O2CB=m +# CONFIG_OCFS2_FS_STATS is not set +CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m +CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m +CONFIG_OCTEON_EP_VF=m +CONFIG_OF_FPGA_REGION=m +CONFIG_OF_GPIO=y +CONFIG_OF_KUNIT_TEST=m +CONFIG_OF_OVERLAY=y +CONFIG_OF_PMEM=m +# CONFIG_OF_UNITTEST is not set +CONFIG_OF=y +# CONFIG_OMFS_FS is not set +# CONFIG_OPAL_CORE is not set +# CONFIG_OPEN_DICE is not set +CONFIG_OPENVSWITCH_GENEVE=m +CONFIG_OPENVSWITCH_GRE=m +CONFIG_OPENVSWITCH=m +CONFIG_OPENVSWITCH_VXLAN=m +CONFIG_OPT3001=m +CONFIG_OPT4001=m +CONFIG_OPTPROBES=y +CONFIG_ORANGEFS_FS=m +CONFIG_OSF_PARTITION=y +CONFIG_OSNOISE_TRACER=y +CONFIG_OVERFLOW_KUNIT_TEST=m +# CONFIG_OVERLAY_FS_DEBUG is not set +# CONFIG_OVERLAY_FS_INDEX is not set +CONFIG_OVERLAY_FS=m +# CONFIG_OVERLAY_FS_METACOPY is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +CONFIG_PA12203001=m +CONFIG_PAC1934=m +CONFIG_PACKET_DIAG=y +CONFIG_PACKET=y +CONFIG_PACKING=y +CONFIG_PAGE_EXTENSION=y +CONFIG_PAGE_OWNER=y +CONFIG_PAGE_POISONING=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_REPORTING=y +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_TABLE_CHECK is not set +# CONFIG_PANEL_CHANGE_MESSAGE is not set +# CONFIG_PANEL is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PANTHERLORD_FF=y +CONFIG_PARAVIRT_TIME_ACCOUNTING=y +CONFIG_PARAVIRT=y +CONFIG_PARMAN=m +# CONFIG_PARPORT is not set +# CONFIG_PARPORT_PC is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_PATA_ACPI is not set +CONFIG_PATA_ALI=m +CONFIG_PATA_AMD=m +CONFIG_PATA_ARTOP=m +# CONFIG_PATA_ATIIXP is not set +CONFIG_PATA_ATP867X=m +CONFIG_PATA_CMD640_PCI=m +CONFIG_PATA_CMD64X=m +CONFIG_PATA_CS5520=m +CONFIG_PATA_CS5530=m +CONFIG_PATA_CS5535=m +CONFIG_PATA_CS5536=m +# CONFIG_PATA_CYPRESS is not set +CONFIG_PATA_EFAR=m +CONFIG_PATA_HPT366=m +CONFIG_PATA_HPT37X=m +CONFIG_PATA_HPT3X2N=m +# CONFIG_PATA_HPT3X3_DMA is not set +CONFIG_PATA_HPT3X3=m +CONFIG_PATA_IT8213=m +CONFIG_PATA_IT821X=m +CONFIG_PATA_JMICRON=m +# CONFIG_PATA_LEGACY is not set +CONFIG_PATA_MARVELL=m +# CONFIG_PATA_MPIIX is not set +CONFIG_PATA_NETCELL=m +CONFIG_PATA_NINJA32=m +CONFIG_PATA_NS87410=m +CONFIG_PATA_NS87415=m +# CONFIG_PATA_OF_PLATFORM is not set +# CONFIG_PATA_OLDPIIX is not set +CONFIG_PATA_OPTIDMA=m +CONFIG_PATA_OPTI=m +# CONFIG_PATA_PARPORT is not set +CONFIG_PATA_PDC2027X=m +CONFIG_PATA_PDC_OLD=m +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +CONFIG_PATA_SERVERWORKS=m +CONFIG_PATA_SIL680=m +CONFIG_PATA_SIS=m +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +CONFIG_PATA_VIA=m +CONFIG_PATA_WINBOND=m +# CONFIG_PC104 is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_PCCARD is not set +# CONFIG_PCH_GBE is not set +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_DYNAMIC_OF_NODES is not set +CONFIG_PCIEAER_CXL=y +CONFIG_PCIEAER_INJECT=m +CONFIG_PCIEAER=y +# CONFIG_PCIE_ALTERA is not set +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_PERFORMANCE is not set +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +CONFIG_PCIEASPM=y +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_PEER2PEER is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_CADENCE_HOST=y +CONFIG_PCIE_CADENCE_PLAT_EP=y +# CONFIG_PCIE_CADENCE_PLAT_HOST is not set +CONFIG_PCIE_DPC=y +# CONFIG_PCIE_DW_PLAT_HOST is not set +CONFIG_PCIE_ECRC=y +CONFIG_PCIE_EDR=y +CONFIG_PCIE_FU740=y +# CONFIG_PCIE_LAYERSCAPE_GEN4 is not set +CONFIG_PCIE_MICROCHIP_HOST=y +# CONFIG_PCIE_MOBIVEIL is not set +# CONFIG_PCI_ENDPOINT is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +CONFIG_PCIEPORTBUS=y +CONFIG_PCIE_PTM=y +# CONFIG_PCIE_STARFIVE_HOST is not set +CONFIG_PCIE_XILINX_CPM=y +CONFIG_PCIE_XILINX=y +# CONFIG_PCI_FTPCI100 is not set +# CONFIG_PCI_GOOLPC is not set +CONFIG_PCI_HOST_COMMON=y +CONFIG_PCI_HOST_GENERIC=y +CONFIG_PCI_HYPERV=m +CONFIG_PCI_IOV=y +CONFIG_PCI_J721E_HOST=y +# CONFIG_PCI_MESON is not set +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_MSI=y +CONFIG_PCI_P2PDMA=y +CONFIG_PCI_PASID=y +CONFIG_PCIPCWATCHDOG=m +CONFIG_PCI_PF_STUB=m +CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +CONFIG_PCI_STUB=y +CONFIG_PCI_SW_SWITCHTEC=m +CONFIG_PCI=y +CONFIG_PCNET32=m +CONFIG_PCP_BATCH_SCALE_MAX=5 +CONFIG_PCPU_DEV_REFCNT=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_PCS_XPCS=m +# CONFIG_PDA_POWER is not set +CONFIG_PDC_ADMA=m +CONFIG_PDS_CORE=m +CONFIG_PDS_VDPA=m +CONFIG_PDS_VFIO_PCI=m +# CONFIG_PECI is not set +# CONFIG_PERCPU_STATS is not set +# CONFIG_PERCPU_TEST is not set +CONFIG_PERF_EVENTS_AMD_UNCORE=y +CONFIG_PERF_EVENTS=y +CONFIG_PERSISTENT_KEYRINGS=y +# CONFIG_PER_VMA_LOCK_STATS is not set +CONFIG_PFCP=m +# CONFIG_PHANTOM is not set +# CONFIG_PHONET is not set +CONFIG_PHY_CADENCE_DPHY=m +CONFIG_PHY_CADENCE_DPHY_RX=m +CONFIG_PHY_CADENCE_SALVO=m +CONFIG_PHY_CADENCE_SIERRA=m +CONFIG_PHY_CADENCE_TORRENT=m +# CONFIG_PHY_CAN_TRANSCEIVER is not set +# CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_HI3670_PCIE is not set +# CONFIG_PHY_HI3670_USB is not set +# CONFIG_PHY_LAN966X_SERDES is not set +CONFIG_PHYLIB=y +CONFIG_PHYLINK=m +# CONFIG_PHY_MAPPHONE_MDM6600 is not set +# CONFIG_PHY_OCELOT_SERDES is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_QCOM_EDP is not set +# CONFIG_PHY_QCOM_IPQ4019_USB is not set +# CONFIG_PHY_QCOM_IPQ806X_USB is not set +# CONFIG_PHY_QCOM_USB_HS_28NM is not set +# CONFIG_PHY_QCOM_USB_HSIC is not set +# CONFIG_PHY_QCOM_USB_HS is not set +# CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2 is not set +# CONFIG_PHY_QCOM_USB_SS is not set +CONFIG_PHY_RTK_RTD_USB2PHY=m +CONFIG_PHY_RTK_RTD_USB3PHY=m +# CONFIG_PHY_SAMSUNG_USB2 is not set +# CONFIG_PHYS_RAM_BASE_FIXED is not set +CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=m +# CONFIG_PHY_STARFIVE_JH7110_DPHY_TX is not set +CONFIG_PHY_STARFIVE_JH7110_PCIE=m +CONFIG_PHY_STARFIVE_JH7110_USB=m +# CONFIG_PHY_TUSB1210 is not set +# CONFIG_PI433 is not set +CONFIG_PID_NS=y +CONFIG_PINCONF=y +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_AW9523 is not set +CONFIG_PINCTRL_AXP209=m +CONFIG_PINCTRL_CS42L43=m +CONFIG_PINCTRL_CY8C95X0=m +# CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IPQ6018 is not set +# CONFIG_PINCTRL_IPQ8074 is not set +# CONFIG_PINCTRL_LPASS_LPI is not set +# CONFIG_PINCTRL_MCP23S08 is not set +CONFIG_PINCTRL_MESON=y +# CONFIG_PINCTRL_MICROCHIP_SGPIO is not set +# CONFIG_PINCTRL_MSM8226 is not set +# CONFIG_PINCTRL_MSM8953 is not set +# CONFIG_PINCTRL_MSM8976 is not set +# CONFIG_PINCTRL_MSM is not set +# CONFIG_PINCTRL_OCELOT is not set +# CONFIG_PINCTRL_QCS404 is not set +CONFIG_PINCTRL_RK805=m +# CONFIG_PINCTRL_SC7180 is not set +# CONFIG_PINCTRL_SC8180X is not set +# CONFIG_PINCTRL_SDM660 is not set +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_SM8150 is not set +# CONFIG_PINCTRL_SM8250 is not set +# CONFIG_PINCTRL_SM8350 is not set +CONFIG_PINCTRL_SM8350_LPASS_LPI=m +# CONFIG_PINCTRL_SM8450 is not set +CONFIG_PINCTRL_STARFIVE_JH7100=y +CONFIG_PINCTRL_STARFIVE_JH7110_AON=y +CONFIG_PINCTRL_STARFIVE_JH7110_SYS=y +CONFIG_PINCTRL_STARFIVE_JH7110=y +CONFIG_PINCTRL_STARFIVE=y +# CONFIG_PINCTRL_STMFX is not set +CONFIG_PINCTRL_SUN20I_D1=y +# CONFIG_PINCTRL_SX150X is not set +CONFIG_PINCTRL_TPS6594=m +CONFIG_PINCTRL=y +# CONFIG_PING is not set +CONFIG_PINMUX=y +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +CONFIG_PKCS8_PRIVATE_KEY_PARSER=m +# CONFIG_PL320_MBOX is not set +# CONFIG_PL330_DMA is not set +# CONFIG_PLATFORM_MHU is not set +# CONFIG_PLATFORM_SI4713 is not set +CONFIG_PLAYSTATION_FF=y +# CONFIG_PLFXLC is not set +# CONFIG_PLIP is not set +# CONFIG_PLX_DMA is not set +# CONFIG_PM_ADVANCED_DEBUG is not set +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PMBUS=m +CONFIG_PM_DEBUG=y +# CONFIG_PM_DEVFREQ is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_PMIC_OPREGION is not set +CONFIG_PM_OPP=y +CONFIG_PMS7003=m +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_TRACE_RTC=y +CONFIG_PM_TRACE=y +# CONFIG_PM_USERSPACE_AUTOSLEEP is not set +# CONFIG_PMU_SYSFS is not set +# CONFIG_PM_WAKELOCKS is not set +CONFIG_PM=y +CONFIG_PNFS_BLOCK=m +CONFIG_PNP_DEBUG_MESSAGES=y +# CONFIG_POLARFIRE_SOC_MAILBOX is not set +CONFIG_PORTABLE=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_TIMERS=y +CONFIG_POWERCAP=y +# CONFIG_POWER_RESET_BRCMKONA is not set +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_GPIO=y +# CONFIG_POWER_RESET_LINKSTATION is not set +# CONFIG_POWER_RESET_LTC2952 is not set +# CONFIG_POWER_RESET_REGULATOR is not set +CONFIG_POWER_RESET_RESTART=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_TPS65086=y +# CONFIG_POWER_RESET_VEXPRESS is not set +CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +CONFIG_POWER_SUPPLY=y +# CONFIG_PPC_PROT_SAO_LPAR is not set +CONFIG_PPC_QUEUED_SPINLOCKS=y +CONFIG_PPC_RTAS_FILTER=y +CONFIG_PPDEV=m +CONFIG_PPP_ASYNC=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_FILTER=y +CONFIG_PPP=m +CONFIG_PPP_MPPE=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPPOATM=m +# CONFIG_PPPOE_HASH_BITS_1 is not set +# CONFIG_PPPOE_HASH_BITS_2 is not set +CONFIG_PPPOE_HASH_BITS_4=y +# CONFIG_PPPOE_HASH_BITS_8 is not set +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPS_CLIENT_GPIO=m +# CONFIG_PPS_CLIENT_KTIMER is not set +CONFIG_PPS_CLIENT_LDISC=m +# CONFIG_PPS_DEBUG is not set +CONFIG_PPS=y +CONFIG_PPTP=m +CONFIG_PREEMPT_DYNAMIC=y +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_PREEMPT is not set +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_TRACER is not set +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_PRESTERA=m +CONFIG_PRESTERA_PCI=m +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_PRIME_NUMBERS=m +CONFIG_PRINTER=m +# CONFIG_PRINTK_CALLER is not set +CONFIG_PRINTK_INDEX=y +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=12 +CONFIG_PRINTK_TIME=y +CONFIG_PRINTK=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_PRISM2_USB is not set +CONFIG_PROBE_EVENTS_BTF_ARGS=y +CONFIG_PROC_CHILDREN=y +# CONFIG_PROCESSOR_SELECT is not set +CONFIG_PROC_EVENTS=y +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_VMCORE_DEVICE_DUMP=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +CONFIG_PROFILING=y +CONFIG_PROVE_CXL_LOCKING=y +# CONFIG_PROVE_LOCKING is not set +# CONFIG_PROVE_NVDIMM_LOCKING is not set +# CONFIG_PROVE_RAW_LOCK_NESTING is not set +CONFIG_PSAMPLE=m +# CONFIG_PSE_CONTROLLER is not set +# CONFIG_PSI_DEFAULT_DISABLED is not set +CONFIG_PSI=y +# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_842_COMPRESS=y +# CONFIG_PSTORE_BLK is not set +CONFIG_PSTORE_COMPRESS=y +# CONFIG_PSTORE_CONSOLE is not set +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZ4_COMPRESS=m +# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZ4HC_COMPRESS=m +# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set +CONFIG_PSTORE_LZO_COMPRESS=m +# CONFIG_PSTORE_PMSG is not set +CONFIG_PSTORE_RAM=m +CONFIG_PSTORE=y +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +# CONFIG_PTDUMP_DEBUGFS is not set +CONFIG_PTE_MARKER_UFFD_WP=y +CONFIG_PTP_1588_CLOCK_FC3W=m +CONFIG_PTP_1588_CLOCK_IDT82P33=m +CONFIG_PTP_1588_CLOCK_IDTCM=m +# CONFIG_PTP_1588_CLOCK_INES is not set +CONFIG_PTP_1588_CLOCK_KVM=m +CONFIG_PTP_1588_CLOCK_MOCK=m +# CONFIG_PTP_1588_CLOCK_OCP is not set +CONFIG_PTP_1588_CLOCK_PCH=m +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_DFL_TOD=m +# CONFIG_PVPANIC_MMIO is not set +# CONFIG_PVPANIC_PCI is not set +CONFIG_PVPANIC=y +# CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m +# CONFIG_PWM_CLK is not set +# CONFIG_PWM_DEBUG is not set +CONFIG_PWM_DWC=m +# CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m +CONFIG_PWM_HIBVT=m +# CONFIG_PWM_MICROCHIP_CORE is not set +CONFIG_PWM_OMAP_DMTIMER=m +# CONFIG_PWM_PCA9685 is not set +CONFIG_PWM_SIFIVE=y +CONFIG_PWM_SYSFS=y +# CONFIG_PWM_XILINX is not set +CONFIG_PWM=y +CONFIG_PWRSEQ_EMMC=y +CONFIG_PWRSEQ_SD8787=m +CONFIG_PWRSEQ_SIMPLE=m +CONFIG_QAT_VFIO_PCI=m +# CONFIG_QCA7000_SPI is not set +# CONFIG_QCA7000_UART is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m +# CONFIG_QCOM_A7PLL is not set +# CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_EMAC is not set +# CONFIG_QCOM_GPI_DMA is not set +# CONFIG_QCOM_HIDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_IPCC is not set +# CONFIG_QCOM_LMH is not set +# CONFIG_QCOM_OCMEM is not set +CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set +# CONFIG_QCOM_PMIC_GLINK is not set +# CONFIG_QCOM_PMIC_PDCHARGER_ULOG is not set +# CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set +# CONFIG_QCOM_SCM is not set +# CONFIG_QCOM_SPM is not set +# CONFIG_QCS_TURING_404 is not set +CONFIG_QEDE=m +CONFIG_QEDF=m +CONFIG_QEDI=m +CONFIG_QED=m +CONFIG_QED_SRIOV=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QLA3XXX=m +CONFIG_QLCNIC_DCB=y +CONFIG_QLCNIC_HWMON=y +CONFIG_QLCNIC=m +CONFIG_QLCNIC_SRIOV=y +CONFIG_QLGE=m +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +CONFIG_QRTR=m +CONFIG_QRTR_MHI=m +# CONFIG_QRTR_SMD is not set +# CONFIG_QRTR_TUN is not set +CONFIG_QSEMI_PHY=m +CONFIG_QTNFMAC_PCIE=m +# CONFIG_QUICC_ENGINE is not set +CONFIG_QUOTACTL=y +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_NETLINK_INTERFACE=y +CONFIG_QUOTA=y +CONFIG_R6040=m +CONFIG_R8169=m +CONFIG_R8712U=m +CONFIG_RADIO_ADAPTERS=m +CONFIG_RADIO_MAXIRADIO=m +CONFIG_RADIO_SAA7706H=m +CONFIG_RADIO_SHARK2=m +CONFIG_RADIO_SHARK=m +CONFIG_RADIO_SI470X=m +CONFIG_RADIO_SI4713=m +CONFIG_RADIO_TEA5764=m +# CONFIG_RADIO_TEF6862 is not set +CONFIG_RADIO_WL1273=m +# CONFIG_RAID6_PQ_BENCHMARK is not set +CONFIG_RAID_ATTRS=m +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_RANDOMIZE_BASE=y +CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y +CONFIG_RANDOMIZE_KSTACK_OFFSET=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_RANDOM_KMALLOC_CACHES=y +CONFIG_RANDOM_TRUST_BOOTLOADER=y +CONFIG_RANDOM_TRUST_CPU=y +# CONFIG_RANDSTRUCT_FULL is not set +CONFIG_RANDSTRUCT_NONE=y +# CONFIG_RANDSTRUCT_PERFORMANCE is not set +CONFIG_RAPIDIO_CHMAN=m +CONFIG_RAPIDIO_CPS_GEN2=m +CONFIG_RAPIDIO_CPS_XX=m +# CONFIG_RAPIDIO_DEBUG is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_ENUM_BASIC=m +CONFIG_RAPIDIO=m +CONFIG_RAPIDIO_MPORT_CDEV=m +CONFIG_RAPIDIO_RXS_GEN3=m +CONFIG_RAPIDIO_TSI568=m +CONFIG_RAPIDIO_TSI57X=m +CONFIG_RAPIDIO_TSI721=m +CONFIG_RAS_FMPM=m +CONFIG_RATIONAL_KUNIT_TEST=m +# CONFIG_RAVE_SP_CORE is not set +# CONFIG_RBTREE_TEST is not set +CONFIG_RC_ATI_REMOTE=m +CONFIG_RC_CORE=y +CONFIG_RC_DECODERS=y +CONFIG_RC_DEVICES=y +CONFIG_RC_LOOPBACK=m +CONFIG_RC_MAP=m +# CONFIG_RCU_CPU_STALL_CPUTIME is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_EQS_DEBUG is not set +CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=0 +# CONFIG_RCU_EXPERT is not set +# CONFIG_RCU_LAZY is not set +# CONFIG_RCU_NOCB_CPU_DEFAULT_ALL is not set +CONFIG_RCU_NOCB_CPU=y +# CONFIG_RCU_REF_SCALE_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set +CONFIG_RCU_TORTURE_TEST=m +# CONFIG_RCU_TRACE is not set +CONFIG_RC_XBOX_DVD=m +CONFIG_RD_BZIP2=y +CONFIG_RD_GZIP=y +CONFIG_RD_LZ4=y +CONFIG_RD_LZMA=y +CONFIG_RD_LZO=y +CONFIG_RDMA_RXE=m +CONFIG_RDMA_SIW=m +# CONFIG_RDS_DEBUG is not set +CONFIG_RDS=m +CONFIG_RDS_RDMA=m +CONFIG_RDS_TCP=m +CONFIG_RD_XZ=y +CONFIG_RD_ZSTD=y +# CONFIG_READABLE_ASM is not set +CONFIG_READ_ONLY_THP_FOR_FS=y +CONFIG_REALTEK_AUTOPM=y +CONFIG_REALTEK_PHY=m +# CONFIG_REED_SOLOMON_TEST is not set +# CONFIG_REGMAP_BUILD is not set +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_KUNIT=m +CONFIG_REGMAP_SPI=m +CONFIG_REGMAP=y +# CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m +# CONFIG_REGULATOR_ACT8865 is not set +# CONFIG_REGULATOR_AD5398 is not set +CONFIG_REGULATOR_ANATOP=m +CONFIG_REGULATOR_AW37503=m +CONFIG_REGULATOR_AXP20X=m +CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m +CONFIG_REGULATOR_DA9063=m +# CONFIG_REGULATOR_DA9121 is not set +# CONFIG_REGULATOR_DA9210 is not set +# CONFIG_REGULATOR_DA9211 is not set +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_FAN53555 is not set +# CONFIG_REGULATOR_FAN53880 is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_ISL9305 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +# CONFIG_REGULATOR_LTC3589 is not set +# CONFIG_REGULATOR_LTC3676 is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX20086 is not set +CONFIG_REGULATOR_MAX20411=m +CONFIG_REGULATOR_MAX5970=m +CONFIG_REGULATOR_MAX597X=m +CONFIG_REGULATOR_MAX77503=m +CONFIG_REGULATOR_MAX77650=m +# CONFIG_REGULATOR_MAX77826 is not set +CONFIG_REGULATOR_MAX77857=m +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +CONFIG_REGULATOR_MAX8893=m +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MCP16502 is not set +CONFIG_REGULATOR_MP5416=m +# CONFIG_REGULATOR_MP8859 is not set +CONFIG_REGULATOR_MP886X=m +# CONFIG_REGULATOR_MPQ7920 is not set +# CONFIG_REGULATOR_MT6311 is not set +CONFIG_REGULATOR_MT6370=m +# CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set +# CONFIG_REGULATOR_PF8X00 is not set +# CONFIG_REGULATOR_PFUZE100 is not set +# CONFIG_REGULATOR_PV88060 is not set +# CONFIG_REGULATOR_PV88080 is not set +# CONFIG_REGULATOR_PV88090 is not set +CONFIG_REGULATOR_PWM=y +CONFIG_REGULATOR_RAA215300=m +# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set +CONFIG_REGULATOR_RT4801=m +CONFIG_REGULATOR_RT4803=m +CONFIG_REGULATOR_RT4831=m +CONFIG_REGULATOR_RT5120=m +CONFIG_REGULATOR_RT5190A=m +CONFIG_REGULATOR_RT5739=m +CONFIG_REGULATOR_RT5759=m +CONFIG_REGULATOR_RT6160=m +CONFIG_REGULATOR_RT6190=m +CONFIG_REGULATOR_RT6245=m +CONFIG_REGULATOR_RTMV20=m +CONFIG_REGULATOR_RTQ2134=m +CONFIG_REGULATOR_RTQ2208=m +CONFIG_REGULATOR_RTQ6752=m +# CONFIG_REGULATOR_SLG51000 is not set +# CONFIG_REGULATOR_SUN20I is not set +CONFIG_REGULATOR_SY7636A=m +# CONFIG_REGULATOR_SY8106A is not set +# CONFIG_REGULATOR_SY8824X is not set +# CONFIG_REGULATOR_SY8827N is not set +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +CONFIG_REGULATOR_TPS6286X=m +# CONFIG_REGULATOR_TPS6287X is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS65132 is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_REGULATOR_TPS6594=m +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +CONFIG_REGULATOR_VCTRL=m +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_VQMMC_IPQ4019 is not set +CONFIG_REGULATOR_WM8994=m +CONFIG_REGULATOR=y +# CONFIG_REISERFS_CHECK is not set +CONFIG_REISERFS_FS=m +CONFIG_REISERFS_FS_POSIX_ACL=y +CONFIG_REISERFS_FS_SECURITY=y +CONFIG_REISERFS_FS_XATTR=y +CONFIG_REISERFS_PROC_INFO=y +CONFIG_RELAY=y +# CONFIG_RELOCATABLE_TEST is not set +CONFIG_RELOCATABLE=y +# CONFIG_REMOTEPROC_CDEV is not set +CONFIG_REMOTEPROC=y +CONFIG_REMOTE_TARGET=m +# CONFIG_RENESAS_PHY is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +CONFIG_RESET_GPIO=m +# CONFIG_RESET_INTEL_GW is not set +CONFIG_RESET_POLARFIRE_SOC=y +CONFIG_RESET_SIMPLE=y +CONFIG_RESET_STARFIVE_JH7100=y +CONFIG_RESET_STARFIVE_JH7110=y +CONFIG_RESET_STARFIVE_JH71X0=y +# CONFIG_RESET_TI_SYSCON is not set +CONFIG_RESET_TI_TPS380X=m +CONFIG_RESOURCE_KUNIT_TEST=m +# CONFIG_RFD77402 is not set +# CONFIG_RFD_FTL is not set +CONFIG_RFKILL_GPIO=m +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y +# CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set +CONFIG_RICHTEK_RTQ6056=m +CONFIG_RING_BUFFER_BENCHMARK=m +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +CONFIG_RIONET=m +CONFIG_RIONET_RX_SIZE=128 +CONFIG_RIONET_TX_SIZE=128 +CONFIG_RISCV_ALTERNATIVE_EARLY=y +CONFIG_RISCV_ALTERNATIVE=y +CONFIG_RISCV_BASE_PMU=y +# CONFIG_RISCV_BOOT_SPINWAIT is not set +# CONFIG_RISCV_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_RISCV_EMULATED_UNALIGNED_ACCESS is not set +CONFIG_RISCV_INTC=y +CONFIG_RISCV_ISA_C=y +CONFIG_RISCV_ISA_FALLBACK=y +CONFIG_RISCV_ISA_SVNAPOT=y +CONFIG_RISCV_ISA_SVPBMT=y +CONFIG_RISCV_ISA_V_DEFAULT_ENABLE=y +CONFIG_RISCV_ISA_VENDOR_EXT_ANDES=y +CONFIG_RISCV_ISA_V_PREEMPTIVE=y +CONFIG_RISCV_ISA_V_UCOPY_THRESHOLD=768 +CONFIG_RISCV_ISA_V=y +CONFIG_RISCV_ISA_ZAWRS=y +CONFIG_RISCV_ISA_ZBA=y +CONFIG_RISCV_ISA_ZBB=y +CONFIG_RISCV_ISA_ZBC=y +CONFIG_RISCV_ISA_ZICBOM=y +CONFIG_RISCV_ISA_ZICBOZ=y +CONFIG_RISCV_MISALIGNED=y +# CONFIG_RISCV_MODULE_LINKING_KUNIT is not set +CONFIG_RISCV_PLIC=y +CONFIG_RISCV_PMU_LEGACY=y +CONFIG_RISCV_PMU_SBI=y +CONFIG_RISCV_PMU=y +CONFIG_RISCV_PROBE_UNALIGNED_ACCESS=y +CONFIG_RISCV_SBI_CPUIDLE=y +# CONFIG_RISCV_SBI_V01 is not set +CONFIG_RISCV_SBI=y +CONFIG_RISCV_TIMER=y +CONFIG_RMI4_CORE=m +CONFIG_RMI4_F03=y +CONFIG_RMI4_F11=y +CONFIG_RMI4_F12=y +CONFIG_RMI4_F30=y +CONFIG_RMI4_F34=y +CONFIG_RMI4_F3A=y +# CONFIG_RMI4_F54 is not set +CONFIG_RMI4_F55=y +CONFIG_RMI4_I2C=m +CONFIG_RMI4_SMB=m +CONFIG_RMI4_SPI=m +CONFIG_RMNET=m +# CONFIG_ROCKCHIP_PHY is not set +CONFIG_ROCKER=m +# CONFIG_ROHM_BM1390 is not set +# CONFIG_ROHM_BU27008 is not set +CONFIG_ROHM_BU27034=m +CONFIG_ROMFS_BACKED_BY_BLOCK=y +# CONFIG_ROMFS_BACKED_BY_BOTH is not set +# CONFIG_ROMFS_BACKED_BY_MTD is not set +CONFIG_ROMFS_FS=m +CONFIG_ROSE=m +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA1=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y +CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y +# CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_DES is not set +CONFIG_RPCSEC_GSS_KRB5_KUNIT_TEST=m +CONFIG_RPCSEC_GSS_KRB5=m +CONFIG_RPMSG_CHAR=m +CONFIG_RPMSG_CTRL=m +CONFIG_RPMSG=m +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +CONFIG_RPMSG_TTY=m +CONFIG_RPMSG_VIRTIO=m +CONFIG_RPMSG_WWAN_CTRL=m +CONFIG_RPR0521=m +CONFIG_RPS=y +CONFIG_RSEQ=y +CONFIG_RSI_91X=m +CONFIG_RSI_COEX=y +CONFIG_RSI_DEBUGFS=y +CONFIG_RSI_SDIO=m +CONFIG_RSI_USB=m +CONFIG_RT2400PCI=m +CONFIG_RT2500PCI=m +CONFIG_RT2500USB=m +CONFIG_RT2800PCI=m +CONFIG_RT2800PCI_RT3290=y +CONFIG_RT2800PCI_RT33XX=y +CONFIG_RT2800PCI_RT35XX=y +CONFIG_RT2800PCI_RT53XX=y +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT3573=y +CONFIG_RT2800USB_RT35XX=y +CONFIG_RT2800USB_RT53XX=y +CONFIG_RT2800USB_RT55XX=y +CONFIG_RT2800USB_UNKNOWN=y +# CONFIG_RT2X00_DEBUG is not set +CONFIG_RT2X00_LIB_DEBUGFS=y +CONFIG_RT2X00=m +CONFIG_RT61PCI=m +CONFIG_RT73USB=m +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DEBUG is not set +# CONFIG_RTC_DRV_ABB5ZES3 is not set +CONFIG_RTC_DRV_ABEOZ9=m +CONFIG_RTC_DRV_ABX80X=m +CONFIG_RTC_DRV_BQ32K=m +# CONFIG_RTC_DRV_CADENCE is not set +CONFIG_RTC_DRV_CMOS=y +CONFIG_RTC_DRV_DA9063=m +CONFIG_RTC_DRV_DS1286=m +# CONFIG_RTC_DRV_DS1302 is not set +CONFIG_RTC_DRV_DS1305=m +# CONFIG_RTC_DRV_DS1307_CENTURY is not set +CONFIG_RTC_DRV_DS1307=m +CONFIG_RTC_DRV_DS1343=m +CONFIG_RTC_DRV_DS1347=m +CONFIG_RTC_DRV_DS1374=m +CONFIG_RTC_DRV_DS1374_WDT=y +CONFIG_RTC_DRV_DS1390=m +CONFIG_RTC_DRV_DS1511=m +CONFIG_RTC_DRV_DS1553=m +CONFIG_RTC_DRV_DS1672=m +CONFIG_RTC_DRV_DS1685_FAMILY=m +CONFIG_RTC_DRV_DS1685=y +# CONFIG_RTC_DRV_DS1689 is not set +# CONFIG_RTC_DRV_DS17285 is not set +CONFIG_RTC_DRV_DS1742=m +# CONFIG_RTC_DRV_DS17485 is not set +# CONFIG_RTC_DRV_DS17885 is not set +CONFIG_RTC_DRV_DS2404=m +# CONFIG_RTC_DRV_DS3232_HWMON is not set +CONFIG_RTC_DRV_DS3232=m +CONFIG_RTC_DRV_EFI=m +CONFIG_RTC_DRV_EM3027=m +CONFIG_RTC_DRV_FM3130=m +# CONFIG_RTC_DRV_FTRTC010 is not set +CONFIG_RTC_DRV_GOLDFISH=y +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +# CONFIG_RTC_DRV_HYM8563 is not set +CONFIG_RTC_DRV_ISL12022=m +CONFIG_RTC_DRV_ISL12026=m +CONFIG_RTC_DRV_ISL1208=m +CONFIG_RTC_DRV_M41T80=m +CONFIG_RTC_DRV_M41T80_WDT=y +CONFIG_RTC_DRV_M41T93=m +CONFIG_RTC_DRV_M41T94=m +CONFIG_RTC_DRV_M48T35=m +CONFIG_RTC_DRV_M48T59=m +# CONFIG_RTC_DRV_M48T86 is not set +CONFIG_RTC_DRV_MAX31335=m +CONFIG_RTC_DRV_MAX6900=m +CONFIG_RTC_DRV_MAX6902=m +CONFIG_RTC_DRV_MAX6916=m +CONFIG_RTC_DRV_MAX77686=m +CONFIG_RTC_DRV_MCP795=m +CONFIG_RTC_DRV_MSM6242=m +CONFIG_RTC_DRV_NCT3018Y=m +CONFIG_RTC_DRV_PCF2123=m +CONFIG_RTC_DRV_PCF2127=m +CONFIG_RTC_DRV_PCF85063=m +CONFIG_RTC_DRV_PCF8523=m +# CONFIG_RTC_DRV_PCF85363 is not set +CONFIG_RTC_DRV_PCF8563=m +CONFIG_RTC_DRV_PCF8583=m +# CONFIG_RTC_DRV_PL030 is not set +# CONFIG_RTC_DRV_PL031 is not set +# CONFIG_RTC_DRV_PM8XXX is not set +# CONFIG_RTC_DRV_POLARFIRE_SOC is not set +CONFIG_RTC_DRV_R7301=m +CONFIG_RTC_DRV_R9701=m +CONFIG_RTC_DRV_RP5C01=m +CONFIG_RTC_DRV_RS5C348=m +CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_RV3028=m +CONFIG_RTC_DRV_RV3029C2=m +CONFIG_RTC_DRV_RV3029_HWMON=y +CONFIG_RTC_DRV_RV3032=m +# CONFIG_RTC_DRV_RV8803 is not set +CONFIG_RTC_DRV_RX4581=m +# CONFIG_RTC_DRV_RX6110 is not set +CONFIG_RTC_DRV_RX8010=m +CONFIG_RTC_DRV_RX8025=m +# CONFIG_RTC_DRV_RX8111 is not set +CONFIG_RTC_DRV_RX8581=m +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_SA1100 is not set +CONFIG_RTC_DRV_SD3078=m +# CONFIG_RTC_DRV_SNVS is not set +CONFIG_RTC_DRV_STK17TA8=m +# CONFIG_RTC_DRV_TEST is not set +CONFIG_RTC_DRV_TPS6594=m +CONFIG_RTC_DRV_V3020=m +CONFIG_RTC_DRV_X1205=m +# CONFIG_RTC_DRV_ZYNQMP is not set +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +CONFIG_RTC_HCTOSYS=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_LIB_KUNIT_TEST=m +CONFIG_RTC_NVMEM=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +CONFIG_RTC_SYSTOHC=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_RTL8180=m +CONFIG_RTL8187=m +CONFIG_RTL8188EE=m +CONFIG_RTL8192CE=m +# CONFIG_RTL8192CU is not set +CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m +CONFIG_RTL8192EE=m +CONFIG_RTL8192E=m +CONFIG_RTL8192SE=m +# CONFIG_RTL8192U is not set +CONFIG_RTL8723AE=m +CONFIG_RTL8723BE=m +CONFIG_RTL8723BS=m +CONFIG_RTL8821AE=m +CONFIG_RTL8XXXU=m +CONFIG_RTL8XXXU_UNTESTED=y +CONFIG_RTL_CARDS=m +CONFIG_RTLLIB_CRYPTO_CCMP=m +CONFIG_RTLLIB_CRYPTO_TKIP=m +CONFIG_RTLLIB_CRYPTO_WEP=m +CONFIG_RTLLIB=m +# CONFIG_RTLWIFI_DEBUG is not set +CONFIG_RTLWIFI=m +# CONFIG_RTS5208 is not set +CONFIG_RTW88_8723CS=m +CONFIG_RTW88_8723DE=m +CONFIG_RTW88_8723DS=m +CONFIG_RTW88_8723DU=m +CONFIG_RTW88_8821CE=m +CONFIG_RTW88_8821CS=m +CONFIG_RTW88_8821CU=m +CONFIG_RTW88_8822BE=m +CONFIG_RTW88_8822BS=m +CONFIG_RTW88_8822BU=m +CONFIG_RTW88_8822CE=m +CONFIG_RTW88_8822CS=m +CONFIG_RTW88_8822CU=m +# CONFIG_RTW88_DEBUGFS is not set +# CONFIG_RTW88_DEBUG is not set +CONFIG_RTW88=m +CONFIG_RTW89_8851BE=m +CONFIG_RTW89_8852AE=m +CONFIG_RTW89_8852BE=m +CONFIG_RTW89_8852CE=m +CONFIG_RTW89_8922AE=m +# CONFIG_RTW89_DEBUGFS is not set +# CONFIG_RTW89_DEBUGMSG is not set +CONFIG_RTW89=m +# CONFIG_RUNTIME_KERNEL_TESTING_MENU is not set +CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +# CONFIG_RUST is not set +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RV_MON_WWNR=y +CONFIG_RV_REACTORS=y +CONFIG_RV_REACT_PANIC=y +CONFIG_RV_REACT_PRINTK=y +CONFIG_RV=y +CONFIG_RXKAD=y +# CONFIG_RXPERF is not set +CONFIG_S2IO=m +# CONFIG_S390_KPROBES_SANITY_TEST is not set +# CONFIG_S390_MODULES_SANITY_TEST is not set +# CONFIG_SAMPLE_FPROBE is not set +# CONFIG_SAMPLES is not set +CONFIG_SATA_ACARD_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=m +CONFIG_SATA_AHCI=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_HIGHBANK is not set +CONFIG_SATA_INIC162X=m +CONFIG_SATA_MOBILE_LPM_POLICY=3 +CONFIG_SATA_MV=m +CONFIG_SATA_NV=m +CONFIG_SATA_PMP=y +CONFIG_SATA_PROMISE=m +CONFIG_SATA_QSTOR=m +CONFIG_SATA_SIL24=m +CONFIG_SATA_SIL=m +CONFIG_SATA_SIS=m +CONFIG_SATA_SVW=m +CONFIG_SATA_SX4=m +CONFIG_SATA_ULI=m +CONFIG_SATA_VIA=m +CONFIG_SATA_VITESSE=m +# CONFIG_SATA_ZPODD is not set +# CONFIG_SBC7240_WDT is not set +# CONFIG_SBC8360_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +CONFIG_SBP_TARGET=m +# CONFIG_SC1200_WDT is not set +CONFIG_SC92031=m +# CONFIG_SCA3000 is not set +CONFIG_SCA3300=m +CONFIG_SCD30_CORE=m +CONFIG_SCD30_I2C=m +CONFIG_SCD30_SERIAL=m +# CONFIG_SCD4X is not set +# CONFIG_SCF_TORTURE_TEST is not set +CONFIG_SCHED_AUTOGROUP=y +CONFIG_SCHED_CLUSTER=y +CONFIG_SCHED_CORE=y +CONFIG_SCHED_DEBUG=y +# CONFIG_SCHED_MC_PRIO is not set +CONFIG_SCHED_MC=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_THERMAL_PRESSURE=y +CONFIG_SCHED_TRACER=y +CONFIG_SC_LPASS_CORECC_7180=m +# CONFIG_SCR24X is not set +CONFIG_SCSI_3W_9XXX=m +CONFIG_SCSI_3W_SAS=m +CONFIG_SCSI_AACRAID=m +CONFIG_SCSI_ACARD=m +# CONFIG_SCSI_ADVANSYS is not set +CONFIG_SCSI_AIC79XX=m +CONFIG_SCSI_AIC7XXX=m +# CONFIG_SCSI_AIC94XX is not set +CONFIG_SCSI_AM53C974=m +CONFIG_SCSI_ARCMSR=m +CONFIG_SCSI_BFA_FC=m +CONFIG_SCSI_BNX2_ISCSI=m +CONFIG_SCSI_BNX2X_FCOE=m +CONFIG_SCSI_BUSLOGIC=m +CONFIG_SCSI_CHELSIO_FCOE=m +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_CXGB3_ISCSI=m +CONFIG_SCSI_CXGB4_ISCSI=m +CONFIG_SCSI_DC395x=m +CONFIG_SCSI_DEBUG=m +CONFIG_SCSI_DH_ALUA=m +CONFIG_SCSI_DH_EMC=m +CONFIG_SCSI_DH_HP_SW=m +CONFIG_SCSI_DH_RDAC=m +CONFIG_SCSI_DH=y +CONFIG_SCSI_DMX3191D=m +# CONFIG_SCSI_DPT_I2O is not set +CONFIG_SCSI_EFCT=m +CONFIG_SCSI_ENCLOSURE=m +CONFIG_SCSI_ESAS2R=m +CONFIG_SCSI_FC_ATTRS=m +CONFIG_SCSI_FDOMAIN_PCI=m +CONFIG_SCSI_FLASHPOINT=y +# CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE is not set +# CONFIG_SCSI_HISI_SAS is not set +CONFIG_SCSI_HPSA=m +CONFIG_SCSI_HPTIOP=m +# CONFIG_SCSI_IMM is not set +CONFIG_SCSI_INIA100=m +CONFIG_SCSI_INITIO=m +CONFIG_SCSI_IPR_DUMP=y +CONFIG_SCSI_IPR=m +CONFIG_SCSI_IPR_TRACE=y +CONFIG_SCSI_IPS=m +CONFIG_SCSI_ISCSI_ATTRS=m +CONFIG_SCSI_LIB_KUNIT_TEST=m +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_SCSI_LPFC_DEBUG_FS is not set +CONFIG_SCSI_LPFC=m +CONFIG_SCSI_MPI3MR=m +CONFIG_SCSI_MPT2SAS=m +CONFIG_SCSI_MPT2SAS_MAX_SGE=128 +CONFIG_SCSI_MPT3SAS=m +CONFIG_SCSI_MPT3SAS_MAX_SGE=128 +# CONFIG_SCSI_MVSAS_DEBUG is not set +CONFIG_SCSI_MVSAS=m +CONFIG_SCSI_MVSAS_TASKLET=y +CONFIG_SCSI_MVUMI=m +CONFIG_SCSI_MYRB=m +CONFIG_SCSI_MYRS=m +# CONFIG_SCSI_NSP32 is not set +CONFIG_SCSI_PM8001=m +CONFIG_SCSI_PMCRAID=m +# CONFIG_SCSI_PPA is not set +CONFIG_SCSI_PROC_FS=y +CONFIG_SCSI_PROTO_TEST=m +CONFIG_SCSI_QLA_FC=m +CONFIG_SCSI_QLA_ISCSI=m +CONFIG_SCSI_QLOGIC_1280=m +CONFIG_SCSI_SAS_ATA=y +CONFIG_SCSI_SAS_ATTRS=m +CONFIG_SCSI_SAS_HOST_SMP=y +CONFIG_SCSI_SAS_LIBSAS=m +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_SMARTPQI=m +# CONFIG_SCSI_SNIC_DEBUG_FS is not set +CONFIG_SCSI_SNIC=m +CONFIG_SCSI_SPI_ATTRS=m +CONFIG_SCSI_SRP_ATTRS=m +CONFIG_SCSI_STEX=m +CONFIG_SCSI_SYM53C8XX_2=m +CONFIG_SCSI_SYM53C8XX_DEFAULT_TAGS=16 +CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=1 +CONFIG_SCSI_SYM53C8XX_MAX_TAGS=64 +CONFIG_SCSI_SYM53C8XX_MMIO=y +CONFIG_SCSI_UFS_BSG=y +CONFIG_SCSI_UFS_CDNS_PLATFORM=m +# CONFIG_SCSI_UFS_DWC_TC_PCI is not set +# CONFIG_SCSI_UFS_DWC_TC_PLATFORM is not set +# CONFIG_SCSI_UFS_FAULT_INJECTION is not set +# CONFIG_SCSI_UFSHCD is not set +CONFIG_SCSI_UFS_HPB=y +CONFIG_SCSI_UFS_HWMON=y +CONFIG_SCSI_VIRTIO=m +CONFIG_SCSI_WD719X=m +CONFIG_SCSI=y +CONFIG_SCTP_COOKIE_HMAC_MD5=y +CONFIG_SCTP_COOKIE_HMAC_SHA1=y +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y +# CONFIG_SD_ADC_MODULATOR is not set +CONFIG_SDIO_UART=m +# CONFIG_SDX_GCC_55 is not set +# CONFIG_SECCOMP_CACHE_DEBUG is not set +CONFIG_SECCOMP=y +# CONFIG_SECONDARY_TRUSTED_KEYRING_SIGNED_BY_BUILTIN is not set +CONFIG_SECONDARY_TRUSTED_KEYRING=y +CONFIG_SECRETMEM=y +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_SECURITY_APPARMOR is not set +CONFIG_SECURITY_DMESG_RESTRICT=y +CONFIG_SECURITYFS=y +CONFIG_SECURITY_INFINIBAND=y +CONFIG_SECURITY_LANDLOCK=y +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_LOCKDOWN_LSM_EARLY is not set +CONFIG_SECURITY_LOCKDOWN_LSM=y +CONFIG_SECURITY_NETWORK_XFRM=y +CONFIG_SECURITY_NETWORK=y +CONFIG_SECURITY_PATH=y +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 +# CONFIG_SECURITY_SELINUX_DEBUG is not set +CONFIG_SECURITY_SELINUX_DEVELOP=y +# CONFIG_SECURITY_SELINUX_DISABLE is not set +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX=y +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_YAMA=y +# CONFIG_SEG_LED_GPIO is not set +# CONFIG_SENSEAIR_SUNRISE_CO2 is not set +# CONFIG_SENSIRION_SGP30 is not set +# CONFIG_SENSIRION_SGP40 is not set +# CONFIG_SENSORS_ACBEL_FSG032 is not set +CONFIG_SENSORS_ACPI_POWER=m +CONFIG_SENSORS_AD7314=m +CONFIG_SENSORS_AD7414=m +CONFIG_SENSORS_AD7418=m +CONFIG_SENSORS_ADC128D818=m +CONFIG_SENSORS_ADCXX=m +CONFIG_SENSORS_ADM1021=m +CONFIG_SENSORS_ADM1025=m +CONFIG_SENSORS_ADM1026=m +CONFIG_SENSORS_ADM1029=m +CONFIG_SENSORS_ADM1031=m +# CONFIG_SENSORS_ADM1177 is not set +CONFIG_SENSORS_ADM1266=m +CONFIG_SENSORS_ADM1275=m +CONFIG_SENSORS_ADM9240=m +CONFIG_SENSORS_ADP1050=m +CONFIG_SENSORS_ADS7828=m +CONFIG_SENSORS_ADS7871=m +CONFIG_SENSORS_ADT7310=m +CONFIG_SENSORS_ADT7410=m +CONFIG_SENSORS_ADT7411=m +CONFIG_SENSORS_ADT7462=m +CONFIG_SENSORS_ADT7470=m +CONFIG_SENSORS_ADT7475=m +# CONFIG_SENSORS_AHT10 is not set +CONFIG_SENSORS_AMC6821=m +CONFIG_SENSORS_APDS990X=m +CONFIG_SENSORS_AQUACOMPUTER_D5NEXT=m +# CONFIG_SENSORS_AS370 is not set +CONFIG_SENSORS_ASC7621=m +CONFIG_SENSORS_ASUS_ROG_RYUJIN=m +# CONFIG_SENSORS_ASUS_WMI_EC is not set +# CONFIG_SENSORS_ASUS_WMI is not set +CONFIG_SENSORS_ATXP1=m +CONFIG_SENSORS_AXI_FAN_CONTROL=m +CONFIG_SENSORS_BEL_PFE=m +CONFIG_SENSORS_BH1770=m +CONFIG_SENSORS_BPA_RS600=m +CONFIG_SENSORS_CHIPCAP2=m +CONFIG_SENSORS_CORSAIR_CPRO=m +CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m +CONFIG_SENSORS_DELTA_AHE50DC_FAN=m +CONFIG_SENSORS_DME1737=m +CONFIG_SENSORS_DPS920AB=m +CONFIG_SENSORS_DRIVETEMP=m +CONFIG_SENSORS_DS1621=m +CONFIG_SENSORS_DS620=m +CONFIG_SENSORS_EMC1403=m +# CONFIG_SENSORS_EMC2103 is not set +CONFIG_SENSORS_EMC2305=m +CONFIG_SENSORS_EMC6W201=m +CONFIG_SENSORS_F71805F=m +CONFIG_SENSORS_F71882FG=m +CONFIG_SENSORS_F75375S=m +CONFIG_SENSORS_FSP_3Y=m +CONFIG_SENSORS_FTSTEUTATES=m +CONFIG_SENSORS_G760A=m +CONFIG_SENSORS_G762=m +CONFIG_SENSORS_GIGABYTE_WATERFORCE=m +CONFIG_SENSORS_GL518SM=m +CONFIG_SENSORS_GL520SM=m +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_HMC5843_I2C is not set +# CONFIG_SENSORS_HMC5843_SPI is not set +CONFIG_SENSORS_HP_WMI=m +CONFIG_SENSORS_HS3001=m +# CONFIG_SENSORS_I5K_AMB is not set +CONFIG_SENSORS_IBMAEM=m +# CONFIG_SENSORS_IBM_CFFPS is not set +CONFIG_SENSORS_IBMPEX=m +# CONFIG_SENSORS_IIO_HWMON is not set +CONFIG_SENSORS_INA209=m +CONFIG_SENSORS_INA238=m +CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_INA3221=m +# CONFIG_SENSORS_INSPUR_IPSPS is not set +CONFIG_SENSORS_INTEL_M10_BMC_HWMON=m +# CONFIG_SENSORS_IR35221 is not set +# CONFIG_SENSORS_IR36021 is not set +# CONFIG_SENSORS_IR38064 is not set +# CONFIG_SENSORS_IRPS5401 is not set +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_SENSORS_ISL68137 is not set +CONFIG_SENSORS_IT87=m +CONFIG_SENSORS_JC42=m +CONFIG_SENSORS_LINEAGE=m +CONFIG_SENSORS_LIS3_I2C=m +CONFIG_SENSORS_LIS3LV02D=m +# CONFIG_SENSORS_LIS3_SPI is not set +CONFIG_SENSORS_LM25066=m +CONFIG_SENSORS_LM25066_REGULATOR=y +CONFIG_SENSORS_LM63=m +CONFIG_SENSORS_LM70=m +CONFIG_SENSORS_LM73=m +CONFIG_SENSORS_LM75=m +CONFIG_SENSORS_LM77=m +CONFIG_SENSORS_LM78=m +CONFIG_SENSORS_LM80=m +CONFIG_SENSORS_LM83=m +CONFIG_SENSORS_LM85=m +CONFIG_SENSORS_LM87=m +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_LM92=m +CONFIG_SENSORS_LM93=m +CONFIG_SENSORS_LM95234=m +CONFIG_SENSORS_LM95241=m +CONFIG_SENSORS_LM95245=m +CONFIG_SENSORS_LT7182S=m +CONFIG_SENSORS_LTC2945=m +CONFIG_SENSORS_LTC2947_I2C=m +CONFIG_SENSORS_LTC2947_SPI=m +CONFIG_SENSORS_LTC2978=m +# CONFIG_SENSORS_LTC2978_REGULATOR is not set +CONFIG_SENSORS_LTC2990=m +CONFIG_SENSORS_LTC2991=m +# CONFIG_SENSORS_LTC2992 is not set +CONFIG_SENSORS_LTC3815=m +CONFIG_SENSORS_LTC4151=m +CONFIG_SENSORS_LTC4215=m +CONFIG_SENSORS_LTC4222=m +CONFIG_SENSORS_LTC4245=m +CONFIG_SENSORS_LTC4260=m +CONFIG_SENSORS_LTC4261=m +# CONFIG_SENSORS_LTC4282 is not set +# CONFIG_SENSORS_LTC4286 is not set +CONFIG_SENSORS_MAX1111=m +# CONFIG_SENSORS_MAX127 is not set +# CONFIG_SENSORS_MAX15301 is not set +CONFIG_SENSORS_MAX16064=m +CONFIG_SENSORS_MAX16065=m +CONFIG_SENSORS_MAX1619=m +# CONFIG_SENSORS_MAX16601 is not set +CONFIG_SENSORS_MAX1668=m +CONFIG_SENSORS_MAX197=m +# CONFIG_SENSORS_MAX20730 is not set +CONFIG_SENSORS_MAX20751=m +CONFIG_SENSORS_MAX31722=m +# CONFIG_SENSORS_MAX31730 is not set +CONFIG_SENSORS_MAX31760=m +# CONFIG_SENSORS_MAX31785 is not set +CONFIG_SENSORS_MAX31790=m +CONFIG_SENSORS_MAX34440=m +CONFIG_SENSORS_MAX6620=m +# CONFIG_SENSORS_MAX6621 is not set +CONFIG_SENSORS_MAX6639=m +CONFIG_SENSORS_MAX6642=m +CONFIG_SENSORS_MAX6650=m +CONFIG_SENSORS_MAX6697=m +CONFIG_SENSORS_MAX8688=m +CONFIG_SENSORS_MC34VR500=m +CONFIG_SENSORS_MCP3021=m +CONFIG_SENSORS_MLXREG_FAN=m +# CONFIG_SENSORS_MP2856 is not set +CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m +CONFIG_SENSORS_MP2975=m +CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m +CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m +# CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m +CONFIG_SENSORS_MPQ7932=m +CONFIG_SENSORS_MPQ7932_REGULATOR=y +CONFIG_SENSORS_MPQ8785=m +CONFIG_SENSORS_MR75203=m +CONFIG_SENSORS_NCT6683=m +CONFIG_SENSORS_NCT6775_I2C=m +CONFIG_SENSORS_NCT6775=m +CONFIG_SENSORS_NCT7802=m +CONFIG_SENSORS_NCT7904=m +CONFIG_SENSORS_NPCM7XX=m +CONFIG_SENSORS_NTC_THERMISTOR=m +CONFIG_SENSORS_NZXT_KRAKEN2=m +CONFIG_SENSORS_NZXT_KRAKEN3=m +CONFIG_SENSORS_NZXT_SMART2=m +# CONFIG_SENSORS_OCC_P8_I2C is not set +CONFIG_SENSORS_PC87360=m +CONFIG_SENSORS_PC87427=m +CONFIG_SENSORS_PCF8591=m +CONFIG_SENSORS_PIM4328=m +CONFIG_SENSORS_PLI1209BC=m +CONFIG_SENSORS_PLI1209BC_REGULATOR=y +CONFIG_SENSORS_PM6764TR=m +CONFIG_SENSORS_PMBUS=m +CONFIG_SENSORS_POWERZ=m +CONFIG_SENSORS_POWR1220=m +CONFIG_SENSORS_PT5161L=m +CONFIG_SENSORS_PWM_FAN=m +# CONFIG_SENSORS_PXE1610 is not set +CONFIG_SENSORS_Q54SJ108A2=m +CONFIG_SENSORS_RM3100_I2C=m +CONFIG_SENSORS_RM3100_SPI=m +# CONFIG_SENSORS_SBRMI is not set +CONFIG_SENSORS_SBTSI=m +CONFIG_SENSORS_SCH5627=m +CONFIG_SENSORS_SCH5636=m +CONFIG_SENSORS_SFCTEMP=y +CONFIG_SENSORS_SHT15=m +CONFIG_SENSORS_SHT21=m +CONFIG_SENSORS_SHT3x=m +# CONFIG_SENSORS_SHT4x is not set +CONFIG_SENSORS_SHTC1=m +CONFIG_SENSORS_SIS5595=m +# CONFIG_SENSORS_SMM665 is not set +CONFIG_SENSORS_SMSC47B397=m +CONFIG_SENSORS_SMSC47M192=m +CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m +# CONFIG_SENSORS_STPDDC60 is not set +# CONFIG_SENSORS_STTS751 is not set +CONFIG_SENSORS_SURFACE_FAN=m +CONFIG_SENSORS_SY7636A=m +CONFIG_SENSORS_TC654=m +CONFIG_SENSORS_TC74=m +CONFIG_SENSORS_TDA38640=m +CONFIG_SENSORS_TDA38640_REGULATOR=y +CONFIG_SENSORS_THMC50=m +CONFIG_SENSORS_TMP102=m +CONFIG_SENSORS_TMP103=m +CONFIG_SENSORS_TMP108=m +CONFIG_SENSORS_TMP401=m +CONFIG_SENSORS_TMP421=m +CONFIG_SENSORS_TMP464=m +CONFIG_SENSORS_TMP513=m +# CONFIG_SENSORS_TPS23861 is not set +CONFIG_SENSORS_TPS40422=m +CONFIG_SENSORS_TPS53679=m +CONFIG_SENSORS_TPS546D24=m +CONFIG_SENSORS_TSL2550=m +# CONFIG_SENSORS_TSL2563 is not set +CONFIG_SENSORS_UCD9000=m +CONFIG_SENSORS_UCD9200=m +CONFIG_SENSORS_VIA686A=m +CONFIG_SENSORS_VT1211=m +CONFIG_SENSORS_VT8231=m +CONFIG_SENSORS_W83627EHF=m +CONFIG_SENSORS_W83627HF=m +CONFIG_SENSORS_W83773G=m +CONFIG_SENSORS_W83781D=m +CONFIG_SENSORS_W83791D=m +CONFIG_SENSORS_W83792D=m +CONFIG_SENSORS_W83793=m +# CONFIG_SENSORS_W83795_FANCTRL is not set +CONFIG_SENSORS_W83795=m +CONFIG_SENSORS_W83L785TS=m +CONFIG_SENSORS_W83L786NG=m +CONFIG_SENSORS_XDP710=m +# CONFIG_SENSORS_XDPE122 is not set +CONFIG_SENSORS_XDPE152=m +# CONFIG_SENSORS_XGENE is not set +CONFIG_SENSORS_ZL6100=m +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_CS=m +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +CONFIG_SERIAL_8250_DFL=m +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_DW=y +CONFIG_SERIAL_8250_EXAR=m +CONFIG_SERIAL_8250_EXTENDED=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_MANY_PORTS=y +# CONFIG_SERIAL_8250_MID is not set +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_PCI1XXXX=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_PERICOM=y +CONFIG_SERIAL_8250_PNP=y +CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_RT288X=y +CONFIG_SERIAL_8250_RUNTIME_UARTS=32 +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250=y +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_AMBA_PL010 is not set +# CONFIG_SERIAL_AMBA_PL011 is not set +CONFIG_SERIAL_ARC=m +CONFIG_SERIAL_ARC_NR_PORTS=1 +# CONFIG_SERIAL_BCM63XX is not set +# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +# CONFIG_SERIAL_EARLYCON_RISCV_SBI is not set +# CONFIG_SERIAL_EARLYCON_SEMIHOST is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_IMX_EARLYCON is not set +CONFIG_SERIAL_JSM=m +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_LANTIQ is not set +CONFIG_SERIAL_LITEUART_CONSOLE=y +CONFIG_SERIAL_LITEUART_MAX_PORTS=1 +CONFIG_SERIAL_LITEUART=y +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +CONFIG_SERIAL_NONSTANDARD=y +CONFIG_SERIAL_OF_PLATFORM=y +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_RP2 is not set +CONFIG_SERIAL_SC16IS7XX_I2C=m +CONFIG_SERIAL_SC16IS7XX=m +CONFIG_SERIAL_SC16IS7XX_SPI=m +# CONFIG_SERIAL_SCCNXP is not set +CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_SIFIVE_CONSOLE=y +CONFIG_SERIAL_SIFIVE=y +# CONFIG_SERIAL_SPRD is not set +# CONFIG_SERIAL_ST_ASC is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_UARTLITE is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +CONFIG_SERIO_ALTERA_PS2=m +# CONFIG_SERIO_AMBAKMI is not set +# CONFIG_SERIO_APBPS2 is not set +CONFIG_SERIO_ARC_PS2=m +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_GPIO_PS2 is not set +# CONFIG_SERIO_I8042 is not set +# CONFIG_SERIO_LIBPS2 is not set +# CONFIG_SERIO_OLPC_APSP is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +# CONFIG_SERIO_PS2MULT is not set +CONFIG_SERIO_RAW=m +CONFIG_SERIO_SERPORT=m +CONFIG_SERIO=y +CONFIG_SFC_FALCON=m +CONFIG_SFC_FALCON_MTD=y +# CONFIG_SFC is not set +CONFIG_SF_PDMA=y +CONFIG_SFP=m +# CONFIG_SGETMASK_SYSCALL is not set +CONFIG_SGI_PARTITION=y +# CONFIG_SHADOW_CALL_STACK is not set +CONFIG_SHMEM=y +# CONFIG_SHRINKER_DEBUG is not set +CONFIG_SHUFFLE_PAGE_ALLOCATOR=y +# CONFIG_SI1133 is not set +# CONFIG_SI1145 is not set +# CONFIG_SI7005 is not set +# CONFIG_SI7020 is not set +# CONFIG_SIEMENS_SIMATIC_IPC is not set +CONFIG_SIFIVE_CCACHE=y +CONFIG_SIFIVE_PLIC=y +CONFIG_SIGNALFD=y +CONFIG_SIGNED_PE_FILE_VERIFICATION=y +# CONFIG_SIOX is not set +CONFIG_SIPHASH_KUNIT_TEST=m +CONFIG_SIS190=m +CONFIG_SIS900=m +# CONFIG_SKGE_DEBUG is not set +CONFIG_SKGE_GENESIS=y +CONFIG_SKGE=m +# CONFIG_SKY2_DEBUG is not set +CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y +CONFIG_SLAB_FREELIST_HARDENED=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_MERGE_DEFAULT is not set +# CONFIG_SLIMBUS is not set +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLIP=m +# CONFIG_SLIP_MODE_SLIP6 is not set +CONFIG_SLIP_SMART=y +CONFIG_SLUB_CPU_PARTIAL=y +# CONFIG_SLUB_DEBUG_ON is not set +CONFIG_SLUB_DEBUG=y +CONFIG_SLUB_KUNIT_TEST=m +# CONFIG_SLUB_STATS is not set +# CONFIG_SLUB_TINY is not set +CONFIG_SLUB=y +CONFIG_SMARTJOYPLUS_FF=y +# CONFIG_SMB_SERVER is not set +CONFIG_SMC_DIAG=m +# CONFIG_SMC_LO is not set +CONFIG_SMC=m +# CONFIG_SM_FTL is not set +CONFIG_SMP=y +CONFIG_SMSC911X=m +CONFIG_SMSC9420=m +CONFIG_SMSC_PHY=m +CONFIG_SMSC_SCH311X_WDT=m +CONFIG_SMS_SDIO_DRV=m +# CONFIG_SMS_SIANO_DEBUGFS is not set +CONFIG_SMS_SIANO_MDTV=m +CONFIG_SMS_SIANO_RC=y +CONFIG_SMS_USB_DRV=m +# CONFIG_SM_VIDEOCC_8150 is not set +CONFIG_SND_AC97_POWER_SAVE_DEFAULT=0 +CONFIG_SND_AC97_POWER_SAVE=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALI5451 is not set +CONFIG_SND_ALOOP=m +CONFIG_SND_ALS300=m +CONFIG_SND_ALS4000=m +# CONFIG_SND_AMD_ACP_CONFIG is not set +# CONFIG_SND_ASIHPI is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_ATMEL_SOC is not set +CONFIG_SND_AU8810=m +CONFIG_SND_AU8820=m +CONFIG_SND_AU8830=m +CONFIG_SND_AUDIO_GRAPH_CARD2_CUSTOM_SAMPLE=m +CONFIG_SND_AUDIO_GRAPH_CARD2=m +CONFIG_SND_AUDIO_GRAPH_CARD=m +# CONFIG_SND_AW2 is not set +CONFIG_SND_AZT3328=m +CONFIG_SND_BCD2000=m +# CONFIG_SND_BCM63XX_I2S_WHISTLER is not set +CONFIG_SND_BEBOB=m +CONFIG_SND_BT87X=m +# CONFIG_SND_BT87X_OVERCLOCK is not set +CONFIG_SND_CA0106=m +CONFIG_SND_CMIPCI=m +CONFIG_SND_COMPRESS_OFFLOAD=m +CONFIG_SND_CORE_TEST=m +CONFIG_SND_CS4281=m +CONFIG_SND_CS46XX=m +CONFIG_SND_CS46XX_NEW_DSP=y +CONFIG_SND_CS5530=m +CONFIG_SND_CS5535AUDIO=m +# CONFIG_SND_CTL_DEBUG is not set +CONFIG_SND_CTL_FAST_LOOKUP=y +# CONFIG_SND_CTL_INPUT_VALIDATION is not set +# CONFIG_SND_CTL_VALIDATION is not set +CONFIG_SND_CTXFI=m +CONFIG_SND_DARLA20=m +CONFIG_SND_DARLA24=m +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_DEBUG_VERBOSE is not set +CONFIG_SND_DESIGNWARE_I2S=m +# CONFIG_SND_DESIGNWARE_PCM is not set +CONFIG_SND_DICE=m +CONFIG_SND_DMAENGINE_PCM=m +CONFIG_SND_DRIVERS=y +CONFIG_SND_DUMMY=m +CONFIG_SND_DYNAMIC_MINORS=y +CONFIG_SND_ECHO3G=m +CONFIG_SND_EMU10K1=m +CONFIG_SND_EMU10K1X=m +CONFIG_SND_ENS1370=m +CONFIG_SND_ENS1371=m +CONFIG_SND_ES1938=m +CONFIG_SND_ES1968_INPUT=y +CONFIG_SND_ES1968=m +CONFIG_SND_ES1968_RADIO=y +CONFIG_SND_FIREFACE=m +CONFIG_SND_FIREWORKS=m +CONFIG_SND_FM801=m +CONFIG_SND_FM801_TEA575X_BOOL=y +CONFIG_SND_GINA20=m +CONFIG_SND_GINA24=m +CONFIG_SND_HDA_CIRRUS_SCODEC_KUNIT_TEST=m +CONFIG_SND_HDA_CODEC_ANALOG=m +CONFIG_SND_HDA_CODEC_CA0110=m +CONFIG_SND_HDA_CODEC_CA0132_DSP=y +CONFIG_SND_HDA_CODEC_CA0132=m +CONFIG_SND_HDA_CODEC_CIRRUS=m +CONFIG_SND_HDA_CODEC_CMEDIA=m +CONFIG_SND_HDA_CODEC_CONEXANT=m +CONFIG_SND_HDA_CODEC_CS8409=m +CONFIG_SND_HDA_CODEC_HDMI=m +CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m +CONFIG_SND_HDA_CODEC_SI3054=m +CONFIG_SND_HDA_CODEC_SIGMATEL=m +CONFIG_SND_HDA_CODEC_VIA=m +# CONFIG_SND_HDA_CTL_DEV_ID is not set +CONFIG_SND_HDA_GENERIC=m +CONFIG_SND_HDA_HWDEP=y +CONFIG_SND_HDA_INPUT_BEEP_MODE=0 +CONFIG_SND_HDA_INPUT_BEEP=y +CONFIG_SND_HDA_INTEL_HDMI_SILENT_STREAM=y +CONFIG_SND_HDA_INTEL=m +CONFIG_SND_HDA_PATCH_LOADER=y +CONFIG_SND_HDA_POWER_SAVE_DEFAULT=1 +CONFIG_SND_HDA_PREALLOC_SIZE=2048 +CONFIG_SND_HDA_RECONFIG=y +CONFIG_SND_HDA_SCODEC_CS35L41_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L41_SPI=m +CONFIG_SND_HDA_SCODEC_CS35L56_I2C=m +CONFIG_SND_HDA_SCODEC_CS35L56_SPI=m +CONFIG_SND_HDA_SCODEC_TAS2781_I2C=m +# CONFIG_SND_HDA_TEGRA is not set +CONFIG_SND_HDSP=m +CONFIG_SND_HDSPM=m +CONFIG_SND_HRTIMER=m +# CONFIG_SND_I2S_HI6210_I2S is not set +CONFIG_SND_ICE1712=m +CONFIG_SND_ICE1724=m +# CONFIG_SND_IMX_SOC is not set +CONFIG_SND_INDIGODJ=m +CONFIG_SND_INDIGODJX=m +CONFIG_SND_INDIGOIO=m +CONFIG_SND_INDIGOIOX=m +CONFIG_SND_INDIGO=m +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_INTEL_BYT_PREFER_SOF is not set +CONFIG_SND_ISIGHT=m +# CONFIG_SND_JACK_INJECTION_DEBUG is not set +CONFIG_SND_JACK=y +# CONFIG_SND_KIRKWOOD_SOC_ARMADA370_DB is not set +# CONFIG_SND_KIRKWOOD_SOC is not set +CONFIG_SND_KORG1212=m +CONFIG_SND_LAYLA20=m +CONFIG_SND_LAYLA24=m +CONFIG_SND_LOLA=m +CONFIG_SND_LX6464ES=m +CONFIG_SND=m +CONFIG_SND_MAESTRO3_INPUT=y +CONFIG_SND_MAESTRO3=m +CONFIG_SND_MAX_CARDS=32 +# CONFIG_SND_MESON_AIU is not set +# CONFIG_SND_MESON_G12A_TOACODEC is not set +# CONFIG_SND_MESON_G12A_TOHDMITX is not set +# CONFIG_SND_MESON_GX_SOUND_CARD is not set +CONFIG_SND_MIA=m +CONFIG_SND_MIXART=m +CONFIG_SND_MIXER_OSS=m +# CONFIG_SND_MMP_SOC_SSPA is not set +CONFIG_SND_MONA=m +CONFIG_SND_MPU401=m +CONFIG_SND_MTPAV=m +CONFIG_SND_MTS64=m +CONFIG_SND_NM256=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_OXFW=m +CONFIG_SND_OXYGEN=m +CONFIG_SND_PCI=y +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_PCMTEST=m +CONFIG_SND_PCM_TIMER=y +# CONFIG_SND_PCSP is not set +CONFIG_SND_PCXHR=m +CONFIG_SND_PORTMAN2X4=m +# CONFIG_SND_PPC is not set +CONFIG_SND_PROC_FS=y +CONFIG_SND_RIPTIDE=m +CONFIG_SND_RME32=m +CONFIG_SND_RME9652=m +CONFIG_SND_RME96=m +# CONFIG_SND_SAMSUNG_PCM is not set +# CONFIG_SND_SAMSUNG_SPDIF is not set +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_SEQ_HRTIMER_DEFAULT=y +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQUENCER_OSS=m +CONFIG_SND_SEQ_UMP=y +CONFIG_SND_SERIAL_GENERIC=m +CONFIG_SND_SERIAL_U16550=m +CONFIG_SND_SIMPLE_CARD=m +CONFIG_SND_SIMPLE_CARD_UTILS=m +# CONFIG_SND_SIS7019 is not set +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AC97_CODEC=m +# CONFIG_SND_SOC_ADAU1372_I2C is not set +# CONFIG_SND_SOC_ADAU1372_SPI is not set +# CONFIG_SND_SOC_ADAU1701 is not set +CONFIG_SND_SOC_ADAU1761_I2C=m +CONFIG_SND_SOC_ADAU1761_SPI=m +CONFIG_SND_SOC_ADAU7002=m +CONFIG_SND_SOC_ADAU7118_HW=m +CONFIG_SND_SOC_ADAU7118_I2C=m +CONFIG_SND_SOC_ADI_AXI_I2S=m +CONFIG_SND_SOC_ADI_AXI_SPDIF=m +CONFIG_SND_SOC_ADI=m +# CONFIG_SND_SOC_AK4104 is not set +# CONFIG_SND_SOC_AK4118 is not set +# CONFIG_SND_SOC_AK4375 is not set +# CONFIG_SND_SOC_AK4458 is not set +# CONFIG_SND_SOC_AK4554 is not set +# CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m +# CONFIG_SND_SOC_AK4642 is not set +# CONFIG_SND_SOC_AK5386 is not set +CONFIG_SND_SOC_AK5558=m +# CONFIG_SND_SOC_ALC5623 is not set +# CONFIG_SND_SOC_AMD_ACP3x is not set +# CONFIG_SND_SOC_AMD_ACP5x is not set +# CONFIG_SND_SOC_AMD_ACP6x is not set +# CONFIG_SND_SOC_AMD_ACP_COMMON is not set +# CONFIG_SND_SOC_AMD_ACP is not set +# CONFIG_SND_SOC_AMD_CZ_DA7219MX98357_MACH is not set +# CONFIG_SND_SOC_AMD_CZ_RT5645_MACH is not set +# CONFIG_SND_SOC_AMD_PS is not set +# CONFIG_SND_SOC_AMD_PS_MACH is not set +# CONFIG_SND_SOC_AMD_RENOIR is not set +# CONFIG_SND_SOC_AMD_RENOIR_MACH is not set +# CONFIG_SND_SOC_AMD_RPL_ACP6x is not set +# CONFIG_SND_SOC_AMD_RV_RT5682_MACH is not set +# CONFIG_SND_SOC_AMD_VANGOGH_MACH is not set +# CONFIG_SND_SOC_AMD_YC_MACH is not set +# CONFIG_SND_SOC_APQ8016_SBC is not set +# CONFIG_SND_SOC_ARNDALE is not set +CONFIG_SND_SOC_AUDIO_IIO_AUX=m +CONFIG_SND_SOC_AW8738=m +CONFIG_SND_SOC_AW87390=m +CONFIG_SND_SOC_AW88261=m +CONFIG_SND_SOC_AW88395=m +CONFIG_SND_SOC_AW88399=m +CONFIG_SND_SOC_BD28623=m +CONFIG_SND_SOC_BT_SCO=m +CONFIG_SND_SOC_CARD_KUNIT_TEST=m +CONFIG_SND_SOC_CHV3_CODEC=m +CONFIG_SND_SOC_CHV3_I2S=m +# CONFIG_SND_SOC_CROS_EC_CODEC is not set +# CONFIG_SND_SOC_CS35L32 is not set +# CONFIG_SND_SOC_CS35L33 is not set +CONFIG_SND_SOC_CS35L34=m +CONFIG_SND_SOC_CS35L35=m +CONFIG_SND_SOC_CS35L36=m +# CONFIG_SND_SOC_CS35L41_I2C is not set +# CONFIG_SND_SOC_CS35L41_SPI is not set +CONFIG_SND_SOC_CS35L45_I2C=m +CONFIG_SND_SOC_CS35L45_SPI=m +CONFIG_SND_SOC_CS35L56_I2C=m +CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m +CONFIG_SND_SOC_CS4234=m +# CONFIG_SND_SOC_CS4265 is not set +# CONFIG_SND_SOC_CS4270 is not set +# CONFIG_SND_SOC_CS4271_I2C is not set +# CONFIG_SND_SOC_CS4271_SPI is not set +CONFIG_SND_SOC_CS42L42=m +CONFIG_SND_SOC_CS42L42_SDW=m +CONFIG_SND_SOC_CS42L43=m +CONFIG_SND_SOC_CS42L43_SDW=m +# CONFIG_SND_SOC_CS42L51_I2C is not set +# CONFIG_SND_SOC_CS42L52 is not set +# CONFIG_SND_SOC_CS42L56 is not set +# CONFIG_SND_SOC_CS42L73 is not set +CONFIG_SND_SOC_CS42L83=m +# CONFIG_SND_SOC_CS42XX8_I2C is not set +CONFIG_SND_SOC_CS43130=m +# CONFIG_SND_SOC_CS4341 is not set +# CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m +# CONFIG_SND_SOC_CS53L30 is not set +CONFIG_SND_SOC_CS_AMP_LIB_TEST=m +CONFIG_SND_SOC_CX2072X=m +CONFIG_SND_SOC_DA7213=m +# CONFIG_SND_SOC_DAVINCI_MCASP is not set +CONFIG_SND_SOC_DMIC=m +CONFIG_SND_SOC_ES7134=m +# CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m +# CONFIG_SND_SOC_ES8316 is not set +CONFIG_SND_SOC_ES8326=m +CONFIG_SND_SOC_ES8328_I2C=m +CONFIG_SND_SOC_ES8328=m +CONFIG_SND_SOC_ES8328_SPI=m +# CONFIG_SND_SOC_FSL_ASOC_CARD is not set +# CONFIG_SND_SOC_FSL_ASRC is not set +# CONFIG_SND_SOC_FSL_AUD2HTX is not set +# CONFIG_SND_SOC_FSL_AUDMIX is not set +# CONFIG_SND_SOC_FSL_EASRC is not set +# CONFIG_SND_SOC_FSL_ESAI is not set +# CONFIG_SND_SOC_FSL_MICFIL is not set +# CONFIG_SND_SOC_FSL_MQS is not set +# CONFIG_SND_SOC_FSL_RPMSG is not set +# CONFIG_SND_SOC_FSL_SAI is not set +# CONFIG_SND_SOC_FSL_SPDIF is not set +# CONFIG_SND_SOC_FSL_SSI is not set +# CONFIG_SND_SOC_FSL_XCVR is not set +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_SOC_GTM601 is not set +CONFIG_SND_SOC_HDAC_HDA=m +CONFIG_SND_SOC_HDAC_HDMI=m +CONFIG_SND_SOC_HDA=m +CONFIG_SND_SOC_HDMI_CODEC=m +# CONFIG_SND_SOC_ICS43432 is not set +CONFIG_SND_SOC_IDT821034=m +# CONFIG_SND_SOC_IMG is not set +# CONFIG_SND_SOC_IMX_AUDIO_RPMSG is not set +# CONFIG_SND_SOC_IMX_AUDMIX is not set +# CONFIG_SND_SOC_IMX_AUDMUX is not set +# CONFIG_SND_SOC_IMX_CARD is not set +# CONFIG_SND_SOC_IMX_ES8328 is not set +# CONFIG_SND_SOC_IMX_HDMI is not set +# CONFIG_SND_SOC_IMX_PCM_RPMSG is not set +# CONFIG_SND_SOC_IMX_RPMSG is not set +# CONFIG_SND_SOC_IMX_SGTL5000 is not set +# CONFIG_SND_SOC_IMX_SPDIF is not set +# CONFIG_SND_SOC_INNO_RK3036 is not set +# CONFIG_SND_SOC_INTEL_AVS is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_DA7219 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_DMIC is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_HDAUDIO is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_I2S_TEST is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98357A is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98373 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_MAX98927 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_NAU8825 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_PROBE is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT274 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT286 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT298 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_RT5682 is not set +# CONFIG_SND_SOC_INTEL_AVS_MACH_SSM4567 is not set +# CONFIG_SND_SOC_INTEL_BDW_RT5650_MACH is not set +# CONFIG_SND_SOC_INTEL_BDW_RT5677_MACH is not set +# CONFIG_SND_SOC_INTEL_BROADWELL_MACH is not set +# CONFIG_SND_SOC_INTEL_BXT_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_BXT_RT298_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_CX2072X_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_DA7213_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_ES8316_MACH is not set +# CONFIG_SND_SOC_INTEL_BYT_CHT_NOCODEC_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_RT5651_MACH is not set +# CONFIG_SND_SOC_INTEL_BYTCR_WM5102_MACH is not set +# CONFIG_SND_SOC_INTEL_CATPT is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_MAX98090_TI_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_NAU8824_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH is not set +# CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH is not set +# CONFIG_SND_SOC_INTEL_CML_H is not set +# CONFIG_SND_SOC_INTEL_CML_LP_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_CML_LP is not set +# CONFIG_SND_SOC_INTEL_EHL_RT5660_MACH is not set +# CONFIG_SND_SOC_INTEL_GLK_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_GLK_RT5682_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_HASWELL_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_DA7219_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5660_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5663_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_KBL_RT5663_RT5514_MAX98927_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_HDA_DSP_GENERIC_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_MAX98357A_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_NAU88L25_SSM4567_MACH is not set +# CONFIG_SND_SOC_INTEL_SKL_RT286_MACH is not set +# CONFIG_SND_SOC_INTEL_SKYLAKE_HDAUDIO_CODEC is not set +# CONFIG_SND_SOC_INTEL_SKYLAKE is not set +# CONFIG_SND_SOC_INTEL_SOF_CML_RT1011_RT5682_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_DA7219_MAX98373_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_ES8336_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_PCM512x_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_RT5682_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_SSP_AMP_MACH is not set +# CONFIG_SND_SOC_INTEL_SOF_WM8804_MACH is not set +# CONFIG_SND_SOC_INTEL_SOUNDWIRE_SOF_MACH is not set +# CONFIG_SND_SOC_INTEL_SST is not set +# CONFIG_SND_SOC_INTEL_SST_TOPLEVEL is not set +# CONFIG_SND_SOC_INTEL_USER_FRIENDLY_LONG_NAMES is not set +CONFIG_SND_SOC_JH7110_PWMDAC=m +CONFIG_SND_SOC_JH7110_TDM=m +# CONFIG_SND_SOC_LPASS_RX_MACRO is not set +# CONFIG_SND_SOC_LPASS_TX_MACRO is not set +# CONFIG_SND_SOC_LPASS_VA_MACRO is not set +# CONFIG_SND_SOC_LPASS_WSA_MACRO is not set +CONFIG_SND_SOC=m +CONFIG_SND_SOC_MAX9759=m +CONFIG_SND_SOC_MAX98088=m +# CONFIG_SND_SOC_MAX98090 is not set +# CONFIG_SND_SOC_MAX98357A is not set +CONFIG_SND_SOC_MAX98363=m +CONFIG_SND_SOC_MAX98373_I2C=m +CONFIG_SND_SOC_MAX98373=m +CONFIG_SND_SOC_MAX98373_SDW=m +CONFIG_SND_SOC_MAX98388=m +CONFIG_SND_SOC_MAX98390=m +CONFIG_SND_SOC_MAX98396=m +# CONFIG_SND_SOC_MAX98504 is not set +CONFIG_SND_SOC_MAX98520=m +# CONFIG_SND_SOC_MAX9860 is not set +CONFIG_SND_SOC_MAX9867=m +CONFIG_SND_SOC_MAX98927=m +# CONFIG_SND_SOC_MESON_T9015 is not set +# CONFIG_SND_SOC_MSM8916_WCD_ANALOG is not set +# CONFIG_SND_SOC_MSM8916_WCD_DIGITAL is not set +# CONFIG_SND_SOC_MSM8996 is not set +# CONFIG_SND_SOC_MT6351 is not set +# CONFIG_SND_SOC_MT6358 is not set +# CONFIG_SND_SOC_MT6660 is not set +# CONFIG_SND_SOC_MTK_BTCVSD is not set +# CONFIG_SND_SOC_NAU8315 is not set +# CONFIG_SND_SOC_NAU8540 is not set +# CONFIG_SND_SOC_NAU8810 is not set +# CONFIG_SND_SOC_NAU8821 is not set +# CONFIG_SND_SOC_NAU8822 is not set +CONFIG_SND_SOC_NAU8824=m +# CONFIG_SND_SOC_NAU8825 is not set +# CONFIG_SND_SOC_ODROID is not set +# CONFIG_SND_SOC_OMAP_ABE_TWL6040 is not set +# CONFIG_SND_SOC_OMAP_DMIC is not set +# CONFIG_SND_SOC_OMAP_HDMI is not set +# CONFIG_SND_SOC_OMAP_MCBSP is not set +# CONFIG_SND_SOC_OMAP_MCPDM is not set +# CONFIG_SND_SOC_PCM1681 is not set +CONFIG_SND_SOC_PCM1789_I2C=m +# CONFIG_SND_SOC_PCM179X_I2C is not set +# CONFIG_SND_SOC_PCM179X_SPI is not set +CONFIG_SND_SOC_PCM186X_I2C=m +CONFIG_SND_SOC_PCM186X_SPI=m +CONFIG_SND_SOC_PCM3060_I2C=m +CONFIG_SND_SOC_PCM3060_SPI=m +# CONFIG_SND_SOC_PCM3168A_I2C is not set +# CONFIG_SND_SOC_PCM3168A_SPI is not set +# CONFIG_SND_SOC_PCM5102A is not set +# CONFIG_SND_SOC_PCM512x_I2C is not set +# CONFIG_SND_SOC_PCM512x is not set +# CONFIG_SND_SOC_PCM512x_SPI is not set +CONFIG_SND_SOC_PCM6240=m +# CONFIG_SND_SOC_PEB2466 is not set +# CONFIG_SND_SOC_QCOM is not set +# CONFIG_SND_SOC_QDSP6 is not set +# CONFIG_SND_SOC_RK3288_HDMI_ANALOG is not set +# CONFIG_SND_SOC_RK3328 is not set +# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set +# CONFIG_SND_SOC_RK817 is not set +CONFIG_SND_SOC_RL6231=m +CONFIG_SND_SOC_RT1017_SDCA_SDW=m +# CONFIG_SND_SOC_RT1308 is not set +# CONFIG_SND_SOC_RT1308_SDW is not set +# CONFIG_SND_SOC_RT1316_SDW is not set +CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m +# CONFIG_SND_SOC_RT5616 is not set +# CONFIG_SND_SOC_RT5631 is not set +CONFIG_SND_SOC_RT5640=m +CONFIG_SND_SOC_RT5659=m +CONFIG_SND_SOC_RT5660=m +# CONFIG_SND_SOC_RT5663 is not set +# CONFIG_SND_SOC_RT5677 is not set +# CONFIG_SND_SOC_RT5677_SPI is not set +CONFIG_SND_SOC_RT5682_SDW=m +CONFIG_SND_SOC_RT700_SDW=m +CONFIG_SND_SOC_RT711_SDCA_SDW=m +CONFIG_SND_SOC_RT711_SDW=m +CONFIG_SND_SOC_RT712_SDCA_DMIC_SDW=m +# CONFIG_SND_SOC_RT712_SDCA_SDW is not set +CONFIG_SND_SOC_RT715_SDCA_SDW=m +CONFIG_SND_SOC_RT715_SDW=m +CONFIG_SND_SOC_RT722_SDCA_SDW=m +# CONFIG_SND_SOC_RT9120 is not set +CONFIG_SND_SOC_RTQ9128=m +# CONFIG_SND_SOC_SAMSUNG_ARIES_WM8994 is not set +# CONFIG_SND_SOC_SAMSUNG is not set +# CONFIG_SND_SOC_SAMSUNG_MIDAS_WM1811 is not set +# CONFIG_SND_SOC_SAMSUNG_SMDK_SPDIF is not set +# CONFIG_SND_SOC_SAMSUNG_SMDK_WM8994 is not set +# CONFIG_SND_SOC_SC7180 is not set +# CONFIG_SND_SOC_SDM845 is not set +# CONFIG_SND_SOC_SDW_MOCKUP is not set +# CONFIG_SND_SOC_SGTL5000 is not set +CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m +CONFIG_SND_SOC_SIMPLE_MUX=m +# CONFIG_SND_SOC_SM8250 is not set +CONFIG_SND_SOC_SMA1303=m +# CONFIG_SND_SOC_SMDK_WM8994_PCM is not set +# CONFIG_SND_SOC_SNOW is not set +CONFIG_SND_SOC_SOF_ACPI=m +# CONFIG_SND_SOC_SOF_ALDERLAKE is not set +# CONFIG_SND_SOC_SOF_AMD_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_APOLLOLAKE is not set +# CONFIG_SND_SOC_SOF_BAYTRAIL is not set +# CONFIG_SND_SOC_SOF_BROADWELL is not set +# CONFIG_SND_SOC_SOF_CANNONLAKE is not set +# CONFIG_SND_SOC_SOF_COFFEELAKE is not set +# CONFIG_SND_SOC_SOF_COMETLAKE is not set +# CONFIG_SND_SOC_SOF_DEVELOPER_SUPPORT is not set +# CONFIG_SND_SOC_SOF_ELKHARTLAKE is not set +# CONFIG_SND_SOC_SOF_GEMINILAKE is not set +# CONFIG_SND_SOC_SOF_HDA_AUDIO_CODEC is not set +# CONFIG_SND_SOC_SOF_HDA_LINK is not set +# CONFIG_SND_SOC_SOF_ICELAKE is not set +# CONFIG_SND_SOC_SOF_IMX8M_SUPPORT is not set +# CONFIG_SND_SOC_SOF_IMX8_SUPPORT is not set +# CONFIG_SND_SOC_SOF_IMX_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_INTEL_SOUNDWIRE is not set +# CONFIG_SND_SOC_SOF_INTEL_TOPLEVEL is not set +# CONFIG_SND_SOC_SOF_JASPERLAKE is not set +# CONFIG_SND_SOC_SOF_KABYLAKE is not set +# CONFIG_SND_SOC_SOF_MERRIFIELD is not set +# CONFIG_SND_SOC_SOF_METEORLAKE is not set +# CONFIG_SND_SOC_SOF_MT8195 is not set +# CONFIG_SND_SOC_SOF_OF is not set +CONFIG_SND_SOC_SOF_PCI=m +# CONFIG_SND_SOC_SOF_SKYLAKE is not set +# CONFIG_SND_SOC_SOF_TIGERLAKE is not set +CONFIG_SND_SOC_SOF_TOPLEVEL=y +CONFIG_SND_SOC_SPDIF=m +# CONFIG_SND_SOC_SRC4XXX_I2C is not set +# CONFIG_SND_SOC_SSM2305 is not set +# CONFIG_SND_SOC_SSM2518 is not set +# CONFIG_SND_SOC_SSM2602_I2C is not set +# CONFIG_SND_SOC_SSM2602_SPI is not set +CONFIG_SND_SOC_SSM3515=m +# CONFIG_SND_SOC_SSM4567 is not set +# CONFIG_SND_SOC_STA32X is not set +# CONFIG_SND_SOC_STA350 is not set +CONFIG_SND_SOC_STARFIVE=m +# CONFIG_SND_SOC_STI_SAS is not set +# CONFIG_SND_SOC_STM32_DFSDM is not set +# CONFIG_SND_SOC_STM32_I2S is not set +# CONFIG_SND_SOC_STM32_SAI is not set +# CONFIG_SND_SOC_STM32_SPDIFRX is not set +# CONFIG_SND_SOC_STORM is not set +# CONFIG_SND_SOC_TAS2552 is not set +CONFIG_SND_SOC_TAS2562=m +CONFIG_SND_SOC_TAS2764=m +CONFIG_SND_SOC_TAS2770=m +CONFIG_SND_SOC_TAS2780=m +CONFIG_SND_SOC_TAS2781_I2C=m +# CONFIG_SND_SOC_TAS5086 is not set +# CONFIG_SND_SOC_TAS571X is not set +# CONFIG_SND_SOC_TAS5720 is not set +CONFIG_SND_SOC_TAS5805M=m +CONFIG_SND_SOC_TAS6424=m +CONFIG_SND_SOC_TDA7419=m +# CONFIG_SND_SOC_TEGRA186_DSPK is not set +# CONFIG_SND_SOC_TEGRA20_AC97 is not set +# CONFIG_SND_SOC_TEGRA20_DAS is not set +# CONFIG_SND_SOC_TEGRA20_I2S is not set +# CONFIG_SND_SOC_TEGRA20_SPDIF is not set +# CONFIG_SND_SOC_TEGRA210_ADMAIF is not set +# CONFIG_SND_SOC_TEGRA210_AHUB is not set +# CONFIG_SND_SOC_TEGRA210_DMIC is not set +# CONFIG_SND_SOC_TEGRA210_I2S is not set +# CONFIG_SND_SOC_TEGRA30_AHUB is not set +# CONFIG_SND_SOC_TEGRA30_I2S is not set +# CONFIG_SND_SOC_TEGRA_ALC5632 is not set +# CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD is not set +# CONFIG_SND_SOC_TEGRA is not set +# CONFIG_SND_SOC_TEGRA_MACHINE_DRV is not set +# CONFIG_SND_SOC_TEGRA_MAX98090 is not set +# CONFIG_SND_SOC_TEGRA_RT5640 is not set +# CONFIG_SND_SOC_TEGRA_RT5677 is not set +# CONFIG_SND_SOC_TEGRA_SGTL5000 is not set +# CONFIG_SND_SOC_TEGRA_TRIMSLICE is not set +# CONFIG_SND_SOC_TEGRA_WM8753 is not set +# CONFIG_SND_SOC_TEGRA_WM8903 is not set +# CONFIG_SND_SOC_TEGRA_WM9712 is not set +# CONFIG_SND_SOC_TFA9879 is not set +# CONFIG_SND_SOC_TFA989X is not set +CONFIG_SND_SOC_TLV320ADC3XXX=m +CONFIG_SND_SOC_TLV320ADCX140=m +# CONFIG_SND_SOC_TLV320AIC23_I2C is not set +# CONFIG_SND_SOC_TLV320AIC23 is not set +# CONFIG_SND_SOC_TLV320AIC23_SPI is not set +# CONFIG_SND_SOC_TLV320AIC31XX is not set +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_TLV320AIC32X4_SPI=m +# CONFIG_SND_SOC_TLV320AIC3X_I2C is not set +# CONFIG_SND_SOC_TLV320AIC3X is not set +# CONFIG_SND_SOC_TLV320AIC3X_SPI is not set +# CONFIG_SND_SOC_TOPOLOGY_BUILD is not set +CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m +# CONFIG_SND_SOC_TPA6130A2 is not set +# CONFIG_SND_SOC_TS3A227E is not set +CONFIG_SND_SOC_TSCS42XX=m +# CONFIG_SND_SOC_TSCS454 is not set +# CONFIG_SND_SOC_UDA1334 is not set +CONFIG_SND_SOC_UTILS_KUNIT_TEST=m +# CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m +# CONFIG_SND_SOC_WCD938X_SDW is not set +CONFIG_SND_SOC_WCD939X_SDW=m +# CONFIG_SND_SOC_WM8510 is not set +# CONFIG_SND_SOC_WM8523 is not set +CONFIG_SND_SOC_WM8524=m +# CONFIG_SND_SOC_WM8580 is not set +# CONFIG_SND_SOC_WM8711 is not set +# CONFIG_SND_SOC_WM8728 is not set +CONFIG_SND_SOC_WM8731_I2C=m +CONFIG_SND_SOC_WM8731=m +CONFIG_SND_SOC_WM8731_SPI=m +# CONFIG_SND_SOC_WM8737 is not set +# CONFIG_SND_SOC_WM8741 is not set +# CONFIG_SND_SOC_WM8750 is not set +# CONFIG_SND_SOC_WM8753 is not set +# CONFIG_SND_SOC_WM8770 is not set +# CONFIG_SND_SOC_WM8776 is not set +# CONFIG_SND_SOC_WM8782 is not set +CONFIG_SND_SOC_WM8804_I2C=m +CONFIG_SND_SOC_WM8804=m +# CONFIG_SND_SOC_WM8804_SPI is not set +# CONFIG_SND_SOC_WM8903 is not set +# CONFIG_SND_SOC_WM8904 is not set +CONFIG_SND_SOC_WM8940=m +# CONFIG_SND_SOC_WM8960 is not set +CONFIG_SND_SOC_WM8961=m +# CONFIG_SND_SOC_WM8962 is not set +# CONFIG_SND_SOC_WM8974 is not set +# CONFIG_SND_SOC_WM8978 is not set +# CONFIG_SND_SOC_WM8985 is not set +# CONFIG_SND_SOC_WSA881X is not set +CONFIG_SND_SOC_WSA883X=m +CONFIG_SND_SOC_WSA884X=m +# CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER is not set +# CONFIG_SND_SOC_XILINX_I2S is not set +# CONFIG_SND_SOC_XILINX_SPDIF is not set +# CONFIG_SND_SOC_XTFPGA_I2S is not set +CONFIG_SND_SOC_ZL38060=m +CONFIG_SND_SONICVIBES=m +# CONFIG_SND_SPI is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_ACPI is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM is not set +# CONFIG_SND_SST_ATOM_HIFI2_PLATFORM_PCI is not set +# CONFIG_SND_SUN4I_CODEC is not set +# CONFIG_SND_SUN4I_I2S is not set +# CONFIG_SND_SUN4I_SPDIF is not set +# CONFIG_SND_SUN50I_CODEC_ANALOG is not set +# CONFIG_SND_SUN8I_CODEC_ANALOG is not set +# CONFIG_SND_SUN8I_CODEC is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_TEST_COMPONENT is not set +CONFIG_SND_TRIDENT=m +CONFIG_SND_UMP_LEGACY_RAWMIDI=y +CONFIG_SND_USB_6FIRE=m +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_USB_AUDIO_MIDI_V2=y +CONFIG_SND_USB_CAIAQ_INPUT=y +CONFIG_SND_USB_CAIAQ=m +CONFIG_SND_USB_HIFACE=m +CONFIG_SND_USB_PODHD=m +CONFIG_SND_USB_POD=m +CONFIG_SND_USB_TONEPORT=m +CONFIG_SND_USB_UA101=m +CONFIG_SND_USB_US122L=m +CONFIG_SND_USB_USX2Y=m +CONFIG_SND_USB_VARIAX=m +CONFIG_SND_USB=y +# CONFIG_SND_VERBOSE_PRINTK is not set +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +CONFIG_SND_VIRMIDI=m +CONFIG_SND_VIRTIO=m +CONFIG_SND_VIRTUOSO=m +CONFIG_SND_VX222=m +# CONFIG_SND_X86 is not set +# CONFIG_SND_XEN_FRONTEND is not set +CONFIG_SND_YMFPCI=m +CONFIG_SNET_VDPA=m +CONFIG_SOC_STARFIVE=y +# CONFIG_SOC_TI is not set +CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM=y +CONFIG_SOFTLOCKUP_DETECTOR=y +CONFIG_SOFT_WATCHDOG=m +CONFIG_SOLARIS_X86_PARTITION=y +CONFIG_SONY_FF=y +# CONFIG_SONYPI is not set +CONFIG_SOUND=m +CONFIG_SOUND_OSS_CORE_PRECLAIM=y +# CONFIG_SOUNDWIRE_AMD is not set +# CONFIG_SOUNDWIRE_CADENCE is not set +CONFIG_SOUNDWIRE_GENERIC_ALLOCATION=m +# CONFIG_SOUNDWIRE_INTEL is not set +# CONFIG_SOUNDWIRE is not set +# CONFIG_SOUNDWIRE_QCOM is not set +CONFIG_SPARSE_IRQ=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_SPARSEMEM=y +CONFIG_SPEAKUP=m +CONFIG_SPEAKUP_SYNTH_ACNTSA=m +CONFIG_SPEAKUP_SYNTH_APOLLO=m +CONFIG_SPEAKUP_SYNTH_AUDPTR=m +CONFIG_SPEAKUP_SYNTH_BNS=m +# CONFIG_SPEAKUP_SYNTH_DECEXT is not set +CONFIG_SPEAKUP_SYNTH_DECTLK=m +# CONFIG_SPEAKUP_SYNTH_DUMMY is not set +CONFIG_SPEAKUP_SYNTH_LTLK=m +CONFIG_SPEAKUP_SYNTH_SOFT=m +CONFIG_SPEAKUP_SYNTH_SPKOUT=m +CONFIG_SPEAKUP_SYNTH_TXPRT=m +CONFIG_SPI_ALTERA_CORE=m +CONFIG_SPI_ALTERA_DFL=m +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_AMD=y +CONFIG_SPI_AX88796C_COMPRESSION=y +CONFIG_SPI_AX88796C=m +# CONFIG_SPI_AXI_SPI_ENGINE is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_CADENCE is not set +CONFIG_SPI_CADENCE_QUADSPI=m +# CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m +# CONFIG_SPI_CS42L43 is not set +# CONFIG_SPI_DEBUG is not set +# CONFIG_SPI_DESIGNWARE is not set +CONFIG_SPI_DLN2=m +CONFIG_SPI_FSL_LPSPI=m +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_GPIO is not set +# CONFIG_SPI_HISI_KUNPENG is not set +# CONFIG_SPI_HISI_SFC_V3XX is not set +# CONFIG_SPI_LANTIQ_SSC is not set +# CONFIG_SPI_LOOPBACK_TEST is not set +CONFIG_SPI_MASTER=y +CONFIG_SPI_MEM=y +CONFIG_SPI_MICROCHIP_CORE=m +CONFIG_SPI_MICROCHIP_CORE_QSPI=m +CONFIG_SPI_MUX=m +# CONFIG_SPI_MXIC is not set +# CONFIG_SPI_OC_TINY is not set +CONFIG_SPI_PCI1XXXX=m +# CONFIG_SPI_PL022 is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_ROCKCHIP is not set +# CONFIG_SPI_SC18IS602 is not set +CONFIG_SPI_SIFIVE=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_SLAVE_SYSTEM_CONTROL=m +CONFIG_SPI_SLAVE_TIME=m +CONFIG_SPI_SN_F_OSPI=m +CONFIG_SPI_SPIDEV=m +# CONFIG_SPI_TLE62X0 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +CONFIG_SPI=y +# CONFIG_SPI_ZYNQMP_GQSPI is not set +# CONFIG_SPMI_HISI3670 is not set +# CONFIG_SPMI is not set +# CONFIG_SPS30_I2C is not set +# CONFIG_SPS30_SERIAL is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT is not set +# CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI is not set +CONFIG_SQUASHFS_COMPILE_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_COMPILE_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_DECOMP_MULTI is not set +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_DECOMP_SINGLE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +# CONFIG_SQUASHFS_FILE_CACHE is not set +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_SRAM is not set +# CONFIG_SRF04 is not set +# CONFIG_SRF08 is not set +CONFIG_SSB_DRIVER_GPIO=y +CONFIG_SSB_DRIVER_PCICORE=y +CONFIG_SSB=m +CONFIG_SSB_PCIHOST=y +CONFIG_SSB_SDIOHOST=y +# CONFIG_SSFDC is not set +CONFIG_SSIF_IPMI_BMC=m +CONFIG_STACKDEPOT_MAX_FRAMES=64 +CONFIG_STACK_HASH_ORDER=20 +CONFIG_STACKINIT_KUNIT_TEST=m +CONFIG_STACKPROTECTOR_PER_TASK=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_STACKPROTECTOR=y +# CONFIG_STACKTRACE_BUILD_ID is not set +CONFIG_STACK_TRACER=y +CONFIG_STACK_VALIDATION=y +# CONFIG_STAGING_MEDIA_DEPRECATED is not set +CONFIG_STAGING_MEDIA=y +CONFIG_STAGING=y +CONFIG_STANDALONE=y +CONFIG_STARFIVE_JH8100_INTC=y +# CONFIG_STARFIVE_STARLINK_CACHE is not set +# CONFIG_STARFIVE_STARLINK_PMU is not set +CONFIG_STARFIVE_WATCHDOG=y +# CONFIG_STATIC_CALL_SELFTEST is not set +# CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_STE10XP=m +CONFIG_STEAM_FF=y +CONFIG_STK3310=m +# CONFIG_STK8312 is not set +# CONFIG_STK8BA50 is not set +# CONFIG_STM_DUMMY is not set +CONFIG_STM=m +CONFIG_STMMAC_ETH=m +# CONFIG_STMMAC_PCI is not set +CONFIG_STMMAC_PLATFORM=m +# CONFIG_STMMAC_SELFTESTS is not set +# CONFIG_STM_PROTO_BASIC is not set +# CONFIG_STM_PROTO_SYS_T is not set +# CONFIG_STM_SOURCE_CONSOLE is not set +# CONFIG_STM_SOURCE_FTRACE is not set +# CONFIG_STM_SOURCE_HEARTBEAT is not set +CONFIG_STRCAT_KUNIT_TEST=m +CONFIG_STRICT_DEVMEM=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_STRING_HELPERS_KUNIT_TEST=m +CONFIG_STRING_KUNIT_TEST=m +# CONFIG_STRING_SELFTEST is not set +CONFIG_STRIP_ASM_SYMS=y +CONFIG_STRSCPY_KUNIT_TEST=m +CONFIG_ST_UVIS25_I2C=m +CONFIG_ST_UVIS25=m +CONFIG_ST_UVIS25_SPI=m +CONFIG_SUN20I_D1_CCU=y +CONFIG_SUN20I_D1_R_CCU=y +# CONFIG_SUN50I_DE2_BUS is not set +# CONFIG_SUN50I_IOMMU is not set +CONFIG_SUNDANCE=m +# CONFIG_SUNDANCE_MMIO is not set +CONFIG_SUNGEM=m +CONFIG_SUN_PARTITION=y +CONFIG_SUNRPC_DEBUG=y +CONFIG_SUNRPC_DISABLE_INSECURE_ENCTYPES=y +CONFIG_SUNRPC_GSS=m +CONFIG_SUNRPC=m +CONFIG_SUNRPC_XPRT_RDMA=m +# CONFIG_SURFACE_3_POWER_OPREGION is not set +CONFIG_SURFACE_ACPI_NOTIFY=m +CONFIG_SURFACE_AGGREGATOR_BUS=y +CONFIG_SURFACE_AGGREGATOR_CDEV=m +# CONFIG_SURFACE_AGGREGATOR_ERROR_INJECTION is not set +CONFIG_SURFACE_AGGREGATOR_HUB=m +CONFIG_SURFACE_AGGREGATOR=m +CONFIG_SURFACE_AGGREGATOR_REGISTRY=m +CONFIG_SURFACE_AGGREGATOR_TABLET_SWITCH=m +CONFIG_SURFACE_DTX=m +CONFIG_SURFACE_GPE=m +CONFIG_SURFACE_HID=m +CONFIG_SURFACE_HOTPLUG=m +CONFIG_SURFACE_KBD=m +CONFIG_SURFACE_PLATFORM_PROFILE=m +CONFIG_SURFACE_PLATFORMS=y +CONFIG_SURFACE_PRO3_BUTTON=m +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_SUSPEND=y +CONFIG_SWAP=y +# CONFIG_SWIOTLB_DYNAMIC is not set +# CONFIG_SW_SYNC is not set +CONFIG_SX9310=m +CONFIG_SX9324=m +CONFIG_SX9360=m +# CONFIG_SX9500 is not set +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_SYNC_FILE=y +CONFIG_SYNCLINK_GT=m +CONFIG_SYN_COOKIES=y +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +CONFIG_SYNTH_EVENTS=y +CONFIG_SYSCON_REBOOT_MODE=y +CONFIG_SYSCTL_KUNIT_TEST=m +CONFIG_SYSCTL=y +CONFIG_SYSFB_SIMPLEFB=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_SYSFS_SYSCALL=y +# CONFIG_SYSTEM76_ACPI is not set +CONFIG_SYSTEM_BLACKLIST_AUTH_UPDATE=y +CONFIG_SYSTEM_BLACKLIST_HASH_LIST="" +CONFIG_SYSTEM_BLACKLIST_KEYRING=y +CONFIG_SYSTEM_EXTRA_CERTIFICATE_SIZE=4096 +CONFIG_SYSTEM_EXTRA_CERTIFICATE=y +# CONFIG_SYSTEMPORT is not set +# CONFIG_SYSTEM_REVOCATION_LIST is not set +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSV68_PARTITION is not set +CONFIG_SYSV_FS=m +CONFIG_SYSVIPC=y +# CONFIG_T5403 is not set +CONFIG_TABLET_SERIAL_WACOM4=m +CONFIG_TABLET_USB_ACECAD=m +CONFIG_TABLET_USB_AIPTEK=m +CONFIG_TABLET_USB_HANWANG=m +CONFIG_TABLET_USB_KBTAB=m +CONFIG_TABLET_USB_PEGASUS=m +CONFIG_TARGET_CORE=m +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_TASKS_RCU=y +CONFIG_TASKSTATS=y +CONFIG_TASK_XACCT=y +CONFIG_TCG_ATMEL=m +CONFIG_TCG_CRB=y +# CONFIG_TCG_INFINEON is not set +CONFIG_TCG_NSC=m +CONFIG_TCG_TIS_I2C_ATMEL=m +CONFIG_TCG_TIS_I2C_CR50=m +CONFIG_TCG_TIS_I2C_INFINEON=m +CONFIG_TCG_TIS_I2C=m +CONFIG_TCG_TIS_I2C_NUVOTON=m +CONFIG_TCG_TIS_SPI_CR50=y +CONFIG_TCG_TIS_SPI=m +# CONFIG_TCG_TIS_ST33ZP24_I2C is not set +# CONFIG_TCG_TIS_ST33ZP24_SPI is not set +CONFIG_TCG_TIS=y +CONFIG_TCG_TPM2_HMAC=y +CONFIG_TCG_TPM=y +CONFIG_TCG_VTPM_PROXY=m +# CONFIG_TCG_XEN is not set +CONFIG_TCM_FC=m +CONFIG_TCM_FILEIO=m +CONFIG_TCM_IBLOCK=m +CONFIG_TCM_PSCSI=m +# CONFIG_TCM_QLA2XXX_DEBUG is not set +CONFIG_TCM_QLA2XXX=m +CONFIG_TCM_USER2=m +CONFIG_TCP_AO=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BBR=m +CONFIG_TCP_CONG_BIC=m +CONFIG_TCP_CONG_CDG=m +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_DCTCP=m +CONFIG_TCP_CONG_HSTCP=m +CONFIG_TCP_CONG_HTCP=m +CONFIG_TCP_CONG_HYBLA=m +CONFIG_TCP_CONG_ILLINOIS=m +CONFIG_TCP_CONG_LP=m +CONFIG_TCP_CONG_NV=m +CONFIG_TCP_CONG_SCALABLE=m +CONFIG_TCP_CONG_VEGAS=m +CONFIG_TCP_CONG_VENO=m +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_YEAH=m +CONFIG_TCP_MD5SIG=y +# CONFIG_TCS3414 is not set +# CONFIG_TCS3472 is not set +CONFIG_TDX_GUEST_DRIVER=m +CONFIG_TEE=m +CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m +CONFIG_TELCLOCK=m +CONFIG_TERANETICS_PHY=m +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +# CONFIG_TEST_BITMAP is not set +# CONFIG_TEST_BITOPS is not set +# CONFIG_TEST_BLACKHOLE_DEV is not set +CONFIG_TEST_BPF=m +# CONFIG_TEST_CLOCKSOURCE_WATCHDOG is not set +CONFIG_TEST_CPUMASK=m +# CONFIG_TEST_DHRY is not set +# CONFIG_TEST_DIV64 is not set +# CONFIG_TEST_DYNAMIC_DEBUG is not set +# CONFIG_TEST_FIRMWARE is not set +# CONFIG_TEST_FPU is not set +# CONFIG_TEST_FREE_PAGES is not set +# CONFIG_TEST_HASH is not set +# CONFIG_TEST_HEXDUMP is not set +CONFIG_TEST_HMM=m +# CONFIG_TEST_IDA is not set +CONFIG_TEST_IOV_ITER=m +# CONFIG_TEST_KMOD is not set +CONFIG_TEST_KSTRTOX=y +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_TEST_LKM is not set +CONFIG_TEST_LOCKUP=m +# CONFIG_TEST_MAPLE_TREE is not set +# CONFIG_TEST_MEMCAT_P is not set +# CONFIG_TEST_MEMINIT is not set +# CONFIG_TEST_MIN_HEAP is not set +# CONFIG_TEST_OBJAGG is not set +# CONFIG_TEST_OBJPOOL is not set +# CONFIG_TEST_OVERFLOW is not set +# CONFIG_TEST_PARMAN is not set +# CONFIG_TEST_POWER is not set +# CONFIG_TEST_PRINTF is not set +# CONFIG_TEST_REF_TRACKER is not set +# CONFIG_TEST_RHASHTABLE is not set +# CONFIG_TEST_SCANF is not set +# CONFIG_TEST_SIPHASH is not set +CONFIG_TEST_SORT=m +# CONFIG_TEST_STACKINIT is not set +# CONFIG_TEST_STATIC_KEYS is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_STRSCPY is not set +# CONFIG_TEST_SYSCTL is not set +# CONFIG_TEST_UBSAN is not set +# CONFIG_TEST_UDELAY is not set +# CONFIG_TEST_USER_COPY is not set +# CONFIG_TEST_UUID is not set +CONFIG_TEST_VMALLOC=m +# CONFIG_TEST_XARRAY is not set +# CONFIG_THERMAL_DEBUGFS is not set +# CONFIG_THERMAL_DEFAULT_GOV_BANG_BANG is not set +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +# CONFIG_THERMAL_EMULATION is not set +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_FAIR_SHARE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_THERMAL_HWMON=y +# CONFIG_THERMAL_MMIO is not set +CONFIG_THERMAL_NETLINK=y +# CONFIG_THERMAL_OF is not set +CONFIG_THERMAL_STATISTICS=y +# CONFIG_THERMAL_WRITABLE_TRIPS is not set +CONFIG_THERMAL=y +CONFIG_THREAD_SIZE_ORDER=2 +CONFIG_THRUSTMASTER_FF=y +# CONFIG_TI_ADC081C is not set +# CONFIG_TI_ADC0832 is not set +# CONFIG_TI_ADC084S021 is not set +# CONFIG_TI_ADC108S102 is not set +# CONFIG_TI_ADC12138 is not set +CONFIG_TI_ADC128S052=m +# CONFIG_TI_ADC161S626 is not set +CONFIG_TI_ADS1015=m +CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set +# CONFIG_TI_ADS124S08 is not set +# CONFIG_TI_ADS1298 is not set +CONFIG_TI_ADS131E08=m +CONFIG_TI_ADS7924=m +# CONFIG_TI_ADS7950 is not set +CONFIG_TI_ADS8344=m +# CONFIG_TI_ADS8688 is not set +# CONFIG_TICK_CPU_ACCOUNTING is not set +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TI_DAC082S085 is not set +# CONFIG_TI_DAC5571 is not set +CONFIG_TI_DAC7311=m +# CONFIG_TI_DAC7612 is not set +CONFIG_TIFM_7XX1=m +CONFIG_TIFM_CORE=m +CONFIG_TIGON3_HWMON=y +CONFIG_TIGON3=m +CONFIG_TI_LMP92064=m +CONFIG_TIME_KUNIT_TEST=m +CONFIG_TIME_NS=y +CONFIG_TIMERFD=y +CONFIG_TIMERLAT_TRACER=y +# CONFIG_TINYDRM_HX8357D is not set +CONFIG_TINYDRM_ILI9163=m +# CONFIG_TINYDRM_ILI9225 is not set +# CONFIG_TINYDRM_ILI9341 is not set +CONFIG_TINYDRM_ILI9486=m +# CONFIG_TINYDRM_MI0283QT is not set +# CONFIG_TINYDRM_REPAPER is not set +# CONFIG_TINYDRM_ST7586 is not set +# CONFIG_TINYDRM_ST7735R is not set +CONFIG_TIPC_CRYPTO=y +CONFIG_TIPC_DIAG=m +CONFIG_TIPC=m +# CONFIG_TIPC_MEDIA_IB is not set +CONFIG_TIPC_MEDIA_UDP=y +# CONFIG_TI_ST is not set +# CONFIG_TI_TLC4541 is not set +# CONFIG_TI_TMAG5273 is not set +CONFIG_TI_TSC2046=m +CONFIG_TLAN=m +CONFIG_TLS_DEVICE=y +CONFIG_TLS=m +# CONFIG_TLS_TOE is not set +# CONFIG_TMP006 is not set +# CONFIG_TMP007 is not set +CONFIG_TMP117=m +CONFIG_TMPFS_INODE64=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_QUOTA=y +CONFIG_TMPFS_XATTR=y +CONFIG_TMPFS=y +CONFIG_TORTURE_TEST=m +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_ADC is not set +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AR1021_I2C is not set +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +# CONFIG_TOUCHSCREEN_ATMEL_MXT_T37 is not set +CONFIG_TOUCHSCREEN_AUO_PIXCIR=m +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_BU21029 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set +# CONFIG_TOUCHSCREEN_CHIPONE_ICN8505 is not set +CONFIG_TOUCHSCREEN_COLIBRI_VF50=m +CONFIG_TOUCHSCREEN_CY8CTMA140=m +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set +CONFIG_TOUCHSCREEN_CYTTSP5=m +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DMI is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +CONFIG_TOUCHSCREEN_EDT_FT5X06=m +CONFIG_TOUCHSCREEN_EETI=m +CONFIG_TOUCHSCREEN_EGALAX=m +# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set +# CONFIG_TOUCHSCREEN_EKTF2127 is not set +CONFIG_TOUCHSCREEN_ELAN=m +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_EXC3000 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_I2C is not set +# CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI is not set +# CONFIG_TOUCHSCREEN_GOODIX is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_HIDEEP is not set +CONFIG_TOUCHSCREEN_HIMAX_HX83112B=m +CONFIG_TOUCHSCREEN_HYCON_HY46XX=m +CONFIG_TOUCHSCREEN_HYNITRON_CSTXXX=m +CONFIG_TOUCHSCREEN_ILI210X=m +CONFIG_TOUCHSCREEN_ILITEK=m +CONFIG_TOUCHSCREEN_IMAGIS=m +# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +CONFIG_TOUCHSCREEN_IQS5XX=m +CONFIG_TOUCHSCREEN_IQS7211=m +# CONFIG_TOUCHSCREEN_MAX11801 is not set +CONFIG_TOUCHSCREEN_MCS5000=m +# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set +CONFIG_TOUCHSCREEN_MK712=m +CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_MSG2638=m +# CONFIG_TOUCHSCREEN_MTOUCH is not set +CONFIG_TOUCHSCREEN_NOVATEK_NVT_TS=m +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +CONFIG_TOUCHSCREEN_PIXCIR=m +CONFIG_TOUCHSCREEN_RM_TS=m +# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set +# CONFIG_TOUCHSCREEN_S6SY761 is not set +CONFIG_TOUCHSCREEN_SILEAD=m +CONFIG_TOUCHSCREEN_SIS_I2C=m +CONFIG_TOUCHSCREEN_ST1232=m +# CONFIG_TOUCHSCREEN_STMFTS is not set +# CONFIG_TOUCHSCREEN_SUR40 is not set +# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set +# CONFIG_TOUCHSCREEN_SX8654 is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_TOUCHSCREEN_TS4800=m +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +CONFIG_TOUCHSCREEN_TSC2007_IIO=y +CONFIG_TOUCHSCREEN_TSC2007=m +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +CONFIG_TOUCHSCREEN_USB_3M=y +CONFIG_TOUCHSCREEN_USB_COMPOSITE=m +CONFIG_TOUCHSCREEN_USB_DMC_TSC10=y +CONFIG_TOUCHSCREEN_USB_E2I=y +CONFIG_TOUCHSCREEN_USB_EASYTOUCH=y +CONFIG_TOUCHSCREEN_USB_EGALAX=y +CONFIG_TOUCHSCREEN_USB_ELO=y +CONFIG_TOUCHSCREEN_USB_ETT_TC45USB=y +CONFIG_TOUCHSCREEN_USB_ETURBO=y +CONFIG_TOUCHSCREEN_USB_GENERAL_TOUCH=y +CONFIG_TOUCHSCREEN_USB_GOTOP=y +CONFIG_TOUCHSCREEN_USB_GUNZE=y +CONFIG_TOUCHSCREEN_USB_IDEALTEK=y +CONFIG_TOUCHSCREEN_USB_IRTOUCH=y +CONFIG_TOUCHSCREEN_USB_ITM=y +CONFIG_TOUCHSCREEN_USB_JASTEC=y +CONFIG_TOUCHSCREEN_USB_NEXIO=y +CONFIG_TOUCHSCREEN_USB_PANJIT=y +CONFIG_TOUCHSCREEN_USB_ZYTRONIC=y +CONFIG_TOUCHSCREEN_WACOM_I2C=m +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set +# CONFIG_TOUCHSCREEN_WM97XX is not set +CONFIG_TOUCHSCREEN_ZET6223=m +CONFIG_TOUCHSCREEN_ZFORCE=m +CONFIG_TOUCHSCREEN_ZINITIX=m +# CONFIG_TPL0102 is not set +CONFIG_TPM_KEY_PARSER=m +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +CONFIG_TPS6594_ESM=m +CONFIG_TPS6594_PFSM=m +# CONFIG_TPS68470_PMIC_OPREGION is not set +CONFIG_TRACE_EVAL_MAP_FILE=y +# CONFIG_TRACE_EVENT_INJECT is not set +# CONFIG_TRACE_MMIO_ACCESS is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS is not set +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +# CONFIG_TRANSPARENT_HUGEPAGE_NEVER is not set +CONFIG_TRANSPARENT_HUGEPAGE=y +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_TRUSTED_KEYS_TEE=y +CONFIG_TRUSTED_KEYS_TPM=y +CONFIG_TRUSTED_KEYS=y +# CONFIG_TS4800_IRQ is not set +# CONFIG_TS4800_WATCHDOG is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2591 is not set +CONFIG_TSL2772=m +# CONFIG_TSL4531 is not set +CONFIG_TSNEP=m +# CONFIG_TSNEP_SELFTESTS is not set +# CONFIG_TSYS01 is not set +# CONFIG_TSYS02D is not set +# CONFIG_TTY_PRINTK is not set +CONFIG_TTY=y +CONFIG_TULIP=m +CONFIG_TULIP_MMIO=y +# CONFIG_TULIP_MWI is not set +# CONFIG_TULIP_NAPI is not set +CONFIG_TUNE_GENERIC=y +CONFIG_TUN=m +# CONFIG_TUN_VNET_CROSS_LE is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +CONFIG_TXGBE=m +# CONFIG_TYPEC_ANX7411 is not set +CONFIG_TYPEC_DP_ALTMODE=m +CONFIG_TYPEC_FUSB302=m +CONFIG_TYPEC_HD3SS3220=m +CONFIG_TYPEC=m +CONFIG_TYPEC_MUX_FSA4480=m +CONFIG_TYPEC_MUX_GPIO_SBU=m +CONFIG_TYPEC_MUX_IT5205=m +CONFIG_TYPEC_MUX_NB7VPQ904M=m +CONFIG_TYPEC_MUX_PI3USB30532=m +CONFIG_TYPEC_MUX_PTN36502=m +# CONFIG_TYPEC_MUX_WCD939X_USBSS is not set +CONFIG_TYPEC_NVIDIA_ALTMODE=m +# CONFIG_TYPEC_QCOM_PMIC is not set +# CONFIG_TYPEC_RT1711H is not set +CONFIG_TYPEC_RT1719=m +CONFIG_TYPEC_STUSB160X=m +CONFIG_TYPEC_TCPCI=m +CONFIG_TYPEC_TCPCI_MAXIM=m +CONFIG_TYPEC_TCPCI_MT6370=m +CONFIG_TYPEC_TCPM=m +CONFIG_TYPEC_TPS6598X=m +CONFIG_TYPEC_UCSI=m +CONFIG_TYPEC_WUSB3801=m +CONFIG_TYPHOON=m +CONFIG_UACCE=m +CONFIG_UAPI_HEADER_TEST=y +CONFIG_UBIFS_ATIME_SUPPORT=y +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_AUTHENTICATION=y +CONFIG_UBIFS_FS=m +CONFIG_UBIFS_FS_SECURITY=y +CONFIG_UBIFS_FS_XATTR=y +# CONFIG_UBSAN_ALIGNMENT is not set +# CONFIG_UBSAN_BOOL is not set +CONFIG_UBSAN_BOUNDS=y +# CONFIG_UBSAN_DIV_ZERO is not set +# CONFIG_UBSAN_ENUM is not set +CONFIG_UBSAN_SANITIZE_ALL=y +CONFIG_UBSAN_SHIFT=y +# CONFIG_UBSAN_SIGNED_WRAP is not set +# CONFIG_UBSAN_TRAP is not set +# CONFIG_UBSAN_UNREACHABLE is not set +CONFIG_UBSAN=y +CONFIG_UCLAMP_BUCKETS_COUNT=5 +CONFIG_UCLAMP_TASK_GROUP=y +CONFIG_UCLAMP_TASK=y +CONFIG_UCSI_ACPI=m +CONFIG_UCSI_CCG=m +CONFIG_UCSI_STM32G0=m +CONFIG_UDF_FS=m +CONFIG_UDMABUF=y +# CONFIG_UEVENT_HELPER is not set +# CONFIG_UFS_DEBUG is not set +CONFIG_UFS_FS=m +# CONFIG_UFS_FS_WRITE is not set +CONFIG_UHID=m +CONFIG_UID16=y +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_CIF is not set +CONFIG_UIO_DFL=m +# CONFIG_UIO_DMEM_GENIRQ is not set +CONFIG_UIO_HV_GENERIC=m +CONFIG_UIO=m +# CONFIG_UIO_MF624 is not set +# CONFIG_UIO_NETX is not set +CONFIG_UIO_PCI_GENERIC=m +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_PRUSS is not set +# CONFIG_UIO_SERCOS3 is not set +CONFIG_ULI526X=m +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_UNICODE_NORMALIZATION_SELFTEST is not set +CONFIG_UNICODE_UTF8_DATA=y +CONFIG_UNICODE=y +CONFIG_UNIX98_PTYS=y +CONFIG_UNIX_DIAG=y +CONFIG_UNIXWARE_DISKLABEL=y +CONFIG_UNIX=y +CONFIG_UNUSED_KSYMS_WHITELIST="" +# CONFIG_UNWINDER_FRAME_POINTER is not set +CONFIG_UPROBE_EVENTS=y +# CONFIG_US5182D is not set +# CONFIG_USB4_DEBUGFS_WRITE is not set +# CONFIG_USB4_DMA_TEST is not set +# CONFIG_USB4_KUNIT_TEST is not set +CONFIG_USB4_NET=m +CONFIG_USB4=y +CONFIG_USB_ACM=m +CONFIG_USB_ADUTUX=m +CONFIG_USB_ALI_M5632=y +# CONFIG_USB_AMD5536UDC is not set +CONFIG_USB_AN2720=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +CONFIG_USB_APPLEDISPLAY=m +CONFIG_USB_ARMLINUX=y +CONFIG_USB_ATM=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_BDC_UDC is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_CATC=m +# CONFIG_USB_CDC_COMPOSITE is not set +CONFIG_USB_CDNS2_UDC=m +CONFIG_USB_CDNS3_GADGET=y +CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_CDNS3=m +CONFIG_USB_CDNS3_PCI_WRAP=m +CONFIG_USB_CDNS3_STARFIVE=m +# CONFIG_USB_CDNSP_GADGET is not set +# CONFIG_USB_CDNSP_HOST is not set +CONFIG_USB_CDNSP_PCI=m +CONFIG_USB_CDNS_SUPPORT=m +CONFIG_USB_CHAOSKEY=m +CONFIG_USB_CHIPIDEA_GENERIC=m +CONFIG_USB_CHIPIDEA_IMX=m +# CONFIG_USB_CHIPIDEA is not set +CONFIG_USB_CHIPIDEA_MSM=m +CONFIG_USB_CHIPIDEA_NPCM=m +CONFIG_USB_CHIPIDEA_PCI=m +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_EEM=y +# CONFIG_USB_CONFIGFS_F_FS is not set +CONFIG_USB_CONFIGFS_F_HID=y +# CONFIG_USB_CONFIGFS_F_LB_SS is not set +CONFIG_USB_CONFIGFS_F_MIDI2=y +# CONFIG_USB_CONFIGFS_F_MIDI is not set +# CONFIG_USB_CONFIGFS_F_PRINTER is not set +CONFIG_USB_CONFIGFS_F_TCM=y +# CONFIG_USB_CONFIGFS_F_UAC1 is not set +# CONFIG_USB_CONFIGFS_F_UAC1_LEGACY is not set +# CONFIG_USB_CONFIGFS_F_UAC2 is not set +# CONFIG_USB_CONFIGFS_F_UVC is not set +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_OBEX=y +# CONFIG_USB_CONFIGFS_RNDIS is not set +CONFIG_USB_CONFIGFS_SERIAL=y +# CONFIG_USB_CONN_GPIO is not set +CONFIG_USB_CXACRU=m +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +CONFIG_USB_DEFAULT_AUTHORIZATION_MODE=1 +CONFIG_USB_DEFAULT_PERSIST=y +CONFIG_USB_DSBR=m +# CONFIG_USB_DUMMY_HCD is not set +# CONFIG_USB_DWC2_DEBUG is not set +CONFIG_USB_DWC2_DUAL_ROLE=y +# CONFIG_USB_DWC2_HOST is not set +CONFIG_USB_DWC2=m +CONFIG_USB_DWC2_PCI=m +# CONFIG_USB_DWC2_PERIPHERAL is not set +# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set +CONFIG_USB_DWC3_DUAL_ROLE=y +# CONFIG_USB_DWC3_GADGET is not set +# CONFIG_USB_DWC3_HAPS is not set +# CONFIG_USB_DWC3_HOST is not set +CONFIG_USB_DWC3=m +CONFIG_USB_DWC3_OF_SIMPLE=m +CONFIG_USB_DWC3_PCI=m +CONFIG_USB_DWC3_ULPI=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +CONFIG_USB_EMI26=m +CONFIG_USB_EMI62=m +CONFIG_USB_EPSON2888=y +# CONFIG_USB_ETH is not set +CONFIG_USB_EZUSB_FX2=m +# CONFIG_USB_FEW_INIT_RETRIES is not set +# CONFIG_USB_FOTG210_HCD is not set +# CONFIG_USB_FUNCTIONFS is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGETFS is not set +CONFIG_USB_GADGET=m +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 +# CONFIG_USB_GADGET_TARGET is not set +CONFIG_USB_GADGET_VBUS_DRAW=100 +# CONFIG_USB_GADGET_XILINX is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_HID is not set +CONFIG_USB_GL860=m +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GOKU is not set +CONFIG_USB_GPIO_VBUS=m +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_GR_UDC is not set +CONFIG_USB_G_SERIAL=m +CONFIG_USB_GSPCA_BENQ=m +CONFIG_USB_GSPCA_CONEX=m +CONFIG_USB_GSPCA_CPIA1=m +CONFIG_USB_GSPCA_DTCS033=m +CONFIG_USB_GSPCA_ETOMS=m +CONFIG_USB_GSPCA_FINEPIX=m +CONFIG_USB_GSPCA_JEILINJ=m +CONFIG_USB_GSPCA_JL2005BCD=m +CONFIG_USB_GSPCA_KINECT=m +CONFIG_USB_GSPCA_KONICA=m +CONFIG_USB_GSPCA=m +CONFIG_USB_GSPCA_MARS=m +CONFIG_USB_GSPCA_MR97310A=m +CONFIG_USB_GSPCA_NW80X=m +CONFIG_USB_GSPCA_OV519=m +CONFIG_USB_GSPCA_OV534_9=m +CONFIG_USB_GSPCA_OV534=m +CONFIG_USB_GSPCA_PAC207=m +CONFIG_USB_GSPCA_PAC7302=m +CONFIG_USB_GSPCA_PAC7311=m +CONFIG_USB_GSPCA_SE401=m +CONFIG_USB_GSPCA_SN9C2028=m +CONFIG_USB_GSPCA_SN9C20X=m +CONFIG_USB_GSPCA_SONIXB=m +CONFIG_USB_GSPCA_SONIXJ=m +CONFIG_USB_GSPCA_SPCA1528=m +CONFIG_USB_GSPCA_SPCA500=m +CONFIG_USB_GSPCA_SPCA501=m +CONFIG_USB_GSPCA_SPCA505=m +CONFIG_USB_GSPCA_SPCA506=m +CONFIG_USB_GSPCA_SPCA508=m +CONFIG_USB_GSPCA_SPCA561=m +CONFIG_USB_GSPCA_SQ905C=m +CONFIG_USB_GSPCA_SQ905=m +CONFIG_USB_GSPCA_SQ930X=m +CONFIG_USB_GSPCA_STK014=m +CONFIG_USB_GSPCA_STK1135=m +CONFIG_USB_GSPCA_STV0680=m +CONFIG_USB_GSPCA_SUNPLUS=m +CONFIG_USB_GSPCA_T613=m +CONFIG_USB_GSPCA_TOPRO=m +CONFIG_USB_GSPCA_TOUPTEK=m +CONFIG_USB_GSPCA_TV8532=m +CONFIG_USB_GSPCA_VC032X=m +CONFIG_USB_GSPCA_VICAM=m +CONFIG_USB_GSPCA_XIRLINK_CIT=m +CONFIG_USB_GSPCA_ZC3XX=m +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_USB_HCD_BCMA is not set +# CONFIG_USB_HCD_SSB is not set +# CONFIG_USB_HCD_TEST_MODE is not set +CONFIG_USB_HIDDEV=y +CONFIG_USB_HID=y +CONFIG_USB_HSIC_USB3503=m +CONFIG_USB_HSIC_USB4604=m +CONFIG_USB_HSO=m +CONFIG_USB_HUB_USB251XB=m +CONFIG_USB_IDMOUSE=m +CONFIG_USB_IOWARRIOR=m +CONFIG_USBIP_CORE=m +# CONFIG_USBIP_DEBUG is not set +CONFIG_USB_IPHETH=m +CONFIG_USBIP_HOST=m +CONFIG_USBIP_VHCI_HCD=m +CONFIG_USBIP_VHCI_HC_PORTS=8 +CONFIG_USBIP_VHCI_NR_HCS=1 +CONFIG_USBIP_VUDC=m +CONFIG_USB_ISIGHTFW=m +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_ISP1760_DUAL_ROLE=y +# CONFIG_USB_ISP1760_GADGET_ROLE is not set +# CONFIG_USB_ISP1760_HOST_ROLE is not set +# CONFIG_USB_ISP1760 is not set +CONFIG_USB_KAWETH=m +CONFIG_USB_KC2190=y +CONFIG_USB_KEENE=m +CONFIG_USB_LAN78XX=m +CONFIG_USB_LCD=m +CONFIG_USB_LD=m +CONFIG_USB_LEDS_TRIGGER_USBPORT=m +CONFIG_USB_LED_TRIG=y +CONFIG_USB_LEGOTOWER=m +# CONFIG_USB_LINK_LAYER_TEST is not set +# CONFIG_USB_LJCA is not set +CONFIG_USB_M5602=m +# CONFIG_USB_M66592 is not set +CONFIG_USB_MA901=m +# CONFIG_USB_MASS_STORAGE is not set +CONFIG_USB_MAX3420_UDC=m +# CONFIG_USB_MAX3421_HCD is not set +CONFIG_USB_MDC800=m +CONFIG_USB_MICROTEK=m +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_USB_MON=y +CONFIG_USB_MR800=m +# CONFIG_USB_MUSB_GADGET is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_MUSB_HOST is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +CONFIG_USB_NET_AQC111=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_CDC_EEM=m +CONFIG_USB_NET_CDC_MBIM=m +CONFIG_USB_NET_CDC_NCM=m +CONFIG_USB_NET_CDC_SUBSET=m +CONFIG_USB_NET_CH9200=m +CONFIG_USB_NET_CX82310_ETH=m +CONFIG_USB_NET_DM9601=m +CONFIG_USB_NET_DRIVERS=y +CONFIG_USB_NET_GL620A=m +CONFIG_USB_NET_HUAWEI_CDC_NCM=m +CONFIG_USB_NET_INT51X1=m +CONFIG_USB_NET_KALMIA=m +CONFIG_USB_NET_MCS7830=m +CONFIG_USB_NET_NET1080=m +CONFIG_USB_NET_PLUSB=m +CONFIG_USB_NET_QMI_WWAN=m +CONFIG_USB_NET_RNDIS_HOST=m +CONFIG_USB_NET_SMSC75XX=m +CONFIG_USB_NET_SMSC95XX=m +CONFIG_USB_NET_SR9700=m +# CONFIG_USB_NET_SR9800 is not set +CONFIG_USB_NET_ZAURUS=m +CONFIG_USB_OHCI_HCD_PCI=y +CONFIG_USB_OHCI_HCD_PLATFORM=m +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_ONBOARD_DEV=m +CONFIG_USB_ONBOARD_HUB=m +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set +CONFIG_USB_OTG_FSM=m +# CONFIG_USB_OTG_PRODUCTLIST is not set +CONFIG_USB_OTG=y +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_PCI_AMD=y +CONFIG_USB_PCI=y +CONFIG_USBPCWATCHDOG=m +CONFIG_USB_PEGASUS=m +CONFIG_USB_PHY=y +CONFIG_USB_PRINTER=m +CONFIG_USB_PULSE8_CEC=m +# CONFIG_USB_PWC_DEBUG is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +CONFIG_USB_PWC=m +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_R8A66597 is not set +CONFIG_USB_RAINSHADOW_CEC=m +# CONFIG_USB_RAREMONO is not set +CONFIG_USB_RAW_GADGET=m +CONFIG_USB_ROLE_SWITCH=y +CONFIG_USB_RTL8150=m +CONFIG_USB_RTL8152=m +CONFIG_USB_RTL8153_ECM=m +CONFIG_USB_S2255=m +CONFIG_USB_SERIAL_AIRCABLE=m +CONFIG_USB_SERIAL_ARK3116=m +CONFIG_USB_SERIAL_BELKIN=m +CONFIG_USB_SERIAL_CH341=m +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_CP210X=m +CONFIG_USB_SERIAL_CYBERJACK=m +CONFIG_USB_SERIAL_CYPRESS_M8=m +CONFIG_USB_SERIAL_DEBUG=m +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m +CONFIG_USB_SERIAL_EDGEPORT=m +CONFIG_USB_SERIAL_EDGEPORT_TI=m +CONFIG_USB_SERIAL_EMPEG=m +CONFIG_USB_SERIAL_F81232=m +CONFIG_USB_SERIAL_F8153X=m +CONFIG_USB_SERIAL_FTDI_SIO=m +CONFIG_USB_SERIAL_GARMIN=m +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_IPAQ=m +CONFIG_USB_SERIAL_IPW=m +CONFIG_USB_SERIAL_IR=m +CONFIG_USB_SERIAL_IUU=m +CONFIG_USB_SERIAL_KEYSPAN=m +CONFIG_USB_SERIAL_KEYSPAN_PDA=m +CONFIG_USB_SERIAL_KLSI=m +CONFIG_USB_SERIAL_KOBIL_SCT=m +CONFIG_USB_SERIAL_MCT_U232=m +# CONFIG_USB_SERIAL_METRO is not set +CONFIG_USB_SERIAL_MOS7720=m +CONFIG_USB_SERIAL_MOS7840=m +# CONFIG_USB_SERIAL_MXUPORT is not set +CONFIG_USB_SERIAL_NAVMAN=m +CONFIG_USB_SERIAL_OMNINET=m +CONFIG_USB_SERIAL_OPTICON=m +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_SERIAL_OTI6858=m +CONFIG_USB_SERIAL_PL2303=m +CONFIG_USB_SERIAL_QCAUX=m +CONFIG_USB_SERIAL_QT2=m +CONFIG_USB_SERIAL_QUALCOMM=m +CONFIG_USB_SERIAL_SAFE=m +CONFIG_USB_SERIAL_SAFE_PADDED=y +CONFIG_USB_SERIAL_SIERRAWIRELESS=m +CONFIG_USB_SERIAL_SIMPLE=m +CONFIG_USB_SERIAL_SPCP8X5=m +CONFIG_USB_SERIAL_SSU100=m +CONFIG_USB_SERIAL_SYMBOL=m +CONFIG_USB_SERIAL_TI=m +CONFIG_USB_SERIAL_UPD78F0730=m +CONFIG_USB_SERIAL_VISOR=m +CONFIG_USB_SERIAL_WHITEHEAT=m +# CONFIG_USB_SERIAL_WISHBONE is not set +CONFIG_USB_SERIAL_XR=m +CONFIG_USB_SERIAL_XSENS_MT=m +CONFIG_USB_SERIAL=y +CONFIG_USB_SEVSEG=m +CONFIG_USB_SI470X=m +# CONFIG_USB_SI4713 is not set +CONFIG_USB_SIERRA_NET=m +CONFIG_USB_SISUSBVGA=m +# CONFIG_USB_SL811_CS is not set +CONFIG_USB_SL811_HCD_ISO=y +CONFIG_USB_SL811_HCD=m +CONFIG_USB_SNP_UDC_PLAT=m +CONFIG_USB_SPEEDTOUCH=m +CONFIG_USB_STKWEBCAM=m +CONFIG_USB_STORAGE_ALAUDA=m +CONFIG_USB_STORAGE_CYPRESS_ATACB=m +CONFIG_USB_STORAGE_DATAFAB=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_ENE_UB6250=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_KARMA=m +CONFIG_USB_STORAGE=m +CONFIG_USB_STORAGE_ONETOUCH=m +CONFIG_USB_STORAGE_REALTEK=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STV06XX=m +CONFIG_USB_SUPPORT=y +# CONFIG_USB_TEST is not set +CONFIG_USB_TMC=m +CONFIG_USB_TRANCEVIBRATOR=m +CONFIG_USB_UAS=m +CONFIG_USB_UEAGLEATM=m +CONFIG_USB_UHCI_HCD=y +CONFIG_USB_ULPI_BUS=m +CONFIG_USB_USBNET=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VL600=m +CONFIG_USB_WDM=m +CONFIG_USB_XEN_HCD=m +CONFIG_USB_XHCI_DBGCAP=y +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_HISTB is not set +CONFIG_USB_XHCI_PCI_RENESAS=y +CONFIG_USB_XHCI_PCI=y +CONFIG_USB_XHCI_PLATFORM=m +CONFIG_USB_XUSBATM=m +CONFIG_USB=y +CONFIG_USB_YUREX=m +# CONFIG_USB_ZERO is not set +CONFIG_USB_ZR364XX=m +# CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m +# CONFIG_USER_DECRYPTED_DATA is not set +# CONFIG_USER_EVENTS is not set +CONFIG_USERFAULTFD=y +CONFIG_U_SERIAL_CONSOLE=y +# CONFIG_USERIO is not set +CONFIG_USER_NS=y +CONFIG_UTS_NS=y +# CONFIG_UV_SYSFS is not set +# CONFIG_V4L2_FLASH_LED_CLASS is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_V4L_PLATFORM_DRIVERS is not set +CONFIG_V4L_TEST_DRIVERS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_VCAP=y +CONFIG_VCHIQ_CDEV=y +CONFIG_VCNL3020=m +# CONFIG_VCNL4000 is not set +CONFIG_VCNL4035=m +CONFIG_VCPU_STALL_DETECTOR=m +CONFIG_VDPA=m +CONFIG_VDPA_SIM_BLOCK=m +CONFIG_VDPA_SIM=m +CONFIG_VDPA_SIM_NET=m +CONFIG_VDPA_USER=m +CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set +# CONFIG_VEML6070 is not set +# CONFIG_VEML6075 is not set +CONFIG_VETH=m +# CONFIG_VF610_ADC is not set +# CONFIG_VF610_DAC is not set +CONFIG_VFAT_FS=m +CONFIG_VFIO_CONTAINER=y +# CONFIG_VFIO_DEBUGFS is not set +# CONFIG_VFIO_DEVICE_CDEV is not set +CONFIG_VFIO_GROUP=y +CONFIG_VFIO_IOMMU_TYPE1=m +CONFIG_VFIO=m +CONFIG_VFIO_MDEV=m +# CONFIG_VFIO_NOIOMMU is not set +CONFIG_VFIO_PCI=m +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_VGA_ARB=y +CONFIG_VGA_CONSOLE=y +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_VHOST_MENU=y +CONFIG_VHOST_NET=m +CONFIG_VHOST_SCSI=m +CONFIG_VHOST_VDPA=m +CONFIG_VHOST_VSOCK=m +CONFIG_VIA_RHINE=m +CONFIG_VIA_RHINE_MMIO=y +CONFIG_VIA_VELOCITY=m +CONFIG_VIDEO_AD5820=m +# CONFIG_VIDEO_AD9389B is not set +CONFIG_VIDEO_ADP1653=m +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_ADV748X is not set +# CONFIG_VIDEO_ADV7511 is not set +# CONFIG_VIDEO_ADV7604_CEC is not set +# CONFIG_VIDEO_ADV7604 is not set +# CONFIG_VIDEO_ADV7842_CEC is not set +# CONFIG_VIDEO_ADV7842 is not set +# CONFIG_VIDEO_ADV_DEBUG is not set +CONFIG_VIDEO_AK7375=m +# CONFIG_VIDEO_AK881X is not set +# CONFIG_VIDEO_ALVIUM_CSI2 is not set +CONFIG_VIDEO_AR0521=m +CONFIG_VIDEO_AU0828=m +# CONFIG_VIDEO_AU0828_RC is not set +CONFIG_VIDEO_AU0828_V4L2=y +# CONFIG_VIDEO_BT819 is not set +CONFIG_VIDEO_BT848=m +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_CADENCE_CSI2RX is not set +CONFIG_VIDEO_CADENCE_CSI2TX=m +# CONFIG_VIDEO_CADENCE is not set +# CONFIG_VIDEO_CAFE_CCIC is not set +CONFIG_VIDEO_CAMERA_SENSOR=y +CONFIG_VIDEO_CCS=m +CONFIG_VIDEO_CS5345=m +CONFIG_VIDEO_CS53L32A=m +CONFIG_VIDEO_CX18_ALSA=m +CONFIG_VIDEO_CX18=m +CONFIG_VIDEO_CX231XX_ALSA=m +CONFIG_VIDEO_CX231XX_DVB=m +CONFIG_VIDEO_CX231XX=m +CONFIG_VIDEO_CX231XX_RC=y +CONFIG_VIDEO_CX23885=m +# CONFIG_VIDEO_CX25821 is not set +CONFIG_VIDEO_CX25840=m +CONFIG_VIDEO_CX88_ALSA=m +CONFIG_VIDEO_CX88_BLACKBIRD=m +CONFIG_VIDEO_CX88_DVB=m +CONFIG_VIDEO_CX88_ENABLE_VP3054=y +CONFIG_VIDEO_CX88=m +CONFIG_VIDEO_CX88_VP3054=m +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_DS90UB913=m +CONFIG_VIDEO_DS90UB953=m +CONFIG_VIDEO_DS90UB960=m +# CONFIG_VIDEO_DT3155 is not set +CONFIG_VIDEO_DW9714=m +CONFIG_VIDEO_DW9719=m +CONFIG_VIDEO_DW9768=m +CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set +CONFIG_VIDEO_EM28XX_ALSA=m +CONFIG_VIDEO_EM28XX_DVB=m +CONFIG_VIDEO_EM28XX=m +CONFIG_VIDEO_EM28XX_RC=m +CONFIG_VIDEO_EM28XX_V4L2=m +CONFIG_VIDEO_ET8EK8=m +CONFIG_VIDEO_FB_IVTV=m +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set +CONFIG_VIDEO_GC2145=m +CONFIG_VIDEO_GO7007_LOADER=m +CONFIG_VIDEO_GO7007=m +CONFIG_VIDEO_GO7007_USB=m +CONFIG_VIDEO_GO7007_USB_S2250_BOARD=m +CONFIG_VIDEO_GS1662=m +CONFIG_VIDEO_HDPVR=m +CONFIG_VIDEO_HEXIUM_GEMINI=m +CONFIG_VIDEO_HEXIUM_ORION=m +CONFIG_VIDEO_HI556=m +CONFIG_VIDEO_HI846=m +CONFIG_VIDEO_HI847=m +# CONFIG_VIDEO_I2C is not set +CONFIG_VIDEO_IMX208=m +CONFIG_VIDEO_IMX214=m +CONFIG_VIDEO_IMX219=m +CONFIG_VIDEO_IMX258=m +CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m +CONFIG_VIDEO_IMX290=m +CONFIG_VIDEO_IMX296=m +CONFIG_VIDEO_IMX319=m +CONFIG_VIDEO_IMX334=m +CONFIG_VIDEO_IMX335=m +CONFIG_VIDEO_IMX355=m +CONFIG_VIDEO_IMX412=m +CONFIG_VIDEO_IMX415=m +# CONFIG_VIDEO_IPU3_CIO2 is not set +CONFIG_VIDEO_IR_I2C=m +# CONFIG_VIDEO_ISL7998X is not set +# CONFIG_VIDEO_IVTV_ALSA is not set +CONFIG_VIDEO_IVTV=m +# CONFIG_VIDEO_KS0127 is not set +CONFIG_VIDEO_LM3560=m +CONFIG_VIDEO_LM3646=m +CONFIG_VIDEO_M52790=m +# CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m +# CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set +# CONFIG_VIDEO_MGB4 is not set +# CONFIG_VIDEO_ML86V7667 is not set +CONFIG_VIDEO_MSP3400=m +CONFIG_VIDEO_MT9M001=m +# CONFIG_VIDEO_MT9M111 is not set +CONFIG_VIDEO_MT9M114=m +CONFIG_VIDEO_MT9P031=m +CONFIG_VIDEO_MT9T112=m +CONFIG_VIDEO_MT9V011=m +CONFIG_VIDEO_MT9V032=m +CONFIG_VIDEO_MT9V111=m +CONFIG_VIDEO_MXB=m +CONFIG_VIDEO_OG01A1B=m +CONFIG_VIDEO_OV01A10=m +CONFIG_VIDEO_OV02A10=m +CONFIG_VIDEO_OV08D10=m +CONFIG_VIDEO_OV08X40=m +CONFIG_VIDEO_OV13858=m +CONFIG_VIDEO_OV13B10=m +CONFIG_VIDEO_OV2640=m +CONFIG_VIDEO_OV2659=m +CONFIG_VIDEO_OV2680=m +CONFIG_VIDEO_OV2685=m +CONFIG_VIDEO_OV2740=m +CONFIG_VIDEO_OV4689=m +CONFIG_VIDEO_OV5640=m +CONFIG_VIDEO_OV5645=m +CONFIG_VIDEO_OV5647=m +CONFIG_VIDEO_OV5648=m +CONFIG_VIDEO_OV5670=m +CONFIG_VIDEO_OV5675=m +CONFIG_VIDEO_OV5693=m +CONFIG_VIDEO_OV5695=m +CONFIG_VIDEO_OV64A40=m +CONFIG_VIDEO_OV6650=m +CONFIG_VIDEO_OV7251=m +CONFIG_VIDEO_OV7640=m +# CONFIG_VIDEO_OV7670 is not set +CONFIG_VIDEO_OV772X=m +CONFIG_VIDEO_OV7740=m +CONFIG_VIDEO_OV8856=m +CONFIG_VIDEO_OV8858=m +CONFIG_VIDEO_OV8865=m +CONFIG_VIDEO_OV9282=m +CONFIG_VIDEO_OV9640=m +CONFIG_VIDEO_OV9650=m +CONFIG_VIDEO_OV9734=m +# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set +CONFIG_VIDEO_PVRUSB2_DVB=y +CONFIG_VIDEO_PVRUSB2=m +CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m +CONFIG_VIDEO_RDACM20=m +# CONFIG_VIDEO_RDACM21 is not set +CONFIG_VIDEO_RJ54N1=m +CONFIG_VIDEO_ROCKCHIP_VDEC=m +CONFIG_VIDEO_S5C73M3=m +CONFIG_VIDEO_S5K4ECGX=m +CONFIG_VIDEO_S5K5BAF=m +CONFIG_VIDEO_S5K6A3=m +CONFIG_VIDEO_SAA6588=m +# CONFIG_VIDEO_SAA7110 is not set +CONFIG_VIDEO_SAA711X=m +CONFIG_VIDEO_SAA7127=m +CONFIG_VIDEO_SAA7134_ALSA=m +CONFIG_VIDEO_SAA7134_DVB=m +CONFIG_VIDEO_SAA7134_GO7007=m +CONFIG_VIDEO_SAA7134=m +CONFIG_VIDEO_SAA7134_RC=y +CONFIG_VIDEO_SAA7146=m +CONFIG_VIDEO_SAA7146_VV=m +CONFIG_VIDEO_SAA7164=m +CONFIG_VIDEO_SAA717X=m +# CONFIG_VIDEO_SAA7185 is not set +CONFIG_VIDEO_SOLO6X10=m +CONFIG_VIDEO_SONY_BTF_MPX=m +CONFIG_VIDEO_STK1160_COMMON=m +CONFIG_VIDEO_STK1160=m +# CONFIG_VIDEO_STKWEBCAM is not set +CONFIG_VIDEO_STM32_DMA2D=m +# CONFIG_VIDEO_ST_MIPID02 is not set +CONFIG_VIDEO_ST_VGXY61=m +CONFIG_VIDEO_TC358743_CEC=y +# CONFIG_VIDEO_TC358743 is not set +# CONFIG_VIDEO_TC358746 is not set +# CONFIG_VIDEO_TDA1997X is not set +CONFIG_VIDEO_TDA7432=m +CONFIG_VIDEO_TDA9840=m +CONFIG_VIDEO_TEA6415C=m +CONFIG_VIDEO_TEA6420=m +# CONFIG_VIDEO_TEGRA_TPG is not set +# CONFIG_VIDEO_THP7312 is not set +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_THS8200 is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +CONFIG_VIDEO_TM6000_ALSA=m +CONFIG_VIDEO_TM6000_DVB=m +CONFIG_VIDEO_TM6000=m +CONFIG_VIDEO_TUNER=m +CONFIG_VIDEO_TVAUDIO=m +# CONFIG_VIDEO_TVP514X is not set +CONFIG_VIDEO_TVP5150=m +# CONFIG_VIDEO_TVP7002 is not set +CONFIG_VIDEO_TW2804=m +# CONFIG_VIDEO_TW5864 is not set +CONFIG_VIDEO_TW686X=m +# CONFIG_VIDEO_TW68 is not set +# CONFIG_VIDEO_TW9900 is not set +CONFIG_VIDEO_TW9903=m +CONFIG_VIDEO_TW9906=m +# CONFIG_VIDEO_TW9910 is not set +CONFIG_VIDEO_UDA1342=m +CONFIG_VIDEO_UPD64031A=m +CONFIG_VIDEO_UPD64083=m +CONFIG_VIDEO_USBTV=m +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set +CONFIG_VIDEO_VICODEC=m +CONFIG_VIDEO_VIM2M=m +CONFIG_VIDEO_VIMC=m +CONFIG_VIDEO_VISL=m +CONFIG_VIDEO_VIVID_CEC=y +CONFIG_VIDEO_VIVID=m +CONFIG_VIDEO_VIVID_MAX_DEVS=64 +CONFIG_VIDEO_VP27SMPX=m +# CONFIG_VIDEO_VPX3220 is not set +CONFIG_VIDEO_WM8739=m +CONFIG_VIDEO_WM8775=m +# CONFIG_VIDEO_XILINX is not set +# CONFIG_VIDEO_ZORAN is not set +# CONFIG_VIPERBOARD_ADC is not set +CONFIG_VIRT_CPU_ACCOUNTING_GEN=y +# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set +CONFIG_VIRT_DRIVERS=y +CONFIG_VIRTIO_BALLOON=m +CONFIG_VIRTIO_BLK=m +CONFIG_VIRTIO_CONSOLE=m +# CONFIG_VIRTIO_DEBUG is not set +CONFIG_VIRTIO_FS=m +# CONFIG_VIRTIO_HARDEN_NOTIFICATION is not set +CONFIG_VIRTIO_INPUT=m +# CONFIG_VIRTIO_IOMMU is not set +CONFIG_VIRTIO_MEM=m +CONFIG_VIRTIO_MENU=y +CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES=y +CONFIG_VIRTIO_MMIO=m +CONFIG_VIRTIO_NET=m +CONFIG_VIRTIO_PCI_LEGACY=y +CONFIG_VIRTIO_PCI=y +# CONFIG_VIRTIO_PMEM is not set +CONFIG_VIRTIO_VDPA=m +CONFIG_VIRTIO_VFIO_PCI=m +CONFIG_VIRTIO_VSOCKETS=m +CONFIG_VIRTIO=y +CONFIG_VIRTUALIZATION=y +CONFIG_VIRT_WIFI=m +# CONFIG_VISL_DEBUGFS is not set +CONFIG_VITESSE_PHY=m +CONFIG_VL53L0X_I2C=m +CONFIG_VL6180=m +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_VLAN_8021Q=m +CONFIG_VLAN_8021Q_MVRP=y +CONFIG_VMAP_STACK=y +# CONFIG_VME_BUS is not set +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VMGENID=y +# CONFIG_VMLINUX_MAP is not set +# CONFIG_VMSPLIT_1G is not set +# CONFIG_VMSPLIT_2G is not set +# CONFIG_VMSPLIT_3G_OPT is not set +CONFIG_VMSPLIT_3G=y +# CONFIG_VMXNET3 is not set +CONFIG_VORTEX=m +CONFIG_VP_VDPA=m +CONFIG_VSOCKETS_DIAG=m +CONFIG_VSOCKETS_LOOPBACK=m +CONFIG_VSOCKETS=m +CONFIG_VSOCKMON=m +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +CONFIG_VT_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_VT=y +# CONFIG_VXFS_FS is not set +# CONFIG_VXGE_DEBUG_TRACE_ALL is not set +CONFIG_VXGE=m +CONFIG_VXLAN=m +# CONFIG_VZ89X is not set +CONFIG_W1_CON=y +CONFIG_W1=m +# CONFIG_W1_MASTER_AMD_AXI is not set +# CONFIG_W1_MASTER_DS1WM is not set +CONFIG_W1_MASTER_DS2482=m +CONFIG_W1_MASTER_DS2490=m +# CONFIG_W1_MASTER_GPIO is not set +# CONFIG_W1_MASTER_MATROX is not set +# CONFIG_W1_MASTER_SGI is not set +CONFIG_W1_MASTER_UART=m +CONFIG_W1_SLAVE_DS2405=m +CONFIG_W1_SLAVE_DS2406=m +CONFIG_W1_SLAVE_DS2408=m +# CONFIG_W1_SLAVE_DS2408_READBACK is not set +CONFIG_W1_SLAVE_DS2413=m +CONFIG_W1_SLAVE_DS2423=m +CONFIG_W1_SLAVE_DS2430=m +CONFIG_W1_SLAVE_DS2431=m +CONFIG_W1_SLAVE_DS2433_CRC=y +CONFIG_W1_SLAVE_DS2433=m +CONFIG_W1_SLAVE_DS2438=m +# CONFIG_W1_SLAVE_DS250X is not set +CONFIG_W1_SLAVE_DS2780=m +CONFIG_W1_SLAVE_DS2781=m +CONFIG_W1_SLAVE_DS2805=m +CONFIG_W1_SLAVE_DS28E04=m +# CONFIG_W1_SLAVE_DS28E17 is not set +CONFIG_W1_SLAVE_SMEM=m +CONFIG_W1_SLAVE_THERM=m +CONFIG_W83627HF_WDT=m +CONFIG_W83877F_WDT=m +CONFIG_W83977F_WDT=m +# CONFIG_WAFER_WDT is not set +# CONFIG_WAN is not set +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +CONFIG_WATCHDOG_CORE=y +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +# CONFIG_WATCHDOG_HRTIMER_PRETIMEOUT is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_PRETIMEOUT_GOV is not set +CONFIG_WATCHDOG_SYSFS=y +CONFIG_WATCHDOG=y +CONFIG_WATCH_QUEUE=y +# CONFIG_WCN36XX_DEBUGFS is not set +CONFIG_WCN36XX=m +CONFIG_WDAT_WDT=m +CONFIG_WDTPCI=m +# CONFIG_WERROR is not set +# CONFIG_WFX is not set +CONFIG_WIL6210_DEBUGFS=y +CONFIG_WIL6210_ISR_COR=y +CONFIG_WIL6210=m +# CONFIG_WIL6210_TRACING is not set +# CONFIG_WILC1000_SDIO is not set +# CONFIG_WILC1000_SPI is not set +CONFIG_WILINK_PLATFORM_DATA=y +CONFIG_WINBOND_840=m +# CONFIG_WIREGUARD_DEBUG is not set +CONFIG_WIREGUARD=m +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_HOTKEY=m +CONFIG_WIRELESS=y +CONFIG_WIZNET_BUS_ANY=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_W5100=m +CONFIG_WIZNET_W5100_SPI=m +CONFIG_WIZNET_W5300=m +CONFIG_WL1251=m +CONFIG_WL1251_SDIO=m +CONFIG_WL1251_SPI=m +CONFIG_WL12XX=m +CONFIG_WL18XX=m +# CONFIG_WLAN_VENDOR_ADMTEK is not set +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_WLAN_VENDOR_ATMEL is not set +CONFIG_WLAN_VENDOR_BROADCOM=y +# CONFIG_WLAN_VENDOR_CISCO is not set +CONFIG_WLAN_VENDOR_INTEL=y +# CONFIG_WLAN_VENDOR_INTERSIL is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y +# CONFIG_WLAN_VENDOR_PURELIFI is not set +CONFIG_WLAN_VENDOR_QUANTENNA=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +# CONFIG_WLAN_VENDOR_SILABS is not set +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN=y +CONFIG_WLCORE=m +CONFIG_WLCORE_SDIO=m +CONFIG_WLCORE_SPI=m +CONFIG_WPCM450_SOC=m +# CONFIG_WQ_CPU_INTENSIVE_REPORT is not set +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +# CONFIG_WQ_WATCHDOG is not set +CONFIG_WWAN_DEBUGFS=y +CONFIG_WWAN_HWSIM=m +CONFIG_WWAN=y +# CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_X25 is not set +CONFIG_X9250=m +CONFIG_XDP_SOCKETS_DIAG=m +CONFIG_XDP_SOCKETS=y +# CONFIG_XEN_GRANT_DMA_ALLOC is not set +CONFIG_XEN_MEMORY_HOTPLUG_LIMIT=512 +CONFIG_XEN_PRIVCMD_EVENTFD=y +CONFIG_XEN_PRIVCMD_IRQFD=y +CONFIG_XEN_PRIVCMD=m +# CONFIG_XEN_PVCALLS_FRONTEND is not set +CONFIG_XEN_PVHVM_GUEST=y +CONFIG_XEN_UNPOPULATED_ALLOC=y +# CONFIG_XEN_VIRTIO_FORCE_GRANT is not set +CONFIG_XEN_VIRTIO=y +CONFIG_XFRM_INTERFACE=m +CONFIG_XFRM_MIGRATE=y +CONFIG_XFRM_OFFLOAD=y +CONFIG_XFRM_STATISTICS=y +CONFIG_XFRM_SUB_POLICY=y +# CONFIG_XFRM_USER_COMPAT is not set +CONFIG_XFRM_USER=y +CONFIG_XFRM=y +# CONFIG_XFS_DEBUG is not set +CONFIG_XFS_FS=m +# CONFIG_XFS_ONLINE_REPAIR is not set +# CONFIG_XFS_ONLINE_SCRUB_STATS is not set +CONFIG_XFS_ONLINE_SCRUB=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_RT=y +CONFIG_XFS_SUPPORT_ASCII_CI=y +CONFIG_XFS_SUPPORT_V4=y +# CONFIG_XFS_WARN is not set +# CONFIG_XIL_AXIS_FIFO is not set +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_DMA is not set +CONFIG_XILINX_EMACLITE=m +CONFIG_XILINX_GMII2RGMII=m +# CONFIG_XILINX_INTC is not set +CONFIG_XILINX_LL_TEMAC=m +CONFIG_XILINX_PR_DECOUPLER=m +# CONFIG_XILINX_SDFEC is not set +CONFIG_XILINX_VCU=m +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_XILINX_XADC is not set +CONFIG_XILINX_XDMA=m +# CONFIG_XILINX_ZYNQMP_DPDMA is not set +CONFIG_XILLYBUS=m +# CONFIG_XILLYBUS_OF is not set +CONFIG_XILLYBUS_PCIE=m +CONFIG_XILLYUSB=m +# CONFIG_XIP_KERNEL is not set +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_MICROLZMA=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_SPARC=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC=y +# CONFIG_YAMAHA_YAS530 is not set +CONFIG_YAM=m +CONFIG_YELLOWFIN=m +# CONFIG_YENTA is not set +# CONFIG_YOGABOOK_WMI is not set +CONFIG_Z3FOLD=y +CONFIG_ZBUD=y +# CONFIG_ZD1211RW_DEBUG is not set +CONFIG_ZD1211RW=m +# CONFIG_ZERO_CALL_USED_REGS is not set +CONFIG_ZEROPLUS_FF=y +# CONFIG_ZIIRAVE_WATCHDOG is not set +CONFIG_ZISOFS=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_DFLTCC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZONE_DMA=y +CONFIG_ZONEFS_FS=m +CONFIG_ZOPT2201=m +# CONFIG_ZPA2326 is not set +# CONFIG_ZRAM_DEF_COMP_842 is not set +# CONFIG_ZRAM_DEF_COMP_LZ4HC is not set +# CONFIG_ZRAM_DEF_COMP_LZ4 is not set +# CONFIG_ZRAM_DEF_COMP_LZO is not set +CONFIG_ZRAM_DEF_COMP_LZORLE=y +# CONFIG_ZRAM_DEF_COMP_ZSTD is not set +CONFIG_ZRAM=m +# CONFIG_ZRAM_MEMORY_TRACKING is not set +CONFIG_ZRAM_MULTI_COMP=y +# CONFIG_ZRAM_TRACK_ENTRY_ACTIME is not set +# CONFIG_ZRAM_WRITEBACK is not set +CONFIG_ZSMALLOC_CHAIN_SIZE=8 +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_ZSMALLOC=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +# CONFIG_ZSWAP_DEFAULT_ON is not set +CONFIG_ZSWAP_EXCLUSIVE_LOADS_DEFAULT_ON=y +CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y +CONFIG_ZSWAP=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_I2C_NCT6775=m +CONFIG_ZENIFY=y +CONFIG_NTSYNC=y +CONFIG_TCP_CONG_BBR2=m +CONFIG_SND_SOC_AW87XXX=m +CONFIG_SCHED_BORE=y +CONFIG_MIN_BASE_SLICE_NS=1000000 +CONFIG_SCHED_CLASS_EXT=y +CONFIG_HID_IPTS=m +CONFIG_HID_ITHC=m +CONFIG_SURFACE_BOOK1_DGPU_SWITCH=m +CONFIG_IPC_CLASSES=y +CONFIG_LEDS_TPS68470=m +CONFIG_SENSORS_SURFACE_TEMP=m +CONFIG_AMD_PRIVATE_COLOR=y +CONFIG_DRM_APPLETBDRM=m +CONFIG_HID_APPLETB_BL=m +CONFIG_HID_APPLETB_KBD=m +CONFIG_HID_APPLE_MAGIC_BACKLIGHT=m +CONFIG_APPLE_BCE=m +CONFIG_HID_ASUS_ALLY=m +CONFIG_ASUS_ARMOURY=m diff --git a/SOURCES/kernel-s390x-debug-fedora.config b/SOURCES/kernel-s390x-debug-fedora.config index 08be104..e05c638 100644 --- a/SOURCES/kernel-s390x-debug-fedora.config +++ b/SOURCES/kernel-s390x-debug-fedora.config @@ -117,6 +117,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -190,7 +191,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -306,7 +307,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PTDUMP_DEBUGFS=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set @@ -418,6 +418,7 @@ CONFIG_AUTOFS_FS=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_BCMA=y CONFIG_B43_BUSES_BCMA_AND_SSB=y @@ -455,6 +456,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -489,6 +491,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -530,6 +533,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m # CONFIG_BE2ISCSI is not set CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -583,6 +587,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -875,6 +880,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1245,6 +1251,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1445,6 +1452,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1478,6 +1486,7 @@ CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1557,11 +1566,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1577,6 +1588,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1863,6 +1875,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2024,7 +2037,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2068,7 +2083,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2208,7 +2222,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2219,6 +2233,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2226,6 +2241,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2572,6 +2588,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2720,6 +2737,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -2730,6 +2748,7 @@ CONFIG_INPUT_ATLAS_BTNS=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3127,6 +3146,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3228,6 +3248,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3267,9 +3288,9 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set -CONFIG_LEDS_GPIO=m CONFIG_LEDS_GROUP_MULTICOLOR=m # CONFIG_LEDS_IS31FL319X is not set CONFIG_LEDS_IS31FL32XX=m @@ -3297,8 +3318,6 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3309,10 +3328,10 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m @@ -3322,6 +3341,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3556,7 +3576,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CEC_RC=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_MEDIA_CONTROLLER_DVB=y -CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER is not set CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_PCI_SUPPORT=y CONFIG_MEDIA_PLATFORM_DRIVERS=y @@ -3582,6 +3602,7 @@ CONFIG_MEGARAID_MM=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3606,6 +3627,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3621,6 +3643,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BD9571MWV is not set CONFIG_MFD_CORE=m # CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3684,6 +3708,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4154,6 +4179,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4258,8 +4284,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4366,6 +4394,7 @@ CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_LITEX=y # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y # CONFIG_NET_VENDOR_MICREL is not set CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4670,6 +4699,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4693,6 +4723,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m # CONFIG_OF is not set @@ -4839,6 +4870,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4966,6 +4998,8 @@ CONFIG_POWERCAP=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5068,10 +5102,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM is not set CONFIG_PWM_OMAP_DMTIMER=m @@ -5096,6 +5132,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5218,10 +5255,12 @@ CONFIG_REGMAP_I2C=m CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5329,7 +5368,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL is not set +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5373,6 +5414,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5504,8 +5546,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5549,6 +5592,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5810,6 +5860,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -5925,10 +5976,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -5974,6 +6029,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6113,6 +6170,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6222,6 +6280,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6333,6 +6392,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6377,6 +6437,7 @@ CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6395,6 +6456,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6403,6 +6465,7 @@ CONFIG_SND_SOC_CX2072X=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6572,6 +6635,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -6709,6 +6773,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6827,6 +6892,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -7054,6 +7120,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7134,6 +7201,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7767,6 +7835,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7791,6 +7860,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7880,6 +7950,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -7889,6 +7960,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -7907,6 +7980,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -7926,6 +8000,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -7978,6 +8054,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8043,6 +8120,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -8337,7 +8415,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-s390x-debug-rhel.config b/SOURCES/kernel-s390x-debug-rhel.config index dba2e6e..79a0f2c 100644 --- a/SOURCES/kernel-s390x-debug-rhel.config +++ b/SOURCES/kernel-s390x-debug-rhel.config @@ -98,6 +98,7 @@ CONFIG_ACPI_VIDEO=m # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -374,6 +375,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -387,6 +389,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -411,6 +414,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -480,6 +484,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -858,6 +863,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -990,7 +996,6 @@ CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1096,6 +1101,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1220,6 +1226,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1235,11 +1242,10 @@ CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set CONFIG_DIAG288_WATCHDOG=m -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_API_DEBUG=y @@ -1297,6 +1303,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1312,7 +1319,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1328,6 +1335,7 @@ CONFIG_DRM_AMD_DC=y # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1367,6 +1375,7 @@ CONFIG_DRM_HYPERV=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1414,11 +1423,13 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1433,6 +1444,7 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1658,6 +1670,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_DEBUG=y CONFIG_EDAC_DMC520=m @@ -1695,10 +1708,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set # CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1706,10 +1722,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y # CONFIG_ETHOC is not set CONFIG_ETHTOOL_NETLINK=y @@ -1806,6 +1826,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1865,17 +1886,17 @@ CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -1945,8 +1966,7 @@ CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2014,6 +2034,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2021,6 +2042,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2353,7 +2375,7 @@ CONFIG_I40EVF=m # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_IBM_PARTITION=y @@ -2367,6 +2389,7 @@ CONFIG_ICE_SWITCHDEV=y # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2577,6 +2600,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -2866,6 +2890,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -2947,16 +2972,11 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM=m CONFIG_KVM_MAX_NR_VCPUS=4096 CONFIG_KVM_PROVE_MMU=y # CONFIG_KVM_S390_UCONTROL is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set # CONFIG_KXCJK1013 is not set @@ -2966,6 +2986,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3034,10 +3057,10 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_TRIGGER_ACTIVITY is not set CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m @@ -3047,6 +3070,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3185,6 +3209,7 @@ CONFIG_MARCH_Z14=y CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3273,9 +3298,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y # CONFIG_MEDIA_SUPPORT is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3285,6 +3307,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3310,6 +3333,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3323,6 +3347,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3384,6 +3410,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3865,8 +3892,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -3877,8 +3906,7 @@ CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m # CONFIG_NETIUCV is not set -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -3962,8 +3990,9 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_NET_VENDOR_MYRI is not set @@ -4241,6 +4270,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4259,6 +4289,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4402,6 +4433,7 @@ CONFIG_PCI_P2PDMA=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m # CONFIG_PCI_PRI is not set +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set @@ -4435,6 +4467,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4443,7 +4476,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_LAN966X_SERDES is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4471,6 +4504,8 @@ CONFIG_PID_NS=y # CONFIG_PINCTRL_CS42L43 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set # CONFIG_PINCTRL is not set @@ -4537,6 +4572,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4638,6 +4675,7 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM is not set # CONFIG_PWM_PCA9685 is not set @@ -4647,13 +4685,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4666,6 +4705,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4809,6 +4849,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -4841,6 +4882,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_RESET_CONTROLLER is not set # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -4852,7 +4894,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -4890,6 +4932,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5013,6 +5056,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5052,6 +5096,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5450,9 +5501,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5497,6 +5552,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5627,6 +5683,7 @@ CONFIG_SIGNATURE=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5730,6 +5787,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -5834,6 +5892,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5896,6 +5955,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -5904,6 +5964,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6076,6 +6137,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6212,6 +6274,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6329,6 +6392,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6598,6 +6662,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6645,7 +6710,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y CONFIG_TN3215_CONSOLE=y @@ -7129,6 +7194,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7139,6 +7205,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7149,6 +7216,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7245,6 +7313,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7260,6 +7330,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7279,6 +7350,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7395,6 +7468,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7568,7 +7642,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7628,7 +7702,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-s390x-fedora.config b/SOURCES/kernel-s390x-fedora.config index 2ab7209..54b9857 100644 --- a/SOURCES/kernel-s390x-fedora.config +++ b/SOURCES/kernel-s390x-fedora.config @@ -117,6 +117,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -190,7 +191,7 @@ CONFIG_ADXL372_I2C=m CONFIG_ADXL372_SPI=m CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -306,7 +307,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set @@ -416,6 +416,7 @@ CONFIG_AUTOFS_FS=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y CONFIG_B43_BCMA_PIO=y CONFIG_B43_BCMA=y CONFIG_B43_BUSES_BCMA_AND_SSB=y @@ -453,6 +454,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -487,6 +489,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -528,6 +531,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m # CONFIG_BE2ISCSI is not set CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -581,6 +585,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y # CONFIG_BLK_DEV_SX8 is not set @@ -873,6 +878,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m # CONFIG_CHARGER_BQ25890 is not set # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m # CONFIG_CHARGER_CROS_USBPD is not set # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1243,6 +1249,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m CONFIG_DA311=m # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1434,6 +1441,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1467,6 +1475,7 @@ CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1546,11 +1555,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1566,6 +1577,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -1852,6 +1864,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2005,7 +2018,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m # CONFIG_FIREWIRE_NOSY is not set # CONFIG_FIRMWARE_EDID is not set CONFIG_FIRMWARE_MEMMAP=y @@ -2049,7 +2064,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2189,7 +2203,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2200,6 +2214,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH311X is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2207,6 +2222,7 @@ CONFIG_GPIO_TPS65219=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set CONFIG_GPIO_WM8994=m @@ -2552,6 +2568,7 @@ CONFIG_ICPLUS_PHY=m # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m # CONFIG_IEEE802154_AT86RF230_DEBUGFS is not set @@ -2700,6 +2717,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -2710,6 +2728,7 @@ CONFIG_INPUT_ATLAS_BTNS=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3101,6 +3120,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3202,6 +3222,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3241,9 +3262,9 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set -CONFIG_LEDS_GPIO=m CONFIG_LEDS_GROUP_MULTICOLOR=m # CONFIG_LEDS_IS31FL319X is not set CONFIG_LEDS_IS31FL32XX=m @@ -3271,8 +3292,6 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3283,10 +3302,10 @@ CONFIG_LEDS_REGULATOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set CONFIG_LEDS_TRIGGER_ACTIVITY=m CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m @@ -3296,6 +3315,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3529,7 +3549,7 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_MEDIA_CEC_RC=y CONFIG_MEDIA_CEC_SUPPORT=y CONFIG_MEDIA_CONTROLLER_DVB=y -CONFIG_MEDIA_CONTROLLER=y +# CONFIG_MEDIA_CONTROLLER is not set CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y CONFIG_MEDIA_PCI_SUPPORT=y CONFIG_MEDIA_PLATFORM_DRIVERS=y @@ -3555,6 +3575,7 @@ CONFIG_MEGARAID_MM=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3579,6 +3600,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3594,6 +3616,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BD9571MWV is not set CONFIG_MFD_CORE=m # CONFIG_MFD_CPCAP is not set +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS5535 is not set @@ -3657,6 +3681,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4126,6 +4151,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4230,8 +4256,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4338,6 +4366,7 @@ CONFIG_NET_VENDOR_GOOGLE=y CONFIG_NET_VENDOR_LITEX=y # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y # CONFIG_NET_VENDOR_MICREL is not set CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -4642,6 +4671,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4665,6 +4695,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m # CONFIG_OF is not set @@ -4810,6 +4841,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4937,6 +4969,8 @@ CONFIG_POWERCAP=y # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5039,10 +5073,12 @@ CONFIG_PTP_DFL_TOD=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM is not set CONFIG_PWM_OMAP_DMTIMER=m @@ -5067,6 +5103,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5189,10 +5226,12 @@ CONFIG_REGMAP_I2C=m CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_AW37503=m CONFIG_REGULATOR_BD9571MWV=m +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5300,7 +5339,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL is not set +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5344,6 +5385,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5475,8 +5517,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -5520,6 +5563,13 @@ CONFIG_RTW89_8922AE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5781,6 +5831,7 @@ CONFIG_SENSORS_BPA_RS600=m CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m CONFIG_SENSORS_DPS920AB=m @@ -5896,10 +5947,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -5945,6 +6000,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6084,6 +6141,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6193,6 +6251,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6303,6 +6362,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6347,6 +6407,7 @@ CONFIG_SND_SOC_CS35L45_I2C=m CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6365,6 +6426,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6373,6 +6435,7 @@ CONFIG_SND_SOC_CX2072X=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m # CONFIG_SND_SOC_ES8316 is not set CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6542,6 +6605,7 @@ CONFIG_SND_SOC_RT1017_SDCA_SDW=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -6678,6 +6742,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -6796,6 +6861,7 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set +CONFIG_SPI_CH341=m # CONFIG_SPI_CS42L43 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set @@ -7023,6 +7089,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7103,6 +7170,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -7736,6 +7804,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7760,6 +7829,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7849,6 +7919,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -7858,6 +7929,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -7876,6 +7949,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -7895,6 +7969,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -7947,6 +8023,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8012,6 +8089,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -8306,7 +8384,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-s390x-rhel.config b/SOURCES/kernel-s390x-rhel.config index 893cdd0..3861a37 100644 --- a/SOURCES/kernel-s390x-rhel.config +++ b/SOURCES/kernel-s390x-rhel.config @@ -98,6 +98,7 @@ CONFIG_ACPI_VIDEO=m # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -374,6 +375,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -387,6 +389,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -411,6 +414,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -480,6 +484,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -858,6 +863,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set CONFIG_COMPAT=y # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -990,7 +996,6 @@ CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1096,6 +1101,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1212,6 +1218,7 @@ CONFIG_DEFAULT_NET_SCH="fq_codel" CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m CONFIG_DETECT_HUNG_TASK=y CONFIG_DEV_DAX_CXL=m @@ -1227,11 +1234,10 @@ CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set CONFIG_DIAG288_WATCHDOG=m -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_API_DEBUG_SG is not set @@ -1289,6 +1295,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1304,7 +1311,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1320,6 +1327,7 @@ CONFIG_DRM_AMD_DC=y # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1359,6 +1367,7 @@ CONFIG_DRM_HYPERV=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1406,11 +1415,13 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1425,6 +1436,7 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1650,6 +1662,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_DMC520=m @@ -1687,10 +1700,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set # CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1698,10 +1714,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y # CONFIG_ETHOC is not set CONFIG_ETHTOOL_NETLINK=y @@ -1790,6 +1810,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1849,17 +1870,17 @@ CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -1929,8 +1950,7 @@ CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -1998,6 +2018,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2005,6 +2026,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2337,7 +2359,7 @@ CONFIG_I40EVF=m # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_IBM_PARTITION=y @@ -2351,6 +2373,7 @@ CONFIG_ICE_SWITCHDEV=y # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2561,6 +2584,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -2846,6 +2870,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -2927,16 +2952,11 @@ CONFIG_KUNIT_EXAMPLE_TEST=m CONFIG_KUNIT=m CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y CONFIG_KVM=m CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set # CONFIG_KVM_S390_UCONTROL is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set # CONFIG_KXCJK1013 is not set @@ -2946,6 +2966,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3014,10 +3037,10 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_TRIGGER_ACTIVITY is not set CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m @@ -3027,6 +3050,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3165,6 +3189,7 @@ CONFIG_MARCH_Z14=y CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3253,9 +3278,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y # CONFIG_MEDIA_SUPPORT is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3265,6 +3287,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3290,6 +3313,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3303,6 +3327,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3364,6 +3390,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3845,8 +3872,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -3857,8 +3886,7 @@ CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m # CONFIG_NETIUCV is not set -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -3942,8 +3970,9 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_NET_VENDOR_MYRI is not set @@ -4221,6 +4250,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4239,6 +4269,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4381,6 +4412,7 @@ CONFIG_PCI_P2PDMA=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m # CONFIG_PCI_PRI is not set +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set @@ -4414,6 +4446,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4422,7 +4455,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_LAN966X_SERDES is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4450,6 +4483,8 @@ CONFIG_PID_NS=y # CONFIG_PINCTRL_CS42L43 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set # CONFIG_PINCTRL is not set @@ -4516,6 +4551,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4617,6 +4654,7 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM is not set # CONFIG_PWM_PCA9685 is not set @@ -4626,13 +4664,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4645,6 +4684,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4788,6 +4828,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -4820,6 +4861,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_RESET_CONTROLLER is not set # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -4831,7 +4873,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -4869,6 +4911,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -4992,6 +5035,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5031,6 +5075,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5429,9 +5480,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5476,6 +5531,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5606,6 +5662,7 @@ CONFIG_SIGNATURE=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5709,6 +5766,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -5812,6 +5870,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5874,6 +5933,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -5882,6 +5942,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6054,6 +6115,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6189,6 +6251,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6306,6 +6369,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6575,6 +6639,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6622,7 +6687,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y CONFIG_TN3215_CONSOLE=y @@ -7106,6 +7171,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7116,6 +7182,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7126,6 +7193,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7222,6 +7290,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7237,6 +7307,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7256,6 +7327,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7372,6 +7445,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7545,7 +7619,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7605,7 +7679,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-s390x-zfcpdump-rhel.config b/SOURCES/kernel-s390x-zfcpdump-rhel.config index 93c6e5f..50d4347 100644 --- a/SOURCES/kernel-s390x-zfcpdump-rhel.config +++ b/SOURCES/kernel-s390x-zfcpdump-rhel.config @@ -98,6 +98,7 @@ CONFIG_ACPI_VIDEO=m # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -375,6 +376,7 @@ CONFIG_AUDIT_ARCH=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -388,6 +390,7 @@ CONFIG_AX88796B_PHY=m # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -412,6 +415,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -481,6 +485,7 @@ CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=y # CONFIG_BLK_DEV_SR is not set # CONFIG_BLK_DEV_SX8 is not set @@ -859,6 +864,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y # CONFIG_CONNECTOR is not set CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -991,7 +997,6 @@ CONFIG_CRYPTO_DEV_NITROX_CNN55XX=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1097,6 +1102,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1213,6 +1219,7 @@ CONFIG_DEFAULT_SECURITY_DAC=y # CONFIG_DEFAULT_SECURITY_SELINUX is not set # CONFIG_DEFAULT_SFQ is not set # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +CONFIG_DELL_PC=m CONFIG_DELL_WMI_DDV=m # CONFIG_DETECT_HUNG_TASK is not set CONFIG_DEV_DAX_CXL=m @@ -1228,11 +1235,10 @@ CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set CONFIG_DIAG288_WATCHDOG=m -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_API_DEBUG_SG is not set @@ -1290,6 +1296,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1305,7 +1312,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1321,6 +1328,7 @@ CONFIG_DRM_AMD_DC=y # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1360,6 +1368,7 @@ CONFIG_DRM_HYPERV=m # CONFIG_DRM_I2C_NXP_TDA9950 is not set # CONFIG_DRM_I2C_NXP_TDA998X is not set # CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set # CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE is not set # CONFIG_DRM_IMX8MP_HDMI_PVI is not set # CONFIG_DRM_IMX8QM_LDB is not set @@ -1407,11 +1416,13 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1426,6 +1437,7 @@ CONFIG_DRM_NOUVEAU_GSP_DEFAULT=y # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1651,6 +1663,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set # CONFIG_EDAC_DEBUG is not set CONFIG_EDAC_DMC520=m @@ -1688,10 +1701,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set # CONFIG_ENA_ETHERNET is not set +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=y CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1699,10 +1715,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y # CONFIG_ETHOC is not set CONFIG_ETHTOOL_NETLINK=y @@ -1792,6 +1812,7 @@ CONFIG_FB_EFI=y # CONFIG_FB_METRONOME is not set CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1851,7 +1872,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set # CONFIG_FSCACHE is not set CONFIG_FSCACHE_STATS=y # CONFIG_FS_DAX is not set @@ -1862,6 +1882,7 @@ CONFIG_FSCACHE_STATS=y # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -1935,7 +1956,6 @@ CONFIG_GENEVE=m CONFIG_GENWQE=m CONFIG_GENWQE_PLATFORM_ERROR_RECOVERY=0 # CONFIG_GFS2_FS is not set -CONFIG_GFS2_FS_LOCKING_DLM=y # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2003,6 +2023,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=y +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2010,6 +2031,7 @@ CONFIG_GPIO_SIM=y # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2343,7 +2365,7 @@ CONFIG_I40EVF=m # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m CONFIG_IBM_PARTITION=y @@ -2357,6 +2379,7 @@ CONFIG_ICE_SWITCHDEV=y # CONFIG_IDLE_INJECT is not set CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set # CONFIG_IEEE802154_AT86RF230 is not set @@ -2568,6 +2591,7 @@ CONFIG_INTEL_MEI_GSC_PROXY=m # CONFIG_INTEL_MEI_PXP is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_INTEL_MEI_VSC_HW is not set +# CONFIG_INTEL_PLR_TPMI is not set # CONFIG_INTEL_PMC_CORE is not set # CONFIG_INTEL_PMT_CLASS is not set # CONFIG_INTEL_PMT_CRASHLOG is not set @@ -2854,6 +2878,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -2935,16 +2960,11 @@ CONFIG_KUNIT_EXAMPLE_TEST=m # CONFIG_KUNIT is not set CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set -CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set -CONFIG_KVM_HYPERV=y # CONFIG_KVM is not set CONFIG_KVM_MAX_NR_VCPUS=4096 # CONFIG_KVM_PROVE_MMU is not set # CONFIG_KVM_S390_UCONTROL is not set CONFIG_KVM_SMM=y -CONFIG_KVM_SW_PROTECTED_VM=y # CONFIG_KVM_WERROR is not set # CONFIG_KVM_XEN is not set # CONFIG_KXCJK1013 is not set @@ -2954,6 +2974,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3022,10 +3045,10 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set -# CONFIG_LEDS_TLC591XX is not set # CONFIG_LEDS_TRIGGER_ACTIVITY is not set CONFIG_LEDS_TRIGGER_AUDIO=m CONFIG_LEDS_TRIGGER_BACKLIGHT=m @@ -3035,6 +3058,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3174,6 +3198,7 @@ CONFIG_MARCH_Z14=y CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3262,9 +3287,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y # CONFIG_MEDIA_SUPPORT is not set # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3274,6 +3296,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3299,6 +3322,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3312,6 +3336,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3373,6 +3399,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -3854,8 +3881,10 @@ CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y # CONFIG_NETFS_SUPPORT is not set CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -3867,7 +3896,6 @@ CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m # CONFIG_NETIUCV is not set # CONFIG_NET_KEY is not set -CONFIG_NET_KEY_MIGRATE=y # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -3952,8 +3980,9 @@ CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_NET_VENDOR_LITEX is not set # CONFIG_NET_VENDOR_MARVELL is not set CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_NET_VENDOR_MYRI is not set @@ -4232,6 +4261,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m # CONFIG_NVME_TARGET is not set @@ -4250,6 +4280,7 @@ CONFIG_NVME_TCP_TLS=y # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4393,6 +4424,7 @@ CONFIG_PCI_P2PDMA=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m # CONFIG_PCI_PRI is not set +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set # CONFIG_PCI_STUB is not set @@ -4425,6 +4457,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4433,7 +4466,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_HISI_INNO_USB2 is not set # CONFIG_PHY_HISTB_COMBPHY is not set # CONFIG_PHY_LAN966X_SERDES is not set -# CONFIG_PHYLIB is not set +CONFIG_PHYLIB=y # CONFIG_PHY_MAPPHONE_MDM6600 is not set # CONFIG_PHY_OCELOT_SERDES is not set # CONFIG_PHY_PXA_28NM_HSIC is not set @@ -4461,6 +4494,8 @@ CONFIG_PID_NS=y # CONFIG_PINCTRL_CS42L43 is not set # CONFIG_PINCTRL_CY8C95X0 is not set # CONFIG_PINCTRL_EQUILIBRIUM is not set +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set # CONFIG_PINCTRL is not set @@ -4527,6 +4562,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4629,6 +4666,7 @@ CONFIG_PTP_1588_CLOCK=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set # CONFIG_PWM is not set # CONFIG_PWM_PCA9685 is not set @@ -4638,13 +4676,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4657,6 +4696,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4800,6 +4840,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -4832,6 +4873,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set # CONFIG_RESET_CONTROLLER is not set # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -4843,7 +4885,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y # CONFIG_RFKILL is not set -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -4881,6 +4923,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5004,6 +5047,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5044,6 +5088,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5053,7 +5104,7 @@ CONFIG_RXKAD=y CONFIG_RXPERF=m # CONFIG_S390_GUEST is not set # CONFIG_S390_HYPFS_FS is not set -CONFIG_S390_HYPFS=y +# CONFIG_S390_HYPFS is not set # CONFIG_S390_KPROBES_SANITY_TEST is not set # CONFIG_S390_MODULES_SANITY_TEST is not set CONFIG_S390_PRNG=y @@ -5445,9 +5496,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5492,6 +5547,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5622,6 +5678,7 @@ CONFIG_SIGNALFD=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5725,6 +5782,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -5828,6 +5886,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -5890,6 +5949,7 @@ CONFIG_SND_SOC_CARD_KUNIT_TEST=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -5898,6 +5958,7 @@ CONFIG_SND_SOC_CX2072X=m # CONFIG_SND_SOC_DMIC is not set # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set # CONFIG_SND_SOC_ES8316 is not set # CONFIG_SND_SOC_ES8326 is not set # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6070,6 +6131,7 @@ CONFIG_SND_SOC_MAX98927=m # CONFIG_SND_SOC_RT1308_SDW is not set # CONFIG_SND_SOC_RT1316_SDW is not set CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6205,6 +6267,7 @@ CONFIG_SND_SOC_TOPOLOGY_KUNIT_TEST=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6322,6 +6385,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BITBANG is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6596,6 +6660,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6644,7 +6709,7 @@ CONFIG_TLS=m CONFIG_TMPFS_INODE64=y # CONFIG_TMPFS is not set CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TN3215_CONSOLE=y CONFIG_TN3215=y @@ -7128,6 +7193,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7138,6 +7204,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_MEM2MEM_DRIVERS is not set # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7148,6 +7215,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7244,6 +7312,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7259,6 +7329,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7278,6 +7349,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7394,6 +7467,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7567,7 +7641,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7627,7 +7701,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-debug-fedora.config b/SOURCES/kernel-x86_64-debug-fedora.config index d67dfc7..9dbd8f8 100644 --- a/SOURCES/kernel-x86_64-debug-fedora.config +++ b/SOURCES/kernel-x86_64-debug-fedora.config @@ -135,6 +135,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -209,7 +210,7 @@ CONFIG_ADV_SWBUTTON=m # CONFIG_ADXL372_SPI is not set CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -344,7 +345,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y CONFIG_ARM_PTDUMP_DEBUGFS=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set @@ -460,6 +460,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y # CONFIG_AXP20X_ADC is not set # CONFIG_AXP20X_POWER is not set CONFIG_AXP288_ADC=m @@ -503,6 +504,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -540,6 +542,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -581,6 +584,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -634,6 +638,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SX8=m @@ -928,6 +933,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m CONFIG_CHARGER_BQ25890=m # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1349,6 +1355,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1470,6 +1477,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m # CONFIG_DELL_RBU is not set CONFIG_DELL_SMBIOS=m @@ -1569,6 +1577,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1606,6 +1615,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1667,6 +1677,7 @@ CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 CONFIG_DRM_I915_PXP=y +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1716,11 +1727,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1736,6 +1749,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2057,6 +2071,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2182,6 +2197,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2222,7 +2238,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE_KUNIT_DEVICE_ATTRIBUTE_TEST is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m CONFIG_FIREWIRE_KUNIT_UAPI_TEST=m CONFIG_FIREWIRE=m CONFIG_FIREWIRE_NET=m @@ -2272,7 +2290,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2427,7 +2444,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2439,6 +2456,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2447,6 +2465,7 @@ CONFIG_GPIO_TPS68470=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set CONFIG_GPIO_WHISKEY_COVE=m @@ -2833,6 +2852,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IE6XX_WDT=m CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m @@ -2989,6 +3009,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -3001,6 +3022,7 @@ CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3112,6 +3134,7 @@ CONFIG_INTEL_MRFLD_ADC=m CONFIG_INTEL_MRFLD_PWRBTN=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +CONFIG_INTEL_PLR_TPMI=m CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3480,6 +3503,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_LZ4 is not set @@ -3592,6 +3616,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3632,6 +3657,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -3663,8 +3689,7 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m +# CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3675,6 +3700,7 @@ CONFIG_LEDS_PWM_MULTICOLOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3688,6 +3714,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3946,6 +3973,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3970,6 +3998,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3986,6 +4015,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS47L24 is not set @@ -4054,6 +4085,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4559,6 +4591,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4663,8 +4696,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4771,6 +4806,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5091,6 +5127,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5115,6 +5152,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m # CONFIG_OF is not set @@ -5280,6 +5318,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5453,6 +5492,8 @@ CONFIG_POWERCAP=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5559,12 +5600,14 @@ CONFIG_PVPANIC_MMIO=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set CONFIG_PWM_CRC=y CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_INTEL_LGM is not set CONFIG_PWM_LPSS_PCI=m @@ -5592,6 +5635,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5711,6 +5755,7 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ARIZONA_LDO1=m @@ -5718,6 +5763,7 @@ CONFIG_REGULATOR_ARIZONA_MICSUPP=m CONFIG_REGULATOR_AW37503=m # CONFIG_REGULATOR_AXP20X is not set # CONFIG_REGULATOR_BD9571MWV is not set +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5825,7 +5871,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5869,6 +5917,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -6001,8 +6050,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6046,6 +6096,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -6306,6 +6363,7 @@ CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORETEMP=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELL_SMM=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m @@ -6429,10 +6487,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6479,6 +6541,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6634,6 +6698,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6750,6 +6815,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6862,6 +6928,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6914,6 +6981,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6932,6 +7000,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6940,6 +7009,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -7115,6 +7185,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -7258,6 +7329,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -7385,7 +7457,8 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set -# CONFIG_SPI_CS42L43 is not set +CONFIG_SPI_CH341=m +CONFIG_SPI_CS42L43=m # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_DLN2=m @@ -7627,6 +7700,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7714,6 +7788,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8346,6 +8421,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -8373,6 +8449,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -8464,6 +8541,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -8474,6 +8552,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -8492,6 +8572,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -8513,6 +8594,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -8565,6 +8648,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8630,6 +8714,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -9034,7 +9119,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-debug-rhel.config b/SOURCES/kernel-x86_64-debug-rhel.config index 190f7fc..8990219 100644 --- a/SOURCES/kernel-x86_64-debug-rhel.config +++ b/SOURCES/kernel-x86_64-debug-rhel.config @@ -116,6 +116,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -402,6 +403,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -416,6 +418,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -440,6 +443,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -509,6 +513,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -888,6 +893,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1043,7 +1049,6 @@ CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1157,6 +1162,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1281,6 +1287,7 @@ CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFERRED_STRUCT_PAGE_INIT=y CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m CONFIG_DELL_RBU=m CONFIG_DELL_SMBIOS=m @@ -1307,12 +1314,11 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y CONFIG_DL2K=m # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_API_DEBUG=y @@ -1370,6 +1376,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1385,7 +1392,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1403,6 +1410,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1461,6 +1469,7 @@ CONFIG_DRM_I915=m CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1516,11 +1525,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1535,6 +1546,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1761,6 +1773,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_AMD64=m CONFIG_EDAC_DEBUG=y @@ -1827,10 +1840,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1838,10 +1854,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1933,6 +1953,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1994,17 +2015,17 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -2078,8 +2099,7 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set # CONFIG_GENWQE is not set -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2148,6 +2168,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2155,6 +2176,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2512,13 +2534,13 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set CONFIG_IA32_EMULATION=y # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m # CONFIG_IBM_RTL is not set @@ -2533,6 +2555,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IE6XX_WDT is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set @@ -2769,6 +2792,7 @@ CONFIG_INTEL_MEI_ME=m CONFIG_INTEL_MEI_WDT=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +# CONFIG_INTEL_PLR_TPMI is not set CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3078,6 +3102,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3161,8 +3186,6 @@ CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set CONFIG_KVM_AMD=m CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_GUEST=y CONFIG_KVM_HYPERV=y CONFIG_KVM_INTEL=m @@ -3182,6 +3205,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3249,6 +3275,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3262,6 +3289,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3394,6 +3422,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3483,9 +3512,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3495,6 +3521,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3520,6 +3547,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3533,6 +3561,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3597,6 +3627,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4103,8 +4134,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4114,8 +4147,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4199,8 +4231,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4481,6 +4514,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4500,6 +4534,7 @@ CONFIG_NVSW_SN2201=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4652,6 +4687,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4689,6 +4725,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4733,7 +4770,7 @@ CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=m CONFIG_PINCTRL_CEDARFORK=m # CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CS42L43=m # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_DENVERTON=m CONFIG_PINCTRL_ELKHARTLAKE=m @@ -4741,6 +4778,8 @@ CONFIG_PINCTRL_EMMITSBURG=m # CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_PINCTRL_GEMINILAKE=m CONFIG_PINCTRL_ICELAKE=m +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set CONFIG_PINCTRL_INTEL_PLATFORM=m # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set @@ -4820,6 +4859,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4924,6 +4965,7 @@ CONFIG_PVPANIC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set CONFIG_PWM_LPSS_PCI=m CONFIG_PWM_LPSS_PLATFORM=m @@ -4935,13 +4977,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4954,6 +4997,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -5008,6 +5052,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m CONFIG_RANDOM32_SELFTEST=y CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5091,6 +5136,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -5123,6 +5169,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -5134,7 +5181,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5172,6 +5219,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5296,6 +5344,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5335,6 +5384,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5719,9 +5775,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5766,6 +5826,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5907,6 +5968,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6008,6 +6070,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6117,6 +6180,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6180,6 +6244,7 @@ CONFIG_SND_SOC_CS42L42_SDW=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6188,6 +6253,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6362,6 +6428,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6499,6 +6566,7 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6621,6 +6689,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6911,6 +6980,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6958,7 +7028,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7434,6 +7504,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7446,6 +7517,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set # CONFIG_VBOXGUEST is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7456,6 +7528,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7551,6 +7624,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7566,6 +7641,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7585,6 +7661,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7701,6 +7779,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7958,7 +8037,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8014,7 +8093,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-fedora.config b/SOURCES/kernel-x86_64-fedora.config index 45cb254..8a32200 100644 --- a/SOURCES/kernel-x86_64-fedora.config +++ b/SOURCES/kernel-x86_64-fedora.config @@ -135,6 +135,7 @@ CONFIG_AD7292=m CONFIG_AD7293=m # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +CONFIG_AD7380=m CONFIG_AD74115=m CONFIG_AD74413R=m # CONFIG_AD7476 is not set @@ -209,7 +210,7 @@ CONFIG_ADV_SWBUTTON=m # CONFIG_ADXL372_SPI is not set CONFIG_ADXRS290=m # CONFIG_ADXRS450 is not set -# CONFIG_AF8133J is not set +CONFIG_AF8133J=m # CONFIG_AFE4403 is not set # CONFIG_AFE4404 is not set CONFIG_AFFS_FS=m @@ -344,7 +345,6 @@ CONFIG_ARM64_ERRATUM_2253138=y CONFIG_ARM64_USE_LSE_ATOMICS=y CONFIG_ARM_CMN=m # CONFIG_ARM_MHU_V2 is not set -CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y # CONFIG_ARM_SCMI_TRANSPORT_MAILBOX is not set # CONFIG_ARM_SCMI_TRANSPORT_SMC is not set # CONFIG_ARM_SCMI_TRANSPORT_VIRTIO is not set @@ -458,6 +458,7 @@ CONFIG_AUXDISPLAY=y CONFIG_AX25_DAMA_SLAVE=y CONFIG_AX25=m CONFIG_AX88796B_PHY=m +CONFIG_AX88796B_RUST_PHY=y # CONFIG_AXP20X_ADC is not set # CONFIG_AXP20X_POWER is not set CONFIG_AXP288_ADC=m @@ -501,6 +502,7 @@ CONFIG_BACKLIGHT_KTD253=m # CONFIG_BACKLIGHT_KTD2801 is not set CONFIG_BACKLIGHT_KTZ8866=m CONFIG_BACKLIGHT_LED=m +CONFIG_BACKLIGHT_LM3509=m # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -538,6 +540,7 @@ CONFIG_BATTERY_CW2015=m # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_BATTERY_MAX17042=m +CONFIG_BATTERY_MAX1720X=m # CONFIG_BATTERY_MAX1721X is not set CONFIG_BATTERY_RT5033=m CONFIG_BATTERY_SAMSUNG_SDI=y @@ -579,6 +582,7 @@ CONFIG_BCMGENET=m CONFIG_BCM_NET_PHYPTP=m CONFIG_BCM_VK=m CONFIG_BCM_VK_TTY=y +CONFIG_BD96801_WATCHDOG=m CONFIG_BE2ISCSI=m CONFIG_BE2NET_BE2=y CONFIG_BE2NET_BE3=y @@ -632,6 +636,7 @@ CONFIG_BLK_DEV_RBD=m CONFIG_BLK_DEV_RNBD_CLIENT=m CONFIG_BLK_DEV_RNBD_SERVER=m # CONFIG_BLK_DEV_RSXX is not set +CONFIG_BLK_DEV_RUST_NULL=m CONFIG_BLK_DEV_SD=y CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SX8=m @@ -926,6 +931,7 @@ CONFIG_CHARGER_BQ2515X=m CONFIG_CHARGER_BQ256XX=m CONFIG_CHARGER_BQ25890=m # CONFIG_CHARGER_BQ25980 is not set +CONFIG_CHARGER_CROS_CONTROL=m CONFIG_CHARGER_CROS_PCHG=m CONFIG_CHARGER_CROS_USBPD=m # CONFIG_CHARGER_DETECTOR_MAX14656 is not set @@ -1347,6 +1353,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set CONFIG_DA280=m # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1460,6 +1467,7 @@ CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m # CONFIG_DELL_RBU is not set CONFIG_DELL_SMBIOS=m @@ -1558,6 +1566,7 @@ CONFIG_DM_UNSTRIPED=m CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1595,6 +1604,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +CONFIG_DRM_AMD_ISP=y CONFIG_DRM_AMD_SECURE_DISPLAY=y CONFIG_DRM_ANALOGIX_ANX6345=m CONFIG_DRM_ANALOGIX_ANX7625=m @@ -1656,6 +1666,7 @@ CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 CONFIG_DRM_I915_PXP=y +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1705,11 +1716,13 @@ CONFIG_DRM_PANEL_DSI_CM=m CONFIG_DRM_PANEL_ELIDA_KD35T133=m CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02=m CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D=m +CONFIG_DRM_PANEL_HIMAX_HX83102=m # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +CONFIG_DRM_PANEL_ILITEK_ILI9806E=m # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set CONFIG_DRM_PANEL_ILITEK_ILI9882T=m CONFIG_DRM_PANEL_INNOLUX_EJ030NA=m @@ -1725,6 +1738,7 @@ CONFIG_DRM_PANEL_JDI_R63452=m # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_LG4573 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +CONFIG_DRM_PANEL_LINCOLNTECH_LCD197=m # CONFIG_DRM_PANEL_LVDS is not set CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966=m CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m @@ -2046,6 +2060,7 @@ CONFIG_ENCRYPTED_KEYS=y # CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set CONFIG_ENVELOPE_DETECTOR=m CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -2163,6 +2178,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2203,7 +2219,9 @@ CONFIG_FILE_LOCKING=y # CONFIG_FIND_BIT_BENCHMARK is not set # CONFIG_FIPS_SIGNATURE_SELFTEST is not set # CONFIG_FIREWIRE_KUNIT_DEVICE_ATTRIBUTE_TEST is not set +CONFIG_FIREWIRE_KUNIT_OHCI_SERDES_TEST=m CONFIG_FIREWIRE_KUNIT_PACKET_SERDES_TEST=m +CONFIG_FIREWIRE_KUNIT_SELF_ID_SEQUENCE_HELPER_TEST=m CONFIG_FIREWIRE_KUNIT_UAPI_TEST=m CONFIG_FIREWIRE=m CONFIG_FIREWIRE_NET=m @@ -2253,7 +2271,6 @@ CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAME_POINTER=y CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y @@ -2408,7 +2425,7 @@ CONFIG_GPIO_MLXBF2=m CONFIG_GPIO_MXC=m # CONFIG_GPIO_PCA953X_IRQ is not set CONFIG_GPIO_PCA953X=m -CONFIG_GPIO_PCA9570=m +# CONFIG_GPIO_PCA9570 is not set # CONFIG_GPIO_PCF857X is not set # CONFIG_GPIO_PCH is not set # CONFIG_GPIO_PCIE_IDIO_24 is not set @@ -2420,6 +2437,7 @@ CONFIG_GPIO_PCI_IDIO_16=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_TPIC2810 is not set @@ -2428,6 +2446,7 @@ CONFIG_GPIO_TPS68470=m # CONFIG_GPIO_TS4900 is not set # CONFIG_GPIO_VIPERBOARD is not set CONFIG_GPIO_VIRTIO=m +CONFIG_GPIO_VIRTUSER=m # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set CONFIG_GPIO_WHISKEY_COVE=m @@ -2813,6 +2832,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +CONFIG_IDPF_SINGLEQ=y CONFIG_IE6XX_WDT=m CONFIG_IEEE802154_6LOWPAN=m CONFIG_IEEE802154_ADF7242=m @@ -2969,6 +2989,7 @@ CONFIG_INITRAMFS_SOURCE="" CONFIG_INIT_STACK_ALL_ZERO=y # CONFIG_INIT_STACK_NONE is not set CONFIG_INOTIFY_USER=y +CONFIG_INPUT_88PM886_ONKEY=m # CONFIG_INPUT_AD714X is not set # CONFIG_INPUT_ADXL34X is not set CONFIG_INPUT_APANEL=m @@ -2981,6 +3002,7 @@ CONFIG_INPUT_AXP20X_PEK=m CONFIG_INPUT_CM109=m CONFIG_INPUT_CMA3000_I2C=m CONFIG_INPUT_CMA3000=m +CONFIG_INPUT_CS40L50_VIBRA=m # CONFIG_INPUT_DA7280_HAPTICS is not set # CONFIG_INPUT_DRV260X_HAPTICS is not set # CONFIG_INPUT_DRV2665_HAPTICS is not set @@ -3092,6 +3114,7 @@ CONFIG_INTEL_MRFLD_ADC=m CONFIG_INTEL_MRFLD_PWRBTN=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +CONFIG_INTEL_PLR_TPMI=m CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3454,6 +3477,7 @@ CONFIG_KALLSYMS=y # CONFIG_KCOV is not set # CONFIG_KCSAN is not set CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_KEBA_CP500=m # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_GZIP is not set # CONFIG_KERNEL_LZ4 is not set @@ -3566,6 +3590,7 @@ CONFIG_L2TP=m CONFIG_L2TP_V3=y CONFIG_LAN743X=m CONFIG_LAN966X_DCB=y +CONFIG_LAN966X_OIC=m CONFIG_LAN966X_SWITCH=m # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y @@ -3606,6 +3631,7 @@ CONFIG_LEDS_CLASS_MULTICOLOR=m CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLEVO_MAIL=m CONFIG_LEDS_CR0014114=m +CONFIG_LEDS_CROS_EC=m # CONFIG_LEDS_DAC124S085 is not set # CONFIG_LEDS_EL15203000 is not set CONFIG_LEDS_GPIO=m @@ -3637,8 +3663,7 @@ CONFIG_LEDS_MLXREG=m CONFIG_LEDS_NCP5623=m CONFIG_LEDS_NIC78BX=m # CONFIG_LEDS_OT200 is not set -CONFIG_LEDS_PCA9532_GPIO=y -CONFIG_LEDS_PCA9532=m +# CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set CONFIG_LEDS_PCA995X=m @@ -3649,6 +3674,7 @@ CONFIG_LEDS_PWM_MULTICOLOR=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +CONFIG_LEDS_SY7802=m # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3662,6 +3688,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +CONFIG_LEDS_TRIGGER_INPUT_EVENTS=m CONFIG_LEDS_TRIGGER_MTD=y CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3920,6 +3947,7 @@ CONFIG_MEGARAID_SAS=m CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3944,6 +3972,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +CONFIG_MFD_88PM886_PMIC=y # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3960,6 +3989,8 @@ CONFIG_MFD_BD9571MWV=m CONFIG_MFD_CORE=y # CONFIG_MFD_CPCAP is not set CONFIG_MFD_CROS_EC_DEV=m +CONFIG_MFD_CS40L50_I2C=m +CONFIG_MFD_CS40L50_SPI=m CONFIG_MFD_CS42L43_I2C=m CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_CS47L24 is not set @@ -4028,6 +4059,7 @@ CONFIG_MFD_MAX77714=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +CONFIG_MFD_ROHM_BD96801=m CONFIG_MFD_RSMU_I2C=m CONFIG_MFD_RSMU_SPI=m CONFIG_MFD_RT4831=m @@ -4533,6 +4565,7 @@ CONFIG_NET_DSA_TAG_RTL8_4=m # CONFIG_NET_DSA_TAG_RZN1_A5PSW is not set CONFIG_NET_DSA_TAG_SJA1105=m CONFIG_NET_DSA_TAG_TRAILER=m +# CONFIG_NET_DSA_TAG_VSC73XX_8021Q is not set CONFIG_NET_DSA_TAG_XRS700X=m # CONFIG_NET_DSA_VITESSE_VSC73XX_PLATFORM is not set # CONFIG_NET_DSA_VITESSE_VSC73XX_SPI is not set @@ -4637,8 +4670,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y CONFIG_NET_FOU_IP_TUNNELS=y CONFIG_NET_FOU=m +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4745,6 +4780,7 @@ CONFIG_NET_VENDOR_INTEL=y CONFIG_NET_VENDOR_LITEX=y CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +CONFIG_NET_VENDOR_META=y CONFIG_NET_VENDOR_MICREL=y CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set @@ -5065,6 +5101,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -5089,6 +5126,7 @@ CONFIG_OCFS2_FS_O2CB=m # CONFIG_OCFS2_FS_STATS is not set CONFIG_OCFS2_FS_USERSPACE_CLUSTER=m CONFIG_OCTEON_EP=m +CONFIG_OCTEONEP_VDPA=m CONFIG_OCTEON_EP_VF=m CONFIG_OF_FPGA_REGION=m # CONFIG_OF is not set @@ -5253,6 +5291,7 @@ CONFIG_PCI_PASID=y CONFIG_PCIPCWATCHDOG=m CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +CONFIG_PCI_PWRCTL_PWRSEQ=m CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -5425,6 +5464,8 @@ CONFIG_POWERCAP=y CONFIG_POWER_RESET_TPS65086=y # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +CONFIG_POWER_SEQUENCING=m +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -5531,12 +5572,14 @@ CONFIG_PVPANIC_MMIO=m # CONFIG_PVPANIC_PCI is not set CONFIG_PVPANIC=y # CONFIG_PWM_ATMEL_TCB is not set +CONFIG_PWM_AXI_PWMGEN=m # CONFIG_PWM_CLK is not set CONFIG_PWM_CRC=y CONFIG_PWM_CROS_EC=m # CONFIG_PWM_DEBUG is not set CONFIG_PWM_DWC=m # CONFIG_PWM_FSL_FTM is not set +CONFIG_PWM_GPIO=m CONFIG_PWM_HIBVT=m # CONFIG_PWM_INTEL_LGM is not set CONFIG_PWM_LPSS_PCI=m @@ -5564,6 +5607,7 @@ CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_LMH is not set # CONFIG_QCOM_OCMEM is not set CONFIG_QCOM_PBS=m +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT is not set # CONFIG_QCOM_SCM is not set # CONFIG_QCOM_SPM is not set @@ -5683,6 +5727,7 @@ CONFIG_REGMAP_I2C=y CONFIG_REGMAP_KUNIT=m CONFIG_REGMAP=y # CONFIG_REGULATOR_88PG86X is not set +CONFIG_REGULATOR_88PM886=m # CONFIG_REGULATOR_ACT8865 is not set # CONFIG_REGULATOR_AD5398 is not set CONFIG_REGULATOR_ARIZONA_LDO1=m @@ -5690,6 +5735,7 @@ CONFIG_REGULATOR_ARIZONA_MICSUPP=m CONFIG_REGULATOR_AW37503=m # CONFIG_REGULATOR_AXP20X is not set # CONFIG_REGULATOR_BD9571MWV is not set +CONFIG_REGULATOR_BD96801=m # CONFIG_REGULATOR_DA9121 is not set # CONFIG_REGULATOR_DA9210 is not set # CONFIG_REGULATOR_DA9211 is not set @@ -5797,7 +5843,9 @@ CONFIG_RESOURCE_KUNIT_TEST=m CONFIG_RFKILL_GPIO=m CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m +CONFIG_RFS_ACCEL=y # CONFIG_RH_DISABLE_DEPRECATED is not set +# CONFIG_RHEL_DIFFERENCES is not set CONFIG_RICHTEK_RTQ6056=m CONFIG_RING_BUFFER_BENCHMARK=m # CONFIG_RING_BUFFER_STARTUP_TEST is not set @@ -5841,6 +5889,7 @@ CONFIG_RPMSG_CTRL=m CONFIG_RPMSG_TTY=m # CONFIG_RPMSG_VIRTIO is not set CONFIG_RPR0521=m +CONFIG_RPS=y CONFIG_RSEQ=y CONFIG_RSI_91X=m CONFIG_RSI_COEX=y @@ -5973,8 +6022,9 @@ CONFIG_RTL8180=m CONFIG_RTL8187=m CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m -CONFIG_RTL8192CU=m +# CONFIG_RTL8192CU is not set CONFIG_RTL8192DE=m +CONFIG_RTL8192DU=m CONFIG_RTL8192EE=m CONFIG_RTL8192E=m CONFIG_RTL8192SE=m @@ -6018,6 +6068,13 @@ CONFIG_RTW89_8922AE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y +CONFIG_RUST_OVERFLOW_CHECKS=y +CONFIG_RUST_PHYLIB_ABSTRACTIONS=y +CONFIG_RUST=y CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -6278,6 +6335,7 @@ CONFIG_SENSORS_CHIPCAP2=m CONFIG_SENSORS_CORETEMP=m CONFIG_SENSORS_CORSAIR_CPRO=m CONFIG_SENSORS_CORSAIR_PSU=m +CONFIG_SENSORS_CROS_EC=m CONFIG_SENSORS_DELL_SMM=m CONFIG_SENSORS_DELTA_AHE50DC_FAN=m CONFIG_SENSORS_DME1737=m @@ -6401,10 +6459,14 @@ CONFIG_SENSORS_MCP3021=m CONFIG_SENSORS_MLXREG_FAN=m # CONFIG_SENSORS_MP2856 is not set CONFIG_SENSORS_MP2888=m +CONFIG_SENSORS_MP2891=m CONFIG_SENSORS_MP2975=m CONFIG_SENSORS_MP2975_REGULATOR=y +CONFIG_SENSORS_MP2993=m CONFIG_SENSORS_MP5023=m +CONFIG_SENSORS_MP5920=m # CONFIG_SENSORS_MP5990 is not set +CONFIG_SENSORS_MP9941=m CONFIG_SENSORS_MPQ7932=m CONFIG_SENSORS_MPQ7932_REGULATOR=y CONFIG_SENSORS_MPQ8785=m @@ -6451,6 +6513,8 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +CONFIG_SENSORS_SPD5118_DETECT=y +CONFIG_SENSORS_SPD5118=m # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set CONFIG_SENSORS_SURFACE_FAN=m @@ -6606,6 +6670,7 @@ CONFIG_SKGE_GENESIS=y CONFIG_SKGE=m # CONFIG_SKY2_DEBUG is not set CONFIG_SKY2=m +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6722,6 +6787,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6833,6 +6899,7 @@ CONFIG_SND_SOC_ADI=m # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +CONFIG_SND_SOC_AK4619=m # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set CONFIG_SND_SOC_AK5558=m @@ -6885,6 +6952,7 @@ CONFIG_SND_SOC_CS35L45_SPI=m CONFIG_SND_SOC_CS35L56_I2C=m CONFIG_SND_SOC_CS35L56_SDW=m CONFIG_SND_SOC_CS35L56_SPI=m +CONFIG_SND_SOC_CS40L50=m CONFIG_SND_SOC_CS4234=m # CONFIG_SND_SOC_CS4265 is not set # CONFIG_SND_SOC_CS4270 is not set @@ -6903,6 +6971,7 @@ CONFIG_SND_SOC_CS42L83=m CONFIG_SND_SOC_CS43130=m # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +CONFIG_SND_SOC_CS530X_I2C=m # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6911,6 +6980,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m CONFIG_SND_SOC_ES7134=m # CONFIG_SND_SOC_ES7241 is not set +CONFIG_SND_SOC_ES8311=m CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m CONFIG_SND_SOC_ES8328_I2C=m @@ -7086,6 +7156,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +CONFIG_SND_SOC_RT1320_SDW=m # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set CONFIG_SND_SOC_RT5659=m @@ -7228,6 +7299,7 @@ CONFIG_SND_SOC_TSCS42XX=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +CONFIG_SND_SOC_WCD937X_SDW=m # CONFIG_SND_SOC_WCD938X_SDW is not set CONFIG_SND_SOC_WCD939X_SDW=m # CONFIG_SND_SOC_WM8510 is not set @@ -7355,7 +7427,8 @@ CONFIG_SPI_AX88796C=m # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set # CONFIG_SPI_CADENCE_XSPI is not set -# CONFIG_SPI_CS42L43 is not set +CONFIG_SPI_CH341=m +CONFIG_SPI_CS42L43=m # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_DLN2=m @@ -7597,6 +7670,7 @@ CONFIG_TCP_MD5SIG=y CONFIG_TDX_GUEST_DRIVER=m CONFIG_TEE=m CONFIG_TEHUTI=m +CONFIG_TEHUTI_TN40=m CONFIG_TELCLOCK=m CONFIG_TERANETICS_PHY=m # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set @@ -7684,6 +7758,7 @@ CONFIG_TI_ADC128S052=m # CONFIG_TI_ADC161S626 is not set CONFIG_TI_ADS1015=m CONFIG_TI_ADS1100=m +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set CONFIG_TI_ADS131E08=m @@ -8316,6 +8391,7 @@ CONFIG_USB_YUREX=m # CONFIG_USB_ZERO is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -8343,6 +8419,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m CONFIG_VDPA_USER=m CONFIG_VEML6030=m +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -8434,6 +8511,7 @@ CONFIG_VIDEO_DW9714=m CONFIG_VIDEO_DW9719=m CONFIG_VIDEO_DW9768=m CONFIG_VIDEO_DW9807_VCM=m +# CONFIG_VIDEO_E5010_JPEG_ENC is not set CONFIG_VIDEO_EM28XX_ALSA=m CONFIG_VIDEO_EM28XX_DVB=m CONFIG_VIDEO_EM28XX=m @@ -8444,6 +8522,8 @@ CONFIG_VIDEO_ET8EK8=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set CONFIG_VIDEO_GC0308=m +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set CONFIG_VIDEO_GC2145=m CONFIG_VIDEO_GO7007_LOADER=m CONFIG_VIDEO_GO7007=m @@ -8462,6 +8542,7 @@ CONFIG_VIDEO_IMX214=m CONFIG_VIDEO_IMX219=m CONFIG_VIDEO_IMX258=m CONFIG_VIDEO_IMX274=m +CONFIG_VIDEO_IMX283=m CONFIG_VIDEO_IMX290=m CONFIG_VIDEO_IMX296=m CONFIG_VIDEO_IMX319=m @@ -8483,6 +8564,8 @@ CONFIG_VIDEO_LM3646=m CONFIG_VIDEO_M52790=m CONFIG_VIDEO_MAX9286=m # CONFIG_VIDEO_MAX96712 is not set +CONFIG_VIDEO_MAX96714=m +CONFIG_VIDEO_MAX96717=m # CONFIG_VIDEO_MEM2MEM_DEINTERLACE is not set # CONFIG_VIDEO_MGB4 is not set CONFIG_VIDEO_ML86V7667=m @@ -8535,6 +8618,7 @@ CONFIG_VIDEO_OV9734=m CONFIG_VIDEO_PVRUSB2_DVB=y CONFIG_VIDEO_PVRUSB2=m CONFIG_VIDEO_PVRUSB2_SYSFS=y +CONFIG_VIDEO_RASPBERRYPI_PISP_BE=m CONFIG_VIDEO_RDACM20=m # CONFIG_VIDEO_RDACM21 is not set CONFIG_VIDEO_RJ54N1=m @@ -8600,6 +8684,7 @@ CONFIG_VIDEO_UPD64083=m CONFIG_VIDEO_USBTV=m CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set CONFIG_VIDEO_VICODEC=m CONFIG_VIDEO_VIM2M=m CONFIG_VIDEO_VIMC=m @@ -9004,7 +9089,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-rhel.config b/SOURCES/kernel-x86_64-rhel.config index 3e78e20..8a9c3e6 100644 --- a/SOURCES/kernel-x86_64-rhel.config +++ b/SOURCES/kernel-x86_64-rhel.config @@ -116,6 +116,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -402,6 +403,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -416,6 +418,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -440,6 +443,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -509,6 +513,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -888,6 +893,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1043,7 +1049,6 @@ CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1157,6 +1162,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1273,6 +1279,7 @@ CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFERRED_STRUCT_PAGE_INIT=y CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m CONFIG_DELL_RBU=m CONFIG_DELL_SMBIOS=m @@ -1299,12 +1306,11 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y CONFIG_DL2K=m # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_API_DEBUG_SG is not set @@ -1362,6 +1368,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1377,7 +1384,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1395,6 +1402,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1453,6 +1461,7 @@ CONFIG_DRM_I915=m CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1508,11 +1517,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1527,6 +1538,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1753,6 +1765,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_AMD64=m # CONFIG_EDAC_DEBUG is not set @@ -1819,10 +1832,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1830,10 +1846,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1917,6 +1937,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -1978,17 +1999,17 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -2062,8 +2083,7 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set # CONFIG_GENWQE is not set -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2132,6 +2152,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2139,6 +2160,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2496,13 +2518,13 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set CONFIG_IA32_EMULATION=y # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m # CONFIG_IBM_RTL is not set @@ -2517,6 +2539,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IE6XX_WDT is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set @@ -2753,6 +2776,7 @@ CONFIG_INTEL_MEI_ME=m CONFIG_INTEL_MEI_WDT=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +# CONFIG_INTEL_PLR_TPMI is not set CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3058,6 +3082,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3141,8 +3166,6 @@ CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set CONFIG_KVM_AMD=m CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_GUEST=y CONFIG_KVM_HYPERV=y CONFIG_KVM_INTEL=m @@ -3162,6 +3185,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3229,6 +3255,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3242,6 +3269,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3374,6 +3402,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3463,9 +3492,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3475,6 +3501,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3500,6 +3527,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3513,6 +3541,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3577,6 +3607,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4083,8 +4114,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4094,8 +4127,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4179,8 +4211,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4461,6 +4494,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4480,6 +4514,7 @@ CONFIG_NVSW_SN2201=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4631,6 +4666,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4668,6 +4704,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4712,7 +4749,7 @@ CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=m CONFIG_PINCTRL_CEDARFORK=m # CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CS42L43=m # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_DENVERTON=m CONFIG_PINCTRL_ELKHARTLAKE=m @@ -4720,6 +4757,8 @@ CONFIG_PINCTRL_EMMITSBURG=m # CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_PINCTRL_GEMINILAKE=m CONFIG_PINCTRL_ICELAKE=m +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set CONFIG_PINCTRL_INTEL_PLATFORM=m # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set @@ -4798,6 +4837,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4902,6 +4943,7 @@ CONFIG_PVPANIC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set CONFIG_PWM_LPSS_PCI=m CONFIG_PWM_LPSS_PLATFORM=m @@ -4913,13 +4955,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4932,6 +4975,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -4986,6 +5030,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5069,6 +5114,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -5101,6 +5147,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -5112,7 +5159,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5150,6 +5197,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5274,6 +5322,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5313,6 +5362,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5697,9 +5753,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5744,6 +5804,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5885,6 +5946,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -5986,6 +6048,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6094,6 +6157,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6157,6 +6221,7 @@ CONFIG_SND_SOC_CS42L42_SDW=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6165,6 +6230,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6339,6 +6405,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6475,6 +6542,7 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6597,6 +6665,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6887,6 +6956,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6934,7 +7004,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7410,6 +7480,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7422,6 +7493,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set # CONFIG_VBOXGUEST is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7432,6 +7504,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7527,6 +7600,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7542,6 +7617,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7561,6 +7637,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7677,6 +7755,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7934,7 +8013,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -7990,7 +8069,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-rt-debug-rhel.config b/SOURCES/kernel-x86_64-rt-debug-rhel.config index 033c113..25273f8 100644 --- a/SOURCES/kernel-x86_64-rt-debug-rhel.config +++ b/SOURCES/kernel-x86_64-rt-debug-rhel.config @@ -116,6 +116,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -402,6 +403,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -416,6 +418,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -440,6 +443,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -509,6 +513,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -888,6 +893,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1044,7 +1050,6 @@ CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1158,6 +1163,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1283,6 +1289,7 @@ CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFERRED_STRUCT_PAGE_INIT=y CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m CONFIG_DELL_RBU=m CONFIG_DELL_SMBIOS=m @@ -1309,12 +1316,11 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y CONFIG_DL2K=m # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set CONFIG_DMA_API_DEBUG_SG=y CONFIG_DMA_API_DEBUG=y @@ -1372,6 +1378,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1387,7 +1394,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1405,6 +1412,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1463,6 +1471,7 @@ CONFIG_DRM_I915=m CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1518,11 +1527,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1537,6 +1548,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1799,6 +1811,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_AMD64=m CONFIG_EDAC_DEBUG=y @@ -1865,10 +1878,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1876,10 +1892,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1971,6 +1991,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2032,17 +2053,17 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -2117,8 +2138,7 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set # CONFIG_GENWQE is not set -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2187,6 +2207,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2194,6 +2215,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2552,13 +2574,13 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set CONFIG_IA32_EMULATION=y # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m # CONFIG_IBM_RTL is not set @@ -2573,6 +2595,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IE6XX_WDT is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set @@ -2809,6 +2832,7 @@ CONFIG_INTEL_MEI_ME=m CONFIG_INTEL_MEI_WDT=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +# CONFIG_INTEL_PLR_TPMI is not set CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3118,6 +3142,7 @@ CONFIG_KASAN=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3201,8 +3226,6 @@ CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set CONFIG_KVM_AMD=m CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_GUEST=y CONFIG_KVM_HYPERV=y CONFIG_KVM_INTEL=m @@ -3222,6 +3245,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set CONFIG_LATENCYTOP=y # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3289,6 +3315,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3302,6 +3329,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3343,7 +3371,7 @@ CONFIG_LLC=m CONFIG_LOAD_UEFI_KEYS=y CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_LOCKDEP_BITS=16 +CONFIG_LOCKDEP_BITS=17 CONFIG_LOCKDEP_CHAINS_BITS=18 CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 CONFIG_LOCKDEP_STACK_TRACE_BITS=19 @@ -3434,6 +3462,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3523,14 +3552,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_MSI001 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m -# CONFIG_MEDIA_TUNER_TDA18250 is not set CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3540,6 +3561,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3565,6 +3587,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3578,6 +3601,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3642,6 +3667,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4148,8 +4174,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4159,8 +4187,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4244,8 +4271,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4526,6 +4554,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4545,6 +4574,7 @@ CONFIG_NVSW_SN2201=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4697,6 +4727,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4734,6 +4765,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4778,7 +4810,7 @@ CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=m CONFIG_PINCTRL_CEDARFORK=m # CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CS42L43=m # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_DENVERTON=m CONFIG_PINCTRL_ELKHARTLAKE=m @@ -4786,6 +4818,8 @@ CONFIG_PINCTRL_EMMITSBURG=m # CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_PINCTRL_GEMINILAKE=m CONFIG_PINCTRL_ICELAKE=m +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set CONFIG_PINCTRL_INTEL_PLATFORM=m # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set @@ -4865,6 +4899,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4973,6 +5009,7 @@ CONFIG_PVPANIC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set CONFIG_PWM_LPSS_PCI=m CONFIG_PWM_LPSS_PLATFORM=m @@ -4984,13 +5021,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -5003,6 +5041,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -5057,6 +5096,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m CONFIG_RANDOM32_SELFTEST=y CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5143,6 +5183,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -5175,6 +5216,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -5186,7 +5228,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5224,6 +5266,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5348,6 +5391,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5387,6 +5431,13 @@ CONFIG_RTW89_DEBUGFS=y CONFIG_RTW89_DEBUGMSG=y CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5771,9 +5822,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5818,6 +5873,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5959,6 +6015,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6061,6 +6118,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6170,6 +6228,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6233,6 +6292,7 @@ CONFIG_SND_SOC_CS42L42_SDW=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6241,6 +6301,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6415,6 +6476,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6552,6 +6614,7 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6674,6 +6737,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6964,6 +7028,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -7011,7 +7076,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7488,6 +7553,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7500,6 +7566,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set # CONFIG_VBOXGUEST is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7510,6 +7577,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7605,6 +7673,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7620,6 +7690,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7639,6 +7710,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7755,6 +7828,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -8014,7 +8088,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8075,7 +8149,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel-x86_64-rt-rhel.config b/SOURCES/kernel-x86_64-rt-rhel.config index fc53795..ea320b6 100644 --- a/SOURCES/kernel-x86_64-rt-rhel.config +++ b/SOURCES/kernel-x86_64-rt-rhel.config @@ -116,6 +116,7 @@ CONFIG_ACPI=y # CONFIG_AD7293 is not set # CONFIG_AD7298 is not set # CONFIG_AD7303 is not set +# CONFIG_AD7380 is not set # CONFIG_AD74115 is not set # CONFIG_AD74413R is not set # CONFIG_AD7476 is not set @@ -402,6 +403,7 @@ CONFIG_AUDIT=y CONFIG_AUTOFS_FS=y # CONFIG_AUXDISPLAY is not set CONFIG_AX88796B_PHY=m +# CONFIG_AX88796B_RUST_PHY is not set # CONFIG_B43 is not set # CONFIG_B43LEGACY is not set # CONFIG_B44 is not set @@ -416,6 +418,7 @@ CONFIG_BACKLIGHT_CLASS_DEVICE=y # CONFIG_BACKLIGHT_KTD2801 is not set # CONFIG_BACKLIGHT_KTZ8866 is not set CONFIG_BACKLIGHT_LED=m +# CONFIG_BACKLIGHT_LM3509 is not set # CONFIG_BACKLIGHT_LM3630A is not set # CONFIG_BACKLIGHT_LM3639 is not set CONFIG_BACKLIGHT_LP855X=m @@ -440,6 +443,7 @@ CONFIG_BASE_FULL=y # CONFIG_BATTERY_GOLDFISH is not set # CONFIG_BATTERY_MAX17040 is not set # CONFIG_BATTERY_MAX17042 is not set +# CONFIG_BATTERY_MAX1720X is not set # CONFIG_BATTERY_RT5033 is not set # CONFIG_BATTERY_SAMSUNG_SDI is not set # CONFIG_BATTERY_SBS is not set @@ -509,6 +513,7 @@ CONFIG_BLK_DEV_RAM=m CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_BLK_DEV_RBD=m # CONFIG_BLK_DEV_RSXX is not set +# CONFIG_BLK_DEV_RUST_NULL is not set CONFIG_BLK_DEV_SD=m CONFIG_BLK_DEV_SR=m # CONFIG_BLK_DEV_SX8 is not set @@ -888,6 +893,7 @@ CONFIG_COMPAT_32BIT_TIME=y # CONFIG_COMPAT_BRK is not set # CONFIG_COMPAT_VDSO is not set # CONFIG_COMPILE_TEST is not set +# CONFIG_COMPRESSED_INSTALL is not set CONFIG_CONFIGFS_FS=y CONFIG_CONNECTOR=y CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 @@ -1044,7 +1050,6 @@ CONFIG_CRYPTO_DEV_QAT_DH895xCCVF=m # CONFIG_CRYPTO_DEV_SAFEXCEL is not set CONFIG_CRYPTO_DEV_SP_CCP=y CONFIG_CRYPTO_DEV_SP_PSP=y -# CONFIG_CRYPTO_DEV_TEGRA is not set # CONFIG_CRYPTO_DEV_VIRTIO is not set CONFIG_CRYPTO_DH_RFC7919_GROUPS=y CONFIG_CRYPTO_DH=y @@ -1158,6 +1163,7 @@ CONFIG_CXL_PMEM=m CONFIG_CXL_PMU=m # CONFIG_CXL_REGION_INVALIDATION_TEST is not set CONFIG_CXL_REGION=y +# CONFIG_CZNIC_PLATFORMS is not set # CONFIG_DA280 is not set # CONFIG_DA311 is not set # CONFIG_DAMON_DBGFS_DEPRECATED is not set @@ -1275,6 +1281,7 @@ CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SFQ is not set CONFIG_DEFERRED_STRUCT_PAGE_INIT=y CONFIG_DELL_LAPTOP=m +CONFIG_DELL_PC=m CONFIG_DELL_RBTN=m CONFIG_DELL_RBU=m CONFIG_DELL_SMBIOS=m @@ -1301,12 +1308,11 @@ CONFIG_DEVTMPFS_MOUNT=y CONFIG_DEVTMPFS_SAFE=y CONFIG_DEVTMPFS=y # CONFIG_DHT11 is not set -CONFIG_DIMLIB=m +CONFIG_DIMLIB=y CONFIG_DL2K=m # CONFIG_DLHL60D is not set -CONFIG_DLM_DEBUG=y # CONFIG_DLM_DEPRECATED_API is not set -CONFIG_DLM=m +# CONFIG_DLM is not set # CONFIG_DM9051 is not set # CONFIG_DMA_API_DEBUG is not set # CONFIG_DMA_API_DEBUG_SG is not set @@ -1364,6 +1370,7 @@ CONFIG_DM_UEVENT=y CONFIG_DM_VDO=m CONFIG_DM_VERITY_FEC=y CONFIG_DM_VERITY=m +CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_PLATFORM_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG_SECONDARY_KEYRING=y CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_DM_WRITECACHE=m @@ -1379,7 +1386,7 @@ CONFIG_DP83867_PHY=m # CONFIG_DP83869_PHY is not set CONFIG_DP83TC811_PHY=m # CONFIG_DP83TD510_PHY is not set -# CONFIG_DP83TG720_PHY is not set +CONFIG_DP83TG720_PHY=m # CONFIG_DPM_WATCHDOG is not set # CONFIG_DPOT_DAC is not set # CONFIG_DPS310 is not set @@ -1397,6 +1404,7 @@ CONFIG_DRM_AMDGPU=m # CONFIG_DRM_AMDGPU_SI is not set CONFIG_DRM_AMDGPU_USERPTR=y # CONFIG_DRM_AMDGPU_WERROR is not set +# CONFIG_DRM_AMD_ISP is not set # CONFIG_DRM_AMD_SECURE_DISPLAY is not set # CONFIG_DRM_ANALOGIX_ANX6345 is not set # CONFIG_DRM_ANALOGIX_ANX7625 is not set @@ -1455,6 +1463,7 @@ CONFIG_DRM_I915=m CONFIG_DRM_I915_MAX_REQUEST_BUSYWAIT=8000 CONFIG_DRM_I915_PREEMPT_TIMEOUT=640 CONFIG_DRM_I915_PREEMPT_TIMEOUT_COMPUTE=7500 +# CONFIG_DRM_I915_REPLAY_GPU_HANGS_API is not set CONFIG_DRM_I915_REQUEST_TIMEOUT=20000 # CONFIG_DRM_I915_SELFTEST is not set CONFIG_DRM_I915_STOP_TIMEOUT=100 @@ -1510,11 +1519,13 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set # CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set # CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set +# CONFIG_DRM_PANEL_HIMAX_HX83102 is not set # CONFIG_DRM_PANEL_HIMAX_HX83112A is not set # CONFIG_DRM_PANEL_HIMAX_HX8394 is not set # CONFIG_DRM_PANEL_ILITEK_IL9322 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9341 is not set # CONFIG_DRM_PANEL_ILITEK_ILI9805 is not set +# CONFIG_DRM_PANEL_ILITEK_ILI9806E is not set # CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set # CONFIG_DRM_PANEL_ILITEK_ILI9882T is not set # CONFIG_DRM_PANEL_INNOLUX_EJ030NA is not set @@ -1529,6 +1540,7 @@ CONFIG_DRM_NOUVEAU=m # CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set # CONFIG_DRM_PANEL_LG_LB035Q02 is not set # CONFIG_DRM_PANEL_LG_SW43408 is not set +# CONFIG_DRM_PANEL_LINCOLNTECH_LCD197 is not set # CONFIG_DRM_PANEL_LVDS is not set # CONFIG_DRM_PANEL_MAGNACHIP_D53E6EA8966 is not set # CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set @@ -1791,6 +1803,7 @@ CONFIG_EARLY_PRINTK=y # CONFIG_EBC_C384_WDT is not set # CONFIG_EC_ACER_ASPIRE1 is not set # CONFIG_ECHO is not set +# CONFIG_EC_LENOVO_YOGA_C630 is not set # CONFIG_ECRYPT_FS is not set CONFIG_EDAC_AMD64=m # CONFIG_EDAC_DEBUG is not set @@ -1857,10 +1870,13 @@ CONFIG_EFI_ZBOOT=y CONFIG_ELF_CORE=y # CONFIG_EMBEDDED is not set CONFIG_ENA_ETHERNET=m +# CONFIG_ENC28J60 is not set CONFIG_ENCLOSURE_SERVICES=m CONFIG_ENCRYPTED_KEYS=y +# CONFIG_ENCX24J600 is not set CONFIG_ENERGY_MODEL=y CONFIG_ENIC=m +# CONFIG_ENS160 is not set # CONFIG_ENVELOPE_DETECTOR is not set CONFIG_EPIC100=m CONFIG_EPOLL=y @@ -1868,10 +1884,14 @@ CONFIG_EPOLL=y # CONFIG_EROFS_FS_DEBUG is not set CONFIG_EROFS_FS=m # CONFIG_EROFS_FS_ONDEMAND is not set +# CONFIG_EROFS_FS_PCPU_KTHREAD is not set CONFIG_EROFS_FS_POSIX_ACL=y CONFIG_EROFS_FS_SECURITY=y CONFIG_EROFS_FS_XATTR=y -# CONFIG_EROFS_FS_ZIP is not set +# CONFIG_EROFS_FS_ZIP_DEFLATE is not set +CONFIG_EROFS_FS_ZIP_LZMA=y +CONFIG_EROFS_FS_ZIP=y +# CONFIG_EROFS_FS_ZIP_ZSTD is not set CONFIG_ETHERNET=y CONFIG_ETHOC=m CONFIG_ETHTOOL_NETLINK=y @@ -1955,6 +1975,7 @@ CONFIG_FB_EFI=y CONFIG_FB_MODE_HELPERS=y # CONFIG_FB_N411 is not set # CONFIG_FB_NEOMAGIC is not set +# CONFIG_FBNIC is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_OF is not set # CONFIG_FB_OPENCORES is not set @@ -2016,17 +2037,17 @@ CONFIG_FRAME_POINTER=y # CONFIG_FRAMER is not set CONFIG_FRAME_WARN=2048 CONFIG_FRONTSWAP=y -# CONFIG_FSCACHE_DEBUG is not set CONFIG_FSCACHE_STATS=y CONFIG_FSCACHE=y CONFIG_FS_DAX=y -# CONFIG_FS_ENCRYPTION is not set +CONFIG_FS_ENCRYPTION=y # CONFIG_FSI is not set # CONFIG_FSL_EDMA is not set # CONFIG_FSL_ENETC_IERB is not set # CONFIG_FSL_ENETC is not set # CONFIG_FSL_ENETC_MDIO is not set # CONFIG_FSL_ENETC_VF is not set +# CONFIG_FSL_IFC is not set # CONFIG_FSL_IMX9_DDR_PMU is not set # CONFIG_FSL_PQ_MDIO is not set # CONFIG_FSL_QDMA is not set @@ -2101,8 +2122,7 @@ CONFIG_GENERIC_ISA_DMA=y CONFIG_GENEVE=m # CONFIG_GEN_RTC is not set # CONFIG_GENWQE is not set -CONFIG_GFS2_FS_LOCKING_DLM=y -CONFIG_GFS2_FS=m +# CONFIG_GFS2_FS is not set # CONFIG_GIGABYTE_WMI is not set # CONFIG_GLOB_SELFTEST is not set CONFIG_GLOB=y @@ -2171,6 +2191,7 @@ CONFIG_GPIO_MXC=m # CONFIG_GPIO_SCH is not set # CONFIG_GPIO_SIFIVE is not set CONFIG_GPIO_SIM=m +# CONFIG_GPIO_SLOPPY_LOGIC_ANALYZER is not set # CONFIG_GPIO_SYSCON is not set # CONFIG_GPIO_SYSFS is not set # CONFIG_GPIO_THUNDERX is not set @@ -2178,6 +2199,7 @@ CONFIG_GPIO_SIM=m # CONFIG_GPIO_VF610 is not set # CONFIG_GPIO_VIPERBOARD is not set # CONFIG_GPIO_VIRTIO is not set +# CONFIG_GPIO_VIRTUSER is not set # CONFIG_GPIO_VX855 is not set # CONFIG_GPIO_WATCHDOG is not set # CONFIG_GPIO_WINBOND is not set @@ -2536,13 +2558,13 @@ CONFIG_I2C=y CONFIG_I40E_DCB=y CONFIG_I40E=m CONFIG_I40EVF=m -# CONFIG_I6300ESB_WDT is not set +CONFIG_I6300ESB_WDT=m # CONFIG_I8K is not set # CONFIG_IA32_EMULATION_DEFAULT_DISABLED is not set CONFIG_IA32_EMULATION=y # CONFIG_IAQCORE is not set CONFIG_IAVF=m -# CONFIG_IB700_WDT is not set +CONFIG_IB700_WDT=m # CONFIG_IBM_ASM is not set CONFIG_IBMASR=m # CONFIG_IBM_RTL is not set @@ -2557,6 +2579,7 @@ CONFIG_IDEAPAD_LAPTOP=m CONFIG_IDLE_INJECT=y CONFIG_IDLE_PAGE_TRACKING=y CONFIG_IDPF=m +# CONFIG_IDPF_SINGLEQ is not set # CONFIG_IE6XX_WDT is not set # CONFIG_IEEE802154_6LOWPAN is not set # CONFIG_IEEE802154_ADF7242 is not set @@ -2793,6 +2816,7 @@ CONFIG_INTEL_MEI_ME=m CONFIG_INTEL_MEI_WDT=m CONFIG_INTEL_OAKTRAIL=m CONFIG_INTEL_PCH_THERMAL=m +# CONFIG_INTEL_PLR_TPMI is not set CONFIG_INTEL_PMC_CORE=m CONFIG_INTEL_PMT_CLASS=m CONFIG_INTEL_PMT_CRASHLOG=m @@ -3098,6 +3122,7 @@ CONFIG_KALLSYMS=y CONFIG_KDB_CONTINUE_CATASTROPHIC=0 CONFIG_KDB_DEFAULT_ENABLE=0x0 CONFIG_KDB_KEYBOARD=y +# CONFIG_KEBA_CP500 is not set # CONFIG_KERNEL_BZIP2 is not set CONFIG_KERNEL_GZIP=y CONFIG_KERNEL_IMAGE_BASE=0x3FFE0000000 @@ -3181,8 +3206,6 @@ CONFIG_KUNIT_TEST=m # CONFIG_KUNPENG_HCCS is not set CONFIG_KVM_AMD=m CONFIG_KVM_AMD_SEV=y -# CONFIG_KVM_BOOK3S_HV_P8_TIMING is not set -# CONFIG_KVM_BOOK3S_HV_P9_TIMING is not set CONFIG_KVM_GUEST=y CONFIG_KVM_HYPERV=y CONFIG_KVM_INTEL=m @@ -3202,6 +3225,9 @@ CONFIG_L2TP_ETH=m CONFIG_L2TP_IP=m CONFIG_L2TP=m CONFIG_L2TP_V3=y +CONFIG_LAN743X=m +# CONFIG_LAN966X_OIC is not set +# CONFIG_LAN966X_SWITCH is not set # CONFIG_LAPB is not set # CONFIG_LATENCYTOP is not set # CONFIG_LATTICE_ECP3_CONFIG is not set @@ -3269,6 +3295,7 @@ CONFIG_LEDS_MLXCPLD=m # CONFIG_LEDS_RT8515 is not set # CONFIG_LEDS_SGM3140 is not set # CONFIG_LEDS_SPI_BYTE is not set +# CONFIG_LEDS_SY7802 is not set # CONFIG_LEDS_SYSCON is not set # CONFIG_LEDS_TCA6507 is not set # CONFIG_LEDS_TI_LMU_COMMON is not set @@ -3282,6 +3309,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=m CONFIG_LEDS_TRIGGER_DISK=y CONFIG_LEDS_TRIGGER_GPIO=m CONFIG_LEDS_TRIGGER_HEARTBEAT=m +# CONFIG_LEDS_TRIGGER_INPUT_EVENTS is not set # CONFIG_LEDS_TRIGGER_MTD is not set CONFIG_LEDS_TRIGGER_NETDEV=m CONFIG_LEDS_TRIGGER_ONESHOT=m @@ -3414,6 +3442,7 @@ CONFIG_MANTIS_CORE=m CONFIG_MARVELL_10G_PHY=m CONFIG_MARVELL_88Q2XXX_PHY=m # CONFIG_MARVELL_88X2222_PHY is not set +# CONFIG_MARVELL_CN10K_DPI is not set CONFIG_MARVELL_PHY=m # CONFIG_MATOM is not set # CONFIG_MAX1027 is not set @@ -3503,14 +3532,6 @@ CONFIG_MEDIA_SUPPORT_FILTER=y CONFIG_MEDIA_SUPPORT=m # CONFIG_MEDIATEK_GE_PHY is not set # CONFIG_MEDIA_TEST_SUPPORT is not set -CONFIG_MEDIA_TUNER_M88RS6000T=m -# CONFIG_MEDIA_TUNER_MAX2165 is not set -# CONFIG_MEDIA_TUNER_MSI001 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL301RF is not set -CONFIG_MEDIA_TUNER_QM1D1C0042=m -CONFIG_MEDIA_TUNER_SI2157=m -# CONFIG_MEDIA_TUNER_TDA18250 is not set CONFIG_MEDIA_USB_SUPPORT=y # CONFIG_MEEGOPAD_ANX7428 is not set # CONFIG_MEGARAID_LEGACY is not set @@ -3520,6 +3541,7 @@ CONFIG_MELLANOX_PLATFORM=y # CONFIG_MEM_ALLOC_PROFILING is not set CONFIG_MEMBARRIER=y CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_V1=y CONFIG_MEMCG=y CONFIG_MEMCPY_KUNIT_TEST=m CONFIG_MEMCPY_SLOW_KUNIT_TEST=y @@ -3545,6 +3567,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_88PM800 is not set # CONFIG_MFD_88PM805 is not set # CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_88PM886_PMIC is not set # CONFIG_MFD_AAT2870_CORE is not set # CONFIG_MFD_ACT8945A is not set # CONFIG_MFD_ARIZONA_I2C is not set @@ -3558,6 +3581,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_CPCAP is not set +# CONFIG_MFD_CS40L50_I2C is not set +# CONFIG_MFD_CS40L50_SPI is not set # CONFIG_MFD_CS42L43_I2C is not set CONFIG_MFD_CS42L43_SDW=m # CONFIG_MFD_DA9052_I2C is not set @@ -3622,6 +3647,7 @@ CONFIG_MFD_INTEL_M10_BMC_SPI=m # CONFIG_MFD_ROHM_BD71828 is not set # CONFIG_MFD_ROHM_BD718XX is not set # CONFIG_MFD_ROHM_BD957XMUF is not set +# CONFIG_MFD_ROHM_BD96801 is not set # CONFIG_MFD_RSMU_I2C is not set # CONFIG_MFD_RSMU_SPI is not set # CONFIG_MFD_RT4831 is not set @@ -4128,8 +4154,10 @@ CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER=y +CONFIG_NET_FLOW_LIMIT=y # CONFIG_NET_FOU_IP_TUNNELS is not set # CONFIG_NET_FOU is not set +# CONFIG_NETFS_DEBUG is not set CONFIG_NETFS_STATS=y CONFIG_NETFS_SUPPORT=m CONFIG_NET_HANDSHAKE_KUNIT_TEST=m @@ -4139,8 +4167,7 @@ CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m CONFIG_NET_IPIP=m CONFIG_NET_IPVTI=m -CONFIG_NET_KEY=m -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set # CONFIG_NETKIT is not set CONFIG_NET_L3_MASTER_DEV=y CONFIG_NETLABEL=y @@ -4224,8 +4251,9 @@ CONFIG_NET_VENDOR_INTEL=y # CONFIG_NET_VENDOR_LITEX is not set CONFIG_NET_VENDOR_MARVELL=y CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_NET_VENDOR_META is not set # CONFIG_NET_VENDOR_MICREL is not set -# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MICROCHIP=y # CONFIG_NET_VENDOR_MICROSEMI is not set CONFIG_NET_VENDOR_MICROSOFT=y CONFIG_NET_VENDOR_MYRI=y @@ -4506,6 +4534,7 @@ CONFIG_NVME_MULTIPATH=y CONFIG_NVMEM=y CONFIG_NVME_RDMA=m CONFIG_NVME_TARGET_AUTH=y +# CONFIG_NVME_TARGET_DEBUGFS is not set CONFIG_NVME_TARGET_FCLOOP=m CONFIG_NVME_TARGET_FC=m CONFIG_NVME_TARGET_LOOP=m @@ -4525,6 +4554,7 @@ CONFIG_NVSW_SN2201=m # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_OCFS2_FS is not set CONFIG_OCTEON_EP=m +# CONFIG_OCTEONEP_VDPA is not set CONFIG_OCTEON_EP_VF=m CONFIG_OCXL=m # CONFIG_OF is not set @@ -4676,6 +4706,7 @@ CONFIG_PCI_PASID=y # CONFIG_PCIPCWATCHDOG is not set CONFIG_PCI_PF_STUB=m CONFIG_PCI_PRI=y +# CONFIG_PCI_PWRCTL_PWRSEQ is not set CONFIG_PCI_QUIRKS=y # CONFIG_PCI_REALLOC_ENABLE_AUTO is not set CONFIG_PCI_STUB=y @@ -4713,6 +4744,7 @@ CONFIG_PHY_BCM_SR_USB=m # CONFIG_PHY_CADENCE_TORRENT is not set # CONFIG_PHY_CAN_TRANSCEIVER is not set # CONFIG_PHY_CPCAP_USB is not set +# CONFIG_PHY_FSL_IMX8QM_HSIO is not set # CONFIG_PHY_FSL_LYNX_28G is not set # CONFIG_PHY_FSL_SAMSUNG_HDMI_PHY is not set # CONFIG_PHY_HI3660_USB is not set @@ -4757,7 +4789,7 @@ CONFIG_PINCTRL_BROXTON=m CONFIG_PINCTRL_CANNONLAKE=m CONFIG_PINCTRL_CEDARFORK=m # CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_CS42L43 is not set +CONFIG_PINCTRL_CS42L43=m # CONFIG_PINCTRL_CY8C95X0 is not set CONFIG_PINCTRL_DENVERTON=m CONFIG_PINCTRL_ELKHARTLAKE=m @@ -4765,6 +4797,8 @@ CONFIG_PINCTRL_EMMITSBURG=m # CONFIG_PINCTRL_EQUILIBRIUM is not set CONFIG_PINCTRL_GEMINILAKE=m CONFIG_PINCTRL_ICELAKE=m +# CONFIG_PINCTRL_IMX91 is not set +# CONFIG_PINCTRL_IMX_SCMI is not set CONFIG_PINCTRL_INTEL_PLATFORM=m # CONFIG_PINCTRL_IPQ6018 is not set # CONFIG_PINCTRL_IPQ8074 is not set @@ -4843,6 +4877,8 @@ CONFIG_POWERNV_OP_PANEL=m # CONFIG_POWER_RESET_SYSCON_POWEROFF is not set # CONFIG_POWER_RESET_VEXPRESS is not set CONFIG_POWER_RESET=y +# CONFIG_POWER_SEQUENCING is not set +CONFIG_POWER_SEQUENCING_QCOM_WCN=m # CONFIG_POWER_SUPPLY_DEBUG is not set CONFIG_POWER_SUPPLY_HWMON=y CONFIG_POWER_SUPPLY=y @@ -4951,6 +4987,7 @@ CONFIG_PVPANIC=y # CONFIG_PWM_DEBUG is not set # CONFIG_PWM_DWC is not set # CONFIG_PWM_FSL_FTM is not set +# CONFIG_PWM_GPIO is not set # CONFIG_PWM_HIBVT is not set CONFIG_PWM_LPSS_PCI=m CONFIG_PWM_LPSS_PLATFORM=m @@ -4962,13 +4999,14 @@ CONFIG_PWRSEQ_EMMC=m CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QAT_VFIO_PCI is not set # CONFIG_QCA7000_SPI is not set -# CONFIG_QCA807X_PHY is not set -# CONFIG_QCA808X_PHY is not set -# CONFIG_QCA83XX_PHY is not set +CONFIG_QCA807X_PHY=m +CONFIG_QCA808X_PHY=m +CONFIG_QCA83XX_PHY=m # CONFIG_QCOM_AOSS_QMP is not set # CONFIG_QCOM_APCS_IPC is not set # CONFIG_QCOM_COMMAND_DB is not set # CONFIG_QCOM_CPR is not set +# CONFIG_QCOM_CPUCP_MBOX is not set # CONFIG_QCOM_EBI2 is not set # CONFIG_QCOM_GENI_SE is not set # CONFIG_QCOM_GPI_DMA is not set @@ -4981,6 +5019,7 @@ CONFIG_PWRSEQ_SIMPLE=m # CONFIG_QCOM_MPM is not set # CONFIG_QCOM_OCMEM is not set # CONFIG_QCOM_PDC is not set +# CONFIG_QCOM_PD_MAPPER is not set # CONFIG_QCOM_QFPROM is not set # CONFIG_QCOM_RAMP_CTRL is not set # CONFIG_QCOM_RMTFS_MEM is not set @@ -5035,6 +5074,7 @@ CONFIG_RADIO_TEA575X=m CONFIG_RAID_ATTRS=m # CONFIG_RANDOM32_SELFTEST is not set CONFIG_RANDOMIZE_BASE=y +# CONFIG_RANDOMIZE_IDENTITY_BASE is not set CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y CONFIG_RANDOMIZE_KSTACK_OFFSET=y CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa @@ -5121,6 +5161,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=m # CONFIG_REGULATOR_MCP16502 is not set # CONFIG_REGULATOR_MT6311 is not set # CONFIG_REGULATOR_NETLINK_EVENTS is not set +# CONFIG_REGULATOR_PCA9450 is not set # CONFIG_REGULATOR_PF8X00 is not set # CONFIG_REGULATOR_PFUZE100 is not set # CONFIG_REGULATOR_PV88060 is not set @@ -5153,6 +5194,7 @@ CONFIG_RENESAS_PHY=m # CONFIG_RESET_ATTACK_MITIGATION is not set CONFIG_RESET_CONTROLLER=y # CONFIG_RESET_GPIO is not set +CONFIG_RESET_IMX8MP_AUDIOMIX=y # CONFIG_RESET_INTEL_GW is not set # CONFIG_RESET_QCOM_PDC is not set # CONFIG_RESET_SIMPLE is not set @@ -5164,7 +5206,7 @@ CONFIG_RESOURCE_KUNIT_TEST=m # CONFIG_RFKILL_GPIO is not set CONFIG_RFKILL_INPUT=y CONFIG_RFKILL=m -CONFIG_RH_DISABLE_DEPRECATED=y +CONFIG_RFS_ACCEL=y CONFIG_RHEL_DIFFERENCES=y # CONFIG_RICHTEK_RTQ6056 is not set CONFIG_RING_BUFFER_BENCHMARK=m @@ -5202,6 +5244,7 @@ CONFIG_RPCSEC_GSS_KRB5=m # CONFIG_RPMSG_QCOM_GLINK_RPM is not set # CONFIG_RPMSG_VIRTIO is not set # CONFIG_RPR0521 is not set +CONFIG_RPS=y CONFIG_RSEQ=y # CONFIG_RT2400PCI is not set # CONFIG_RT2500PCI is not set @@ -5326,6 +5369,7 @@ CONFIG_RTL8188EE=m CONFIG_RTL8192CE=m CONFIG_RTL8192CU=m CONFIG_RTL8192DE=m +# CONFIG_RTL8192DU is not set CONFIG_RTL8192EE=m CONFIG_RTL8192SE=m # CONFIG_RTL8192U is not set @@ -5365,6 +5409,13 @@ CONFIG_RTW89_8852CE=m # CONFIG_RTW89_DEBUGMSG is not set CONFIG_RTW89=m CONFIG_RUNTIME_TESTING_MENU=y +# CONFIG_RUST_BUILD_ASSERT_ALLOW is not set +# CONFIG_RUST_DEBUG_ASSERTIONS is not set +# CONFIG_RUST_EXTRA_LOCKDEP is not set +# CONFIG_RUST_FW_LOADER_ABSTRACTIONS is not set +# CONFIG_RUST is not set +# CONFIG_RUST_OVERFLOW_CHECKS is not set +# CONFIG_RUST_PHYLIB_ABSTRACTIONS is not set CONFIG_RV_MON_WWNR=y CONFIG_RV_REACTORS=y CONFIG_RV_REACT_PANIC=y @@ -5749,9 +5800,13 @@ CONFIG_SENSORS_MCP3021=m # CONFIG_SENSORS_MLXREG_FAN is not set # CONFIG_SENSORS_MP2856 is not set # CONFIG_SENSORS_MP2888 is not set +# CONFIG_SENSORS_MP2891 is not set # CONFIG_SENSORS_MP2975 is not set +# CONFIG_SENSORS_MP2993 is not set # CONFIG_SENSORS_MP5023 is not set +# CONFIG_SENSORS_MP5920 is not set # CONFIG_SENSORS_MP5990 is not set +# CONFIG_SENSORS_MP9941 is not set # CONFIG_SENSORS_MPQ7932 is not set # CONFIG_SENSORS_MPQ8785 is not set # CONFIG_SENSORS_MR75203 is not set @@ -5796,6 +5851,7 @@ CONFIG_SENSORS_SIS5595=m CONFIG_SENSORS_SMSC47B397=m CONFIG_SENSORS_SMSC47M192=m CONFIG_SENSORS_SMSC47M1=m +# CONFIG_SENSORS_SPD5118 is not set # CONFIG_SENSORS_STPDDC60 is not set # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SY7636A is not set @@ -5937,6 +5993,7 @@ CONFIG_SIGNED_PE_FILE_VERIFICATION=y CONFIG_SIPHASH_KUNIT_TEST=m # CONFIG_SKGE is not set # CONFIG_SKY2 is not set +CONFIG_SLAB_BUCKETS=y CONFIG_SLAB_FREELIST_HARDENED=y CONFIG_SLAB_FREELIST_RANDOM=y # CONFIG_SLAB_MERGE_DEFAULT is not set @@ -6039,6 +6096,7 @@ CONFIG_SND_HDA_CODEC_CONEXANT=m CONFIG_SND_HDA_CODEC_CS8409=m CONFIG_SND_HDA_CODEC_HDMI=m CONFIG_SND_HDA_CODEC_REALTEK=m +CONFIG_SND_HDA_CODEC_SENARYTECH=m CONFIG_SND_HDA_CODEC_SI3054=m CONFIG_SND_HDA_CODEC_SIGMATEL=m CONFIG_SND_HDA_CODEC_VIA=m @@ -6147,6 +6205,7 @@ CONFIG_SND_SEQ_UMP=y # CONFIG_SND_SOC_AK4458 is not set # CONFIG_SND_SOC_AK4554 is not set # CONFIG_SND_SOC_AK4613 is not set +# CONFIG_SND_SOC_AK4619 is not set # CONFIG_SND_SOC_AK4642 is not set # CONFIG_SND_SOC_AK5386 is not set # CONFIG_SND_SOC_AK5558 is not set @@ -6210,6 +6269,7 @@ CONFIG_SND_SOC_CS42L42_SDW=m # CONFIG_SND_SOC_CS43130 is not set # CONFIG_SND_SOC_CS4341 is not set # CONFIG_SND_SOC_CS4349 is not set +# CONFIG_SND_SOC_CS530X_I2C is not set # CONFIG_SND_SOC_CS53L30 is not set CONFIG_SND_SOC_CS_AMP_LIB_TEST=m CONFIG_SND_SOC_CX2072X=m @@ -6218,6 +6278,7 @@ CONFIG_SND_SOC_DA7213=m CONFIG_SND_SOC_DMIC=m # CONFIG_SND_SOC_ES7134 is not set # CONFIG_SND_SOC_ES7241 is not set +# CONFIG_SND_SOC_ES8311 is not set CONFIG_SND_SOC_ES8316=m CONFIG_SND_SOC_ES8326=m # CONFIG_SND_SOC_ES8328_I2C is not set @@ -6392,6 +6453,7 @@ CONFIG_SND_SOC_RT1308=m CONFIG_SND_SOC_RT1308_SDW=m CONFIG_SND_SOC_RT1316_SDW=m CONFIG_SND_SOC_RT1318_SDW=m +# CONFIG_SND_SOC_RT1320_SDW is not set # CONFIG_SND_SOC_RT5616 is not set # CONFIG_SND_SOC_RT5631 is not set # CONFIG_SND_SOC_RT5659 is not set @@ -6528,6 +6590,7 @@ CONFIG_SND_SOC_TS3A227E=m # CONFIG_SND_SOC_UDA1334 is not set CONFIG_SND_SOC_UTILS_KUNIT_TEST=m # CONFIG_SND_SOC_WCD9335 is not set +# CONFIG_SND_SOC_WCD937X_SDW is not set # CONFIG_SND_SOC_WCD938X_SDW is not set # CONFIG_SND_SOC_WCD939X_SDW is not set # CONFIG_SND_SOC_WM8510 is not set @@ -6650,6 +6713,7 @@ CONFIG_SPI_AMD=y # CONFIG_SPI_BUTTERFLY is not set # CONFIG_SPI_CADENCE is not set # CONFIG_SPI_CADENCE_QUADSPI is not set +# CONFIG_SPI_CH341 is not set # CONFIG_SPI_DEBUG is not set # CONFIG_SPI_DESIGNWARE is not set CONFIG_SPI_FSL_LPSPI=m @@ -6940,6 +7004,7 @@ CONFIG_THUNDERX2_PMU=m # CONFIG_TI_ADC161S626 is not set # CONFIG_TI_ADS1015 is not set # CONFIG_TI_ADS1100 is not set +# CONFIG_TI_ADS1119 is not set # CONFIG_TI_ADS124S08 is not set # CONFIG_TI_ADS1298 is not set # CONFIG_TI_ADS131E08 is not set @@ -6987,7 +7052,7 @@ CONFIG_TLS=m # CONFIG_TMP117 is not set CONFIG_TMPFS_INODE64=y CONFIG_TMPFS_POSIX_ACL=y -# CONFIG_TMPFS_QUOTA is not set +CONFIG_TMPFS_QUOTA=y CONFIG_TMPFS_XATTR=y CONFIG_TMPFS=y # CONFIG_TOOLCHAIN_DEFAULT_CPU is not set @@ -7464,6 +7529,7 @@ CONFIG_USB=y # CONFIG_USB_YUREX is not set CONFIG_USB_ZR364XX=m # CONFIG_USELIB is not set +CONFIG_USERCOPY_KUNIT_TEST=m # CONFIG_USER_DECRYPTED_DATA is not set # CONFIG_USER_EVENTS is not set CONFIG_USERFAULTFD=y @@ -7476,6 +7542,7 @@ CONFIG_UV_SYSFS=m # CONFIG_V4L_PLATFORM_DRIVERS is not set # CONFIG_VALIDATE_FS_PARSER is not set # CONFIG_VBOXGUEST is not set +# CONFIG_VCAP is not set # CONFIG_VCNL3020 is not set # CONFIG_VCNL4000 is not set # CONFIG_VCNL4035 is not set @@ -7486,6 +7553,7 @@ CONFIG_VDPA_SIM=m CONFIG_VDPA_SIM_NET=m # CONFIG_VDPA_USER is not set # CONFIG_VEML6030 is not set +# CONFIG_VEML6040 is not set # CONFIG_VEML6070 is not set # CONFIG_VEML6075 is not set CONFIG_VETH=m @@ -7581,6 +7649,8 @@ CONFIG_VIDEO_EM28XX_RC=m CONFIG_VIDEO_FB_IVTV=m # CONFIG_VIDEO_FIXED_MINOR_RANGES is not set # CONFIG_VIDEO_GC0308 is not set +# CONFIG_VIDEO_GC05A2 is not set +# CONFIG_VIDEO_GC08A3 is not set # CONFIG_VIDEO_GC2145 is not set # CONFIG_VIDEO_GO7007 is not set # CONFIG_VIDEO_GS1662 is not set @@ -7596,6 +7666,7 @@ CONFIG_VIDEO_HDPVR=m # CONFIG_VIDEO_IMX219 is not set # CONFIG_VIDEO_IMX258 is not set # CONFIG_VIDEO_IMX274 is not set +# CONFIG_VIDEO_IMX283 is not set # CONFIG_VIDEO_IMX290 is not set # CONFIG_VIDEO_IMX296 is not set # CONFIG_VIDEO_IMX319 is not set @@ -7615,6 +7686,8 @@ CONFIG_VIDEO_IVTV=m # CONFIG_VIDEO_M52790 is not set # CONFIG_VIDEO_M5MOLS is not set # CONFIG_VIDEO_MAX9286 is not set +# CONFIG_VIDEO_MAX96714 is not set +# CONFIG_VIDEO_MAX96717 is not set # CONFIG_VIDEO_MEYE is not set # CONFIG_VIDEO_MGB4 is not set # CONFIG_VIDEO_ML86V7667 is not set @@ -7731,6 +7804,7 @@ CONFIG_VIDEO_TUNER=m # CONFIG_VIDEO_USBTV is not set CONFIG_VIDEO_V4L2=m CONFIG_VIDEO_V4L2_SUBDEV_API=y +# CONFIG_VIDEO_VGXY61 is not set # CONFIG_VIDEO_VP27SMPX is not set # CONFIG_VIDEO_VPX3220 is not set # CONFIG_VIDEO_VS6624 is not set @@ -7990,7 +8064,7 @@ CONFIG_XMON_DEFAULT_RO_MODE=y CONFIG_XZ_DEC_ARMTHUMB=y CONFIG_XZ_DEC_ARM=y CONFIG_XZ_DEC_IA64=y -# CONFIG_XZ_DEC_MICROLZMA is not set +CONFIG_XZ_DEC_MICROLZMA=y CONFIG_XZ_DEC_POWERPC=y CONFIG_XZ_DEC_SPARC=y # CONFIG_XZ_DEC_TEST is not set @@ -8051,7 +8125,6 @@ CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y CONFIG_I2C_NCT6775=m CONFIG_ZENIFY=y CONFIG_NTSYNC=y -CONFIG_USER_NS_UNPRIVILEGED=y CONFIG_TCP_CONG_BBR2=m CONFIG_SND_SOC_AW87XXX=m CONFIG_SCHED_BORE=y diff --git a/SOURCES/kernel.changelog b/SOURCES/kernel.changelog index df4b332..b52bd07 100644 --- a/SOURCES/kernel.changelog +++ b/SOURCES/kernel.changelog @@ -1,360 +1,427 @@ -* Fri Oct 04 2024 Augusto Caringi <acaringi@redhat.com> [6.10.13-0] -- Linux v6.10.13 +* Fri Oct 04 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.11.2-0] +- Linux v6.11.2 Resolves: -* Mon Sep 30 2024 Augusto Caringi <acaringi@redhat.com> [6.10.12-0] -- Linux v6.10.12 +* Mon Sep 30 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.11.1-0] +- media: qcom: camss: Fix ordering of pm_runtime_enable (Bryan O'Donoghue) +- media: qcom: camss: Remove use_count guard in stop_streaming (Bryan O'Donoghue) +- arm64: dts: allwinner: a64: Add GPU thermal trips to the SoC dtsi (Dragan Simic) +- arm64: dts: rockchip: Raise Pinebook Pro's panel backlight PWM frequency (Dragan Simic) +- arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor (Bryan O'Donoghue) +- ARM: dts: bcm2837/bcm2712: adjust local intc node names (Stefan Wahren) +- arm64: dts: broadcom: Add minimal support for Raspberry Pi 5 (Andrea della Porta) +- Linux v6.11.1 Resolves: -* Wed Sep 18 2024 Augusto Caringi <acaringi@redhat.com> [6.10.11-0] -- New config for 6.10.11 (Augusto Caringi) -- Linux v6.10.11 +* Tue Sep 24 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.11.0-0] +- Initial set up for stable Fedora branch (Justin M. Forbes) +- Reset RHEL_RELEASE for 6.12 (Justin M. Forbes) Resolves: -* Thu Sep 12 2024 Augusto Caringi <acaringi@redhat.com> [6.10.10-0] -- Add entry for BugsFixed (Justin M. Forbes) -- drm/nouveau/fb: restore init() for ramgp102 (Ben Skeggs) -- Linux v6.10.10 +* Sun Sep 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-63] +- Linux v6.11.0 Resolves: -* Sun Sep 08 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.9-0] -- Linux v6.10.9 +* Sun Sep 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.d42f7708e27c.62] +- Linux v6.11.0-0.rc7.d42f7708e27c Resolves: -* Wed Sep 04 2024 Augusto Caringi <acaringi@redhat.com> [6.10.8-0] -- Add to BugsFixed (Augusto Caringi) -- xfs: xfs_finobt_count_blocks() walks the wrong btree (Dave Chinner) -- Linux v6.10.8 +* Sat Sep 14 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.b7718454f937.61] +- Consolidate configs into common for 6.11 kernels (Justin M. Forbes) +- Linux v6.11.0-0.rc7.b7718454f937 Resolves: -* Thu Aug 29 2024 Augusto Caringi <acaringi@redhat.com> [6.10.7-0] -- KVM: PPC: Book3S HV nestedv2: Keep nested guest HASHPKEYR in sync (Shivaprasad G Bhat) -- KVM: PPC: Book3S HV: Add one-reg interface for HASHPKEYR register (Shivaprasad G Bhat) -- KVM: PPC: Book3S HV nestedv2: Keep nested guest HASHKEYR in sync (Shivaprasad G Bhat) -- KVM: PPC: Book3S HV: Add one-reg interface for HASHKEYR register (Shivaprasad G Bhat) -- KVM: PPC: Book3S HV nestedv2: Keep nested guest DEXCR in sync (Shivaprasad G Bhat) -- KVM: PPC: Book3S HV: Add one-reg interface for DEXCR register (Shivaprasad G Bhat) -- Revert the F39 commits which should not have pushed (Justin M. Forbes) -- Turn off libbpf dynamic for perf on F39 (Justin M. Forbes) -- Revert "cpupower: Bump soname version" (Justin M. Forbes) -- Drop soname for libcpupower.so since we reverted the bump (Justin M. Forbes) -- Linux v6.10.7 +* Fri Sep 13 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.196145c606d0.60] +- uki-virt: add systemd-cryptsetup module (Vitaly Kuznetsov) +- redhat/docs: fix command to install missing build dependencies (Davide Cavalca) +- spec: Respect rpmbuild --without debuginfo (Orgad Shaneh) +- fedora/configs: enable GPIO expander drivers (Rupinderjit Singh) +- redhat/configs: Switch to the Rust implementation of AX88796B_PHY driver for Fedora (Neal Gompa) +- redhat: Turn on support for Rust code in Fedora (Neal Gompa) +- Turn off RUST for risc-v (Justin M. Forbes) +- Linux v6.11.0-0.rc7.196145c606d0 Resolves: -* Mon Aug 19 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.6-0] -- Add to BugsFixed (Justin M. Forbes) -- selinux: revert our use of vma_is_initial_heap() (Paul Moore) -- Linux v6.10.6 +* Thu Sep 12 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.77f587896757.59] +- gitlab-ci: allow failure of clang LTO pipelines (Michael Hofmann) +- redhat/configs: Consolidate the CONFIG_KVM_BOOK3S_HV_P*_TIMING switches (Thomas Huth) +- redhat/configs: Consolidate the CONFIG_KVM_SW_PROTECTED_VM switch (Thomas Huth) +- redhat/configs: Consolidate the CONFIG_KVM_HYPERV switch (Thomas Huth) +- redhat/configs: Consolidate the CONFIG_KVM_AMD_SEV switch (Thomas Huth) +- Linux v6.11.0-0.rc7.77f587896757 Resolves: -* Wed Aug 14 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.5-0] -- Revert "ata: libata-scsi: Honor the D_SENSE bit for CK_COND=1 and no error" (Niklas Cassel) -- Linux v6.10.5 +* Wed Sep 11 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.8d8d276ba2fb.58] +- Cleanup some riscv CONFIG locations (Justin M. Forbes) +- Fix up pending riscv Fedora configs post merge (Justin M. Forbes) +- Linux v6.11.0-0.rc7.8d8d276ba2fb Resolves: -* Sun Aug 11 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.4-0] -- wifi: brcmfmac: cfg80211: Handle SSID based pmksa deletion (Janne Grunau) -- New config for 6.10.3 (Justin M. Forbes) -- Linux v6.10.4 +* Tue Sep 10 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.bc83b4d1f086.57] +- fedora/configs: Enable SCMI configuration (Rupinderjit Singh) +- Remove S390 special config for PHYLIB (Justin M. Forbes) +- Disable ELN for riscv64 (Isaiah Stapleton) +- redhat: add checks to ensure only building riscv64 on fedora (Isaiah Stapleton) +- redhat: Add missing riscv fedora configs (Isaiah Stapleton) +- Add riscv64 to the CI pipelines (Isaiah Stapleton) +- redhat: Regenerate dist-self-test-data for riscv64 (Isaiah Stapleton) +- redhat: Add riscv config changes for fedora (David Abdurachmanov) +- redhat: Add support for riscv (David Abdurachmanov) +- redhat: Do not include UKI addons twice (Vitaly Kuznetsov) +- redhat: update gating.yml (Michael Hofmann) +- Linux v6.11.0-0.rc7.bc83b4d1f086 Resolves: -* Mon Aug 05 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.3-0] -- Bluetooth: hci_event: Fix setting DISCOVERY_FINDING for passive scanning (Luiz Augusto von Dentz) -- Linux v6.10.3 +* Mon Sep 09 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc7.56] +- Linux v6.11.0-0.rc7 Resolves: -* Sat Jul 27 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.2-0] -- Linux v6.10.2 +* Sun Sep 08 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.d1f2d51b711a.55] +- Linux v6.11.0-0.rc6.d1f2d51b711a Resolves: -* Wed Jul 24 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.1-0] -- Initial set up for stable Fedora branch (Justin M. Forbes) -- Reset RHEL_RELEASE for the 6.11 cycle (Justin M. Forbes) -- redhat/configs: Enable CONFIG_VMWARE_VMCI/CONFIG_VMWARE_VMCI_VSOCKETS for RHEL (Vitaly Kuznetsov) -- Linux v6.10.1 +* Sat Sep 07 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.b31c44928842.54] +- Linux v6.11.0-0.rc6.b31c44928842 Resolves: -* Mon Jul 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-64] -- Linux v6.10.0 +* Fri Sep 06 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.b831f83e40a2.53] +- Linux v6.11.0-0.rc6.b831f83e40a2 Resolves: -* Sun Jul 14 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.4d145e3f830b.63] -- Consolidate configs to common for 6.10 (Justin M. Forbes) -- Linux v6.10.0-0.rc7.4d145e3f830b +* Thu Sep 05 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.c763c4339688.52] +- Linux v6.11.0-0.rc6.c763c4339688 Resolves: -* Sat Jul 13 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.528dd46d0fc3.62] -- redhat/configs: Enable CONFIG_PTP_1588_CLOCK_MOCK in kernel-modules-internal (Davide Caratti) -- fedora: enabled XE GPU drivers on all arches (Peter Robinson) -- Flip SND_SOC_CS35L56_SPI from off to module for RHEL (Justin M. Forbes) -- Flip DIMLIB from built-in to module for RHEL (Justin M. Forbes) -- Linux v6.10.0-0.rc7.528dd46d0fc3 +* Wed Sep 04 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.88fac17500f4.51] +- Linux v6.11.0-0.rc6.88fac17500f4 Resolves: -* Fri Jul 12 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.43db1e03c086.61] -- Linux v6.10.0-0.rc7.43db1e03c086 +* Mon Sep 02 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.67784a74e258.50] +- Linux v6.11.0-0.rc6.67784a74e258 Resolves: -* Thu Jul 11 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.9d9a2f29aefd.60] -- Linux v6.10.0-0.rc7.9d9a2f29aefd +* Sun Sep 01 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc6.49] +- Linux v6.11.0-0.rc6 Resolves: -* Wed Jul 10 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.34afb82a3c67.59] -- not upstream: drop openssl ENGINE API usage (Jan Stancek) -- Linux v6.10.0-0.rc7.34afb82a3c67 +* Sat Aug 31 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.1934261d8974.48] +- Remove CONFIG_FSCACHE_DEBUG as it has been renamed (Justin M. Forbes) +- Set Fedora configs for 6.11 (Justin M. Forbes) +- Linux v6.11.0-0.rc5.1934261d8974 Resolves: -* Mon Jul 08 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.4376e966ecb7.58] -- Also remove the zfcpdump BASE_SMALL config (Justin M. Forbes) -- Linux v6.10.0-0.rc7.4376e966ecb7 +* Fri Aug 30 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.20371ba12063.47] +- Linux v6.11.0-0.rc5.20371ba12063 Resolves: -* Mon Jul 08 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc7.57] -- Linux v6.10.0-0.rc7 +* Thu Aug 29 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.d5d547aa7b51.46] +- redhat/configs: Microchip lan743x driver (Izabela Bakollari) +- Linux v6.11.0-0.rc5.d5d547aa7b51 Resolves: -* Sun Jul 07 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.c6653f49e4fd.56] -- Linux v6.10.0-0.rc6.c6653f49e4fd +* Wed Aug 28 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.86987d84b968.45] +- redhat: include resolve_btfids in kernel-devel (Jan Stancek) +- redhat: workaround CKI cross compilation for scripts (Jan Stancek) +- spec: fix "unexpected argument to non-parametric macro" warnings (Jan Stancek) +- Linux v6.11.0-0.rc5.86987d84b968 +Resolves: RHEL-56069 + +* Tue Aug 27 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.3e9bff3bbe13.44] +- Linux v6.11.0-0.rc5.3e9bff3bbe13 +Resolves: RHEL-49398 + +* Mon Aug 26 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.43] +- Add weakdep support to the kernel spec (Justin M. Forbes) +- redhat: configs: disable PF_KEY in RHEL (Sabrina Dubroca) +- crypto: akcipher - Disable signing and decryption (Vladis Dronov) [RHEL-54183] {CVE-2023-6240} +- crypto: dh - implement FIPS PCT (Vladis Dronov) [RHEL-54183] +- crypto: ecdh - disallow plain "ecdh" usage in FIPS mode (Vladis Dronov) [RHEL-54183] +- crypto: seqiv - flag instantiations as FIPS compliant (Vladis Dronov) [RHEL-54183] +- [kernel] bpf: set default value for bpf_jit_harden (Artem Savkov) [RHEL-51896] +Resolves: RHEL-51896, RHEL-54183 + +* Sun Aug 25 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc5.42] +- Linux v6.11.0-0.rc5 Resolves: -* Sat Jul 06 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.1dd28064d416.55] -- Linux v6.10.0-0.rc6.1dd28064d416 +* Sat Aug 24 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.d2bafcf224f3.41] +- Linux v6.11.0-0.rc4.d2bafcf224f3 Resolves: -* Fri Jul 05 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.661e504db04c.54] -- Linux v6.10.0-0.rc6.661e504db04c +* Fri Aug 23 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.3d5f968a177d.40] +- Linux v6.11.0-0.rc4.3d5f968a177d Resolves: -* Thu Jul 04 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.795c58e4c7fc.53] -- Linux v6.10.0-0.rc6.795c58e4c7fc +* Thu Aug 22 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.872cf28b8df9.39] +- Linux v6.11.0-0.rc4.872cf28b8df9 Resolves: -* Wed Jul 03 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.e9d22f7a6655.52] -- Linux v6.10.0-0.rc6.e9d22f7a6655 +* Wed Aug 21 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.b311c1b497e5.38] +- Linux v6.11.0-0.rc4.b311c1b497e5 Resolves: -* Tue Jul 02 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.1dfe225e9af5.51] -- redhat: Add cgroup kselftests to kernel-selftests-internal (Waiman Long) [RHEL-43556] -- Revert "redhat/configs: Disable CONFIG_INFINIBAND_HFI1 and CONFIG_INFINIBAND_RDMAVT" (Kamal Heib) -- Remove new for GITLAB_TOKEN (Don Zickus) -- Set Fedora configs for 6.10 (Justin M. Forbes) -- Fedora: minor driver updates (Peter Robinson) -- Linux v6.10.0-0.rc6.1dfe225e9af5 -Resolves: RHEL-43556 +* Tue Aug 20 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.6e4436539ae1.37] +- fedora: disable CONFIG_DRM_WERROR (Patrick Talbert) +- Linux v6.11.0-0.rc4.6e4436539ae1 +Resolves: -* Mon Jul 01 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc6.50] -- redhat/configs: Remove obsolete x86 CPU mitigations config files (Waiman Long) -- redhat/configs: increase CONFIG_DEFAULT_MMAP_MIN_ADDR from 32K to 64K for aarch64 (Brian Masney) -- redhat/configs: Re-enable CONFIG_KEXEC for Fedora (Philipp Rudo) -- media: ipu-bridge: Add HIDs from out of tree IPU6 driver ipu-bridge copy (Hans de Goede) -- media: ipu-bridge: Sort ipu_supported_sensors[] array by ACPI HID (Hans de Goede) -- disable LR_WPAN for RHEL10 (Chris von Recklinghausen) [RHEL-40251] -- Linux v6.10.0-0.rc6 -Resolves: RHEL-40251 +* Mon Aug 19 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc4.36] +- Linux v6.11.0-0.rc4 +Resolves: -* Sun Jun 30 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.8282d5af7be8.49] -- Linux v6.10.0-0.rc5.8282d5af7be8 +* Sun Aug 18 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.c3f2d783a459.35] +- Linux v6.11.0-0.rc3.c3f2d783a459 Resolves: -* Sat Jun 29 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.de0a9f448633.48] -- Turn on USB_SERIAL_F81232 for Fedora (Justin M. Forbes) -- Linux v6.10.0-0.rc5.de0a9f448633 +* Sat Aug 17 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.e5fa841af679.34] +- Linux v6.11.0-0.rc3.e5fa841af679 Resolves: -* Fri Jun 28 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.5bbd9b249880.47] -- Linux v6.10.0-0.rc5.5bbd9b249880 +* Fri Aug 16 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.d7a5aa4b3c00.33] +- redhat/configs: Disable dlm in rhel configs (Andrew Price) +- rhel: aarch64: enable required PSCI configs (Peter Robinson) +- Linux v6.11.0-0.rc3.d7a5aa4b3c00 Resolves: -* Thu Jun 27 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.afcd48134c58.46] -- redhat/scripts/filtermods.py: show all parent/child kmods in report (Jan Stancek) -- redhat/kernel.spec: capture filtermods.py return code (Jan Stancek) -- redhat/kernel.spec: fix run of mod-denylist (Jan Stancek) -- gitlab-ci: remove unused RHMAINTAINERS variable (Michael Hofmann) -- gitlab-ci: use environments for jobs that need access to push/gitlab secrets (Michael Hofmann) -- gitlab-ci: default to os-build for all maintenance jobs (Michael Hofmann) -- gitlab-ci: use the common git repo setup cki-gating as well (Michael Hofmann) -- gitlab-ci: help maintenance jobs to cope with missing private key (Michael Hofmann) -- gitlab-ci: use a common git repo setup for all maintenance jobs (Michael Hofmann) -- gitlab-ci: move repo setup script into script template holder (Michael Hofmann) -- gitlab-ci: move maintenance job DIST variable into common template (Michael Hofmann) -- gitlab-ci: move maintenance job rules into common template (Michael Hofmann) -- gitlab-ci: move maintenance job retry field into common template (Michael Hofmann) -- gitlab-ci: provide common non-secret schedule trigger variables (Michael Hofmann) -- gitlab-ci: rename .scheduled_setup to .git_setup (Michael Hofmann) -- gitlab-ci: move script snippets into separate template (Michael Hofmann) -- gitlab-ci: rename maintenance jobs (Michael Hofmann) -- gitlab-ci: introduce job template for maintenance jobs (Michael Hofmann) -- Linux v6.10.0-0.rc5.afcd48134c58 +* Thu Aug 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.1fb918967b56.32] +- Linux v6.11.0-0.rc3.1fb918967b56 Resolves: -* Wed Jun 26 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.24ca36a562d6.45] -- Turn on KASAN_HW_TAGS for Fedora aarch64 debug kernels (Justin M. Forbes) -- Linux v6.10.0-0.rc5.24ca36a562d6 +* Wed Aug 14 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.6b0f8db921ab.31] +- fedora: Enable AF8133J Magnetometer driver (Peter Robinson) +- Linux v6.11.0-0.rc3.6b0f8db921ab Resolves: -* Tue Jun 25 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc5.44] -- redhat: kernel.spec: add missing sound/soc/sof/sof-audio.h to kernel-devel package (Jaroslav Kysela) +* Tue Aug 13 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.d74da846046a.30] +- redhat: spec: add cachestat kselftest (Eric Chanudet) +- redhat: hmac sign the UKI for FIPS (Vitaly Kuznetsov) +- not upstream: Disable vdso getrandom when FIPS is enabled (Herbert Xu) +- Linux v6.11.0-0.rc3.d74da846046a Resolves: -* Mon Jun 24 2024 Justin M. Forbes <jforbes@fedoraproject.org> [6.10.0-0.rc5.43] -- redhat/kernel.spec: fix attributes of symvers file (Jan Stancek) -- redhat: add filtermods rule for iommu tests (Jan Stancek) -- Linux v6.10.0-0.rc5 +* Mon Aug 12 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc3.29] +- Linux v6.11.0-0.rc3 Resolves: -* Fri Jun 21 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc4.50736169ecc8.42] -- fedora: arm: Enable basic support for S32G-VNP-RDB3 board (Enric Balletbo i Serra) -- Linux v6.10.0-0.rc4.50736169ecc8 +* Sun Aug 11 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.5189dafa4cf9.28] +- Linux v6.11.0-0.rc2.5189dafa4cf9 Resolves: -* Thu Jun 20 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc4.e5b3efbe1ab1.41] -- Linux v6.10.0-0.rc4.e5b3efbe1ab1 +* Sat Aug 10 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.34ac1e82e5a7.27] +- kernel: config: enable erofs lzma compression (Ian Kent) +- fedora: disable RTL8192CU in Fedora (Peter Robinson) +- Linux v6.11.0-0.rc2.34ac1e82e5a7 Resolves: -* Wed Jun 19 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc4.92e5605a199e.40] -- redhat: make bnx2xx drivers unmaintained in rhel-10 (John Meneghini) [RHEL-36646 RHEL-41231] -- Linux v6.10.0-0.rc4.92e5605a199e -Resolves: RHEL-36646, RHEL-41231 +* Fri Aug 09 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.ee9a43b7cfe2.26] +- redhat: Fix the ownership of /lib/modules/<kversion> directory (Vitaly Kuznetsov) +- new configs in drivers/phy (Izabela Bakollari) +- Add support to rh_waived cmdline boot parameter (Ricardo Robaina) [RHEL-26170] +- Linux v6.11.0-0.rc2.ee9a43b7cfe2 +Resolves: RHEL-26170 -* Tue Jun 18 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc4.14d7c92f8df9.39] -- redhat/configs: Disable CONFIG_NFP (Kamal Heib) [RHEL-36647] -- Enable CONFIG_PWRSEQ_{SIMPLIE,EMMC} on aarch64 (Charles Mirabile) -- Linux v6.10.0-0.rc4.14d7c92f8df9 -Resolves: RHEL-36647 +* Thu Aug 08 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.6a0e38264012.25] +- Linux v6.11.0-0.rc2.6a0e38264012 +Resolves: -* Mon Jun 17 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc4.38] -- Fix SERIAL_SC16IS7XX configs for Fedora (Justin M. Forbes) -- Enable ALSA (CONFIG_SND) on aarch64 (Charles Mirabile) [RHEL-40411] -- redhat: Remove DIST_BRANCH variable (Eder Zulian) -- Linux v6.10.0-0.rc4 -Resolves: RHEL-40411 +* Wed Aug 07 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.d4560686726f.24] +- Linux v6.11.0-0.rc2.d4560686726f +Resolves: -* Sun Jun 16 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.a3e18a540541.37] -- Linux v6.10.0-0.rc3.a3e18a540541 +* Tue Aug 06 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.b446a2dae984.23] +- redhat/configs: Disable gfs2 in rhel configs (Andrew Price) +- redhat/uki_addons/virt: add common FIPS addon (Emanuele Giuseppe Esposito) +- redhat/kernel.spec: add uki_addons to create UKI kernel cmdline addons (Emanuele Giuseppe Esposito) +- Linux v6.11.0-0.rc2.b446a2dae984 Resolves: -* Sat Jun 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.44ef20baed8e.36] -- Linux v6.10.0-0.rc3.44ef20baed8e +* Mon Aug 05 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc2.22] +- rh_flags: fix failed when register_sysctl_sz rh_flags_table to kernel (Ricardo Robaina) [RHEL-52629] +- Linux v6.11.0-0.rc2 +Resolves: RHEL-52629 + +* Sun Aug 04 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.defaf1a2113a.21] +- Linux v6.11.0-0.rc1.defaf1a2113a Resolves: -* Fri Jun 14 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.d20f6b3d747c.35] -- Linux v6.10.0-0.rc3.d20f6b3d747c +* Sat Aug 03 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.17712b7ea075.20] +- Linux v6.11.0-0.rc1.17712b7ea075 Resolves: -* Thu Jun 13 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.2ccbdf43d5e7.34] -- Linux v6.10.0-0.rc3.2ccbdf43d5e7 +* Fri Aug 02 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.c0ecd6388360.19] +- redhat/dracut-virt.conf: add systemd-veritysetup module (Emanuele Giuseppe Esposito) +- Linux v6.11.0-0.rc1.c0ecd6388360 Resolves: -* Wed Jun 12 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.2ef5971ff345.33] -- gitlab-ci: merge ark-latest before tagging cki-gating (Michael Hofmann) -- Linux v6.10.0-0.rc3.2ef5971ff345 +* Thu Aug 01 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.21b136cc63d2.18] +- redhat/configs: enable CONFIG_LOCK_STAT on the debug kernels for aarch64 (Brian Masney) +- redhat/configs: enable CONFIG_KEYBOARD_GPIO_POLLED for RHEL on aarch64 (Luiz Capitulino) +- redhat/configs: fedora: Enable new Qualcomm configs (Andrew Halaney) +- redhat/configs: fedora: Disable CONFIG_QCOM_PD_MAPPER for non aarch64 (Andrew Halaney) +- redhat/configs/fedora: set CONFIG_CRYPTO_CURVE25519_PPC64 (Dan Horák) +- fedora: Updates for 6.11 merge (Peter Robinson) +- fedora: enable new mipi sensors and devices (Peter Robinson) +- Linux v6.11.0-0.rc1.21b136cc63d2 Resolves: -* Tue Jun 11 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.32] -- gitlab-ci: do not merge ark-latest for gating pipelines for Rawhide (Michael Hofmann) -- disable CONFIG_KVM_INTEL_PROVE_VE (Paolo Bonzini) -- redhat: remove the merge subtrees script (Derek Barbosa) -- redhat: rhdocs: delete .get_maintainer.conf (Derek Barbosa) -- redhat: rhdocs: Remove the rhdocs directory (Derek Barbosa) -- redhat/configs: Disable CONFIG_QLA3XXX (Kamal Heib) [RHEL-36646] -Resolves: RHEL-36646 +* Wed Jul 31 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.e4fc196f5ba3.17] +- arm64: enable CRYPTO_DEV_TEGRA on RHEL (Peter Robinson) +- redhat/kernel.spec: fix file listed twice warning for "kernel" subdir (Jan Stancek) +- redhat/configs: Double MAX_LOCKDEP_ENTRIES for RT debug kernels (Waiman Long) [RHEL-43425] +- Support the first day after a rebase (Don Zickus) +- Support 2 digit versions properly (Don Zickus) +- Automation cleanups for rebasing rt-devel and automotive-devel (Don Zickus) +- Linux v6.11.0-0.rc1.e4fc196f5ba3 +Resolves: RHEL-43425 -* Mon Jun 10 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc3.31] -- Linux v6.10.0-0.rc3 +* Tue Jul 30 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.94ede2a3e913.16] +- Linux v6.11.0-0.rc1.94ede2a3e913 Resolves: -* Sun Jun 09 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.771ed66105de.30] -- redhat/configs: fedora: Enable some drivers for IPU6 support (Hans de Goede) -- Linux v6.10.0-0.rc2.771ed66105de +* Mon Jul 29 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc1.dc1c8034e31b.15] +- fedora: set CONFIG_REGULATOR_RZG2L_VBCTRL as a module for arm64 (Patrick Talbert) +- Linux v6.11.0-0.rc1.dc1c8034e31b Resolves: -* Sat Jun 08 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.dc772f8237f9.29] -- Linux v6.10.0-0.rc2.dc772f8237f9 +* Sat Jul 27 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.3a7e02c040b1.14] +- Linux v6.11.0-0.rc0.3a7e02c040b1 Resolves: -* Fri Jun 07 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.8a92980606e3.28] -- Linux v6.10.0-0.rc2.8a92980606e3 +* Fri Jul 26 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.1722389b0d86.13] +- gitlab-ci: restore bot pipeline behavior (Michael Hofmann) +- redhat/kernel.spec: drop extra right curly bracket in kernel_kvm_package (Jan Stancek) +- redhat/configs: enable gpio_keys driver for RHEL on aarch64 (Luiz Capitulino) +- Move NET_VENDOR_MICROCHIP from common to rhel (Justin M. Forbes) +- Linux v6.11.0-0.rc0.1722389b0d86 Resolves: -* Thu Jun 06 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.2df0193e62cf.27] -- redhat: add missing UKI_secureboot_cert hunk (Patrick Talbert) -- Linux v6.10.0-0.rc2.2df0193e62cf +* Thu Jul 25 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.c33ffdb70cc6.12] +- Linux v6.11.0-0.rc0.c33ffdb70cc6 Resolves: -* Wed Jun 05 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.32f88d65f01b.26] -- redhat/kernel.spec: keep extra modules in original directories (Jan Stancek) -- Linux v6.10.0-0.rc2.32f88d65f01b +* Wed Jul 24 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.786c8248dbd3.11] +- Linux v6.11.0-0.rc0.786c8248dbd3 Resolves: -* Tue Jun 04 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.2ab795141095.25] -- redhat/configs: Move CONFIG_BLK_CGROUP_IOCOST=y to common/generic (Waiman Long) -- Turn on CONFIG_MFD_QCOM_PM8008 for Fedora aarch64 (Justin M. Forbes) -- Linux v6.10.0-0.rc2.2ab795141095 +* Tue Jul 23 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.66ebbdfdeb09.10] +- redhat/configs: enable some RTCs for RHEL on aarch64 (Luiz Capitulino) +- redhat/configs: enable some regulators for RHEL (Luiz Capitulino) +- redhat/config: disable CXL and CXLFLASH drivers (Dan Horák) +- Linux v6.11.0-0.rc0.66ebbdfdeb09 Resolves: -* Mon Jun 03 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc2.24] -- Linux v6.10.0-0.rc2 +* Mon Jul 22 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.933069701c1b.9] +- Fix up config mismatches in pending (Justin M. Forbes) +- redhat/configs: Enable watchdog devices modelled by qemu (Richard W.M. Jones) [RHEL-40937] +- Linux v6.11.0-0.rc0.933069701c1b +Resolves: RHEL-40937 + +* Mon Jul 22 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.720261cfc732.8] +- rhel: cleanup unused media tuner configs (Peter Robinson) +- all: cleanup MEDIA_CONTROLLER options (Peter Robinson) +- redhat: kernel.spec: add s390x to livepatching kselftest builds (Joe Lawrence) Resolves: -* Sun Jun 02 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.83814698cf48.23] -- Linux v6.10.0-0.rc1.83814698cf48 +* Sat Jul 20 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.720261cfc732.7] +- Flip CONFIG_DIMLIB back to inline (Justin M. Forbes) +- Add vfio/nvgrace-gpu driver CONFIG to RHEL-9.5 ARM64 (Donald Dutile) +- Enable CONFIG_RTC_DRV_TEGRA for RHEL (Luiz Capitulino) Resolves: -* Sat Jun 01 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.cc8ed4d0a848.22] -- Linux v6.10.0-0.rc1.cc8ed4d0a848 +* Fri Jul 19 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.720261cfc732.6] +- redhat: rh_flags: declare proper static methods when !CONFIG_RHEL_DIFFERENCES (Rafael Aquini) +- redhat: configs: enable CONFIG_TMPFS_QUOTA for both Fedora and RHEL (Rafael Aquini) +- Linux v6.11.0-0.rc0.720261cfc732 Resolves: -* Fri May 31 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.4a4be1ad3a6e.21] -- redhat: Build IMA CA certificate into the Fedora kernel (Coiby Xu) -- Move CONFIG_RAS_FMPM to the proper location (Aristeu Rozanski) -- redhat/configs: Remove CONFIG_NET_ACT_IPT (Ivan Vecera) +* Thu Jul 18 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.b1bc554e009e.5] +- Linux v6.11.0-0.rc0.b1bc554e009e +Resolves: + +* Wed Jul 17 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.51835949dda3.4] +- Fix up mismatches in the 6.11 merge window. (Justin M. Forbes) +- Linux v6.11.0-0.rc0.51835949dda3 Resolves: -* Thu May 30 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.4a4be1ad3a6e.20] -- Linux v6.10.0-0.rc1.4a4be1ad3a6e +* Wed Jul 17 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.d67978318827.3] +- Reset Changelog after rebase (Justin M. Forbes) Resolves: -* Wed May 29 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.e0cce98fe279.19] +* Tue Jul 16 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.11.0-0.rc0.d67978318827.2] +- Reset RHEL_RELEASE for the 6.11 cycle (Justin M. Forbes) +- redhat/configs: Enable CONFIG_VMWARE_VMCI/CONFIG_VMWARE_VMCI_VSOCKETS for RHEL (Vitaly Kuznetsov) +- Consolidate configs to common for 6.10 (Justin M. Forbes) +- redhat/configs: Enable CONFIG_PTP_1588_CLOCK_MOCK in kernel-modules-internal (Davide Caratti) +- fedora: enabled XE GPU drivers on all arches (Peter Robinson) +- Flip SND_SOC_CS35L56_SPI from off to module for RHEL (Justin M. Forbes) +- Flip DIMLIB from built-in to module for RHEL (Justin M. Forbes) +- not upstream: drop openssl ENGINE API usage (Jan Stancek) +- Also remove the zfcpdump BASE_SMALL config (Justin M. Forbes) +- redhat: Add cgroup kselftests to kernel-selftests-internal (Waiman Long) [RHEL-43556] +- Revert "redhat/configs: Disable CONFIG_INFINIBAND_HFI1 and CONFIG_INFINIBAND_RDMAVT" (Kamal Heib) +- Remove new for GITLAB_TOKEN (Don Zickus) +- Set Fedora configs for 6.10 (Justin M. Forbes) +- Fedora: minor driver updates (Peter Robinson) +- redhat/configs: Remove obsolete x86 CPU mitigations config files (Waiman Long) +- redhat/configs: increase CONFIG_DEFAULT_MMAP_MIN_ADDR from 32K to 64K for aarch64 (Brian Masney) +- redhat/configs: Re-enable CONFIG_KEXEC for Fedora (Philipp Rudo) +- media: ipu-bridge: Add HIDs from out of tree IPU6 driver ipu-bridge copy (Hans de Goede) +- media: ipu-bridge: Sort ipu_supported_sensors[] array by ACPI HID (Hans de Goede) +- disable LR_WPAN for RHEL10 (Chris von Recklinghausen) [RHEL-40251] +- Turn on USB_SERIAL_F81232 for Fedora (Justin M. Forbes) +- redhat/scripts/filtermods.py: show all parent/child kmods in report (Jan Stancek) +- redhat/kernel.spec: capture filtermods.py return code (Jan Stancek) +- redhat/kernel.spec: fix run of mod-denylist (Jan Stancek) +- gitlab-ci: remove unused RHMAINTAINERS variable (Michael Hofmann) +- gitlab-ci: use environments for jobs that need access to push/gitlab secrets (Michael Hofmann) +- gitlab-ci: default to os-build for all maintenance jobs (Michael Hofmann) +- gitlab-ci: use the common git repo setup cki-gating as well (Michael Hofmann) +- gitlab-ci: help maintenance jobs to cope with missing private key (Michael Hofmann) +- gitlab-ci: use a common git repo setup for all maintenance jobs (Michael Hofmann) +- gitlab-ci: move repo setup script into script template holder (Michael Hofmann) +- gitlab-ci: move maintenance job DIST variable into common template (Michael Hofmann) +- gitlab-ci: move maintenance job rules into common template (Michael Hofmann) +- gitlab-ci: move maintenance job retry field into common template (Michael Hofmann) +- gitlab-ci: provide common non-secret schedule trigger variables (Michael Hofmann) +- gitlab-ci: rename .scheduled_setup to .git_setup (Michael Hofmann) +- gitlab-ci: move script snippets into separate template (Michael Hofmann) +- gitlab-ci: rename maintenance jobs (Michael Hofmann) +- gitlab-ci: introduce job template for maintenance jobs (Michael Hofmann) +- Turn on KASAN_HW_TAGS for Fedora aarch64 debug kernels (Justin M. Forbes) +- redhat: kernel.spec: add missing sound/soc/sof/sof-audio.h to kernel-devel package (Jaroslav Kysela) +- redhat/kernel.spec: fix attributes of symvers file (Jan Stancek) +- redhat: add filtermods rule for iommu tests (Jan Stancek) +- fedora: arm: Enable basic support for S32G-VNP-RDB3 board (Enric Balletbo i Serra) +- redhat: make bnx2xx drivers unmaintained in rhel-10 (John Meneghini) [RHEL-36646 RHEL-41231] +- redhat/configs: Disable CONFIG_NFP (Kamal Heib) [RHEL-36647] +- Enable CONFIG_PWRSEQ_{SIMPLIE,EMMC} on aarch64 (Charles Mirabile) +- Fix SERIAL_SC16IS7XX configs for Fedora (Justin M. Forbes) +- Enable ALSA (CONFIG_SND) on aarch64 (Charles Mirabile) [RHEL-40411] +- redhat: Remove DIST_BRANCH variable (Eder Zulian) +- gitlab-ci: merge ark-latest before tagging cki-gating (Michael Hofmann) +- gitlab-ci: do not merge ark-latest for gating pipelines for Rawhide (Michael Hofmann) +- disable CONFIG_KVM_INTEL_PROVE_VE (Paolo Bonzini) +- redhat: remove the merge subtrees script (Derek Barbosa) +- redhat: rhdocs: delete .get_maintainer.conf (Derek Barbosa) +- redhat: rhdocs: Remove the rhdocs directory (Derek Barbosa) +- redhat/configs: Disable CONFIG_QLA3XXX (Kamal Heib) [RHEL-36646] +- redhat/configs: fedora: Enable some drivers for IPU6 support (Hans de Goede) +- redhat: add missing UKI_secureboot_cert hunk (Patrick Talbert) +- redhat/kernel.spec: keep extra modules in original directories (Jan Stancek) +- redhat/configs: Move CONFIG_BLK_CGROUP_IOCOST=y to common/generic (Waiman Long) +- Turn on CONFIG_MFD_QCOM_PM8008 for Fedora aarch64 (Justin M. Forbes) +- redhat: Build IMA CA certificate into the Fedora kernel (Coiby Xu) +- Move CONFIG_RAS_FMPM to the proper location (Aristeu Rozanski) +- redhat/configs: Remove CONFIG_NET_ACT_IPT (Ivan Vecera) - gitlab-ci: add kernel-automotive pipelines (Michael Hofmann) - Enable CEC support for TC358743 (Peter Robinson) - fedora: arm: Enable ARCH_R9A09G057 (Peter Robinson) - fedora: updates for the 6.10 kernel (Peter Robinson) - fedora: arm: Enable the MAX96706 GMSL module (Peter Robinson) -- Linux v6.10.0-0.rc1.e0cce98fe279 -Resolves: - -* Tue May 28 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.2bfcfd584ff5.18] -- Linux v6.10.0-0.rc1.2bfcfd584ff5 -Resolves: - -* Mon May 27 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc1.17] - redhat: Switch UKI to using its own SecureBoot cert (from system-sb-certs) (Jan Stancek) - redhat: Add RHEL specifc .sbat section to UKI (Jan Stancek) - kernel.spec: add iommu selftests to kernel-selftests-internal (Eder Zulian) [RHEL-32895] -- Linux v6.10.0-0.rc1 -Resolves: RHEL-32895 - -* Sun May 26 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.c13320499ba0.16] -- Linux v6.10.0-0.rc0.c13320499ba0 -Resolves: - -* Sat May 25 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.56fb6f92854f.15] -- Linux v6.10.0-0.rc0.56fb6f92854f -Resolves: - -* Fri May 24 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.6d69b6c12fce.14] -- Linux v6.10.0-0.rc0.6d69b6c12fce -Resolves: - -* Fri May 24 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.c760b3725e52.13] - redhat/configs: fedora: aarch64: Re-enable CUSE (Neal Gompa) -Resolves: - -* Thu May 23 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.c760b3725e52.12] -- Linux v6.10.0-0.rc0.c760b3725e52 -Resolves: - -* Wed May 22 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.29c73fc794c8.11] - redhat: pass correct RPM_VMLINUX_H to bpftool install (Jan Stancek) - rh_flags: Rename rh_features to rh_flags (Ricardo Robaina) [RHEL-32987] - kernel: rh_features: fix reading empty feature list from /proc (Ricardo Robaina) [RHEL-32987] @@ -362,48 +429,13 @@ Resolves: - rh_features: convert to atomic allocation (Ricardo Robaina) [RHEL-32987] - add rh_features to /proc (Ricardo Robaina) [RHEL-32987] - add support for rh_features (Ricardo Robaina) [RHEL-32987] -- Linux v6.10.0-0.rc0.29c73fc794c8 -Resolves: RHEL-32987 - -* Tue May 21 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.8f6a15f095a6.10] - Drop kexec_load syscall support (Baoquan He) -- Linux v6.10.0-0.rc0.8f6a15f095a6 -Resolves: - -* Mon May 20 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.eb6a9339efeb.9] - New configs in lib/kunit (Fedora Kernel Team) -- Linux v6.10.0-0.rc0.eb6a9339efeb -Resolves: - -* Sun May 19 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.0450d2083be6.8] -- Linux v6.10.0-0.rc0.0450d2083be6 -Resolves: - -* Sat May 18 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.4b377b4868ef.7] -- Linux v6.10.0-0.rc0.4b377b4868ef -Resolves: - -* Fri May 17 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.ea5f6ad9ad96.6] - Turn off KUNIT_FAULT_TEST as it causes problems for CI (Justin M. Forbes) - Add a config entry in pending for CONFIG_DRM_MSM_VALIDATE_XML (Justin M. Forbes) -- Linux v6.10.0-0.rc0.ea5f6ad9ad96 -Resolves: - -* Thu May 16 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.3c999d1ae3c7.5] - Flip CONFIG_SND_SOC_CS35L56_SPI in pending to avoid a mismatch (Justin M. Forbes) -- Linux v6.10.0-0.rc0.3c999d1ae3c7 -Resolves: - -* Wed May 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.1b294a1f3561.4] - Fix up a mismatch for RHEL (Justin M. Forbes) -- Linux v6.10.0-0.rc0.1b294a1f3561 -Resolves: - -* Wed May 15 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.a5131c3fdf26.3] - Reset changelog after rebase (Justin M. Forbes) -Resolves: - -* Tue May 14 2024 Fedora Kernel Team <kernel-team@fedoraproject.org> [6.10.0-0.rc0.a5131c3fdf26.2] - Reset RHEL_RELEASE to 0 for 6.10 (Justin M. Forbes) - configs: move CONFIG_BLK_DEV_UBLK into rhel/configs/generic (Ming Lei) - configs: move CONFIG_BLK_SED_OPAL into redhat/configs/common/generic (Ming Lei) @@ -2755,5 +2787,5 @@ Resolves: - [initial commit] Add scripts (Laura Abbott) - [initial commit] Add configs (Laura Abbott) - [initial commit] Add Makefiles (Laura Abbott) -- Linux v6.10.0-0.rc0.a5131c3fdf26 -Resolves: RHEL-23931, RHEL-32110, rhbz#1471185, rhbz#1495307, rhbz#1509329, rhbz#1518076, rhbz#1518874, rhbz#1519554, rhbz#1546831, rhbz#1559877, rhbz#1561171, rhbz#1563590, rhbz#1565704, rhbz#1565717, rhbz#1572321, rhbz#1574502, rhbz#1590829, rhbz#1595918, rhbz#1598366, rhbz#1602033, rhbz#1609604, rhbz#1610493, rhbz#1613522, rhbz#1638087, rhbz#1652256, rhbz#1652266, rhbz#1663728, rhbz#1670017, rhbz#1722136, rhbz#1730649, rhbz#1802694, rhbz#1810301, rhbz#1821565, rhbz#1831065, rhbz#1855161, rhbz#1856174, rhbz#1856176, rhbz#1858592, rhbz#1858594, rhbz#1858596, rhbz#1858599, rhbz#1869674, rhbz#1871130, rhbz#1876435, rhbz#1876436, rhbz#1876977, rhbz#1877192, rhbz#1880486, rhbz#1890304, rhbz#1903201, rhbz#1915073, rhbz#1915290, rhbz#1930649, rhbz#1939095, rhbz#1940075, rhbz#1940794, rhbz#1943423, rhbz#1945002, rhbz#1945179, rhbz#1945477, rhbz#1947240, rhbz#1948340, rhbz#1952426, rhbz#1952863, rhbz#1953486, rhbz#1956988, rhbz#1957210, rhbz#1957219, rhbz#1957305, rhbz#1957636, rhbz#1957819, rhbz#1961178, rhbz#1962936, rhbz#1964537, rhbz#1967640, rhbz#1972795, rhbz#1976270, rhbz#1976835, rhbz#1976877, rhbz#1976884, rhbz#1977056, rhbz#1977529, rhbz#1978539, rhbz#1979379, rhbz#1981406, rhbz#1983298, rhbz#1986223, rhbz#1988254, rhbz#1988384, rhbz#1990040, rhbz#1993393, rhbz#1994858, rhbz#1998953, rhbz#2000835, rhbz#2002344, rhbz#2004233, rhbz#2004821, rhbz#2006813, rhbz#2007430, rhbz#2012226, rhbz#2014492, rhbz#2019377, rhbz#2020132, rhbz#2022578, rhbz#2023782, rhbz#2024595, rhbz#2025985, rhbz#2026319, rhbz#2027506, rhbz#2031547, rhbz#2032758, rhbz#2034670, rhbz#2038999, rhbz#2040643, rhbz#2041184, rhbz#2041186, rhbz#2041365, rhbz#2041990, rhbz#2042240, rhbz#2042241, rhbz#2043141, rhbz#2044155, rhbz#2053836, rhbz#2054579, rhbz#2062054, rhbz#2062909, rhbz#2071969, rhbz#2089765, rhbz#2115876, rhbz#2120968, rhbz#2122595, rhbz#2140017, rhbz#2142658, rhbz#2149273, rhbz#2153073, rhbz#2166911, rhbz#2188441, rhbz#2208834, rhbz#2216678, rhbz#2227793, rhbz#2231407, rhbz#2233269 +- Linux v6.11.0-0.rc0.d67978318827 +Resolves: RHEL-23931, RHEL-32110, RHEL-32895, RHEL-32987, RHEL-36646, RHEL-36647, RHEL-40251, RHEL-40411, RHEL-41231, RHEL-43556, rhbz#1471185, rhbz#1495307, rhbz#1509329, rhbz#1518076, rhbz#1518874, rhbz#1519554, rhbz#1546831, rhbz#1559877, rhbz#1561171, rhbz#1563590, rhbz#1565704, rhbz#1565717, rhbz#1572321, rhbz#1574502, rhbz#1590829, rhbz#1595918, rhbz#1598366, rhbz#1602033, rhbz#1609604, rhbz#1610493, rhbz#1613522, rhbz#1638087, rhbz#1652256, rhbz#1652266, rhbz#1663728, rhbz#1670017, rhbz#1722136, rhbz#1730649, rhbz#1802694, rhbz#1810301, rhbz#1821565, rhbz#1831065, rhbz#1855161, rhbz#1856174, rhbz#1856176, rhbz#1858592, rhbz#1858594, rhbz#1858596, rhbz#1858599, rhbz#1869674, rhbz#1871130, rhbz#1876435, rhbz#1876436, rhbz#1876977, rhbz#1877192, rhbz#1880486, rhbz#1890304, rhbz#1903201, rhbz#1915073, rhbz#1915290, rhbz#1930649, rhbz#1939095, rhbz#1940075, rhbz#1940794, rhbz#1943423, rhbz#1945002, rhbz#1945179, rhbz#1945477, rhbz#1947240, rhbz#1948340, rhbz#1952426, rhbz#1952863, rhbz#1953486, rhbz#1956988, rhbz#1957210, rhbz#1957219, rhbz#1957305, rhbz#1957636, rhbz#1957819, rhbz#1961178, rhbz#1962936, rhbz#1964537, rhbz#1967640, rhbz#1972795, rhbz#1976270, rhbz#1976835, rhbz#1976877, rhbz#1976884, rhbz#1977056, rhbz#1977529, rhbz#1978539, rhbz#1979379, rhbz#1981406, rhbz#1983298, rhbz#1986223, rhbz#1988254, rhbz#1988384, rhbz#1990040, rhbz#1993393, rhbz#1994858, rhbz#1998953, rhbz#2000835, rhbz#2002344, rhbz#2004233, rhbz#2004821, rhbz#2006813, rhbz#2007430, rhbz#2012226, rhbz#2014492, rhbz#2019377, rhbz#2020132, rhbz#2022578, rhbz#2023782, rhbz#2024595, rhbz#2025985, rhbz#2026319, rhbz#2027506, rhbz#2031547, rhbz#2032758, rhbz#2034670, rhbz#2038999, rhbz#2040643, rhbz#2041184, rhbz#2041186, rhbz#2041365, rhbz#2041990, rhbz#2042240, rhbz#2042241, rhbz#2043141, rhbz#2044155, rhbz#2053836, rhbz#2054579, rhbz#2062054, rhbz#2062909, rhbz#2071969, rhbz#2089765, rhbz#2115876, rhbz#2120968, rhbz#2122595, rhbz#2140017, rhbz#2142658, rhbz#2149273, rhbz#2153073, rhbz#2166911, rhbz#2188441, rhbz#2208834, rhbz#2216678, rhbz#2227793, rhbz#2231407, rhbz#2233269 diff --git a/SOURCES/lenovo-legion-laptop.patch b/SOURCES/lenovo-legion-laptop.patch index 6faae9b..cff38b0 100644 --- a/SOURCES/lenovo-legion-laptop.patch +++ b/SOURCES/lenovo-legion-laptop.patch @@ -49,7 +49,7 @@ new file mode 100644 index 000000000..5ec0a518f --- /dev/null +++ b/drivers/platform/x86/legion-laptop.c -@@ -0,0 +1,6089 @@ +@@ -0,0 +1,6088 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * legion-laptop.c - Extra Lenovo Legion laptop support, in @@ -6047,7 +6047,7 @@ index 000000000..5ec0a518f + return err; +} + -+static int legion_remove(struct platform_device *pdev) ++static void legion_remove(struct platform_device *pdev) +{ + struct legion_private *priv = dev_get_drvdata(&pdev->dev); + @@ -6075,7 +6075,6 @@ index 000000000..5ec0a518f + legion_shared_exit(priv); + + pr_info("Legion platform unloaded\n"); -+ return 0; +} + +static int legion_resume(struct platform_device *pdev) @@ -6139,6 +6138,3 @@ index 000000000..5ec0a518f +} + +module_exit(legion_exit); --- -2.43.2 - diff --git a/SOURCES/linux-surface.patch b/SOURCES/linux-surface.patch index 9d19868..7219718 100644 --- a/SOURCES/linux-surface.patch +++ b/SOURCES/linux-surface.patch @@ -1,4 +1,4 @@ -From 2dd7c57b604b7cae49efcebc5fb6e46f7401a69b Mon Sep 17 00:00:00 2001 +From 3072491a57e495f0c1cea7d177f23b7e1b2dce4f Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sun, 9 Jun 2024 19:48:58 +0200 Subject: [PATCH] Revert "efi/x86: Set the PE/COFF header's NX compat flag @@ -35,7 +35,7 @@ index b5c79f43359b..a1bbedd989e4 100644 -- 2.46.1 -From 8c63d9f68dff804be41fcf71b725a1e28c78118f Mon Sep 17 00:00:00 2001 +From 5c2e6c9e2424f940b98ac772b9e8c6bae07563c9 Mon Sep 17 00:00:00 2001 From: "J. Eduardo" <j.eduardo@gmail.com> Date: Sun, 25 Aug 2024 14:17:45 +0200 Subject: [PATCH] PM: hibernate: Add a lockdown_hibernate parameter @@ -53,10 +53,10 @@ Patchset: secureboot 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt -index c82446cef8e2..2ae1a6fda7f9 100644 +index 09126bb8cc9f..d4203d40146e 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt -@@ -3000,6 +3000,11 @@ +@@ -3020,6 +3020,11 @@ to extract confidential information from the kernel are also disabled. @@ -110,7 +110,7 @@ index 0a213f69a9e4..8e4f9dcc9f4c 100644 -- 2.46.1 -From 3d3aec0cd78fd07d406486dd140daa7baf1fba7c Mon Sep 17 00:00:00 2001 +From 5e2a56c28a75458faee96311074a886d18df278e Mon Sep 17 00:00:00 2001 From: Tsuchiya Yuto <kitakar@gmail.com> Date: Sun, 18 Oct 2020 16:42:44 +0900 Subject: [PATCH] (surface3-oemb) add DMI matches for Surface 3 with broken DMI @@ -190,7 +190,7 @@ index 51187b1e0ed2..bfb83ce8d8f8 100644 /* * Match for the GPDwin which unfortunately uses somewhat diff --git a/sound/soc/intel/common/soc-acpi-intel-cht-match.c b/sound/soc/intel/common/soc-acpi-intel-cht-match.c -index 5e2ec60e2954..207868c699f2 100644 +index e4c3492a0c28..0b930c91bccb 100644 --- a/sound/soc/intel/common/soc-acpi-intel-cht-match.c +++ b/sound/soc/intel/common/soc-acpi-intel-cht-match.c @@ -27,6 +27,14 @@ static const struct dmi_system_id cht_table[] = { @@ -211,7 +211,7 @@ index 5e2ec60e2954..207868c699f2 100644 -- 2.46.1 -From a50739a5e7b0ca9f6bca85606f2b9389a9dd6bec Mon Sep 17 00:00:00 2001 +From d3dce7daa7c9b02fffc26ab4b001dd28bacc0354 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl> Date: Tue, 3 Nov 2020 13:28:04 +0100 Subject: [PATCH] mwifiex: Add quirk resetting the PCI bridge on MS Surface @@ -378,7 +378,7 @@ index d6ff964aec5b..5d30ae39d65e 100644 -- 2.46.1 -From 883ef69235ff8daa9653576dd6104460f60b7bde Mon Sep 17 00:00:00 2001 +From 9769338807b783cee28ff7bccbaa0e60c684be9f Mon Sep 17 00:00:00 2001 From: Tsuchiya Yuto <kitakar@gmail.com> Date: Sun, 4 Oct 2020 00:11:49 +0900 Subject: [PATCH] mwifiex: pcie: disable bridge_d3 for Surface gen4+ @@ -533,7 +533,7 @@ index 5d30ae39d65e..c14eb56eb911 100644 -- 2.46.1 -From 9e1720f0132e61bc6f738284080c6925941e1a91 Mon Sep 17 00:00:00 2001 +From f9801752d406cd308af5286c21bb27d946d3e9c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl> Date: Thu, 25 Mar 2021 11:33:02 +0100 Subject: [PATCH] Bluetooth: btusb: Lower passive lescan interval on Marvell @@ -569,7 +569,7 @@ Patchset: mwifiex 1 file changed, 15 insertions(+) diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c -index 0927f51867c2..3d3573829631 100644 +index 51d9d4532dda..e62c565ebc6d 100644 --- a/drivers/bluetooth/btusb.c +++ b/drivers/bluetooth/btusb.c @@ -65,6 +65,7 @@ static struct usb_driver btusb_driver; @@ -588,7 +588,7 @@ index 0927f51867c2..3d3573829631 100644 /* Intel Bluetooth devices */ { USB_DEVICE(0x8087, 0x0025), .driver_info = BTUSB_INTEL_COMBINED }, -@@ -4448,6 +4450,19 @@ static int btusb_probe(struct usb_interface *intf, +@@ -3856,6 +3858,19 @@ static int btusb_probe(struct usb_interface *intf, if (id->driver_info & BTUSB_MARVELL) hdev->set_bdaddr = btusb_set_bdaddr_marvell; @@ -611,7 +611,7 @@ index 0927f51867c2..3d3573829631 100644 -- 2.46.1 -From 68efac8fe5bd9af5e3c3e1d3cf7d9d2a3a5f4248 Mon Sep 17 00:00:00 2001 +From 137690d1fd93f0c5f723f1734e2b8db6709f806e Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 27 Feb 2021 00:45:52 +0100 Subject: [PATCH] ath10k: Add module parameters to override board files @@ -633,10 +633,10 @@ Patchset: ath10k 1 file changed, 57 insertions(+) diff --git a/drivers/net/wireless/ath/ath10k/core.c b/drivers/net/wireless/ath/ath10k/core.c -index bdf0552cd1c3..e062cc687689 100644 +index b3294287bce1..2936fdae823c 100644 --- a/drivers/net/wireless/ath/ath10k/core.c +++ b/drivers/net/wireless/ath/ath10k/core.c -@@ -39,6 +39,9 @@ static bool fw_diag_log; +@@ -40,6 +40,9 @@ static bool fw_diag_log; /* frame mode values are mapped as per enum ath10k_hw_txrx_mode */ unsigned int ath10k_frame_mode = ATH10K_HW_TXRX_NATIVE_WIFI; @@ -646,7 +646,7 @@ index bdf0552cd1c3..e062cc687689 100644 unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) | BIT(ATH10K_FW_CRASH_DUMP_CE_DATA); -@@ -51,6 +54,9 @@ module_param(fw_diag_log, bool, 0644); +@@ -52,6 +55,9 @@ module_param(fw_diag_log, bool, 0644); module_param_named(frame_mode, ath10k_frame_mode, uint, 0644); module_param_named(coredump_mask, ath10k_coredump_mask, ulong, 0444); @@ -656,7 +656,7 @@ index bdf0552cd1c3..e062cc687689 100644 MODULE_PARM_DESC(debug_mask, "Debugging mask"); MODULE_PARM_DESC(uart_print, "Uart target debugging"); MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode"); -@@ -60,6 +66,9 @@ MODULE_PARM_DESC(frame_mode, +@@ -61,6 +67,9 @@ MODULE_PARM_DESC(frame_mode, MODULE_PARM_DESC(coredump_mask, "Bitfield of what to include in firmware crash file"); MODULE_PARM_DESC(fw_diag_log, "Diag based fw log debugging"); @@ -666,7 +666,7 @@ index bdf0552cd1c3..e062cc687689 100644 static const struct ath10k_hw_params ath10k_hw_params_list[] = { { .id = QCA988X_HW_2_0_VERSION, -@@ -914,6 +923,42 @@ static int ath10k_init_configure_target(struct ath10k *ar) +@@ -931,6 +940,42 @@ static int ath10k_init_configure_target(struct ath10k *ar) return 0; } @@ -709,7 +709,7 @@ index bdf0552cd1c3..e062cc687689 100644 static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, const char *dir, const char *file) -@@ -928,6 +973,18 @@ static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, +@@ -945,6 +990,18 @@ static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar, if (dir == NULL) dir = "."; @@ -731,7 +731,7 @@ index bdf0552cd1c3..e062cc687689 100644 -- 2.46.1 -From 7e608ebdf188a298503111e503a4cc2fc3880f7c Mon Sep 17 00:00:00 2001 +From 349269d5e90409c3dd12e022da4771c6a66752b6 Mon Sep 17 00:00:00 2001 From: Dorian Stoll <dorian.stoll@tmsp.io> Date: Thu, 30 Jul 2020 13:21:53 +0200 Subject: [PATCH] mei: me: Add Icelake device ID for iTouch @@ -770,7 +770,7 @@ index 6589635f8ba3..a1df48a434e2 100644 -- 2.46.1 -From 8b12cf7a1fe199057c7a39087d233f62fd4d6a93 Mon Sep 17 00:00:00 2001 +From 9c052968302b202812f519f38839dd00d3621795 Mon Sep 17 00:00:00 2001 From: Liban Hannan <liban.p@gmail.com> Date: Tue, 12 Apr 2022 23:31:12 +0100 Subject: [PATCH] iommu: Use IOMMU passthrough mode for IPTS @@ -794,7 +794,7 @@ Patchset: ipts 1 file changed, 29 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c -index e9bea0305c26..6ee97bf7b6a9 100644 +index 4aa070cf56e7..5df658b9811b 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -40,6 +40,11 @@ @@ -824,7 +824,7 @@ index e9bea0305c26..6ee97bf7b6a9 100644 const struct iommu_ops intel_iommu_ops; static const struct iommu_dirty_ops intel_dirty_ops; -@@ -2195,6 +2202,9 @@ static int device_def_domain_type(struct device *dev) +@@ -2156,6 +2163,9 @@ static int device_def_domain_type(struct device *dev) if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) return IOMMU_DOMAIN_IDENTITY; @@ -834,7 +834,7 @@ index e9bea0305c26..6ee97bf7b6a9 100644 } return 0; -@@ -2495,6 +2505,9 @@ static int __init init_dmars(void) +@@ -2456,6 +2466,9 @@ static int __init init_dmars(void) iommu_set_root_entry(iommu); } @@ -844,7 +844,7 @@ index e9bea0305c26..6ee97bf7b6a9 100644 check_tylersburg_isoch(); ret = si_domain_init(hw_pass_through); -@@ -4617,6 +4630,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev) +@@ -4699,6 +4712,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev) disable_igfx_iommu = 1; } @@ -863,7 +863,7 @@ index e9bea0305c26..6ee97bf7b6a9 100644 /* G4x/GM45 integrated gfx dmar support is totally busted. */ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2a40, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e00, quirk_iommu_igfx); -@@ -4652,6 +4677,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx); +@@ -4734,6 +4759,10 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx); @@ -877,7 +877,7 @@ index e9bea0305c26..6ee97bf7b6a9 100644 -- 2.46.1 -From fd63fc042c6554c75134e4dab8e4a1d74c495d05 Mon Sep 17 00:00:00 2001 +From 4d098196ff771e07ce301632377779c94dfa7cb4 Mon Sep 17 00:00:00 2001 From: Dorian Stoll <dorian.stoll@tmsp.io> Date: Sun, 11 Dec 2022 12:00:59 +0100 Subject: [PATCH] hid: Add support for Intel Precise Touch and Stylus @@ -955,10 +955,10 @@ index 08446c89eff6..ccddfba86004 100644 + endif # HID_SUPPORT diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile -index ce71b53ea6c5..de41081b6a5a 100644 +index e40f1ddebbb7..bdb17cffca2f 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile -@@ -171,3 +171,5 @@ obj-$(INTEL_ISH_FIRMWARE_DOWNLOADER) += intel-ish-hid/ +@@ -169,3 +169,5 @@ obj-$(INTEL_ISH_FIRMWARE_DOWNLOADER) += intel-ish-hid/ obj-$(CONFIG_AMD_SFH_HID) += amd-sfh-hid/ obj-$(CONFIG_SURFACE_HID_CORE) += surface-hid/ @@ -3972,7 +3972,7 @@ index 000000000000..1f966b8b32c4 -- 2.46.1 -From dc65c76763207057a6797b0ef844c3f58e6a6e15 Mon Sep 17 00:00:00 2001 +From 153d9fcfbe1cd5765470d42ae7aa82825dc9ffc3 Mon Sep 17 00:00:00 2001 From: Dorian Stoll <dorian.stoll@tmsp.io> Date: Sun, 11 Dec 2022 12:03:38 +0100 Subject: [PATCH] iommu: intel: Disable source id verification for ITHC @@ -3984,7 +3984,7 @@ Patchset: ithc 1 file changed, 16 insertions(+) diff --git a/drivers/iommu/intel/irq_remapping.c b/drivers/iommu/intel/irq_remapping.c -index e4a70886678c..961a33b87c24 100644 +index e090ca07364b..e575193615bf 100644 --- a/drivers/iommu/intel/irq_remapping.c +++ b/drivers/iommu/intel/irq_remapping.c @@ -389,6 +389,22 @@ static int set_msi_sid(struct irte *irte, struct pci_dev *dev) @@ -4013,7 +4013,7 @@ index e4a70886678c..961a33b87c24 100644 -- 2.46.1 -From c3ddc02f7b0e27c09233022d7bbfd6b72ca12d2e Mon Sep 17 00:00:00 2001 +From e3fd5a2f58e174fab58d777ad43a2fb378e58ce9 Mon Sep 17 00:00:00 2001 From: quo <tuple@list.ru> Date: Sun, 11 Dec 2022 12:10:54 +0100 Subject: [PATCH] hid: Add support for Intel Touch Host Controller @@ -4071,10 +4071,10 @@ index ccddfba86004..8e2ea8175bfb 100644 + endif # HID_SUPPORT diff --git a/drivers/hid/Makefile b/drivers/hid/Makefile -index de41081b6a5a..9d156f1b3910 100644 +index bdb17cffca2f..8987177f8b81 100644 --- a/drivers/hid/Makefile +++ b/drivers/hid/Makefile -@@ -173,3 +173,4 @@ obj-$(CONFIG_AMD_SFH_HID) += amd-sfh-hid/ +@@ -171,3 +171,4 @@ obj-$(CONFIG_AMD_SFH_HID) += amd-sfh-hid/ obj-$(CONFIG_SURFACE_HID_CORE) += surface-hid/ obj-$(CONFIG_HID_IPTS) += ipts/ @@ -6743,7 +6743,7 @@ index 000000000000..aec320d4e945 -- 2.46.1 -From 3e6733db885b3a91339039897cbf0f3e05cda2a5 Mon Sep 17 00:00:00 2001 +From 046b4dd2291ee2e379f529037eab24d6b0cee56e Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 30 Dec 2023 18:07:54 +0100 Subject: [PATCH] hwmon: Add thermal sensor driver for Surface Aggregator @@ -6765,10 +6765,10 @@ Patchset: surface-sam create mode 100644 drivers/hwmon/surface_temp.c diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig -index e14ae18a973b..76eabe3e4435 100644 +index b60fe2e58ad6..70c6385f0ed6 100644 --- a/drivers/hwmon/Kconfig +++ b/drivers/hwmon/Kconfig -@@ -2093,6 +2093,16 @@ config SENSORS_SURFACE_FAN +@@ -2080,6 +2080,16 @@ config SENSORS_SURFACE_FAN Select M or Y here, if you want to be able to read the fan's speed. @@ -6786,11 +6786,11 @@ index e14ae18a973b..76eabe3e4435 100644 tristate "Texas Instruments ADC128D818" depends on I2C diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile -index e3f25475d1f0..eff74ab7f720 100644 +index b1c7056c37db..3ce8d6a9202e 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile -@@ -209,6 +209,7 @@ obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o - obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o +@@ -209,6 +209,7 @@ obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o + obj-$(CONFIG_SENSORS_SPD5118) += spd5118.o obj-$(CONFIG_SENSORS_STTS751) += stts751.o obj-$(CONFIG_SENSORS_SURFACE_FAN)+= surface_fan.o +obj-$(CONFIG_SENSORS_SURFACE_TEMP)+= surface_temp.o @@ -6971,7 +6971,7 @@ index 000000000000..48c3e826713f -- 2.46.1 -From 3e4479ac556ff21b45485822edb0980bbb27fdba Mon Sep 17 00:00:00 2001 +From e8afedc65f5b36c2e2845e7b5848750785512817 Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 30 Dec 2023 18:12:23 +0100 Subject: [PATCH] hwmon: surface_temp: Add support for sensor names @@ -7166,7 +7166,7 @@ index 48c3e826713f..4c08926139db 100644 -- 2.46.1 -From 134830c02674d93c2433bb898de34d1b84467f86 Mon Sep 17 00:00:00 2001 +From 3f6a1691ef17be41dcf06a10d9f61f8f782c89eb Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 25 Jul 2020 17:19:53 +0200 Subject: [PATCH] i2c: acpi: Implement RawBytes read access @@ -7277,7 +7277,7 @@ index 14ae0cfc325e..6197c5252d2a 100644 -- 2.46.1 -From 61af2c864646d5582463f9e5fbf06a96e0c4300d Mon Sep 17 00:00:00 2001 +From 2e305391186160d0098b014174322fc7bf80f778 Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 13 Feb 2021 16:41:18 +0100 Subject: [PATCH] platform/surface: Add driver for Surface Book 1 dGPU switch @@ -7474,7 +7474,7 @@ index 000000000000..68db237734a1 -- 2.46.1 -From 02f4deefe4c0ab63cd6771198cd05d5798fcc80f Mon Sep 17 00:00:00 2001 +From 0200cc75ca3e977b952b064efa6a1f1eb013b782 Mon Sep 17 00:00:00 2001 From: Sachi King <nakato@nakato.io> Date: Tue, 5 Oct 2021 00:05:09 +1100 Subject: [PATCH] Input: soc_button_array - support AMD variant Surface devices @@ -7496,7 +7496,7 @@ Patchset: surface-button 1 file changed, 8 insertions(+), 25 deletions(-) diff --git a/drivers/input/misc/soc_button_array.c b/drivers/input/misc/soc_button_array.c -index f6d060377d18..b8603f74eb28 100644 +index 5c5d407fe965..4e1bfe90e730 100644 --- a/drivers/input/misc/soc_button_array.c +++ b/drivers/input/misc/soc_button_array.c @@ -540,8 +540,8 @@ static const struct soc_device_data soc_device_MSHW0028 = { @@ -7551,7 +7551,7 @@ index f6d060377d18..b8603f74eb28 100644 -- 2.46.1 -From fbdda31b4a3ce2a7113fa831056830b6b46cf0df Mon Sep 17 00:00:00 2001 +From 193f349dc523cfb1d718c3f3f7f1a3e1152bb726 Mon Sep 17 00:00:00 2001 From: Sachi King <nakato@nakato.io> Date: Tue, 5 Oct 2021 00:22:57 +1100 Subject: [PATCH] platform/surface: surfacepro3_button: don't load on amd @@ -7623,7 +7623,7 @@ index 2755601f979c..4240c98ca226 100644 -- 2.46.1 -From edc26a9d993aca624b164989945d6bbcc5c7a856 Mon Sep 17 00:00:00 2001 +From 5685742814d25f3e7bf875d953edb3606cadf964 Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sat, 18 Feb 2023 01:02:49 +0100 Subject: [PATCH] USB: quirks: Add USB_QUIRK_DELAY_INIT for Surface Go 3 @@ -7664,7 +7664,7 @@ index 13171454f959..a83beefd25f3 100644 -- 2.46.1 -From 43bac5cac64c45b423509196acdb2261c3f0a7ba Mon Sep 17 00:00:00 2001 +From 996f946c80d5a28b533d2cb173faadf0421c05ae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonas=20Dre=C3=9Fler?= <verdre@v0yd.nl> Date: Thu, 5 Nov 2020 13:09:45 +0100 Subject: [PATCH] hid/multitouch: Turn off Type Cover keyboard backlight when @@ -7897,7 +7897,7 @@ index 99812c0f830b..0b3b51e37149 100644 -- 2.46.1 -From 41478ba3be0680c18610cb66f5344abadff1b82d Mon Sep 17 00:00:00 2001 +From 299f2254f1ea935f2f59c9150556dc6e26aa6ddb Mon Sep 17 00:00:00 2001 From: PJungkamp <p.jungkamp@gmail.com> Date: Fri, 25 Feb 2022 12:04:25 +0100 Subject: [PATCH] hid/multitouch: Add support for surface pro type cover tablet @@ -8196,7 +8196,7 @@ index 0b3b51e37149..481b97dce830 100644 -- 2.46.1 -From fe6c6b6e8d581aeca114902ec5f962a44a0ee3ff Mon Sep 17 00:00:00 2001 +From 90fe04d6368553e9f920dc9ab000460d0b592cfa Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sun, 19 Feb 2023 22:12:24 +0100 Subject: [PATCH] PCI: Add quirk to prevent calling shutdown mehtod @@ -8221,7 +8221,7 @@ Patchset: surface-shutdown 3 files changed, 40 insertions(+) diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c -index af2996d0d17f..3ce0fb61257d 100644 +index f412ef73a6e4..9892cd72dd2c 100644 --- a/drivers/pci/pci-driver.c +++ b/drivers/pci/pci-driver.c @@ -505,6 +505,9 @@ static void pci_device_shutdown(struct device *dev) @@ -8235,10 +8235,10 @@ index af2996d0d17f..3ce0fb61257d 100644 if (drv && drv->shutdown) diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 568410e64ce6..f59d8fb36335 100644 +index a2ce4e08edf5..18b80d14bdfb 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c -@@ -6273,3 +6273,39 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) +@@ -6277,3 +6277,39 @@ static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); #endif @@ -8279,10 +8279,10 @@ index 568410e64ce6..f59d8fb36335 100644 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x466d, quirk_no_shutdown); // Thunderbolt 4 NHI +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x46a8, quirk_no_shutdown); // GPU diff --git a/include/linux/pci.h b/include/linux/pci.h -index cafc5ab1cbcb..64bb5aca2c13 100644 +index 4cf89a4b4cbc..bb633c76d3a5 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h -@@ -465,6 +465,7 @@ struct pci_dev { +@@ -466,6 +466,7 @@ struct pci_dev { unsigned int no_command_memory:1; /* No PCI_COMMAND_MEMORY */ unsigned int rom_bar_overlap:1; /* ROM BAR disable broken */ unsigned int rom_attr_enabled:1; /* Display of ROM attribute enabled? */ @@ -8293,7 +8293,7 @@ index cafc5ab1cbcb..64bb5aca2c13 100644 -- 2.46.1 -From d0443743ccc9c4d76192f7bbf0152990e461945e Mon Sep 17 00:00:00 2001 +From 27ed0b03b6cfdbc60743f77b546fe4f157a1d512 Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Sun, 12 Mar 2023 01:41:57 +0100 Subject: [PATCH] platform/surface: gpe: Add support for Surface Pro 9 @@ -8344,7 +8344,7 @@ index 62fd4004db31..103fc4468262 100644 -- 2.46.1 -From e7b32369a9dc01221dc44a1250c425d8ebc9b28b Mon Sep 17 00:00:00 2001 +From 60b2e713e86789d7d6f7f28a46f8fa32c181a56a Mon Sep 17 00:00:00 2001 From: Hans de Goede <hdegoede@redhat.com> Date: Sun, 10 Oct 2021 20:56:57 +0200 Subject: [PATCH] ACPI: delay enumeration of devices with a _DEP pointing to an @@ -8404,10 +8404,10 @@ Patchset: cameras 1 file changed, 3 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c -index cdc5a74092c7..e3a16c14a29e 100644 +index 22ae7829a915..0fe281280316 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c -@@ -2176,6 +2176,9 @@ static acpi_status acpi_bus_check_add_2(acpi_handle handle, u32 lvl_not_used, +@@ -2185,6 +2185,9 @@ static acpi_status acpi_bus_check_add_2(acpi_handle handle, u32 lvl_not_used, static void acpi_default_enumeration(struct acpi_device *device) { @@ -8420,7 +8420,7 @@ index cdc5a74092c7..e3a16c14a29e 100644 -- 2.46.1 -From aa71d469b9000984bfbd4ee4f596517db89bcb46 Mon Sep 17 00:00:00 2001 +From a06834b1abe43c0afbb5f4a1e1a1e85f249cab18 Mon Sep 17 00:00:00 2001 From: zouxiaoh <xiaohong.zou@intel.com> Date: Fri, 25 Jun 2021 08:52:59 +0800 Subject: [PATCH] iommu: intel-ipu: use IOMMU passthrough mode for Intel IPUs @@ -8446,7 +8446,7 @@ Patchset: cameras 1 file changed, 30 insertions(+) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c -index 6ee97bf7b6a9..a1f86bde277a 100644 +index 5df658b9811b..7e3c58c872a7 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -45,6 +45,13 @@ @@ -8478,7 +8478,7 @@ index 6ee97bf7b6a9..a1f86bde277a 100644 #define IDENTMAP_IPTS 16 const struct iommu_ops intel_iommu_ops; -@@ -2203,6 +2212,9 @@ static int device_def_domain_type(struct device *dev) +@@ -2164,6 +2173,9 @@ static int device_def_domain_type(struct device *dev) if ((iommu_identity_mapping & IDENTMAP_AZALIA) && IS_AZALIA(pdev)) return IOMMU_DOMAIN_IDENTITY; @@ -8488,7 +8488,7 @@ index 6ee97bf7b6a9..a1f86bde277a 100644 if ((iommu_identity_mapping & IDENTMAP_IPTS) && IS_IPTS(pdev)) return IOMMU_DOMAIN_IDENTITY; } -@@ -2505,6 +2517,9 @@ static int __init init_dmars(void) +@@ -2466,6 +2478,9 @@ static int __init init_dmars(void) iommu_set_root_entry(iommu); } @@ -8498,7 +8498,7 @@ index 6ee97bf7b6a9..a1f86bde277a 100644 if (!dmar_map_ipts) iommu_identity_mapping |= IDENTMAP_IPTS; -@@ -4630,6 +4645,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev) +@@ -4712,6 +4727,18 @@ static void quirk_iommu_igfx(struct pci_dev *dev) disable_igfx_iommu = 1; } @@ -8517,7 +8517,7 @@ index 6ee97bf7b6a9..a1f86bde277a 100644 static void quirk_iommu_ipts(struct pci_dev *dev) { if (!IS_IPTS(dev)) -@@ -4677,6 +4704,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx); +@@ -4759,6 +4786,9 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1632, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163A, quirk_iommu_igfx); DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x163D, quirk_iommu_igfx); @@ -8530,7 +8530,7 @@ index 6ee97bf7b6a9..a1f86bde277a 100644 -- 2.46.1 -From fb1981ea8427c311f08860ddbb2ea1b7e1ddd313 Mon Sep 17 00:00:00 2001 +From 11ccfff2684694956fb2156f8216c1275a6bd97d Mon Sep 17 00:00:00 2001 From: Daniel Scally <djrscally@gmail.com> Date: Sun, 10 Oct 2021 20:57:02 +0200 Subject: [PATCH] platform/x86: int3472: Enable I2c daisy chain @@ -8567,7 +8567,7 @@ index 1e107fd49f82..e3e1696e7f0e 100644 -- 2.46.1 -From ae05619486ea72603af63628e7f7a0c3b4f045ac Mon Sep 17 00:00:00 2001 +From 469d8067637b158a501d8fa221cf7f922c021345 Mon Sep 17 00:00:00 2001 From: Daniel Scally <dan.scally@ideasonboard.com> Date: Thu, 2 Mar 2023 12:59:39 +0000 Subject: [PATCH] platform/x86: int3472: Remap reset GPIO for INT347E @@ -8623,7 +8623,7 @@ index 07b302e09340..baad1e50ca81 100644 -- 2.46.1 -From 7066acd9423a7eecc94d22397095e04f4a47aba8 Mon Sep 17 00:00:00 2001 +From 7a741f318b87a42d351d142512d55f0407a7e9e3 Mon Sep 17 00:00:00 2001 From: Daniel Scally <dan.scally@ideasonboard.com> Date: Tue, 21 Mar 2023 13:45:26 +0000 Subject: [PATCH] media: i2c: Clarify that gain is Analogue gain in OV7251 @@ -8662,7 +8662,7 @@ index 30f61e04ecaf..9c1292ca8552 100644 -- 2.46.1 -From 9feb537c1c69e0d01ad3ed713959fcf371dc2db6 Mon Sep 17 00:00:00 2001 +From 8baca29ff57339999c716555b4f1d961abbec3b2 Mon Sep 17 00:00:00 2001 From: Daniel Scally <dan.scally@ideasonboard.com> Date: Wed, 22 Mar 2023 11:01:42 +0000 Subject: [PATCH] media: v4l2-core: Acquire privacy led in @@ -8681,10 +8681,10 @@ Patchset: cameras 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/media/v4l2-core/v4l2-async.c b/drivers/media/v4l2-core/v4l2-async.c -index c477723c07bf..83413048eb35 100644 +index ee884a8221fb..4f6bafd900ee 100644 --- a/drivers/media/v4l2-core/v4l2-async.c +++ b/drivers/media/v4l2-core/v4l2-async.c -@@ -795,6 +795,10 @@ int __v4l2_async_register_subdev(struct v4l2_subdev *sd, struct module *module) +@@ -799,6 +799,10 @@ int __v4l2_async_register_subdev(struct v4l2_subdev *sd, struct module *module) INIT_LIST_HEAD(&sd->asc_list); @@ -8696,7 +8696,7 @@ index c477723c07bf..83413048eb35 100644 * No reference taken. The reference is held by the device (struct * v4l2_subdev.dev), and async sub-device does not exist independently diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c -index 89c7192148df..44eca113e772 100644 +index f19c8adf2c61..923ed1b5ab8b 100644 --- a/drivers/media/v4l2-core/v4l2-fwnode.c +++ b/drivers/media/v4l2-core/v4l2-fwnode.c @@ -1219,10 +1219,6 @@ int v4l2_async_register_subdev_sensor(struct v4l2_subdev *sd) @@ -8713,7 +8713,7 @@ index 89c7192148df..44eca113e772 100644 -- 2.46.1 -From 580ca92681c7c6bafa132b81043fbd0857b5da6b Mon Sep 17 00:00:00 2001 +From fbcac39c13e09ce4cc8ad3d4520fd03863eb52f0 Mon Sep 17 00:00:00 2001 From: Kate Hsuan <hpa@redhat.com> Date: Tue, 21 Mar 2023 23:37:16 +0800 Subject: [PATCH] platform: x86: int3472: Add MFD cell for tps68470 LED @@ -8754,7 +8754,7 @@ index e3e1696e7f0e..423dc555093f 100644 -- 2.46.1 -From ef863c4385da78967765505ccd3702371a32d70e Mon Sep 17 00:00:00 2001 +From 8bbe05d964175fdebb1cd0693aade238df967362 Mon Sep 17 00:00:00 2001 From: Kate Hsuan <hpa@redhat.com> Date: Tue, 21 Mar 2023 23:37:17 +0800 Subject: [PATCH] include: mfd: tps68470: Add masks for LEDA and LEDB @@ -8795,7 +8795,7 @@ index 7807fa329db0..2d2abb25b944 100644 -- 2.46.1 -From e81fa0ec83149cf15d779fea0ba7435f8fd28898 Mon Sep 17 00:00:00 2001 +From 8776136058fe2e8b5b1edaab6693448b37fa219d Mon Sep 17 00:00:00 2001 From: Kate Hsuan <hpa@redhat.com> Date: Tue, 21 Mar 2023 23:37:18 +0800 Subject: [PATCH] leds: tps68470: Add LED control for tps68470 @@ -8818,10 +8818,10 @@ Patchset: cameras create mode 100644 drivers/leds/leds-tps68470.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig -index 05e6af88b88c..c120eb0b5aa8 100644 +index 8d9d8da376e4..d8597897aa83 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig -@@ -909,6 +909,18 @@ config LEDS_TPS6105X +@@ -933,6 +933,18 @@ config LEDS_TPS6105X It is a single boost converter primarily for white LEDs and audio amplifiers. @@ -8841,10 +8841,10 @@ index 05e6af88b88c..c120eb0b5aa8 100644 tristate "LED support for SGI Octane machines" depends on LEDS_CLASS diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile -index effdfc6f1e95..6ce609b2cdac 100644 +index 18afbb5a23ee..a1d16c0af82d 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile -@@ -86,6 +86,7 @@ obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o +@@ -88,6 +88,7 @@ obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o obj-$(CONFIG_LEDS_TI_LMU_COMMON) += leds-ti-lmu-common.o obj-$(CONFIG_LEDS_TLC591XX) += leds-tlc591xx.o obj-$(CONFIG_LEDS_TPS6105X) += leds-tps6105x.o @@ -9046,7 +9046,7 @@ index 000000000000..35aeb5db89c8 -- 2.46.1 -From afce9fb83bf7355d5ceb4a6958023dd07e00cfdf Mon Sep 17 00:00:00 2001 +From 6e4b702fd02830ba9de5ac4fbb2eae53b02aeedc Mon Sep 17 00:00:00 2001 From: mojyack <mojyack@gmail.com> Date: Sat, 3 Feb 2024 12:59:53 +0900 Subject: [PATCH] media: staging: ipu3-imgu: Fix multiple calls of s_stream on @@ -9093,7 +9093,7 @@ index 3df58eb3e882..81aff2d5d898 100644 -- 2.46.1 -From 10cc9e54fa6067a0c08dc4f2c0f5bf029e3a4ed1 Mon Sep 17 00:00:00 2001 +From 3a0e7fc61359fbfd0fef1b35579fa8f5039bb8a3 Mon Sep 17 00:00:00 2001 From: mojyack <mojyack@gmail.com> Date: Tue, 26 Mar 2024 05:55:44 +0900 Subject: [PATCH] media: i2c: dw9719: fix probe error on surface go 2 @@ -9125,7 +9125,7 @@ index c626ed845928..0094cfda57ea 100644 -- 2.46.1 -From 04f1ce03393e660c6275004e0ccda0f1e4481f8b Mon Sep 17 00:00:00 2001 +From 9d8082e995819cd474ea46b99e44f5e52f63818a Mon Sep 17 00:00:00 2001 From: Sachi King <nakato@nakato.io> Date: Sat, 29 May 2021 17:47:38 +1000 Subject: [PATCH] ACPI: Add quirk for Surface Laptop 4 AMD missing irq 7 @@ -9148,7 +9148,7 @@ Patchset: amd-gpio 1 file changed, 17 insertions(+) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c -index 4bf82dbd2a6b..7a8cb090c656 100644 +index 9f4618dcd704..639fa57b6398 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c @@ -22,6 +22,7 @@ @@ -9159,7 +9159,7 @@ index 4bf82dbd2a6b..7a8cb090c656 100644 #include <asm/e820/api.h> #include <asm/irqdomain.h> -@@ -1216,6 +1217,17 @@ static void __init mp_config_acpi_legacy_irqs(void) +@@ -1132,6 +1133,17 @@ static void __init mp_config_acpi_legacy_irqs(void) } } @@ -9177,7 +9177,7 @@ index 4bf82dbd2a6b..7a8cb090c656 100644 /* * Parse IOAPIC related entries in MADT * returns 0 on success, < 0 on error -@@ -1271,6 +1283,11 @@ static int __init acpi_parse_madt_ioapic_entries(void) +@@ -1187,6 +1199,11 @@ static int __init acpi_parse_madt_ioapic_entries(void) acpi_sci_ioapic_setup(acpi_gbl_FADT.sci_interrupt, 0, 0, acpi_gbl_FADT.sci_interrupt); @@ -9192,7 +9192,7 @@ index 4bf82dbd2a6b..7a8cb090c656 100644 -- 2.46.1 -From a05e3240a282702699117da0e657a46bc960a944 Mon Sep 17 00:00:00 2001 +From fc1eda8b7c4c5a183ba34d88a5778e68e49c59e5 Mon Sep 17 00:00:00 2001 From: Maximilian Luz <luzmaximilian@gmail.com> Date: Thu, 3 Jun 2021 14:04:26 +0200 Subject: [PATCH] ACPI: Add AMD 13" Surface Laptop 4 model to irq 7 override @@ -9207,10 +9207,10 @@ Patchset: amd-gpio 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c -index 7a8cb090c656..0faafc323e67 100644 +index 639fa57b6398..2449b256e19b 100644 --- a/arch/x86/kernel/acpi/boot.c +++ b/arch/x86/kernel/acpi/boot.c -@@ -1219,12 +1219,19 @@ static void __init mp_config_acpi_legacy_irqs(void) +@@ -1135,12 +1135,19 @@ static void __init mp_config_acpi_legacy_irqs(void) static const struct dmi_system_id surface_quirk[] __initconst = { { @@ -9234,7 +9234,7 @@ index 7a8cb090c656..0faafc323e67 100644 -- 2.46.1 -From 4e5c87c48625f80729705e6ca756b289dace0452 Mon Sep 17 00:00:00 2001 +From a45bcc81c1b1a9922d759de30798e9f3bd89f1ac Mon Sep 17 00:00:00 2001 From: "Bart Groeneveld | GPX Solutions B.V" <bart@gpxbv.nl> Date: Mon, 5 Dec 2022 16:08:46 +0100 Subject: [PATCH] acpi: allow usage of acpi_tad on HW-reduced platforms @@ -9257,10 +9257,10 @@ Patchset: rtc 1 file changed, 24 insertions(+), 12 deletions(-) diff --git a/drivers/acpi/acpi_tad.c b/drivers/acpi/acpi_tad.c -index 1d670dbe4d1d..71c9e375ca1c 100644 +index b831cb8e53dc..78bd0f926505 100644 --- a/drivers/acpi/acpi_tad.c +++ b/drivers/acpi/acpi_tad.c -@@ -432,6 +432,14 @@ static ssize_t caps_show(struct device *dev, struct device_attribute *attr, +@@ -433,6 +433,14 @@ static ssize_t caps_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RO(caps); @@ -9275,7 +9275,7 @@ index 1d670dbe4d1d..71c9e375ca1c 100644 static ssize_t ac_alarm_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { -@@ -480,15 +488,14 @@ static ssize_t ac_status_show(struct device *dev, struct device_attribute *attr, +@@ -481,15 +489,14 @@ static ssize_t ac_status_show(struct device *dev, struct device_attribute *attr, static DEVICE_ATTR_RW(ac_status); @@ -9294,7 +9294,7 @@ index 1d670dbe4d1d..71c9e375ca1c 100644 }; static ssize_t dc_alarm_store(struct device *dev, struct device_attribute *attr, -@@ -564,13 +571,18 @@ static void acpi_tad_remove(struct platform_device *pdev) +@@ -565,13 +572,18 @@ static void acpi_tad_remove(struct platform_device *pdev) pm_runtime_get_sync(dev); @@ -9315,7 +9315,7 @@ index 1d670dbe4d1d..71c9e375ca1c 100644 if (dd->capabilities & ACPI_TAD_DC_WAKE) { acpi_tad_disable_timer(dev, ACPI_TAD_DC_TIMER); acpi_tad_clear_status(dev, ACPI_TAD_DC_TIMER); -@@ -612,12 +624,6 @@ static int acpi_tad_probe(struct platform_device *pdev) +@@ -613,12 +625,6 @@ static int acpi_tad_probe(struct platform_device *pdev) goto remove_handler; } @@ -9328,7 +9328,7 @@ index 1d670dbe4d1d..71c9e375ca1c 100644 dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL); if (!dd) { ret = -ENOMEM; -@@ -648,6 +654,12 @@ static int acpi_tad_probe(struct platform_device *pdev) +@@ -649,6 +655,12 @@ static int acpi_tad_probe(struct platform_device *pdev) if (ret) goto fail; diff --git a/SOURCES/mt76:-mt7921:-Disable-powersave-features-by-default.patch b/SOURCES/mt76:-mt7921:-Disable-powersave-features-by-default.patch deleted file mode 100644 index a397014..0000000 --- a/SOURCES/mt76:-mt7921:-Disable-powersave-features-by-default.patch +++ /dev/null @@ -1,42 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jan200101 <sentrycraft123@gmail.com> -Date: Mon, 27 Nov 2023 15:25:48 +0100 -Subject: [PATCH] mt76: mt7921: Disable powersave features by default - -This brings WiFi latency down considerably and makes latency consistent by -disabling runtime PM and typical powersave features by default. The actual -power consumption difference is inconsequential on desktops and laptops, -while the performance difference is monumental. Latencies of 20+ ms are no -longer observed after this change, and the connection is much more stable. - -Signed-off-by: Jan200101 <sentrycraft123@gmail.com> ---- - drivers/net/wireless/mediatek/mt76/mt7921/init.c | 8 ++------ - 1 file changed, 2 insertions(+), 6 deletions(-) - -diff --git a/drivers/net/wireless/mediatek/mt76/mt7921/init.c b/drivers/net/wireless/mediatek/mt76/mt7921/init.c -index ff63f37f67d9..840b4c606c83 100644 ---- a/drivers/net/wireless/mediatek/mt76/mt7921/init.c -+++ b/drivers/net/wireless/mediatek/mt76/mt7921/init.c -@@ -220,12 +220,6 @@ int mt7921_register_device(struct mt792x_dev *dev) - dev->pm.idle_timeout = MT792x_PM_TIMEOUT; - dev->pm.stats.last_wake_event = jiffies; - dev->pm.stats.last_doze_event = jiffies; -- if (!mt76_is_usb(&dev->mt76)) { -- dev->pm.enable_user = true; -- dev->pm.enable = true; -- dev->pm.ds_enable_user = true; -- dev->pm.ds_enable = true; -- } - - if (!mt76_is_mmio(&dev->mt76)) - hw->extra_tx_headroom += MT_SDIO_TXD_SIZE + MT_SDIO_HDR_SIZE; -@@ -240,6 +234,8 @@ int mt7921_register_device(struct mt792x_dev *dev) - if (ret) - return ret; - -+ hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; -+ - hw->wiphy->reg_notifier = mt7921_regd_notifier; - dev->mphy.sband_2g.sband.ht_cap.cap |= - IEEE80211_HT_CAP_LDPC_CODING | diff --git a/SOURCES/partial-clang-debug-snip.config b/SOURCES/partial-clang-debug-snip.config index 19fa152..16523eb 100644 --- a/SOURCES/partial-clang-debug-snip.config +++ b/SOURCES/partial-clang-debug-snip.config @@ -1,3 +1,4 @@ # clang +# CONFIG_DRM_WERROR is not set CONFIG_KASAN_STACK=y # CONFIG_KMSAN is not set diff --git a/SOURCES/partial-clang-snip.config b/SOURCES/partial-clang-snip.config index 841c19d..5a90de8 100644 --- a/SOURCES/partial-clang-snip.config +++ b/SOURCES/partial-clang-snip.config @@ -1,3 +1,4 @@ # clang +# CONFIG_DRM_WERROR is not set # CONFIG_KASAN_STACK is not set # CONFIG_KMSAN is not set diff --git a/SOURCES/partial-clang_lto-aarch64-debug-snip.config b/SOURCES/partial-clang_lto-aarch64-debug-snip.config index 0178f37..ff106f3 100644 --- a/SOURCES/partial-clang_lto-aarch64-debug-snip.config +++ b/SOURCES/partial-clang_lto-aarch64-debug-snip.config @@ -1,3 +1,4 @@ # clang_lto +# CONFIG_DRM_WERROR is not set CONFIG_KASAN_STACK=y # CONFIG_KMSAN is not set diff --git a/SOURCES/partial-clang_lto-aarch64-snip.config b/SOURCES/partial-clang_lto-aarch64-snip.config index 9e30765..ebab7f7 100644 --- a/SOURCES/partial-clang_lto-aarch64-snip.config +++ b/SOURCES/partial-clang_lto-aarch64-snip.config @@ -1,4 +1,5 @@ # clang_lto +# CONFIG_DRM_WERROR is not set # CONFIG_KASAN_STACK is not set # CONFIG_KMSAN is not set CONFIG_LTO_CLANG_THIN=y diff --git a/SOURCES/partial-clang_lto-x86_64-debug-snip.config b/SOURCES/partial-clang_lto-x86_64-debug-snip.config index 0178f37..ff106f3 100644 --- a/SOURCES/partial-clang_lto-x86_64-debug-snip.config +++ b/SOURCES/partial-clang_lto-x86_64-debug-snip.config @@ -1,3 +1,4 @@ # clang_lto +# CONFIG_DRM_WERROR is not set CONFIG_KASAN_STACK=y # CONFIG_KMSAN is not set diff --git a/SOURCES/partial-clang_lto-x86_64-snip.config b/SOURCES/partial-clang_lto-x86_64-snip.config index 9e30765..ebab7f7 100644 --- a/SOURCES/partial-clang_lto-x86_64-snip.config +++ b/SOURCES/partial-clang_lto-x86_64-snip.config @@ -1,4 +1,5 @@ # clang_lto +# CONFIG_DRM_WERROR is not set # CONFIG_KASAN_STACK is not set # CONFIG_KMSAN is not set CONFIG_LTO_CLANG_THIN=y diff --git a/SOURCES/patch-6.10-redhat.patch b/SOURCES/patch-6.11-redhat.patch index bea7047..60f889c 100644 --- a/SOURCES/patch-6.10-redhat.patch +++ b/SOURCES/patch-6.11-redhat.patch @@ -1,70 +1,54 @@ - Documentation/virt/kvm/api.rst | 3 + - Makefile | 12 ++ - arch/arm/Kconfig | 4 +- + Makefile | 40 +++ + arch/arm/boot/dts/broadcom/bcm2837.dtsi | 2 +- arch/arm64/Kconfig | 2 +- - arch/powerpc/include/asm/kvm_host.h | 3 + - arch/powerpc/include/uapi/asm/kvm.h | 3 + - arch/powerpc/kvm/book3s_hv.c | 18 +++ - arch/powerpc/kvm/book3s_hv.h | 3 + - arch/powerpc/kvm/book3s_hv_nestedv2.c | 18 +++ + arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 16 ++ + arch/arm64/boot/dts/broadcom/Makefile | 1 + + arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts | 64 +++++ + arch/arm64/boot/dts/broadcom/bcm2712.dtsi | 283 +++++++++++++++++++++ + .../dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 67 +++++ arch/s390/include/asm/ipl.h | 1 + arch/s390/kernel/ipl.c | 5 + arch/s390/kernel/setup.c | 4 + - arch/x86/kernel/setup.c | 22 ++- - certs/extract-cert.c | 25 +--- - crypto/drbg.c | 18 ++- - crypto/rng.c | 149 ++++++++++++++++++--- - drivers/acpi/apei/hest.c | 8 ++ - drivers/acpi/irq.c | 17 ++- - drivers/acpi/scan.c | 9 ++ - drivers/ata/libahci.c | 18 +++ - drivers/char/ipmi/ipmi_dmi.c | 15 +++ - drivers/char/ipmi/ipmi_msghandler.c | 16 ++- - drivers/char/random.c | 122 +++++++++++++++++ + arch/x86/kernel/setup.c | 22 +- + certs/extract-cert.c | 25 +- + crypto/akcipher.c | 6 +- + crypto/dh.c | 25 ++ + crypto/seqiv.c | 15 +- + crypto/testmgr.c | 4 +- + drivers/acpi/apei/hest.c | 8 + + drivers/acpi/irq.c | 17 +- + drivers/acpi/scan.c | 9 + + drivers/ata/libahci.c | 18 ++ + drivers/char/ipmi/ipmi_dmi.c | 15 ++ + drivers/char/ipmi/ipmi_msghandler.c | 16 +- drivers/firmware/efi/Makefile | 1 + - drivers/firmware/efi/efi.c | 124 ++++++++++++----- - drivers/firmware/efi/secureboot.c | 38 ++++++ - drivers/hid/hid-rmi.c | 66 --------- - drivers/hwtracing/coresight/coresight-etm4x-core.c | 19 +++ - drivers/input/rmi4/rmi_driver.c | 124 ++++++++++------- - drivers/iommu/iommu.c | 22 +++ - drivers/media/pci/intel/ipu-bridge.c | 40 ++++-- - drivers/pci/quirks.c | 24 ++++ - drivers/scsi/sd.c | 10 ++ + drivers/firmware/efi/efi.c | 124 ++++++--- + drivers/firmware/efi/secureboot.c | 38 +++ + drivers/hid/hid-rmi.c | 66 ----- + drivers/hwtracing/coresight/coresight-etm4x-core.c | 19 ++ + drivers/input/rmi4/rmi_driver.c | 124 +++++---- + drivers/iommu/iommu.c | 22 ++ + drivers/media/platform/qcom/camss/camss-video.c | 6 - + drivers/media/platform/qcom/camss/camss.c | 5 +- + drivers/pci/quirks.c | 24 ++ + drivers/scsi/sd.c | 10 + drivers/usb/core/hub.c | 7 + - include/linux/crypto.h | 1 + - include/linux/efi.h | 22 ++- + include/linux/crypto.h | 2 + + include/linux/efi.h | 22 +- include/linux/lsm_hook_defs.h | 2 + - include/linux/random.h | 10 ++ include/linux/rmi.h | 1 + include/linux/security.h | 5 + kernel/module/signing.c | 9 +- - scripts/sign-file.c | 29 +--- + scripts/sign-file.c | 29 +-- scripts/tags.sh | 2 + security/integrity/platform_certs/load_uefi.c | 6 +- - security/lockdown/Kconfig | 13 ++ + security/lockdown/Kconfig | 13 + security/lockdown/lockdown.c | 1 + - security/security.c | 12 ++ - 47 files changed, 827 insertions(+), 256 deletions(-) + security/security.c | 12 + + 47 files changed, 974 insertions(+), 241 deletions(-) -diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst -index eec8df1dde06a..88f49dd10cd06 100644 ---- a/Documentation/virt/kvm/api.rst -+++ b/Documentation/virt/kvm/api.rst -@@ -2445,8 +2445,11 @@ registers, find a list below: - PPC KVM_REG_PPC_PSSCR 64 - PPC KVM_REG_PPC_DEC_EXPIRY 64 - PPC KVM_REG_PPC_PTCR 64 -+ PPC KVM_REG_PPC_HASHKEYR 64 -+ PPC KVM_REG_PPC_HASHPKEYR 64 - PPC KVM_REG_PPC_DAWR1 64 - PPC KVM_REG_PPC_DAWRX1 64 -+ PPC KVM_REG_PPC_DEXCR 64 - PPC KVM_REG_PPC_TM_GPR0 64 - ... - PPC KVM_REG_PPC_TM_GPR31 64 diff --git a/Makefile b/Makefile -index 93731d0b1a04a..81291ebb3aa4f 100644 +index 7bcf0c32ea5e..f2c0bc57ebaa 100644 --- a/Makefile +++ b/Makefile @@ -22,6 +22,18 @@ $(if $(filter __%, $(MAKECMDGOALS)), \ @@ -86,27 +70,66 @@ index 93731d0b1a04a..81291ebb3aa4f 100644 # We are using a recursive build, so we need to do a little thinking # to get the ordering right. # -diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig -index ee5115252aac4..7f3796df84041 100644 ---- a/arch/arm/Kconfig -+++ b/arch/arm/Kconfig -@@ -1224,9 +1224,9 @@ config HIGHMEM - If unsure, say n. - - config HIGHPTE -- bool "Allocate 2nd-level pagetables from highmem" if EXPERT -+ bool "Allocate 2nd-level pagetables from highmem" - depends on HIGHMEM -- default y -+ default n - help - The VM uses one page of physical memory for each page table. - For systems with a lot of processes, this can use a lot of +@@ -333,6 +345,17 @@ ifneq ($(filter install,$(MAKECMDGOALS)),) + endif + endif + ++# CKI/cross compilation hack ++# Do we need to rebuild scripts after cross compilation? ++# If kernel was cross-compiled, these scripts have arch of build host. ++REBUILD_SCRIPTS_FOR_CROSS:=0 ++ ++# Regenerating config with incomplete source tree will produce different ++# config options. Disable it. ++ifeq ($(REBUILD_SCRIPTS_FOR_CROSS),1) ++may-sync-config:= ++endif ++ + ifdef mixed-build + # =========================================================================== + # We're called with mixed targets (*config and build targets). +@@ -1849,6 +1872,23 @@ endif + + ifdef CONFIG_MODULES + ++scripts_build: ++ $(MAKE) $(build)=scripts/basic ++ $(MAKE) $(build)=scripts/mod ++ $(MAKE) $(build)=scripts scripts/module.lds ++ $(MAKE) $(build)=scripts scripts/unifdef ++ $(MAKE) $(build)=scripts ++ ++prepare_after_cross: ++ # disable STACK_VALIDATION to avoid building objtool ++ sed -i '/^CONFIG_STACK_VALIDATION/d' ./include/config/auto.conf || true ++ # build minimum set of scripts and resolve_btfids to allow building ++ # external modules ++ $(MAKE) KBUILD_EXTMOD="" M="" scripts_build V=1 ++ $(MAKE) -C tools/bpf/resolve_btfids ++ ++PHONY += prepare_after_cross scripts_build ++ + $(MODORDER): $(build-dir) + @: + +diff --git a/arch/arm/boot/dts/broadcom/bcm2837.dtsi b/arch/arm/boot/dts/broadcom/bcm2837.dtsi +index 84c08b46519d..c281697142b1 100644 +--- a/arch/arm/boot/dts/broadcom/bcm2837.dtsi ++++ b/arch/arm/boot/dts/broadcom/bcm2837.dtsi +@@ -9,7 +9,7 @@ soc { + <0x40000000 0x40000000 0x00001000>; + dma-ranges = <0xc0000000 0x00000000 0x3f000000>; + +- local_intc: local_intc@40000000 { ++ local_intc: interrupt-controller@40000000 { + compatible = "brcm,bcm2836-l1-intc"; + reg = <0x40000000 0x100>; + interrupt-controller; diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig -index cd9772b1fd95e..f3b3d8493c1c2 100644 +index c8cba20a4d11..40a1665236ab 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig -@@ -1364,7 +1364,7 @@ endchoice +@@ -1365,7 +1365,7 @@ endchoice config ARM64_FORCE_52BIT bool "Force 52-bit virtual addresses for userspace" @@ -115,122 +138,498 @@ index cd9772b1fd95e..f3b3d8493c1c2 100644 help For systems with 52-bit userspace VAs enabled, the kernel will attempt to maintain compatibility with older software by providing 48-bit VAs -diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h -index 8abac532146e7..6a0c771d3ce89 100644 ---- a/arch/powerpc/include/asm/kvm_host.h -+++ b/arch/powerpc/include/asm/kvm_host.h -@@ -599,6 +599,9 @@ struct kvm_vcpu_arch { - ulong dawrx0; - ulong dawr1; - ulong dawrx1; -+ ulong dexcr; -+ ulong hashkeyr; -+ ulong hashpkeyr; - ulong ciabr; - ulong cfar; - ulong ppr; -diff --git a/arch/powerpc/include/uapi/asm/kvm.h b/arch/powerpc/include/uapi/asm/kvm.h -index 1691297a766a9..eaeda001784eb 100644 ---- a/arch/powerpc/include/uapi/asm/kvm.h -+++ b/arch/powerpc/include/uapi/asm/kvm.h -@@ -645,6 +645,9 @@ struct kvm_ppc_cpu_char { - #define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) - #define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc4) - #define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc5) -+#define KVM_REG_PPC_DEXCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc6) -+#define KVM_REG_PPC_HASHKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc7) -+#define KVM_REG_PPC_HASHPKEYR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc8) - - /* Transactional Memory checkpointed state: - * This is all GPRs, all VSX regs and a subset of SPRs -diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c -index d8352e4d9cdc7..36068c3ed8a76 100644 ---- a/arch/powerpc/kvm/book3s_hv.c -+++ b/arch/powerpc/kvm/book3s_hv.c -@@ -2349,6 +2349,15 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, - case KVM_REG_PPC_DAWRX1: - *val = get_reg_val(id, kvmppc_get_dawrx1_hv(vcpu)); - break; -+ case KVM_REG_PPC_DEXCR: -+ *val = get_reg_val(id, kvmppc_get_dexcr_hv(vcpu)); -+ break; -+ case KVM_REG_PPC_HASHKEYR: -+ *val = get_reg_val(id, kvmppc_get_hashkeyr_hv(vcpu)); -+ break; -+ case KVM_REG_PPC_HASHPKEYR: -+ *val = get_reg_val(id, kvmppc_get_hashpkeyr_hv(vcpu)); -+ break; - case KVM_REG_PPC_CIABR: - *val = get_reg_val(id, kvmppc_get_ciabr_hv(vcpu)); - break; -@@ -2592,6 +2601,15 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id, - case KVM_REG_PPC_DAWRX1: - kvmppc_set_dawrx1_hv(vcpu, set_reg_val(id, *val) & ~DAWRX_HYP); - break; -+ case KVM_REG_PPC_DEXCR: -+ kvmppc_set_dexcr_hv(vcpu, set_reg_val(id, *val)); -+ break; -+ case KVM_REG_PPC_HASHKEYR: -+ kvmppc_set_hashkeyr_hv(vcpu, set_reg_val(id, *val)); -+ break; -+ case KVM_REG_PPC_HASHPKEYR: -+ kvmppc_set_hashpkeyr_hv(vcpu, set_reg_val(id, *val)); -+ break; - case KVM_REG_PPC_CIABR: - kvmppc_set_ciabr_hv(vcpu, set_reg_val(id, *val)); - /* Don't allow setting breakpoints in hypervisor code */ -diff --git a/arch/powerpc/kvm/book3s_hv.h b/arch/powerpc/kvm/book3s_hv.h -index 47b2c815641e4..a404c9b221c1a 100644 ---- a/arch/powerpc/kvm/book3s_hv.h -+++ b/arch/powerpc/kvm/book3s_hv.h -@@ -116,6 +116,9 @@ KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawr0, 64, KVMPPC_GSID_DAWR0) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawr1, 64, KVMPPC_GSID_DAWR1) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawrx0, 64, KVMPPC_GSID_DAWRX0) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dawrx1, 64, KVMPPC_GSID_DAWRX1) -+KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(dexcr, 64, KVMPPC_GSID_DEXCR) -+KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(hashkeyr, 64, KVMPPC_GSID_HASHKEYR) -+KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(hashpkeyr, 64, KVMPPC_GSID_HASHPKEYR) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(ciabr, 64, KVMPPC_GSID_CIABR) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(wort, 64, KVMPPC_GSID_WORT) - KVMPPC_BOOK3S_HV_VCPU_ACCESSOR(ppr, 64, KVMPPC_GSID_PPR) -diff --git a/arch/powerpc/kvm/book3s_hv_nestedv2.c b/arch/powerpc/kvm/book3s_hv_nestedv2.c -index 342f583147709..eeecea8f202b3 100644 ---- a/arch/powerpc/kvm/book3s_hv_nestedv2.c -+++ b/arch/powerpc/kvm/book3s_hv_nestedv2.c -@@ -193,6 +193,15 @@ static int gs_msg_ops_vcpu_fill_info(struct kvmppc_gs_buff *gsb, - case KVMPPC_GSID_DAWRX1: - rc = kvmppc_gse_put_u32(gsb, iden, vcpu->arch.dawrx1); - break; -+ case KVMPPC_GSID_DEXCR: -+ rc = kvmppc_gse_put_u64(gsb, iden, vcpu->arch.dexcr); -+ break; -+ case KVMPPC_GSID_HASHKEYR: -+ rc = kvmppc_gse_put_u64(gsb, iden, vcpu->arch.hashkeyr); -+ break; -+ case KVMPPC_GSID_HASHPKEYR: -+ rc = kvmppc_gse_put_u64(gsb, iden, vcpu->arch.hashpkeyr); -+ break; - case KVMPPC_GSID_CIABR: - rc = kvmppc_gse_put_u64(gsb, iden, vcpu->arch.ciabr); - break; -@@ -445,6 +454,15 @@ static int gs_msg_ops_vcpu_refresh_info(struct kvmppc_gs_msg *gsm, - case KVMPPC_GSID_DAWRX1: - vcpu->arch.dawrx1 = kvmppc_gse_get_u32(gse); - break; -+ case KVMPPC_GSID_DEXCR: -+ vcpu->arch.dexcr = kvmppc_gse_get_u64(gse); -+ break; -+ case KVMPPC_GSID_HASHKEYR: -+ vcpu->arch.hashkeyr = kvmppc_gse_get_u64(gse); -+ break; -+ case KVMPPC_GSID_HASHPKEYR: -+ vcpu->arch.hashpkeyr = kvmppc_gse_get_u64(gse); -+ break; - case KVMPPC_GSID_CIABR: - vcpu->arch.ciabr = kvmppc_gse_get_u64(gse); - break; +diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +index e868ca5ae753..a5c3920e0f04 100644 +--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi ++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +@@ -263,6 +263,14 @@ gpu0_thermal: gpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 1>; ++ ++ trips { ++ gpu0_crit: gpu0-crit { ++ temperature = <110000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; + }; + + gpu1_thermal: gpu1-thermal { +@@ -270,6 +278,14 @@ gpu1_thermal: gpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&ths 2>; ++ ++ trips { ++ gpu1_crit: gpu1-crit { ++ temperature = <110000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; + }; + }; + +diff --git a/arch/arm64/boot/dts/broadcom/Makefile b/arch/arm64/boot/dts/broadcom/Makefile +index 8b4591ddd27c..92565e9781ad 100644 +--- a/arch/arm64/boot/dts/broadcom/Makefile ++++ b/arch/arm64/boot/dts/broadcom/Makefile +@@ -6,6 +6,7 @@ DTC_FLAGS := -@ + dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rpi-400.dtb \ + bcm2711-rpi-4-b.dtb \ + bcm2711-rpi-cm4-io.dtb \ ++ bcm2712-rpi-5-b.dtb \ + bcm2837-rpi-3-a-plus.dtb \ + bcm2837-rpi-3-b.dtb \ + bcm2837-rpi-3-b-plus.dtb \ +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +new file mode 100644 +index 000000000000..2bdbb6780242 +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712-rpi-5-b.dts +@@ -0,0 +1,64 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++/dts-v1/; ++ ++#include <dt-bindings/gpio/gpio.h> ++#include "bcm2712.dtsi" ++ ++/ { ++ compatible = "raspberrypi,5-model-b", "brcm,bcm2712"; ++ model = "Raspberry Pi 5"; ++ ++ aliases { ++ serial10 = &uart10; ++ }; ++ ++ chosen: chosen { ++ stdout-path = "serial10:115200n8"; ++ }; ++ ++ /* Will be filled by the bootloader */ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0 0 0 0x28000000>; ++ }; ++ ++ sd_io_1v8_reg: sd-io-1v8-reg { ++ compatible = "regulator-gpio"; ++ regulator-name = "vdd-sd-io"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-settling-time-us = <5000>; ++ gpios = <&gio_aon 3 GPIO_ACTIVE_HIGH>; ++ states = <1800000 1>, ++ <3300000 0>; ++ }; ++ ++ sd_vcc_reg: sd-vcc-reg { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc-sd"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ enable-active-high; ++ gpios = <&gio_aon 4 GPIO_ACTIVE_HIGH>; ++ }; ++}; ++ ++/* The Debug UART, on Rpi5 it's on JST-SH 1.0mm 3-pin connector ++ * labeled "UART", i.e. the interface with the system console. ++ */ ++&uart10 { ++ status = "okay"; ++}; ++ ++/* SDIO1 is used to drive the SD card */ ++&sdio1 { ++ vqmmc-supply = <&sd_io_1v8_reg>; ++ vmmc-supply = <&sd_vcc_reg>; ++ bus-width = <4>; ++ sd-uhs-sdr50; ++ sd-uhs-ddr50; ++ sd-uhs-sdr104; ++}; +diff --git a/arch/arm64/boot/dts/broadcom/bcm2712.dtsi b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +new file mode 100644 +index 000000000000..6e5a984c1d4e +--- /dev/null ++++ b/arch/arm64/boot/dts/broadcom/bcm2712.dtsi +@@ -0,0 +1,283 @@ ++// SPDX-License-Identifier: (GPL-2.0 OR MIT) ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ ++/ { ++ compatible = "brcm,bcm2712"; ++ ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ interrupt-parent = <&gicv2>; ++ ++ clocks { ++ /* The oscillator is the root of the clock tree. */ ++ clk_osc: clk-osc { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-output-names = "osc"; ++ clock-frequency = <54000000>; ++ }; ++ ++ clk_vpu: clk-vpu { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <750000000>; ++ clock-output-names = "vpu-clock"; ++ }; ++ ++ clk_uart: clk-uart { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <9216000>; ++ clock-output-names = "uart-clock"; ++ }; ++ ++ clk_emmc2: clk-emmc2 { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <200000000>; ++ clock-output-names = "emmc2-clock"; ++ }; ++ }; ++ ++ cpus: cpus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ /* Source for L1 d/i cache-line-size, cache-sets, cache-size ++ * https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?lang=en ++ * Source for L2 cache-line-size and cache-sets: ++ * https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?lang=en ++ * and for cache-size: ++ * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 ++ */ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x000>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l0>; ++ ++ l2_cache_l0: l2-cache-l0 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x100>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l1>; ++ ++ l2_cache_l1: l2-cache-l1 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ }; ++ ++ cpu2: cpu@2 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x200>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l2>; ++ ++ l2_cache_l2: l2-cache-l2 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ }; ++ ++ cpu3: cpu@3 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a76"; ++ reg = <0x300>; ++ enable-method = "psci"; ++ d-cache-size = <0x10000>; ++ d-cache-line-size = <64>; ++ d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ i-cache-size = <0x10000>; ++ i-cache-line-size = <64>; ++ i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set ++ next-level-cache = <&l2_cache_l3>; ++ ++ l2_cache_l3: l2-cache-l3 { ++ compatible = "cache"; ++ cache-size = <0x80000>; ++ cache-line-size = <128>; ++ cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set ++ cache-level = <2>; ++ cache-unified; ++ next-level-cache = <&l3_cache>; ++ }; ++ }; ++ ++ /* Source for cache-line-size and cache-sets: ++ * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en ++ * Source for cache-size: ++ * https://www.raspberrypi.com/documentation/computers/processors.html#bcm2712 ++ */ ++ l3_cache: l3-cache { ++ compatible = "cache"; ++ cache-size = <0x200000>; ++ cache-line-size = <64>; ++ cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set ++ cache-level = <3>; ++ cache-unified; ++ }; ++ }; ++ ++ psci { ++ method = "smc"; ++ compatible = "arm,psci-1.0", "arm,psci-0.2"; ++ }; ++ ++ rmem: reserved-memory { ++ ranges; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ atf@0 { ++ reg = <0x0 0x0 0x0 0x80000>; ++ no-map; ++ }; ++ ++ cma: linux,cma { ++ compatible = "shared-dma-pool"; ++ size = <0x0 0x4000000>; /* 64MB */ ++ reusable; ++ linux,cma-default; ++ alloc-ranges = <0x0 0x00000000 0x0 0x40000000>; ++ }; ++ }; ++ ++ soc: soc@107c000000 { ++ compatible = "simple-bus"; ++ ranges = <0x00000000 0x10 0x00000000 0x80000000>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ sdio1: mmc@fff000 { ++ compatible = "brcm,bcm2712-sdhci", ++ "brcm,sdhci-brcmstb"; ++ reg = <0x00fff000 0x260>, ++ <0x00fff400 0x200>; ++ reg-names = "host", "cfg"; ++ interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_emmc2>; ++ clock-names = "sw_sdio"; ++ mmc-ddr-3_3v; ++ }; ++ ++ system_timer: timer@7c003000 { ++ compatible = "brcm,bcm2835-system-timer"; ++ reg = <0x7c003000 0x1000>; ++ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; ++ clock-frequency = <1000000>; ++ }; ++ ++ mailbox: mailbox@7c013880 { ++ compatible = "brcm,bcm2835-mbox"; ++ reg = <0x7c013880 0x40>; ++ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; ++ #mbox-cells = <0>; ++ }; ++ ++ local_intc: interrupt-controller@7cd00000 { ++ compatible = "brcm,bcm2836-l1-intc"; ++ reg = <0x7cd00000 0x100>; ++ }; ++ ++ uart10: serial@7d001000 { ++ compatible = "arm,pl011", "arm,primecell"; ++ reg = <0x7d001000 0x200>; ++ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&clk_uart>, <&clk_vpu>; ++ clock-names = "uartclk", "apb_pclk"; ++ arm,primecell-periphid = <0x00241011>; ++ status = "disabled"; ++ }; ++ ++ interrupt-controller@7d517000 { ++ compatible = "brcm,bcm7271-l2-intc"; ++ reg = <0x7d517000 0x10>; ++ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ }; ++ ++ gio_aon: gpio@7d517c00 { ++ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; ++ reg = <0x7d517c00 0x40>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ brcm,gpio-bank-widths = <17 6>; ++ /* The lack of 'interrupt-controller' property here is intended: ++ * don't use GIO_AON as an interrupt controller because it will ++ * clash with the firmware monitoring the PMIC interrupt via the VPU. ++ */ ++ }; ++ ++ gicv2: interrupt-controller@7fff9000 { ++ compatible = "arm,gic-400"; ++ reg = <0x7fff9000 0x1000>, ++ <0x7fffa000 0x2000>, ++ <0x7fffc000 0x2000>, ++ <0x7fffe000 0x2000>; ++ interrupt-controller; ++ #interrupt-cells = <3>; ++ }; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_LOW)>, ++ <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | ++ IRQ_TYPE_LEVEL_LOW)>; ++ }; ++}; +diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +index b27143f81867..320706c88cdd 100644 +--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts ++++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts +@@ -592,6 +592,57 @@ vreg_l10d: ldo10 { + }; + }; + ++&camss { ++ vdda-phy-supply = <&vreg_l6d>; ++ vdda-pll-supply = <&vreg_l4d>; ++ ++ status = "okay"; ++ ++ ports { ++ port@0 { ++ csiphy0_lanes01_ep: endpoint@0 { ++ reg = <0>; ++ clock-lanes = <7>; ++ data-lanes = <0 1>; ++ remote-endpoint = <&ov5675_ep>; ++ }; ++ }; ++ }; ++}; ++ ++&cci2 { ++ status = "okay"; ++}; ++ ++&cci2_i2c1 { ++ camera@10 { ++ compatible = "ovti,ov5675"; ++ reg = <0x10>; ++ ++ reset-gpios = <&tlmm 15 GPIO_ACTIVE_LOW>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&cam_rgb_default>; ++ ++ clocks = <&camcc CAMCC_MCLK3_CLK>; ++ ++ orientation = <0>; /* Front facing */ ++ ++ avdd-supply = <&vreg_l6q>; ++ dvdd-supply = <&vreg_l2q>; ++ dovdd-supply = <&vreg_l7q>; ++ ++ port { ++ ov5675_ep: endpoint { ++ clock-lanes = <0>; ++ data-lanes = <1 2>; ++ link-frequencies = /bits/ 64 <450000000>; ++ remote-endpoint = <&csiphy0_lanes01_ep>; ++ }; ++ }; ++ ++ }; ++}; ++ + &dispcc0 { + status = "okay"; + }; +@@ -1436,6 +1487,22 @@ cam_indicator_en: cam-indicator-en-state { + bias-disable; + }; + ++ cam_rgb_default: cam-rgb-default-state { ++ mclk-pins { ++ pins = "gpio17"; ++ function = "cam_mclk"; ++ drive-strength = <16>; ++ bias-disable; ++ }; ++ ++ sc-rgb-xshut-n-pins { ++ pins = "gpio15"; ++ function = "gpio"; ++ drive-strength = <2>; ++ bias-disable; ++ }; ++ }; ++ + edp_reg_en: edp-reg-en-state { + pins = "gpio25"; + function = "gpio"; diff --git a/arch/s390/include/asm/ipl.h b/arch/s390/include/asm/ipl.h -index b0d00032479d6..afb9544fb0074 100644 +index b0d00032479d..afb9544fb007 100644 --- a/arch/s390/include/asm/ipl.h +++ b/arch/s390/include/asm/ipl.h @@ -139,6 +139,7 @@ int ipl_report_add_component(struct ipl_report *report, struct kexec_buf *kbuf, @@ -242,7 +641,7 @@ index b0d00032479d6..afb9544fb0074 100644 /* * DIAG 308 support diff --git a/arch/s390/kernel/ipl.c b/arch/s390/kernel/ipl.c -index 3a7d6e1722112..8163a2173247e 100644 +index f17bb7bf9392..66e530380ee3 100644 --- a/arch/s390/kernel/ipl.c +++ b/arch/s390/kernel/ipl.c @@ -2479,3 +2479,8 @@ int ipl_report_free(struct ipl_report *report) @@ -255,7 +654,7 @@ index 3a7d6e1722112..8163a2173247e 100644 + return !!ipl_secure_flag; +} diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c -index 610e6f794511a..4fc7aca3f572c 100644 +index a3fea683b227..a3162d93f437 100644 --- a/arch/s390/kernel/setup.c +++ b/arch/s390/kernel/setup.c @@ -49,6 +49,7 @@ @@ -266,7 +665,7 @@ index 610e6f794511a..4fc7aca3f572c 100644 #include <linux/hugetlb.h> #include <linux/kmemleak.h> -@@ -891,6 +892,9 @@ void __init setup_arch(char **cmdline_p) +@@ -910,6 +911,9 @@ void __init setup_arch(char **cmdline_p) log_component_list(); @@ -277,7 +676,7 @@ index 610e6f794511a..4fc7aca3f572c 100644 /* boot_command_line has been already set up in early.c */ *cmdline_p = boot_command_line; diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c -index 05c5aa951da74..da521c6f1cf2d 100644 +index 6129dc2ba784..feaf5fd3f37d 100644 --- a/arch/x86/kernel/setup.c +++ b/arch/x86/kernel/setup.c @@ -21,6 +21,7 @@ @@ -288,7 +687,7 @@ index 05c5aa951da74..da521c6f1cf2d 100644 #include <linux/usb/xhci-dbgp.h> #include <linux/static_call.h> #include <linux/swiotlb.h> -@@ -902,6 +903,13 @@ void __init setup_arch(char **cmdline_p) +@@ -904,6 +905,13 @@ void __init setup_arch(char **cmdline_p) if (efi_enabled(EFI_BOOT)) efi_init(); @@ -302,7 +701,7 @@ index 05c5aa951da74..da521c6f1cf2d 100644 reserve_ibft_region(); x86_init.resources.dmi_setup(); -@@ -1064,19 +1072,7 @@ void __init setup_arch(char **cmdline_p) +@@ -1065,19 +1073,7 @@ void __init setup_arch(char **cmdline_p) /* Allocate bigger log buffer */ setup_log_buf(1); @@ -324,7 +723,7 @@ index 05c5aa951da74..da521c6f1cf2d 100644 reserve_initrd(); diff --git a/certs/extract-cert.c b/certs/extract-cert.c -index 70e9ec89d87d3..f5fb74916cee4 100644 +index 70e9ec89d87d..f5fb74916cee 100644 --- a/certs/extract-cert.c +++ b/certs/extract-cert.c @@ -21,7 +21,6 @@ @@ -366,282 +765,130 @@ index 70e9ec89d87d3..f5fb74916cee4 100644 } else { BIO *b; X509 *x509; -diff --git a/crypto/drbg.c b/crypto/drbg.c -index 3addce90930c3..730b03de596a3 100644 ---- a/crypto/drbg.c -+++ b/crypto/drbg.c -@@ -1494,13 +1494,14 @@ static int drbg_generate(struct drbg_state *drbg, - * Wrapper around drbg_generate which can pull arbitrary long strings - * from the DRBG without hitting the maximum request limitation. - * -- * Parameters: see drbg_generate -+ * Parameters: see drbg_generate, except @reseed, which triggers reseeding - * Return codes: see drbg_generate -- if one drbg_generate request fails, - * the entire drbg_generate_long request fails - */ - static int drbg_generate_long(struct drbg_state *drbg, - unsigned char *buf, unsigned int buflen, -- struct drbg_string *addtl) -+ struct drbg_string *addtl, -+ bool reseed) +diff --git a/crypto/akcipher.c b/crypto/akcipher.c +index e0ff5f4dda6d..098a52ded759 100644 +--- a/crypto/akcipher.c ++++ b/crypto/akcipher.c +@@ -126,14 +126,12 @@ int crypto_register_akcipher(struct akcipher_alg *alg) { - unsigned int len = 0; - unsigned int slice = 0; -@@ -1510,6 +1511,8 @@ static int drbg_generate_long(struct drbg_state *drbg, - slice = ((buflen - len) / drbg_max_request_bytes(drbg)); - chunk = slice ? drbg_max_request_bytes(drbg) : (buflen - len); - mutex_lock(&drbg->drbg_mutex); -+ if (reseed) -+ drbg->seeded = DRBG_SEED_STATE_UNSEEDED; - err = drbg_generate(drbg, buf + len, chunk, addtl); - mutex_unlock(&drbg->drbg_mutex); - if (0 > err) -@@ -1936,6 +1939,7 @@ static int drbg_kcapi_random(struct crypto_rng *tfm, - struct drbg_state *drbg = crypto_rng_ctx(tfm); - struct drbg_string *addtl = NULL; - struct drbg_string string; -+ int err; - - if (slen) { - /* linked list variable is now local to allow modification */ -@@ -1943,7 +1947,15 @@ static int drbg_kcapi_random(struct crypto_rng *tfm, - addtl = &string; - } - -- return drbg_generate_long(drbg, dst, dlen, addtl); -+ err = drbg_generate_long(drbg, dst, dlen, addtl, -+ (crypto_tfm_get_flags(crypto_rng_tfm(tfm)) & -+ CRYPTO_TFM_REQ_NEED_RESEED) == -+ CRYPTO_TFM_REQ_NEED_RESEED); -+ -+ crypto_tfm_clear_flags(crypto_rng_tfm(tfm), -+ CRYPTO_TFM_REQ_NEED_RESEED); -+ -+ return err; - } - - /* -diff --git a/crypto/rng.c b/crypto/rng.c -index 9d8804e464226..5ccb0485ff4b2 100644 ---- a/crypto/rng.c -+++ b/crypto/rng.c -@@ -12,10 +12,13 @@ - #include <linux/atomic.h> - #include <linux/cryptouser.h> - #include <linux/err.h> -+#include <linux/fips.h> - #include <linux/kernel.h> - #include <linux/module.h> - #include <linux/mutex.h> - #include <linux/random.h> -+#include <linux/sched.h> -+#include <linux/sched/signal.h> - #include <linux/seq_file.h> - #include <linux/slab.h> - #include <linux/string.h> -@@ -23,7 +26,9 @@ - - #include "internal.h" - --static DEFINE_MUTEX(crypto_default_rng_lock); -+static ____cacheline_aligned_in_smp DEFINE_MUTEX(crypto_reseed_rng_lock); -+static struct crypto_rng *crypto_reseed_rng; -+static ____cacheline_aligned_in_smp DEFINE_MUTEX(crypto_default_rng_lock); - struct crypto_rng *crypto_default_rng; - EXPORT_SYMBOL_GPL(crypto_default_rng); - static int crypto_default_rng_refcnt; -@@ -106,31 +111,37 @@ struct crypto_rng *crypto_alloc_rng(const char *alg_name, u32 type, u32 mask) - } - EXPORT_SYMBOL_GPL(crypto_alloc_rng); - --int crypto_get_default_rng(void) -+static int crypto_get_rng(struct crypto_rng **rngp) - { - struct crypto_rng *rng; - int err; - -- mutex_lock(&crypto_default_rng_lock); -- if (!crypto_default_rng) { -+ if (!*rngp) { - rng = crypto_alloc_rng("stdrng", 0, 0); - err = PTR_ERR(rng); - if (IS_ERR(rng)) -- goto unlock; -+ return err; - - err = crypto_rng_reset(rng, NULL, crypto_rng_seedsize(rng)); - if (err) { - crypto_free_rng(rng); -- goto unlock; -+ return err; + struct crypto_alg *base = &alg->base; + +- if (!alg->sign) +- alg->sign = akcipher_default_op; ++ alg->sign = akcipher_default_op; + if (!alg->verify) + alg->verify = akcipher_default_op; + if (!alg->encrypt) + alg->encrypt = akcipher_default_op; +- if (!alg->decrypt) +- alg->decrypt = akcipher_default_op; ++ alg->decrypt = akcipher_default_op; + if (!alg->set_priv_key) + alg->set_priv_key = akcipher_default_set_key; + +diff --git a/crypto/dh.c b/crypto/dh.c +index 68d11d66c0b5..6e3e515b2452 100644 +--- a/crypto/dh.c ++++ b/crypto/dh.c +@@ -227,10 +227,35 @@ static int dh_compute_value(struct kpp_request *req) + + /* SP800-56A rev 3 5.6.2.1.3 key check */ + } else { ++ MPI val_pct; ++ + if (dh_is_pubkey_valid(ctx, val)) { + ret = -EAGAIN; + goto err_free_val; + } ++ ++ /* ++ * SP800-56Arev3, 5.6.2.1.4: ("Owner Assurance ++ * of Pair-wise Consistency"): recompute the ++ * public key and check if the results match. ++ */ ++ val_pct = mpi_alloc(0); ++ if (!val_pct) { ++ ret = -ENOMEM; ++ goto err_free_val; ++ } ++ ++ ret = _compute_val(ctx, base, val_pct); ++ if (ret) { ++ mpi_free(val_pct); ++ goto err_free_val; ++ } ++ ++ if (mpi_cmp(val, val_pct) != 0) { ++ fips_fail_notify(); ++ panic("dh: pair-wise consistency test failed\n"); ++ } ++ mpi_free(val_pct); } - -- crypto_default_rng = rng; -+ *rngp = rng; } -- crypto_default_rng_refcnt++; -- err = 0; -+ return 0; -+} -+ -+int crypto_get_default_rng(void) -+{ -+ int err; - --unlock: -+ mutex_lock(&crypto_default_rng_lock); -+ err = crypto_get_rng(&crypto_default_rng); -+ if (!err) -+ crypto_default_rng_refcnt++; - mutex_unlock(&crypto_default_rng_lock); - - return err; -@@ -146,24 +157,33 @@ void crypto_put_default_rng(void) - EXPORT_SYMBOL_GPL(crypto_put_default_rng); - - #if defined(CONFIG_CRYPTO_RNG) || defined(CONFIG_CRYPTO_RNG_MODULE) --int crypto_del_default_rng(void) -+static int crypto_del_rng(struct crypto_rng **rngp, int *refcntp, -+ struct mutex *lock) - { - int err = -EBUSY; - -- mutex_lock(&crypto_default_rng_lock); -- if (crypto_default_rng_refcnt) -+ mutex_lock(lock); -+ if (refcntp && *refcntp) - goto out; - -- crypto_free_rng(crypto_default_rng); -- crypto_default_rng = NULL; -+ crypto_free_rng(*rngp); -+ *rngp = NULL; - - err = 0; - - out: -- mutex_unlock(&crypto_default_rng_lock); -+ mutex_unlock(lock); - - return err; - } -+ -+int crypto_del_default_rng(void) -+{ -+ return crypto_del_rng(&crypto_default_rng, &crypto_default_rng_refcnt, -+ &crypto_default_rng_lock) ?: -+ crypto_del_rng(&crypto_reseed_rng, NULL, -+ &crypto_reseed_rng_lock); -+} - EXPORT_SYMBOL_GPL(crypto_del_default_rng); - #endif - -@@ -217,5 +237,102 @@ void crypto_unregister_rngs(struct rng_alg *algs, int count) +diff --git a/crypto/seqiv.c b/crypto/seqiv.c +index 17e11d51ddc3..9c136a3b6267 100644 +--- a/crypto/seqiv.c ++++ b/crypto/seqiv.c +@@ -132,6 +132,19 @@ static int seqiv_aead_decrypt(struct aead_request *req) + return crypto_aead_decrypt(subreq); } - EXPORT_SYMBOL_GPL(crypto_unregister_rngs); -+static ssize_t crypto_devrandom_read_iter(struct iov_iter *iter, bool reseed) ++static int aead_init_seqiv(struct crypto_aead *aead) +{ -+ struct crypto_rng *rng; -+ u8 tmp[256]; -+ ssize_t ret; -+ -+ if (unlikely(!iov_iter_count(iter))) -+ return 0; -+ -+ if (reseed) { -+ u32 flags = 0; -+ -+ /* If reseeding is requested, acquire a lock on -+ * crypto_reseed_rng so it is not swapped out until -+ * the initial random bytes are generated. -+ * -+ * The algorithm implementation is also protected with -+ * a separate mutex (drbg->drbg_mutex) around the -+ * reseed-and-generate operation. -+ */ -+ mutex_lock(&crypto_reseed_rng_lock); -+ -+ /* If crypto_default_rng is not set, it will be seeded -+ * at creation in __crypto_get_default_rng and thus no -+ * reseeding is needed. -+ */ -+ if (crypto_reseed_rng) -+ flags |= CRYPTO_TFM_REQ_NEED_RESEED; -+ -+ ret = crypto_get_rng(&crypto_reseed_rng); -+ if (ret) { -+ mutex_unlock(&crypto_reseed_rng_lock); -+ return ret; -+ } -+ -+ rng = crypto_reseed_rng; -+ crypto_tfm_set_flags(crypto_rng_tfm(rng), flags); -+ } else { -+ ret = crypto_get_default_rng(); -+ if (ret) -+ return ret; -+ rng = crypto_default_rng; -+ } -+ -+ for (;;) { -+ size_t i, copied; -+ int err; -+ -+ i = min_t(size_t, iov_iter_count(iter), sizeof(tmp)); -+ err = crypto_rng_get_bytes(rng, tmp, i); -+ if (err) { -+ ret = err; -+ break; -+ } -+ -+ copied = copy_to_iter(tmp, i, iter); -+ ret += copied; -+ -+ if (!iov_iter_count(iter)) -+ break; -+ -+ if (need_resched()) { -+ if (signal_pending(current)) -+ break; -+ schedule(); -+ } -+ } -+ -+ if (reseed) -+ mutex_unlock(&crypto_reseed_rng_lock); -+ else -+ crypto_put_default_rng(); -+ memzero_explicit(tmp, sizeof(tmp)); ++ int err; + -+ return ret; -+} ++ err = aead_init_geniv(aead); ++ if (err) ++ return err; + -+static const struct random_extrng crypto_devrandom_rng = { -+ .extrng_read_iter = crypto_devrandom_read_iter, -+ .owner = THIS_MODULE, -+}; ++ crypto_aead_set_flags(aead, CRYPTO_TFM_FIPS_COMPLIANCE); + -+static int __init crypto_rng_init(void) -+{ -+ if (fips_enabled) -+ random_register_extrng(&crypto_devrandom_rng); + return 0; +} + -+static void __exit crypto_rng_exit(void) -+{ -+ random_unregister_extrng(); -+} -+ -+late_initcall(crypto_rng_init); -+module_exit(crypto_rng_exit); -+ - MODULE_LICENSE("GPL"); - MODULE_DESCRIPTION("Random Number Generator"); + static int seqiv_aead_create(struct crypto_template *tmpl, struct rtattr **tb) + { + struct aead_instance *inst; +@@ -149,7 +162,7 @@ static int seqiv_aead_create(struct crypto_template *tmpl, struct rtattr **tb) + inst->alg.encrypt = seqiv_aead_encrypt; + inst->alg.decrypt = seqiv_aead_decrypt; + +- inst->alg.init = aead_init_geniv; ++ inst->alg.init = aead_init_seqiv; + inst->alg.exit = aead_exit_geniv; + + inst->alg.base.cra_ctxsize = sizeof(struct aead_geniv_ctx); +diff --git a/crypto/testmgr.c b/crypto/testmgr.c +index f02cb075bd68..669e306f1cb2 100644 +--- a/crypto/testmgr.c ++++ b/crypto/testmgr.c +@@ -4216,7 +4216,7 @@ static int test_akcipher_one(struct crypto_akcipher *tfm, + * Don't invoke (decrypt or sign) test which require a private key + * for vectors with only a public key. + */ +- if (vecs->public_key_vec) { ++ if (1 || vecs->public_key_vec) { + err = 0; + goto free_all; + } +@@ -5093,14 +5093,12 @@ static const struct alg_test_desc alg_test_descs[] = { + }, { + .alg = "ecdh-nist-p256", + .test = alg_test_kpp, +- .fips_allowed = 1, + .suite = { + .kpp = __VECS(ecdh_p256_tv_template) + } + }, { + .alg = "ecdh-nist-p384", + .test = alg_test_kpp, +- .fips_allowed = 1, + .suite = { + .kpp = __VECS(ecdh_p384_tv_template) + } diff --git a/drivers/acpi/apei/hest.c b/drivers/acpi/apei/hest.c -index 20d757687e3d9..90a13f20f052b 100644 +index 20d757687e3d..90a13f20f052 100644 --- a/drivers/acpi/apei/hest.c +++ b/drivers/acpi/apei/hest.c @@ -142,6 +142,14 @@ static int apei_hest_parse(apei_hest_func_t func, void *data) @@ -660,7 +907,7 @@ index 20d757687e3d9..90a13f20f052b 100644 for (i = 0; i < hest_tab->error_source_count; i++) { len = hest_esrc_len(hest_hdr); diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c -index 1687483ff319e..390b67f19181a 100644 +index 1687483ff319..390b67f19181 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -143,6 +143,7 @@ struct acpi_irq_parse_one_ctx { @@ -703,10 +950,10 @@ index 1687483ff319e..390b67f19181a 100644 return ctx.rc; } diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c -index cdc5a74092c77..45679565878f1 100644 +index 22ae7829a915..1329032ed09b 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c -@@ -1793,6 +1793,15 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device) +@@ -1802,6 +1802,15 @@ static bool acpi_device_enumeration_by_parent(struct acpi_device *device) if (!acpi_match_device_ids(device, ignore_serial_bus_ids)) return false; @@ -723,7 +970,7 @@ index cdc5a74092c77..45679565878f1 100644 acpi_dev_get_resources(device, &resource_list, acpi_check_serial_bus_slave, diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c -index 83431aae74d8b..f2a9c0d644af2 100644 +index fdfa7b266218..f5f8ba457c93 100644 --- a/drivers/ata/libahci.c +++ b/drivers/ata/libahci.c @@ -729,6 +729,24 @@ int ahci_stop_engine(struct ata_port *ap) @@ -752,7 +999,7 @@ index 83431aae74d8b..f2a9c0d644af2 100644 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500); diff --git a/drivers/char/ipmi/ipmi_dmi.c b/drivers/char/ipmi/ipmi_dmi.c -index bbf7029e224be..cf7faa970dd65 100644 +index bbf7029e224b..cf7faa970dd6 100644 --- a/drivers/char/ipmi/ipmi_dmi.c +++ b/drivers/char/ipmi/ipmi_dmi.c @@ -215,6 +215,21 @@ static int __init scan_for_dmi_ipmi(void) @@ -778,7 +1025,7 @@ index bbf7029e224be..cf7faa970dd65 100644 dmi_decode_ipmi((const struct dmi_header *) dev->device_data); diff --git a/drivers/char/ipmi/ipmi_msghandler.c b/drivers/char/ipmi/ipmi_msghandler.c -index e12b531f5c2f3..082707f8dff8c 100644 +index e12b531f5c2f..082707f8dff8 100644 --- a/drivers/char/ipmi/ipmi_msghandler.c +++ b/drivers/char/ipmi/ipmi_msghandler.c @@ -35,6 +35,7 @@ @@ -812,205 +1059,8 @@ index e12b531f5c2f3..082707f8dff8c 100644 mutex_lock(&ipmi_interfaces_mutex); rv = ipmi_register_driver(); mutex_unlock(&ipmi_interfaces_mutex); -diff --git a/drivers/char/random.c b/drivers/char/random.c -index 2597cb43f4387..d860f4f6ba2c7 100644 ---- a/drivers/char/random.c -+++ b/drivers/char/random.c -@@ -51,6 +51,7 @@ - #include <linux/completion.h> - #include <linux/uuid.h> - #include <linux/uaccess.h> -+#include <linux/rcupdate.h> - #include <linux/suspend.h> - #include <linux/siphash.h> - #include <linux/sched/isolation.h> -@@ -309,6 +310,11 @@ static void crng_fast_key_erasure(u8 key[CHACHA_KEY_SIZE], - memzero_explicit(first_block, sizeof(first_block)); - } - -+/* -+ * Hook for external RNG. -+ */ -+static const struct random_extrng __rcu *extrng; -+ - /* - * This function returns a ChaCha state that you may use for generating - * random data. It also returns up to 32 bytes on its own of random data -@@ -739,6 +745,9 @@ static void __cold _credit_init_bits(size_t bits) - } - - -+static const struct file_operations extrng_random_fops; -+static const struct file_operations extrng_urandom_fops; -+ - /********************************************************************** - * - * Entropy collection routines. -@@ -956,6 +965,19 @@ void __init add_bootloader_randomness(const void *buf, size_t len) - credit_init_bits(len * 8); - } - -+void random_register_extrng(const struct random_extrng *rng) -+{ -+ rcu_assign_pointer(extrng, rng); -+} -+EXPORT_SYMBOL_GPL(random_register_extrng); -+ -+void random_unregister_extrng(void) -+{ -+ RCU_INIT_POINTER(extrng, NULL); -+ synchronize_rcu(); -+} -+EXPORT_SYMBOL_GPL(random_unregister_extrng); -+ - #if IS_ENABLED(CONFIG_VMGENID) - static BLOCKING_NOTIFIER_HEAD(vmfork_chain); - -@@ -1365,6 +1387,7 @@ SYSCALL_DEFINE3(getrandom, char __user *, ubuf, size_t, len, unsigned int, flags - { - struct iov_iter iter; - int ret; -+ const struct random_extrng *rng; - - if (flags & ~(GRND_NONBLOCK | GRND_RANDOM | GRND_INSECURE)) - return -EINVAL; -@@ -1376,6 +1399,21 @@ SYSCALL_DEFINE3(getrandom, char __user *, ubuf, size_t, len, unsigned int, flags - if ((flags & (GRND_INSECURE | GRND_RANDOM)) == (GRND_INSECURE | GRND_RANDOM)) - return -EINVAL; - -+ rcu_read_lock(); -+ rng = rcu_dereference(extrng); -+ if (rng && !try_module_get(rng->owner)) -+ rng = NULL; -+ rcu_read_unlock(); -+ -+ if (rng) { -+ ret = import_ubuf(ITER_DEST, ubuf, len, &iter); -+ if (unlikely(ret)) -+ return ret; -+ ret = rng->extrng_read_iter(&iter, !!(flags & GRND_RANDOM)); -+ module_put(rng->owner); -+ return ret; -+ } -+ - if (!crng_ready() && !(flags & GRND_INSECURE)) { - if (flags & GRND_NONBLOCK) - return -EAGAIN; -@@ -1396,6 +1434,12 @@ static __poll_t random_poll(struct file *file, poll_table *wait) - return crng_ready() ? EPOLLIN | EPOLLRDNORM : EPOLLOUT | EPOLLWRNORM; - } - -+static __poll_t extrng_poll(struct file *file, poll_table * wait) -+{ -+ /* extrng pool is always full, always read, no writes */ -+ return EPOLLIN | EPOLLRDNORM; -+} -+ - static ssize_t write_pool_user(struct iov_iter *iter) - { - u8 block[BLAKE2S_BLOCK_SIZE]; -@@ -1536,7 +1580,58 @@ static int random_fasync(int fd, struct file *filp, int on) - return fasync_helper(fd, filp, on, &fasync); - } - -+static int random_open(struct inode *inode, struct file *filp) -+{ -+ const struct random_extrng *rng; -+ -+ rcu_read_lock(); -+ rng = rcu_dereference(extrng); -+ if (rng && !try_module_get(rng->owner)) -+ rng = NULL; -+ rcu_read_unlock(); -+ -+ if (!rng) -+ return 0; -+ -+ filp->f_op = &extrng_random_fops; -+ filp->private_data = rng->owner; -+ -+ return 0; -+} -+ -+static int urandom_open(struct inode *inode, struct file *filp) -+{ -+ const struct random_extrng *rng; -+ -+ rcu_read_lock(); -+ rng = rcu_dereference(extrng); -+ if (rng && !try_module_get(rng->owner)) -+ rng = NULL; -+ rcu_read_unlock(); -+ -+ if (!rng) -+ return 0; -+ -+ filp->f_op = &extrng_urandom_fops; -+ filp->private_data = rng->owner; -+ -+ return 0; -+} -+ -+static int extrng_release(struct inode *inode, struct file *filp) -+{ -+ module_put(filp->private_data); -+ return 0; -+} -+ -+static ssize_t -+extrng_read_iter(struct kiocb *kiocb, struct iov_iter *iter) -+{ -+ return rcu_dereference_raw(extrng)->extrng_read_iter(iter, false); -+} -+ - const struct file_operations random_fops = { -+ .open = random_open, - .read_iter = random_read_iter, - .write_iter = random_write_iter, - .poll = random_poll, -@@ -1549,6 +1644,7 @@ const struct file_operations random_fops = { - }; - - const struct file_operations urandom_fops = { -+ .open = urandom_open, - .read_iter = urandom_read_iter, - .write_iter = random_write_iter, - .unlocked_ioctl = random_ioctl, -@@ -1559,6 +1655,32 @@ const struct file_operations urandom_fops = { - .splice_write = iter_file_splice_write, - }; - -+static const struct file_operations extrng_random_fops = { -+ .open = random_open, -+ .read_iter = extrng_read_iter, -+ .write_iter = random_write_iter, -+ .poll = extrng_poll, -+ .unlocked_ioctl = random_ioctl, -+ .compat_ioctl = compat_ptr_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+ .release = extrng_release, -+ .splice_read = copy_splice_read, -+ .splice_write = iter_file_splice_write, -+}; -+ -+static const struct file_operations extrng_urandom_fops = { -+ .open = urandom_open, -+ .read_iter = extrng_read_iter, -+ .write_iter = random_write_iter, -+ .unlocked_ioctl = random_ioctl, -+ .compat_ioctl = compat_ptr_ioctl, -+ .fasync = random_fasync, -+ .llseek = noop_llseek, -+ .release = extrng_release, -+ .splice_read = copy_splice_read, -+ .splice_write = iter_file_splice_write, -+}; - - /******************************************************************** - * diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile -index a2d0009560d0f..4f3486e6a84b2 100644 +index a2d0009560d0..4f3486e6a84b 100644 --- a/drivers/firmware/efi/Makefile +++ b/drivers/firmware/efi/Makefile @@ -25,6 +25,7 @@ subdir-$(CONFIG_EFI_STUB) += libstub @@ -1022,7 +1072,7 @@ index a2d0009560d0f..4f3486e6a84b2 100644 obj-$(CONFIG_EFI_RCI2_TABLE) += rci2-table.o obj-$(CONFIG_EFI_EMBEDDED_FIRMWARE) += embedded-firmware.o diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c -index fdf07dd6f4591..cfd2b58a34940 100644 +index fdf07dd6f459..cfd2b58a3494 100644 --- a/drivers/firmware/efi/efi.c +++ b/drivers/firmware/efi/efi.c @@ -33,6 +33,7 @@ @@ -1168,7 +1218,7 @@ index fdf07dd6f4591..cfd2b58a34940 100644 diff --git a/drivers/firmware/efi/secureboot.c b/drivers/firmware/efi/secureboot.c new file mode 100644 -index 0000000000000..de0a3714a5d44 +index 000000000000..de0a3714a5d4 --- /dev/null +++ b/drivers/firmware/efi/secureboot.c @@ -0,0 +1,38 @@ @@ -1211,7 +1261,7 @@ index 0000000000000..de0a3714a5d44 + } +} diff --git a/drivers/hid/hid-rmi.c b/drivers/hid/hid-rmi.c -index d4af17fdba467..154f0403cbf4c 100644 +index d4af17fdba46..154f0403cbf4 100644 --- a/drivers/hid/hid-rmi.c +++ b/drivers/hid/hid-rmi.c @@ -321,21 +321,12 @@ static int rmi_input_event(struct hid_device *hdev, u8 *data, int size) @@ -1313,7 +1363,7 @@ index d4af17fdba467..154f0403cbf4c 100644 data->xport.ops = &hid_rmi_ops; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c -index bf01f01964cf9..703896981e8ae 100644 +index bf01f01964cf..703896981e8a 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -10,6 +10,7 @@ @@ -1364,7 +1414,7 @@ index bf01f01964cf9..703896981e8ae 100644 platform_driver_unregister(&etm4_platform_driver); etm4_pm_clear(); diff --git a/drivers/input/rmi4/rmi_driver.c b/drivers/input/rmi4/rmi_driver.c -index ef9ea295f9e03..0103334e8f32c 100644 +index 2168b6cd7167..5d7cda175a0c 100644 --- a/drivers/input/rmi4/rmi_driver.c +++ b/drivers/input/rmi4/rmi_driver.c @@ -182,34 +182,47 @@ void rmi_set_attn_data(struct rmi_device *rmi_dev, unsigned long irq_status, @@ -1556,7 +1606,7 @@ index ef9ea295f9e03..0103334e8f32c 100644 if (data->f01_container->dev.driver) { /* Driver already bound, so enable ATTN now. */ diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c -index 9df7cc75c1bc5..60d541ae39e8d 100644 +index ed6c5cb60c5a..70cb770b78bb 100644 --- a/drivers/iommu/iommu.c +++ b/drivers/iommu/iommu.c @@ -8,6 +8,7 @@ @@ -1567,7 +1617,7 @@ index 9df7cc75c1bc5..60d541ae39e8d 100644 #include <linux/kernel.h> #include <linux/bits.h> #include <linux/bug.h> -@@ -2916,6 +2917,27 @@ int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) +@@ -2932,6 +2933,27 @@ int iommu_dev_disable_feature(struct device *dev, enum iommu_dev_features feat) } EXPORT_SYMBOL_GPL(iommu_dev_disable_feature); @@ -1595,70 +1645,55 @@ index 9df7cc75c1bc5..60d541ae39e8d 100644 /** * iommu_setup_default_domain - Set the default_domain for the group * @group: Group to change -diff --git a/drivers/media/pci/intel/ipu-bridge.c b/drivers/media/pci/intel/ipu-bridge.c -index 61750cc98d705..a0e9a71580b5d 100644 ---- a/drivers/media/pci/intel/ipu-bridge.c -+++ b/drivers/media/pci/intel/ipu-bridge.c -@@ -43,28 +43,46 @@ - * becoming apparent in the future. - * - * Do not add an entry for a sensor that is not actually supported. -+ * -+ * Please keep the list sorted by ACPI HID. - */ - static const struct ipu_sensor_config ipu_supported_sensors[] = { -+ /* Himax HM11B1 */ -+ IPU_SENSOR_CONFIG("HIMX11B1", 1, 384000000), -+ /* Himax HM2170 */ -+ IPU_SENSOR_CONFIG("HIMX2170", 1, 384000000), -+ /* Himax HM2172 */ -+ IPU_SENSOR_CONFIG("HIMX2172", 1, 384000000), -+ /* GalaxyCore GC0310 */ -+ IPU_SENSOR_CONFIG("INT0310", 0), - /* Omnivision OV5693 */ - IPU_SENSOR_CONFIG("INT33BE", 1, 419200000), -+ /* Omnivision OV2740 */ -+ IPU_SENSOR_CONFIG("INT3474", 1, 180000000), - /* Omnivision OV8865 */ - IPU_SENSOR_CONFIG("INT347A", 1, 360000000), - /* Omnivision OV7251 */ - IPU_SENSOR_CONFIG("INT347E", 1, 319200000), -+ /* Hynix Hi-556 */ -+ IPU_SENSOR_CONFIG("INT3537", 1, 437000000), -+ /* Omnivision OV01A10 / OV01A1S */ -+ IPU_SENSOR_CONFIG("OVTI01A0", 1, 400000000), -+ IPU_SENSOR_CONFIG("OVTI01AS", 1, 400000000), -+ /* Omnivision OV02C10 */ -+ IPU_SENSOR_CONFIG("OVTI02C1", 1, 400000000), -+ /* Omnivision OV02E10 */ -+ IPU_SENSOR_CONFIG("OVTI02E1", 1, 360000000), -+ /* Omnivision OV08A10 */ -+ IPU_SENSOR_CONFIG("OVTI08A1", 1, 500000000), -+ /* Omnivision OV08x40 */ -+ IPU_SENSOR_CONFIG("OVTI08F4", 1, 400000000), -+ /* Omnivision OV13B10 */ -+ IPU_SENSOR_CONFIG("OVTI13B1", 1, 560000000), -+ IPU_SENSOR_CONFIG("OVTIDB10", 1, 560000000), - /* Omnivision OV2680 */ - IPU_SENSOR_CONFIG("OVTI2680", 1, 331200000), -- /* Omnivision ov8856 */ -+ /* Omnivision OV8856 */ - IPU_SENSOR_CONFIG("OVTI8856", 3, 180000000, 360000000, 720000000), -- /* Omnivision ov2740 */ -- IPU_SENSOR_CONFIG("INT3474", 1, 180000000), -- /* Hynix hi556 */ -- IPU_SENSOR_CONFIG("INT3537", 1, 437000000), -- /* Omnivision ov13b10 */ -- IPU_SENSOR_CONFIG("OVTIDB10", 1, 560000000), -- /* GalaxyCore GC0310 */ -- IPU_SENSOR_CONFIG("INT0310", 0), -- /* Omnivision ov01a10 */ -- IPU_SENSOR_CONFIG("OVTI01A0", 1, 400000000), - }; +diff --git a/drivers/media/platform/qcom/camss/camss-video.c b/drivers/media/platform/qcom/camss/camss-video.c +index cd72feca618c..3b8fc31d957c 100644 +--- a/drivers/media/platform/qcom/camss/camss-video.c ++++ b/drivers/media/platform/qcom/camss/camss-video.c +@@ -297,12 +297,6 @@ static void video_stop_streaming(struct vb2_queue *q) + + ret = v4l2_subdev_call(subdev, video, s_stream, 0); + +- if (entity->use_count > 1) { +- /* Don't stop if other instances of the pipeline are still running */ +- dev_dbg(video->camss->dev, "Video pipeline still used, don't stop streaming.\n"); +- return; +- } +- + if (ret) { + dev_err(video->camss->dev, "Video pipeline stop failed: %d\n", ret); + return; +diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c +index 51b1d3550421..d64985ca6e88 100644 +--- a/drivers/media/platform/qcom/camss/camss.c ++++ b/drivers/media/platform/qcom/camss/camss.c +@@ -2283,6 +2283,8 @@ static int camss_probe(struct platform_device *pdev) + + v4l2_async_nf_init(&camss->notifier, &camss->v4l2_dev); + ++ pm_runtime_enable(dev); ++ + num_subdevs = camss_of_parse_ports(camss); + if (num_subdevs < 0) { + ret = num_subdevs; +@@ -2323,8 +2325,6 @@ static int camss_probe(struct platform_device *pdev) + } + } + +- pm_runtime_enable(dev); +- + return 0; + + err_register_subdevs: +@@ -2332,6 +2332,7 @@ static int camss_probe(struct platform_device *pdev) + err_v4l2_device_unregister: + v4l2_device_unregister(&camss->v4l2_dev); + v4l2_async_nf_cleanup(&camss->notifier); ++ pm_runtime_disable(dev); + err_genpd_cleanup: + camss_genpd_cleanup(camss); - static const struct ipu_property_names prop_names = { diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c -index 206b76156c051..42a6117c139db 100644 +index 5d57ea27dbc4..304afc09fc11 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -4446,6 +4446,30 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, @@ -1693,10 +1728,10 @@ index 206b76156c051..42a6117c139db 100644 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) * class code. Fix it. diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c -index 5dd100175ec61..b7f3cb9bb3899 100644 +index 53896df7ec2b..98e08f10f60e 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c -@@ -120,6 +120,14 @@ static const char *sd_cache_types[] = { +@@ -122,6 +122,14 @@ static const char *sd_cache_types[] = { "write back, no read (daft)" }; @@ -1708,10 +1743,10 @@ index 5dd100175ec61..b7f3cb9bb3899 100644 +MODULE_PARM_DESC(probe, "async or sync. Setting to 'sync' disables asynchronous " + "device number assignments (sda, sdb, ...)."); + - static void sd_set_flush_flag(struct scsi_disk *sdkp) + static void sd_set_flush_flag(struct scsi_disk *sdkp, + struct queue_limits *lim) { - bool wc = false, fua = false; -@@ -4255,6 +4263,8 @@ static int __init init_sd(void) +@@ -4349,6 +4357,8 @@ static int __init init_sd(void) goto err_out_class; } @@ -1721,7 +1756,7 @@ index 5dd100175ec61..b7f3cb9bb3899 100644 if (err) goto err_out_driver; diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c -index 4b93c0bd1d4bc..b98906237306d 100644 +index 4b93c0bd1d4b..b98906237306 100644 --- a/drivers/usb/core/hub.c +++ b/drivers/usb/core/hub.c @@ -5844,6 +5844,13 @@ static void hub_event(struct work_struct *work) @@ -1739,19 +1774,20 @@ index 4b93c0bd1d4bc..b98906237306d 100644 * disconnected while waiting for the lock to succeed. */ usb_lock_device(hdev); diff --git a/include/linux/crypto.h b/include/linux/crypto.h -index b164da5e129e8..59021b8609a70 100644 +index b164da5e129e..72bfb79b491d 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h -@@ -133,6 +133,7 @@ - #define CRYPTO_TFM_REQ_FORBID_WEAK_KEYS 0x00000100 +@@ -134,6 +134,8 @@ #define CRYPTO_TFM_REQ_MAY_SLEEP 0x00000200 #define CRYPTO_TFM_REQ_MAY_BACKLOG 0x00000400 -+#define CRYPTO_TFM_REQ_NEED_RESEED 0x00000800 ++#define CRYPTO_TFM_FIPS_COMPLIANCE 0x80000000 ++ /* * Miscellaneous stuff. + */ diff --git a/include/linux/efi.h b/include/linux/efi.h -index 418e555459da7..fdd941287ae1d 100644 +index 6bf3c4fe8511..67e5400f7644 100644 --- a/include/linux/efi.h +++ b/include/linux/efi.h @@ -45,6 +45,8 @@ struct screen_info; @@ -1763,7 +1799,7 @@ index 418e555459da7..fdd941287ae1d 100644 typedef unsigned long efi_status_t; typedef u8 efi_bool_t; typedef u16 efi_char16_t; /* UNICODE character */ -@@ -872,6 +874,14 @@ static inline int efi_range_is_wc(unsigned long start, unsigned long len) +@@ -877,6 +879,14 @@ static inline int efi_range_is_wc(unsigned long start, unsigned long len) #define EFI_MEM_ATTR 10 /* Did firmware publish an EFI_MEMORY_ATTRIBUTES table? */ #define EFI_MEM_NO_SOFT_RESERVE 11 /* Is the kernel configured to ignore soft reservations? */ #define EFI_PRESERVE_BS_REGIONS 12 /* Are EFI boot-services memory segments available? */ @@ -1778,7 +1814,7 @@ index 418e555459da7..fdd941287ae1d 100644 #ifdef CONFIG_EFI /* -@@ -883,6 +893,8 @@ static inline bool efi_enabled(int feature) +@@ -888,6 +898,8 @@ static inline bool efi_enabled(int feature) } extern void efi_reboot(enum reboot_mode reboot_mode, const char *__unused); @@ -1787,7 +1823,7 @@ index 418e555459da7..fdd941287ae1d 100644 bool __pure __efi_soft_reserve_enabled(void); static inline bool __pure efi_soft_reserve_enabled(void) -@@ -904,6 +916,8 @@ static inline bool efi_enabled(int feature) +@@ -909,6 +921,8 @@ static inline bool efi_enabled(int feature) static inline void efi_reboot(enum reboot_mode reboot_mode, const char *__unused) {} @@ -1796,7 +1832,7 @@ index 418e555459da7..fdd941287ae1d 100644 static inline bool efi_soft_reserve_enabled(void) { return false; -@@ -918,6 +932,7 @@ static inline void efi_find_mirror(void) {} +@@ -923,6 +937,7 @@ static inline void efi_find_mirror(void) {} #endif extern int efi_status_to_err(efi_status_t status); @@ -1804,7 +1840,7 @@ index 418e555459da7..fdd941287ae1d 100644 /* * Variable Attributes -@@ -1133,13 +1148,6 @@ static inline bool efi_runtime_disabled(void) { return true; } +@@ -1138,13 +1153,6 @@ static inline bool efi_runtime_disabled(void) { return true; } extern void efi_call_virt_check_flags(unsigned long flags, const void *caller); extern unsigned long efi_call_virt_save_flags(void); @@ -1819,7 +1855,7 @@ index 418e555459da7..fdd941287ae1d 100644 enum efi_secureboot_mode efi_get_secureboot_mode(efi_get_variable_t *get_var) { diff --git a/include/linux/lsm_hook_defs.h b/include/linux/lsm_hook_defs.h -index 19c333fafe113..db33ee7f55d54 100644 +index 19c333fafe11..db33ee7f55d5 100644 --- a/include/linux/lsm_hook_defs.h +++ b/include/linux/lsm_hook_defs.h @@ -439,6 +439,8 @@ LSM_HOOK(int, 0, bpf_token_capable, const struct bpf_token *token, int cap) @@ -1831,36 +1867,8 @@ index 19c333fafe113..db33ee7f55d54 100644 #ifdef CONFIG_PERF_EVENTS LSM_HOOK(int, 0, perf_event_open, struct perf_event_attr *attr, int type) -diff --git a/include/linux/random.h b/include/linux/random.h -index b0a940af4fff5..8a52424fd0d50 100644 ---- a/include/linux/random.h -+++ b/include/linux/random.h -@@ -9,6 +9,13 @@ - - #include <uapi/linux/random.h> - -+struct iov_iter; -+ -+struct random_extrng { -+ ssize_t (*extrng_read_iter)(struct iov_iter *iter, bool reseed); -+ struct module *owner; -+}; -+ - struct notifier_block; - - void add_device_randomness(const void *buf, size_t len); -@@ -157,6 +164,9 @@ int random_prepare_cpu(unsigned int cpu); - int random_online_cpu(unsigned int cpu); - #endif - -+void random_register_extrng(const struct random_extrng *rng); -+void random_unregister_extrng(void); -+ - #ifndef MODULE - extern const struct file_operations random_fops, urandom_fops; - #endif diff --git a/include/linux/rmi.h b/include/linux/rmi.h -index ab7eea01ab427..fff7c5f737fc8 100644 +index ab7eea01ab42..fff7c5f737fc 100644 --- a/include/linux/rmi.h +++ b/include/linux/rmi.h @@ -364,6 +364,7 @@ struct rmi_driver_data { @@ -1872,7 +1880,7 @@ index ab7eea01ab427..fff7c5f737fc8 100644 int rmi_register_transport_device(struct rmi_transport_dev *xport); diff --git a/include/linux/security.h b/include/linux/security.h -index de3af33e6ff50..0a37270070e4c 100644 +index 1390f1efb4f0..b9a8ccb1dbdc 100644 --- a/include/linux/security.h +++ b/include/linux/security.h @@ -507,6 +507,7 @@ int security_inode_notifysecctx(struct inode *inode, void *ctx, u32 ctxlen); @@ -1895,7 +1903,7 @@ index de3af33e6ff50..0a37270070e4c 100644 u32 *uctx_len, void *val, size_t val_len, u64 id, u64 flags) diff --git a/kernel/module/signing.c b/kernel/module/signing.c -index a2ff4242e623d..f0d2be1ee4f1c 100644 +index a2ff4242e623..f0d2be1ee4f1 100644 --- a/kernel/module/signing.c +++ b/kernel/module/signing.c @@ -61,10 +61,17 @@ int mod_verify_sig(const void *mod, struct load_info *info) @@ -1918,7 +1926,7 @@ index a2ff4242e623d..f0d2be1ee4f1c 100644 int module_sig_check(struct load_info *info, int flags) diff --git a/scripts/sign-file.c b/scripts/sign-file.c -index 3edb156ae52c3..0114ae1dbf7ff 100644 +index 3edb156ae52c..0114ae1dbf7f 100644 --- a/scripts/sign-file.c +++ b/scripts/sign-file.c @@ -27,7 +27,6 @@ @@ -1972,7 +1980,7 @@ index 3edb156ae52c3..0114ae1dbf7ff 100644 BIO *b; diff --git a/scripts/tags.sh b/scripts/tags.sh -index 191e0461d6d5b..e6f418b3e948b 100755 +index 191e0461d6d5..e6f418b3e948 100755 --- a/scripts/tags.sh +++ b/scripts/tags.sh @@ -16,6 +16,8 @@ fi @@ -1985,7 +1993,7 @@ index 191e0461d6d5b..e6f418b3e948b 100755 # ignore arbitrary directories if [ -n "${IGNORE_DIRS}" ]; then diff --git a/security/integrity/platform_certs/load_uefi.c b/security/integrity/platform_certs/load_uefi.c -index d1fdd113450a6..182e8090cfe85 100644 +index d1fdd113450a..182e8090cfe8 100644 --- a/security/integrity/platform_certs/load_uefi.c +++ b/security/integrity/platform_certs/load_uefi.c @@ -74,7 +74,8 @@ static __init void *get_cert_list(efi_char16_t *name, efi_guid_t *guid, @@ -2009,7 +2017,7 @@ index d1fdd113450a6..182e8090cfe85 100644 } diff --git a/security/lockdown/Kconfig b/security/lockdown/Kconfig -index e84ddf4840101..d0501353a4b95 100644 +index e84ddf484010..d0501353a4b9 100644 --- a/security/lockdown/Kconfig +++ b/security/lockdown/Kconfig @@ -16,6 +16,19 @@ config SECURITY_LOCKDOWN_LSM_EARLY @@ -2033,7 +2041,7 @@ index e84ddf4840101..d0501353a4b95 100644 prompt "Kernel default lockdown mode" default LOCK_DOWN_KERNEL_FORCE_NONE diff --git a/security/lockdown/lockdown.c b/security/lockdown/lockdown.c -index cd84d8ea1dfbf..e4c70a0312bc8 100644 +index cd84d8ea1dfb..e4c70a0312bc 100644 --- a/security/lockdown/lockdown.c +++ b/security/lockdown/lockdown.c @@ -74,6 +74,7 @@ static int lockdown_is_locked_down(enum lockdown_reason what) @@ -2045,7 +2053,7 @@ index cd84d8ea1dfbf..e4c70a0312bc8 100644 const struct lsm_id lockdown_lsmid = { diff --git a/security/security.c b/security/security.c -index 43166e341526c..b8cf110aeb589 100644 +index 43166e341526..b8cf110aeb58 100644 --- a/security/security.c +++ b/security/security.c @@ -5630,6 +5630,18 @@ int security_locked_down(enum lockdown_reason what) diff --git a/SOURCES/rog-ally-audio-fix.patch b/SOURCES/rog-ally-audio-fix.patch deleted file mode 100644 index 5bd8e03..0000000 --- a/SOURCES/rog-ally-audio-fix.patch +++ /dev/null @@ -1,65 +0,0 @@ -diff --git a/sound/pci/hda/cs35l41_hda_property.c b/sound/pci/hda/cs35l41_hda_property.c -index 2b8f8fd52..f4933be4c 100644 ---- a/sound/pci/hda/cs35l41_hda_property.c -+++ b/sound/pci/hda/cs35l41_hda_property.c -@@ -6,8 +6,10 @@ - // - // Author: Stefan Binding <sbinding@opensource.cirrus.com> - -+#include <linux/dmi.h> - #include <linux/acpi.h> - #include <linux/gpio/consumer.h> -+#include <linux/kernel.h> - #include <linux/string.h> - #include "cs35l41_hda_property.h" - #include <linux/spi/spi.h> -@@ -335,6 +337,40 @@ static int lenovo_legion_no_acpi(struct cs35l41_hda *cs35l41, struct device *phy - return 0; - } - -+static int asus_rog_2023_ally_fix(struct cs35l41_hda *cs35l41, struct device *physdev, int id, -+ const char *hid) -+{ -+ const char *rog_ally_bios_ver = dmi_get_system_info(DMI_BIOS_VERSION); -+ const char *rog_ally_bios_num = rog_ally_bios_ver + 6; // Dropping the RC71L. part before the number -+ int rog_ally_bios_int; -+ kstrtoint(rog_ally_bios_num, 10, &rog_ally_bios_int); -+ if(rog_ally_bios_int >= 330){ -+ printk(KERN_INFO "DSD properties exist in the %d BIOS. Not applying DSD override...\n", rog_ally_bios_int); -+ return -ENOENT; //Patch not applicable. Exiting... -+ } -+ -+ struct cs35l41_hw_cfg *hw_cfg = &cs35l41->hw_cfg; -+ -+ dev_info(cs35l41->dev, "Adding DSD properties for %s\n", cs35l41->acpi_subsystem_id); -+ -+ cs35l41->index = id == 0x40 ? 0 : 1; -+ cs35l41->channel_index = 0; -+ cs35l41->reset_gpio = gpiod_get_index(physdev, NULL, 0, GPIOD_OUT_HIGH); -+ cs35l41->speaker_id = cs35l41_get_speaker_id(physdev, 0, 0, 2); -+ hw_cfg->spk_pos = cs35l41->index; -+ hw_cfg->gpio1.func = CS35L41_NOT_USED; -+ hw_cfg->gpio1.valid = true; -+ hw_cfg->gpio2.func = CS35L41_INTERRUPT; -+ hw_cfg->gpio2.valid = true; -+ hw_cfg->bst_type = CS35L41_INT_BOOST; -+ hw_cfg->bst_ind = 1000; /* 1,000nH Inductance value */ -+ hw_cfg->bst_ipk = 4500; /* 4,500mA peak current */ -+ hw_cfg->bst_cap = 24; /* 24 microFarad cap value */ -+ hw_cfg->valid = true; -+ -+ return 0; -+} -+ - struct cs35l41_prop_model { - const char *hid; - const char *ssid; -@@ -418,7 +418,7 @@ - { "CSC3551", "104316A3", generic_dsd_config }, - { "CSC3551", "104316D3", generic_dsd_config }, - { "CSC3551", "104316F3", generic_dsd_config }, -- { "CSC3551", "104317F3", generic_dsd_config }, -+ { "CSC3551", "104317F3", asus_rog_2023_ally_fix }, - { "CSC3551", "10431863", generic_dsd_config }, - { "CSC3551", "104318D3", generic_dsd_config }, - { "CSC3551", "10431A83", generic_dsd_config }, diff --git a/SOURCES/rog-ally-gyro-fix.patch b/SOURCES/rog-ally-gyro-fix.patch deleted file mode 100644 index bed6fc7..0000000 --- a/SOURCES/rog-ally-gyro-fix.patch +++ /dev/null @@ -1,128 +0,0 @@ -From: Jonathan LoBue <jlobue10@gmail.com> -Date: Sun, 25 Feb 2024 14:43:01 -0800 -Subject: [PATCH] iio: imu: bmi323: Implement ACPI method ROTM for mount matrix - -Retrieve mount matrix from ACPI ROTM table. - ---- - drivers/iio/imu/bmi323/bmi323_core.c | 79 ++++++++++++++++++++++++++-- - 1 file changed, 76 insertions(+), 3 deletions(-) - -diff --git a/drivers/iio/imu/bmi323/bmi323_core.c b/drivers/iio/imu/bmi323/bmi323_core.c -index 183af482828f..bb9f05183814 100644 ---- a/drivers/iio/imu/bmi323/bmi323_core.c -+++ b/drivers/iio/imu/bmi323/bmi323_core.c -@@ -7,6 +7,7 @@ - * Datasheet: https://www.bosch-sensortec.com/media/boschsensortec/downloads/datasheets/bst-bmi323-ds000.pdf - */ - -+#include <linux/acpi.h> - #include <linux/bitfield.h> - #include <linux/cleanup.h> - #include <linux/device.h> -@@ -1997,6 +1998,76 @@ static int bmi323_set_bw(struct bmi323_data *data, - FIELD_PREP(BMI323_ACC_GYRO_CONF_BW_MSK, bw)); - } - -+static bool bmi323_acpi_orientation(struct device *dev, -+ struct iio_mount_matrix *orientation) -+{ -+ struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; -+ struct acpi_device *adev = ACPI_COMPANION(dev); -+ char *str; -+ union acpi_object *obj, *elements; -+ acpi_status status; -+ int i, j, val[3]; -+ bool ret = false; -+ -+ if (!acpi_has_method(adev->handle, "ROTM")) -+ return false; -+ -+ status = acpi_evaluate_object(adev->handle, "ROTM", NULL, &buffer); -+ if (ACPI_FAILURE(status)) { -+ dev_err(dev, "Failed to get ACPI mount matrix: %d\n", status); -+ return false; -+ } -+ -+ obj = buffer.pointer; -+ if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3) { -+ dev_err(dev, "Unknown ACPI mount matrix package format\n"); -+ goto out_free_buffer; -+ } -+ -+ elements = obj->package.elements; -+ for (i = 0; i < 3; i++) { -+ if (elements[i].type != ACPI_TYPE_STRING) { -+ dev_err(dev, "Unknown ACPI mount matrix element format\n"); -+ goto out_free_buffer; -+ } -+ -+ str = elements[i].string.pointer; -+ if (sscanf(str, "%d %d %d", &val[0], &val[1], &val[2]) != 3) { -+ dev_err(dev, "Incorrect ACPI mount matrix string format\n"); -+ goto out_free_buffer; -+ } -+ -+ for (j = 0; j < 3; j++) { -+ switch (val[j]) { -+ case -1: str = "-1"; break; -+ case 0: str = "0"; break; -+ case 1: str = "1"; break; -+ default: -+ dev_err(dev, "Invalid value in ACPI mount matrix: %d\n", val[j]); -+ goto out_free_buffer; -+ } -+ orientation->rotation[i * 3 + j] = str; -+ } -+ } -+ -+ ret = true; -+ -+out_free_buffer: -+ kfree(buffer.pointer); -+ return ret; -+} -+ -+static bool bmi323_apply_acpi_orientation(struct device *dev, -+ struct iio_mount_matrix *orientation) -+{ -+ struct acpi_device *adev = ACPI_COMPANION(dev); -+ -+ if (adev) -+ return bmi323_acpi_orientation(dev, orientation); -+ -+ return false; -+} -+ - static int bmi323_init(struct bmi323_data *data) - { - int ret, val; -@@ -2099,9 +2170,11 @@ int bmi323_core_probe(struct device *dev) - if (ret) - return -EINVAL; - -- ret = iio_read_mount_matrix(dev, &data->orientation); -- if (ret) -- return ret; -+ if (!bmi323_apply_acpi_orientation(dev, &data->orientation)) { -+ ret = iio_read_mount_matrix(dev, &data->orientation); -+ if (ret) -+ return ret; -+ } - - indio_dev->name = "bmi323-imu"; - indio_dev->info = &bmi323_info; -diff --git a/drivers/iio/imu/bmi323/bmi323_core.c b/drivers/iio/imu/bmi323/bmi323_core.c -index 0bd5ded..ded8596 100644 ---- a/drivers/iio/imu/bmi323/bmi323_core.c -+++ b/drivers/iio/imu/bmi323/bmi323_core.c -@@ -285,6 +286,9 @@ static const int bmi323_acc_gyro_odr[][2] = { - { 200, 0 }, - { 400, 0 }, - { 800, 0 }, -+ { 1600, 0}, -+ { 3200, 0}, -+ { 6400, 0}, - }; - - static const int bmi323_acc_gyro_odrns[] = { diff --git a/SOURCES/rpminspect.yaml b/SOURCES/rpminspect.yaml index d6287e6..84a2606 100644 --- a/SOURCES/rpminspect.yaml +++ b/SOURCES/rpminspect.yaml @@ -23,7 +23,7 @@ emptyrpm: patches: ignore_list: - linux-kernel-test.patch - - patch-6.10-redhat.patch + - patch-6.11-redhat.patch runpath: ignore: diff --git a/SOURCES/scx-kernel.patch b/SOURCES/scx-kernel.patch index 29e1f22..196bac1 100644 --- a/SOURCES/scx-kernel.patch +++ b/SOURCES/scx-kernel.patch @@ -1,3 +1,184 @@ +From 11276ed2c72c57624c1214e980efd24648be015c Mon Sep 17 00:00:00 2001 +From: Peter Jung <admin@ptr1337.dev> +Date: Fri, 4 Oct 2024 17:12:13 +0200 +Subject: [PATCH] sched-ext + +Signed-off-by: Peter Jung <admin@ptr1337.dev> +--- + Documentation/scheduler/index.rst | 1 + + Documentation/scheduler/sched-ext.rst | 326 + + MAINTAINERS | 13 + + drivers/tty/sysrq.c | 1 + + include/asm-generic/vmlinux.lds.h | 1 + + include/linux/cgroup.h | 4 +- + include/linux/sched.h | 5 + + include/linux/sched/ext.h | 216 + + include/linux/sched/task.h | 8 +- + include/trace/events/sched_ext.h | 32 + + include/uapi/linux/sched.h | 1 + + init/Kconfig | 10 + + init/init_task.c | 12 + + kernel/Kconfig.preempt | 27 +- + kernel/fork.c | 17 +- + kernel/sched/build_policy.c | 11 + + kernel/sched/core.c | 288 +- + kernel/sched/cpufreq_schedutil.c | 50 +- + kernel/sched/debug.c | 3 + + kernel/sched/ext.c | 7262 +++++++++++++++++ + kernel/sched/ext.h | 91 + + kernel/sched/fair.c | 21 +- + kernel/sched/idle.c | 2 + + kernel/sched/sched.h | 203 +- + kernel/sched/syscalls.c | 26 + + lib/dump_stack.c | 1 + + tools/Makefile | 10 +- + tools/sched_ext/.gitignore | 2 + + tools/sched_ext/Makefile | 246 + + tools/sched_ext/README.md | 270 + + .../sched_ext/include/bpf-compat/gnu/stubs.h | 11 + + tools/sched_ext/include/scx/common.bpf.h | 427 + + tools/sched_ext/include/scx/common.h | 75 + + tools/sched_ext/include/scx/compat.bpf.h | 47 + + tools/sched_ext/include/scx/compat.h | 186 + + tools/sched_ext/include/scx/user_exit_info.h | 115 + + tools/sched_ext/scx_central.bpf.c | 361 + + tools/sched_ext/scx_central.c | 135 + + tools/sched_ext/scx_flatcg.bpf.c | 957 +++ + tools/sched_ext/scx_flatcg.c | 233 + + tools/sched_ext/scx_flatcg.h | 51 + + tools/sched_ext/scx_qmap.bpf.c | 813 ++ + tools/sched_ext/scx_qmap.c | 153 + + tools/sched_ext/scx_show_state.py | 40 + + tools/sched_ext/scx_simple.bpf.c | 156 + + tools/sched_ext/scx_simple.c | 107 + + tools/testing/selftests/sched_ext/.gitignore | 6 + + tools/testing/selftests/sched_ext/Makefile | 218 + + tools/testing/selftests/sched_ext/config | 9 + + .../selftests/sched_ext/create_dsq.bpf.c | 58 + + .../testing/selftests/sched_ext/create_dsq.c | 57 + + .../sched_ext/ddsp_bogus_dsq_fail.bpf.c | 42 + + .../selftests/sched_ext/ddsp_bogus_dsq_fail.c | 57 + + .../sched_ext/ddsp_vtimelocal_fail.bpf.c | 39 + + .../sched_ext/ddsp_vtimelocal_fail.c | 56 + + .../selftests/sched_ext/dsp_local_on.bpf.c | 65 + + .../selftests/sched_ext/dsp_local_on.c | 58 + + .../sched_ext/enq_last_no_enq_fails.bpf.c | 21 + + .../sched_ext/enq_last_no_enq_fails.c | 60 + + .../sched_ext/enq_select_cpu_fails.bpf.c | 43 + + .../sched_ext/enq_select_cpu_fails.c | 61 + + tools/testing/selftests/sched_ext/exit.bpf.c | 84 + + tools/testing/selftests/sched_ext/exit.c | 55 + + tools/testing/selftests/sched_ext/exit_test.h | 20 + + .../testing/selftests/sched_ext/hotplug.bpf.c | 61 + + tools/testing/selftests/sched_ext/hotplug.c | 168 + + .../selftests/sched_ext/hotplug_test.h | 15 + + .../sched_ext/init_enable_count.bpf.c | 53 + + .../selftests/sched_ext/init_enable_count.c | 166 + + .../testing/selftests/sched_ext/maximal.bpf.c | 164 + + tools/testing/selftests/sched_ext/maximal.c | 51 + + .../selftests/sched_ext/maybe_null.bpf.c | 36 + + .../testing/selftests/sched_ext/maybe_null.c | 49 + + .../sched_ext/maybe_null_fail_dsp.bpf.c | 25 + + .../sched_ext/maybe_null_fail_yld.bpf.c | 28 + + .../testing/selftests/sched_ext/minimal.bpf.c | 21 + + tools/testing/selftests/sched_ext/minimal.c | 58 + + .../selftests/sched_ext/prog_run.bpf.c | 33 + + tools/testing/selftests/sched_ext/prog_run.c | 78 + + .../testing/selftests/sched_ext/reload_loop.c | 75 + + tools/testing/selftests/sched_ext/runner.c | 201 + + tools/testing/selftests/sched_ext/scx_test.h | 131 + + .../selftests/sched_ext/select_cpu_dfl.bpf.c | 40 + + .../selftests/sched_ext/select_cpu_dfl.c | 72 + + .../sched_ext/select_cpu_dfl_nodispatch.bpf.c | 89 + + .../sched_ext/select_cpu_dfl_nodispatch.c | 72 + + .../sched_ext/select_cpu_dispatch.bpf.c | 41 + + .../selftests/sched_ext/select_cpu_dispatch.c | 70 + + .../select_cpu_dispatch_bad_dsq.bpf.c | 37 + + .../sched_ext/select_cpu_dispatch_bad_dsq.c | 56 + + .../select_cpu_dispatch_dbl_dsp.bpf.c | 38 + + .../sched_ext/select_cpu_dispatch_dbl_dsp.c | 56 + + .../sched_ext/select_cpu_vtime.bpf.c | 92 + + .../selftests/sched_ext/select_cpu_vtime.c | 59 + + .../selftests/sched_ext/test_example.c | 49 + + tools/testing/selftests/sched_ext/util.c | 71 + + tools/testing/selftests/sched_ext/util.h | 13 + + 97 files changed, 16174 insertions(+), 130 deletions(-) + create mode 100644 Documentation/scheduler/sched-ext.rst + create mode 100644 include/linux/sched/ext.h + create mode 100644 include/trace/events/sched_ext.h + create mode 100644 kernel/sched/ext.c + create mode 100644 kernel/sched/ext.h + create mode 100644 tools/sched_ext/.gitignore + create mode 100644 tools/sched_ext/Makefile + create mode 100644 tools/sched_ext/README.md + create mode 100644 tools/sched_ext/include/bpf-compat/gnu/stubs.h + create mode 100644 tools/sched_ext/include/scx/common.bpf.h + create mode 100644 tools/sched_ext/include/scx/common.h + create mode 100644 tools/sched_ext/include/scx/compat.bpf.h + create mode 100644 tools/sched_ext/include/scx/compat.h + create mode 100644 tools/sched_ext/include/scx/user_exit_info.h + create mode 100644 tools/sched_ext/scx_central.bpf.c + create mode 100644 tools/sched_ext/scx_central.c + create mode 100644 tools/sched_ext/scx_flatcg.bpf.c + create mode 100644 tools/sched_ext/scx_flatcg.c + create mode 100644 tools/sched_ext/scx_flatcg.h + create mode 100644 tools/sched_ext/scx_qmap.bpf.c + create mode 100644 tools/sched_ext/scx_qmap.c + create mode 100644 tools/sched_ext/scx_show_state.py + create mode 100644 tools/sched_ext/scx_simple.bpf.c + create mode 100644 tools/sched_ext/scx_simple.c + create mode 100644 tools/testing/selftests/sched_ext/.gitignore + create mode 100644 tools/testing/selftests/sched_ext/Makefile + create mode 100644 tools/testing/selftests/sched_ext/config + create mode 100644 tools/testing/selftests/sched_ext/create_dsq.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/create_dsq.c + create mode 100644 tools/testing/selftests/sched_ext/ddsp_bogus_dsq_fail.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/ddsp_bogus_dsq_fail.c + create mode 100644 tools/testing/selftests/sched_ext/ddsp_vtimelocal_fail.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/ddsp_vtimelocal_fail.c + create mode 100644 tools/testing/selftests/sched_ext/dsp_local_on.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/dsp_local_on.c + create mode 100644 tools/testing/selftests/sched_ext/enq_last_no_enq_fails.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/enq_last_no_enq_fails.c + create mode 100644 tools/testing/selftests/sched_ext/enq_select_cpu_fails.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/enq_select_cpu_fails.c + create mode 100644 tools/testing/selftests/sched_ext/exit.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/exit.c + create mode 100644 tools/testing/selftests/sched_ext/exit_test.h + create mode 100644 tools/testing/selftests/sched_ext/hotplug.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/hotplug.c + create mode 100644 tools/testing/selftests/sched_ext/hotplug_test.h + create mode 100644 tools/testing/selftests/sched_ext/init_enable_count.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/init_enable_count.c + create mode 100644 tools/testing/selftests/sched_ext/maximal.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/maximal.c + create mode 100644 tools/testing/selftests/sched_ext/maybe_null.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/maybe_null.c + create mode 100644 tools/testing/selftests/sched_ext/maybe_null_fail_dsp.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/maybe_null_fail_yld.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/minimal.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/minimal.c + create mode 100644 tools/testing/selftests/sched_ext/prog_run.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/prog_run.c + create mode 100644 tools/testing/selftests/sched_ext/reload_loop.c + create mode 100644 tools/testing/selftests/sched_ext/runner.c + create mode 100644 tools/testing/selftests/sched_ext/scx_test.h + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dfl.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dfl.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dfl_nodispatch.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dfl_nodispatch.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch_bad_dsq.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch_bad_dsq.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch_dbl_dsp.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_dispatch_dbl_dsp.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_vtime.bpf.c + create mode 100644 tools/testing/selftests/sched_ext/select_cpu_vtime.c + create mode 100644 tools/testing/selftests/sched_ext/test_example.c + create mode 100644 tools/testing/selftests/sched_ext/util.c + create mode 100644 tools/testing/selftests/sched_ext/util.h + diff --git a/Documentation/scheduler/index.rst b/Documentation/scheduler/index.rst index 43bd8a145b7a..0611dc3dda8e 100644 --- a/Documentation/scheduler/index.rst @@ -12,10 +193,10 @@ index 43bd8a145b7a..0611dc3dda8e 100644 text_files diff --git a/Documentation/scheduler/sched-ext.rst b/Documentation/scheduler/sched-ext.rst new file mode 100644 -index 000000000000..a707d2181a77 +index 000000000000..6c0d70e2e27d --- /dev/null +++ b/Documentation/scheduler/sched-ext.rst -@@ -0,0 +1,316 @@ +@@ -0,0 +1,326 @@ +========================== +Extensible Scheduler Class +========================== @@ -101,6 +282,15 @@ index 000000000000..a707d2181a77 + # cat /sys/kernel/sched_ext/root/ops + simple + ++You can check if any BPF scheduler has ever been loaded since boot by examining ++this monotonically incrementing counter (a value of zero indicates that no BPF ++scheduler has been loaded): ++ ++.. code-block:: none ++ ++ # cat /sys/kernel/sched_ext/enable_seq ++ 1 ++ +``tools/sched_ext/scx_show_state.py`` is a drgn script which shows more +detailed information: + @@ -114,6 +304,7 @@ index 000000000000..a707d2181a77 + enable_state : enabled (2) + bypass_depth : 0 + nr_rejected : 0 ++ enable_seq : 1 + +If ``CONFIG_SCHED_DEBUG`` is set, whether a given task is on sched_ext can +be determined as follows: @@ -333,10 +524,10 @@ index 000000000000..a707d2181a77 +possible, they are subject to change without warning between kernel +versions. diff --git a/MAINTAINERS b/MAINTAINERS -index 958e935449e5..17d2679d291a 100644 +index c2a7363e86fe..bcfe36daf67a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS -@@ -19917,6 +19917,19 @@ F: include/linux/wait.h +@@ -20364,6 +20364,19 @@ F: include/linux/wait.h F: include/uapi/linux/sched.h F: kernel/sched/ @@ -353,11 +544,11 @@ index 958e935449e5..17d2679d291a 100644 +F: tools/sched_ext/ +F: tools/testing/selftests/sched_ext + - SCSI LIBSAS SUBSYSTEM - R: John Garry <john.g.garry@oracle.com> - R: Jason Yan <yanaijie@huawei.com> + SCIOSENSE ENS160 MULTI-GAS SENSOR DRIVER + M: Gustavo Silva <gustavograzs@gmail.com> + S: Maintained diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c -index e5974b8239c9..167e877b8bef 100644 +index 14f8f00fdcf9..930b04e3d148 100644 --- a/drivers/tty/sysrq.c +++ b/drivers/tty/sysrq.c @@ -531,6 +531,7 @@ static const struct sysrq_key_op *sysrq_key_table[62] = { @@ -369,7 +560,7 @@ index e5974b8239c9..167e877b8bef 100644 NULL, /* T */ NULL, /* U */ diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h -index 70bf1004076b..a8417d31e348 100644 +index 1ae44793132a..19ec49a9179b 100644 --- a/include/asm-generic/vmlinux.lds.h +++ b/include/asm-generic/vmlinux.lds.h @@ -133,6 +133,7 @@ @@ -381,10 +572,10 @@ index 70bf1004076b..a8417d31e348 100644 __sched_class_lowest = .; diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h -index 2150ca60394b..3cdaec701600 100644 +index c60ba0ab1462..7139b33cb104 100644 --- a/include/linux/cgroup.h +++ b/include/linux/cgroup.h -@@ -29,8 +29,6 @@ +@@ -28,8 +28,6 @@ struct kernel_clone_args; @@ -393,7 +584,7 @@ index 2150ca60394b..3cdaec701600 100644 /* * All weight knobs on the default hierarchy should use the following min, * default and max values. The default value is the logarithmic center of -@@ -40,6 +38,8 @@ struct kernel_clone_args; +@@ -39,6 +37,8 @@ struct kernel_clone_args; #define CGROUP_WEIGHT_DFL 100 #define CGROUP_WEIGHT_MAX 10000 @@ -403,10 +594,10 @@ index 2150ca60394b..3cdaec701600 100644 CSS_TASK_ITER_PROCS = (1U << 0), /* walk only threadgroup leaders */ CSS_TASK_ITER_THREADED = (1U << 1), /* walk all threaded css_sets in the domain */ diff --git a/include/linux/sched.h b/include/linux/sched.h -index 76214d7c819d..0f3a107bcd02 100644 +index f8d150343d42..5b4f78fe379d 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h -@@ -80,6 +80,8 @@ struct task_group; +@@ -82,6 +82,8 @@ struct task_group; struct task_struct; struct user_event_mm; @@ -415,7 +606,7 @@ index 76214d7c819d..0f3a107bcd02 100644 /* * Task state bitmask. NOTE! These bits are also * encoded in fs/proc/array.c: get_task_state(). -@@ -802,6 +804,9 @@ struct task_struct { +@@ -810,6 +812,9 @@ struct task_struct { struct sched_rt_entity rt; struct sched_dl_entity dl; struct sched_dl_entity *dl_server; @@ -427,10 +618,10 @@ index 76214d7c819d..0f3a107bcd02 100644 #ifdef CONFIG_SCHED_CORE diff --git a/include/linux/sched/ext.h b/include/linux/sched/ext.h new file mode 100644 -index 000000000000..26e1c33bc844 +index 000000000000..76166d3b14fc --- /dev/null +++ b/include/linux/sched/ext.h -@@ -0,0 +1,204 @@ +@@ -0,0 +1,216 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * BPF extensible scheduler class: Documentation/scheduler/sched-ext.rst @@ -553,9 +744,17 @@ index 000000000000..26e1c33bc844 + __SCX_KF_TERMINAL = SCX_KF_ENQUEUE | SCX_KF_SELECT_CPU | SCX_KF_REST, +}; + ++enum scx_dsq_lnode_flags { ++ SCX_DSQ_LNODE_ITER_CURSOR = 1 << 0, ++ ++ /* high 16 bits can be for iter cursor flags */ ++ __SCX_DSQ_LNODE_PRIV_SHIFT = 16, ++}; ++ +struct scx_dsq_list_node { + struct list_head node; -+ bool is_bpf_iter_cursor; ++ u32 flags; ++ u32 priv; /* can be used by iter cursor */ +}; + +/* @@ -612,15 +811,19 @@ index 000000000000..26e1c33bc844 + * If set, reject future sched_setscheduler(2) calls updating the policy + * to %SCHED_EXT with -%EACCES. + * -+ * If set from ops.init_task() and the task's policy is already -+ * %SCHED_EXT, which can happen while the BPF scheduler is being loaded -+ * or by inhering the parent's policy during fork, the task's policy is -+ * rejected and forcefully reverted to %SCHED_NORMAL. The number of -+ * such events are reported through /sys/kernel/debug/sched_ext::nr_rejected. ++ * Can be set from ops.init_task() while the BPF scheduler is being ++ * loaded (!scx_init_task_args->fork). If set and the task's policy is ++ * already %SCHED_EXT, the task's policy is rejected and forcefully ++ * reverted to %SCHED_NORMAL. The number of such events are reported ++ * through /sys/kernel/debug/sched_ext::nr_rejected. Setting this flag ++ * during fork is not allowed. + */ + bool disallow; /* reject switching into SCX */ + + /* cold fields */ ++#ifdef CONFIG_EXT_GROUP_SCHED ++ struct cgroup *cgrp_moving_from; ++#endif + /* must be the last field, see init_scx_entity() */ + struct list_head tasks_node; +}; @@ -636,7 +839,7 @@ index 000000000000..26e1c33bc844 +#endif /* CONFIG_SCHED_CLASS_EXT */ +#endif /* _LINUX_SCHED_EXT_H */ diff --git a/include/linux/sched/task.h b/include/linux/sched/task.h -index d362aacf9f89..4df2f9055587 100644 +index d362aacf9f89..0f2aeb37bbb0 100644 --- a/include/linux/sched/task.h +++ b/include/linux/sched/task.h @@ -63,7 +63,8 @@ extern asmlinkage void schedule_tail(struct task_struct *prev); @@ -649,6 +852,18 @@ index d362aacf9f89..4df2f9055587 100644 extern void sched_post_fork(struct task_struct *p); extern void sched_dead(struct task_struct *p); +@@ -119,6 +120,11 @@ static inline struct task_struct *get_task_struct(struct task_struct *t) + return t; + } + ++static inline struct task_struct *tryget_task_struct(struct task_struct *t) ++{ ++ return refcount_inc_not_zero(&t->usage) ? t : NULL; ++} ++ + extern void __put_task_struct(struct task_struct *t); + extern void __put_task_struct_rcu_cb(struct rcu_head *rhp); + diff --git a/include/trace/events/sched_ext.h b/include/trace/events/sched_ext.h new file mode 100644 index 000000000000..fe19da7315a9 @@ -699,6 +914,37 @@ index 3bac0a8ceab2..359a14cc76a4 100644 /* Can be ORed in to make sure the process is reverted back to SCHED_NORMAL on fork */ #define SCHED_RESET_ON_FORK 0x40000000 +diff --git a/init/Kconfig b/init/Kconfig +index 08a0d51afaae..e1a88d48d652 100644 +--- a/init/Kconfig ++++ b/init/Kconfig +@@ -1028,9 +1028,13 @@ menuconfig CGROUP_SCHED + tasks. + + if CGROUP_SCHED ++config GROUP_SCHED_WEIGHT ++ def_bool n ++ + config FAIR_GROUP_SCHED + bool "Group scheduling for SCHED_OTHER" + depends on CGROUP_SCHED ++ select GROUP_SCHED_WEIGHT + default CGROUP_SCHED + + config CFS_BANDWIDTH +@@ -1055,6 +1059,12 @@ config RT_GROUP_SCHED + realtime bandwidth for them. + See Documentation/scheduler/sched-rt-group.rst for more information. + ++config EXT_GROUP_SCHED ++ bool ++ depends on SCHED_CLASS_EXT && CGROUP_SCHED ++ select GROUP_SCHED_WEIGHT ++ default y ++ + endif #CGROUP_SCHED + + config SCHED_MM_CID diff --git a/init/init_task.c b/init/init_task.c index eeb110c65fe2..e222722e790b 100644 --- a/init/init_task.c @@ -730,10 +976,10 @@ index eeb110c65fe2..e222722e790b 100644 .ptraced = LIST_HEAD_INIT(init_task.ptraced), .ptrace_entry = LIST_HEAD_INIT(init_task.ptrace_entry), diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt -index c2f1fd95a821..f3d140c3acc1 100644 +index c2f1fd95a821..fe782cd77388 100644 --- a/kernel/Kconfig.preempt +++ b/kernel/Kconfig.preempt -@@ -133,4 +133,28 @@ config SCHED_CORE +@@ -133,4 +133,29 @@ config SCHED_CORE which is the likely usage by Linux distributions, there should be no measurable impact on performance. @@ -741,6 +987,7 @@ index c2f1fd95a821..f3d140c3acc1 100644 +config SCHED_CLASS_EXT + bool "Extensible Scheduling Class" + depends on BPF_SYSCALL && BPF_JIT && DEBUG_INFO_BTF ++ select STACKTRACE if STACKTRACE_SUPPORT + help + This option enables a new scheduler class sched_ext (SCX), which + allows scheduling policies to be implemented as BPF programs to @@ -764,7 +1011,7 @@ index c2f1fd95a821..f3d140c3acc1 100644 + Documentation/scheduler/sched-ext.rst + https://github.com/sched-ext/scx diff --git a/kernel/fork.c b/kernel/fork.c -index 99076dbe27d8..741d962db0d9 100644 +index 238695afc630..69a0a7210060 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -23,6 +23,7 @@ @@ -775,7 +1022,7 @@ index 99076dbe27d8..741d962db0d9 100644 #include <linux/seq_file.h> #include <linux/rtmutex.h> #include <linux/init.h> -@@ -971,6 +972,7 @@ void __put_task_struct(struct task_struct *tsk) +@@ -973,6 +974,7 @@ void __put_task_struct(struct task_struct *tsk) WARN_ON(refcount_read(&tsk->usage)); WARN_ON(tsk == current); @@ -783,7 +1030,7 @@ index 99076dbe27d8..741d962db0d9 100644 io_uring_free(tsk); cgroup_free(tsk); task_numa_free(tsk, true); -@@ -2363,7 +2365,7 @@ __latent_entropy struct task_struct *copy_process( +@@ -2355,7 +2357,7 @@ __latent_entropy struct task_struct *copy_process( retval = perf_event_init_task(p, clone_flags); if (retval) @@ -792,7 +1039,7 @@ index 99076dbe27d8..741d962db0d9 100644 retval = audit_alloc(p); if (retval) goto bad_fork_cleanup_perf; -@@ -2496,7 +2498,9 @@ __latent_entropy struct task_struct *copy_process( +@@ -2488,7 +2490,9 @@ __latent_entropy struct task_struct *copy_process( * cgroup specific, it unconditionally needs to place the task on a * runqueue. */ @@ -803,7 +1050,7 @@ index 99076dbe27d8..741d962db0d9 100644 /* * From this point on we must avoid any synchronous user-space -@@ -2542,13 +2546,13 @@ __latent_entropy struct task_struct *copy_process( +@@ -2534,13 +2538,13 @@ __latent_entropy struct task_struct *copy_process( /* Don't start children in a dying pid namespace */ if (unlikely(!(ns_of_pid(pid)->pid_allocated & PIDNS_ADDING))) { retval = -ENOMEM; @@ -819,7 +1066,7 @@ index 99076dbe27d8..741d962db0d9 100644 } /* No more failure paths after this point. */ -@@ -2622,10 +2626,11 @@ __latent_entropy struct task_struct *copy_process( +@@ -2614,10 +2618,11 @@ __latent_entropy struct task_struct *copy_process( return p; @@ -832,7 +1079,7 @@ index 99076dbe27d8..741d962db0d9 100644 cgroup_cancel_fork(p, args); bad_fork_put_pidfd: if (clone_flags & CLONE_PIDFD) { -@@ -2664,6 +2669,8 @@ __latent_entropy struct task_struct *copy_process( +@@ -2656,6 +2661,8 @@ __latent_entropy struct task_struct *copy_process( audit_free(p); bad_fork_cleanup_perf: perf_event_free_task(p); @@ -842,7 +1089,7 @@ index 99076dbe27d8..741d962db0d9 100644 lockdep_free_task(p); #ifdef CONFIG_NUMA diff --git a/kernel/sched/build_policy.c b/kernel/sched/build_policy.c -index d9dc9ab3773f..e7d539bb721e 100644 +index 39c315182b35..fae1f5c921eb 100644 --- a/kernel/sched/build_policy.c +++ b/kernel/sched/build_policy.c @@ -16,18 +16,25 @@ @@ -871,18 +1118,20 @@ index d9dc9ab3773f..e7d539bb721e 100644 #include <uapi/linux/sched/types.h> -@@ -52,3 +59,6 @@ +@@ -52,4 +59,8 @@ #include "cputime.c" #include "deadline.c" +#ifdef CONFIG_SCHED_CLASS_EXT +# include "ext.c" +#endif ++ + #include "syscalls.c" diff --git a/kernel/sched/core.c b/kernel/sched/core.c -index ebf21373f663..fb6276f74ee6 100644 +index f3951e4a55e5..c792a6feb7a9 100644 --- a/kernel/sched/core.c +++ b/kernel/sched/core.c -@@ -168,7 +168,10 @@ static inline int __task_prio(const struct task_struct *p) +@@ -169,7 +169,10 @@ static inline int __task_prio(const struct task_struct *p) if (p->sched_class == &idle_sched_class) return MAX_RT_PRIO + NICE_WIDTH; /* 140 */ @@ -894,7 +1143,7 @@ index ebf21373f663..fb6276f74ee6 100644 } /* -@@ -197,6 +200,11 @@ static inline bool prio_less(const struct task_struct *a, +@@ -198,6 +201,11 @@ static inline bool prio_less(const struct task_struct *a, if (pa == MAX_RT_PRIO + MAX_NICE) /* fair */ return cfs_prio_less(a, b, in_fi); @@ -906,7 +1155,7 @@ index ebf21373f663..fb6276f74ee6 100644 return false; } -@@ -1254,11 +1262,14 @@ bool sched_can_stop_tick(struct rq *rq) +@@ -1255,11 +1263,14 @@ bool sched_can_stop_tick(struct rq *rq) return true; /* @@ -918,14 +1167,14 @@ index ebf21373f663..fb6276f74ee6 100644 + * involuntary preemption. For SCX, ask. */ - if (rq->nr_running > 1) -+ if (!scx_switched_all() && rq->nr_running > 1) ++ if (scx_enabled() && !scx_can_stop_tick(rq)) + return false; + -+ if (scx_enabled() && !scx_can_stop_tick(rq)) ++ if (rq->cfs.nr_running > 1) return false; /* -@@ -1340,8 +1351,8 @@ static void set_load_weight(struct task_struct *p, bool update_load) +@@ -1341,8 +1352,8 @@ void set_load_weight(struct task_struct *p, bool update_load) * SCHED_OTHER tasks have to update their load when changing their * weight */ @@ -936,7 +1185,7 @@ index ebf21373f663..fb6276f74ee6 100644 else p->se.load = lw; } -@@ -2210,6 +2221,17 @@ inline int task_curr(const struct task_struct *p) +@@ -2031,6 +2042,17 @@ inline int task_curr(const struct task_struct *p) return cpu_curr(task_cpu(p)) == p; } @@ -954,20 +1203,25 @@ index ebf21373f663..fb6276f74ee6 100644 /* * switched_from, switched_to and prio_changed must _NOT_ drop rq->lock, * use the balance_callback list if you want balancing. -@@ -2217,9 +2239,9 @@ inline int task_curr(const struct task_struct *p) - * this means any call to check_class_changed() must be followed by a call to - * balance_callback(). - */ --static inline void check_class_changed(struct rq *rq, struct task_struct *p, -- const struct sched_class *prev_class, -- int oldprio) -+void check_class_changed(struct rq *rq, struct task_struct *p, -+ const struct sched_class *prev_class, -+ int oldprio) +@@ -2289,7 +2311,7 @@ static inline bool rq_has_pinned_tasks(struct rq *rq) + static inline bool is_cpu_allowed(struct task_struct *p, int cpu) { - if (prev_class != p->sched_class) { - if (prev_class->switched_from) -@@ -3982,6 +4004,15 @@ bool cpus_share_resources(int this_cpu, int that_cpu) + /* When not in the task's cpumask, no point in looking further. */ +- if (!cpumask_test_cpu(cpu, p->cpus_ptr)) ++ if (!task_allowed_on_cpu(p, cpu)) + return false; + + /* migrate_disabled() must be allowed to finish. */ +@@ -2298,7 +2320,7 @@ static inline bool is_cpu_allowed(struct task_struct *p, int cpu) + + /* Non kernel threads are not allowed during either online or offline. */ + if (!(p->flags & PF_KTHREAD)) +- return cpu_active(cpu) && task_cpu_possible(cpu, p); ++ return cpu_active(cpu); + + /* KTHREAD_IS_PER_CPU is always allowed. */ + if (kthread_is_per_cpu(p)) +@@ -3775,6 +3797,15 @@ bool cpus_share_resources(int this_cpu, int that_cpu) static inline bool ttwu_queue_cond(struct task_struct *p, int cpu) { @@ -983,7 +1237,7 @@ index ebf21373f663..fb6276f74ee6 100644 /* * Do not complicate things with the async wake_list while the CPU is * in hotplug state. -@@ -4549,6 +4580,10 @@ static void __sched_fork(unsigned long clone_flags, struct task_struct *p) +@@ -4342,6 +4373,10 @@ static void __sched_fork(unsigned long clone_flags, struct task_struct *p) p->rt.on_rq = 0; p->rt.on_list = 0; @@ -994,7 +1248,7 @@ index ebf21373f663..fb6276f74ee6 100644 #ifdef CONFIG_PREEMPT_NOTIFIERS INIT_HLIST_HEAD(&p->preempt_notifiers); #endif -@@ -4789,10 +4824,18 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) +@@ -4582,10 +4617,18 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) if (dl_prio(p->prio)) return -EAGAIN; @@ -1015,7 +1269,7 @@ index ebf21373f663..fb6276f74ee6 100644 init_entity_runnable_average(&p->se); -@@ -4812,7 +4855,7 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) +@@ -4605,7 +4648,7 @@ int sched_fork(unsigned long clone_flags, struct task_struct *p) return 0; } @@ -1024,7 +1278,7 @@ index ebf21373f663..fb6276f74ee6 100644 { unsigned long flags; -@@ -4974,6 +4974,13 @@ +@@ -4632,11 +4675,19 @@ void sched_cgroup_fork(struct task_struct *p, struct kernel_clone_args *kargs) if (p->sched_class->task_fork) p->sched_class->task_fork(p); raw_spin_unlock_irqrestore(&p->pi_lock, flags); @@ -1038,15 +1292,13 @@ index ebf21373f663..fb6276f74ee6 100644 } void sched_post_fork(struct task_struct *p) -@@ -4982,6 +4989,7 @@ - sched_post_fork_bore(p); - #endif // CONFIG_SCHED_BORE + { uclamp_post_fork(p); + scx_post_fork(p); } unsigned long to_ratio(u64 period, u64 runtime) -@@ -5685,6 +5736,7 @@ void sched_tick(void) +@@ -5469,6 +5520,7 @@ void sched_tick(void) calc_global_load_tick(rq); sched_core_tick(rq); task_tick_mm_cid(rq, curr); @@ -1054,7 +1306,7 @@ index ebf21373f663..fb6276f74ee6 100644 rq_unlock(rq, &rf); -@@ -5697,8 +5749,10 @@ void sched_tick(void) +@@ -5481,8 +5533,10 @@ void sched_tick(void) wq_worker_tick(curr); #ifdef CONFIG_SMP @@ -1067,10 +1319,11 @@ index ebf21373f663..fb6276f74ee6 100644 #endif } -@@ -5989,7 +6043,19 @@ static void put_prev_task_balance(struct rq *rq, struct task_struct *prev, +@@ -5772,8 +5826,19 @@ static inline void schedule_debug(struct task_struct *prev, bool preempt) + static void put_prev_task_balance(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) { - #ifdef CONFIG_SMP +-#ifdef CONFIG_SMP + const struct sched_class *start_class = prev->sched_class; const struct sched_class *class; + @@ -1080,23 +1333,28 @@ index ebf21373f663..fb6276f74ee6 100644 + * when waking up from SCHED_IDLE. If @start_class is below SCX, start + * from SCX instead. + */ -+ if (sched_class_above(&ext_sched_class, start_class)) ++ if (scx_enabled() && sched_class_above(&ext_sched_class, start_class)) + start_class = &ext_sched_class; +#endif + /* * We must do the balancing pass before put_prev_task(), such * that when we release the rq->lock the task is in the same -@@ -5998,7 +6064,7 @@ static void put_prev_task_balance(struct rq *rq, struct task_struct *prev, +@@ -5782,11 +5847,10 @@ static void put_prev_task_balance(struct rq *rq, struct task_struct *prev, * We can terminate the balance pass as soon as we know there is * a runnable task of @class priority or higher. */ - for_class_range(class, prev->sched_class, &idle_sched_class) { +- if (class->balance(rq, prev, rf)) + for_active_class_range(class, start_class, &idle_sched_class) { - if (class->balance(rq, prev, rf)) ++ if (class->balance && class->balance(rq, prev, rf)) break; } -@@ -6016,6 +6082,9 @@ __pick_next_task(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) +-#endif + + put_prev_task(rq, prev); + } +@@ -5800,6 +5864,9 @@ __pick_next_task(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) const struct sched_class *class; struct task_struct *p; @@ -1106,7 +1364,7 @@ index ebf21373f663..fb6276f74ee6 100644 /* * Optimization: we know that if all tasks are in the fair class we can * call that function directly, but only if the @prev task wasn't of a -@@ -6056,10 +6125,15 @@ __pick_next_task(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) +@@ -5840,10 +5907,15 @@ __pick_next_task(struct rq *rq, struct task_struct *prev, struct rq_flags *rf) if (prev->dl_server) prev->dl_server = NULL; @@ -1124,7 +1382,7 @@ index ebf21373f663..fb6276f74ee6 100644 } BUG(); /* The idle class should always have a runnable task. */ -@@ -6089,7 +6163,7 @@ static inline struct task_struct *pick_task(struct rq *rq) +@@ -5873,7 +5945,7 @@ static inline struct task_struct *pick_task(struct rq *rq) const struct sched_class *class; struct task_struct *p; @@ -1133,14 +1391,7 @@ index ebf21373f663..fb6276f74ee6 100644 p = class->pick_task(rq); if (p) return p; -@@ -7080,12 +7154,16 @@ int default_wake_function(wait_queue_entry_t *curr, unsigned mode, int wake_flag - } - EXPORT_SYMBOL(default_wake_function); - --static void __setscheduler_prio(struct task_struct *p, int prio) -+void __setscheduler_prio(struct task_struct *p, int prio) - { - if (dl_prio(prio)) +@@ -6870,6 +6942,10 @@ void __setscheduler_prio(struct task_struct *p, int prio) p->sched_class = &dl_sched_class; else if (rt_prio(prio)) p->sched_class = &rt_sched_class; @@ -1151,7 +1402,7 @@ index ebf21373f663..fb6276f74ee6 100644 else p->sched_class = &fair_sched_class; -@@ -7246,6 +7324,7 @@ void rt_mutex_setprio(struct task_struct *p, struct task_struct *pi_task) +@@ -7015,6 +7091,7 @@ void rt_mutex_setprio(struct task_struct *p, struct task_struct *pi_task) } __setscheduler_prio(p, prio); @@ -1159,68 +1410,7 @@ index ebf21373f663..fb6276f74ee6 100644 if (queued) enqueue_task(rq, p, queue_flag); -@@ -7467,6 +7546,25 @@ int sched_core_idle_cpu(int cpu) - #endif - - #ifdef CONFIG_SMP -+/* -+ * Load avg and utiliztion metrics need to be updated periodically and before -+ * consumption. This function updates the metrics for all subsystems except for -+ * the fair class. @rq must be locked and have its clock updated. -+ */ -+bool update_other_load_avgs(struct rq *rq) -+{ -+ u64 now = rq_clock_pelt(rq); -+ const struct sched_class *curr_class = rq->curr->sched_class; -+ unsigned long hw_pressure = arch_scale_hw_pressure(cpu_of(rq)); -+ -+ lockdep_assert_rq_held(rq); -+ -+ return update_rt_rq_load_avg(now, rq, curr_class == &rt_sched_class) | -+ update_dl_rq_load_avg(now, rq, curr_class == &dl_sched_class) | -+ update_hw_load_avg(now, rq, hw_pressure) | -+ update_irq_load_avg(rq, 0); -+} -+ - /* - * This function computes an effective utilization for the given CPU, to be - * used for frequency selection given the linear relation: f = u * f_max. -@@ -7789,6 +7887,10 @@ static int __sched_setscheduler(struct task_struct *p, - goto unlock; - } - -+ retval = scx_check_setscheduler(p, policy); -+ if (retval) -+ goto unlock; -+ - /* - * If not changing anything there's no need to proceed further, - * but store a possible modification of reset_on_fork. -@@ -7891,6 +7993,7 @@ static int __sched_setscheduler(struct task_struct *p, - __setscheduler_prio(p, newprio); - } - __setscheduler_uclamp(p, attr); -+ check_class_changing(rq, p, prev_class); - - if (queued) { - /* -@@ -9066,6 +9169,7 @@ SYSCALL_DEFINE1(sched_get_priority_max, int, policy) - case SCHED_NORMAL: - case SCHED_BATCH: - case SCHED_IDLE: -+ case SCHED_EXT: - ret = 0; - break; - } -@@ -9093,6 +9197,7 @@ SYSCALL_DEFINE1(sched_get_priority_min, int, policy) - case SCHED_NORMAL: - case SCHED_BATCH: - case SCHED_IDLE: -+ case SCHED_EXT: - ret = 0; - } - return ret; -@@ -9188,6 +9293,7 @@ void sched_show_task(struct task_struct *p) +@@ -7429,6 +7506,7 @@ void sched_show_task(struct task_struct *p) print_worker_info(KERN_INFO, p); print_stop_info(KERN_INFO, p); @@ -1228,7 +1418,7 @@ index ebf21373f663..fb6276f74ee6 100644 show_stack(p, NULL, KERN_INFO); put_task_stack(p); } -@@ -9680,6 +9786,8 @@ int sched_cpu_activate(unsigned int cpu) +@@ -7957,6 +8035,8 @@ int sched_cpu_activate(unsigned int cpu) cpuset_cpu_active(); } @@ -1237,7 +1427,7 @@ index ebf21373f663..fb6276f74ee6 100644 /* * Put the rq online, if not already. This happens: * -@@ -9903,6 +9903,8 @@ +@@ -8006,6 +8086,8 @@ int sched_cpu_deactivate(unsigned int cpu) sched_set_rq_offline(rq, cpu); @@ -1246,7 +1436,7 @@ index ebf21373f663..fb6276f74ee6 100644 /* * When going down, decrement the number of cores with SMT present. */ -@@ -10061,11 +10061,15 @@ +@@ -8192,11 +8192,15 @@ int i; /* Make sure the linker didn't screw up */ @@ -1266,7 +1456,17 @@ index ebf21373f663..fb6276f74ee6 100644 #endif #ifdef CONFIG_SCHED_BORE -@@ -10096,6 +10210,7 @@ void __init sched_init(void) +@@ -8218,6 +8304,9 @@ void __init sched_init(void) + root_task_group.shares = ROOT_TASK_GROUP_LOAD; + init_cfs_bandwidth(&root_task_group.cfs_bandwidth, NULL); + #endif /* CONFIG_FAIR_GROUP_SCHED */ ++#ifdef CONFIG_EXT_GROUP_SCHED ++ root_task_group.scx_weight = CGROUP_WEIGHT_DFL; ++#endif /* CONFIG_EXT_GROUP_SCHED */ + #ifdef CONFIG_RT_GROUP_SCHED + root_task_group.rt_se = (struct sched_rt_entity **)ptr; + ptr += nr_cpu_ids * sizeof(void **); +@@ -8363,6 +8452,7 @@ void __init sched_init(void) balance_push_set(smp_processor_id(), false); #endif init_sched_fair_class(); @@ -1274,7 +1474,23 @@ index ebf21373f663..fb6276f74ee6 100644 psi_init(); -@@ -10522,11 +10637,6 @@ void sched_move_task(struct task_struct *tsk) +@@ -8648,6 +8738,7 @@ struct task_group *sched_create_group(struct task_group *parent) + if (!alloc_rt_sched_group(tg, parent)) + goto err; + ++ scx_group_set_weight(tg, CGROUP_WEIGHT_DFL); + alloc_uclamp_sched_group(tg, parent); + + return tg; +@@ -8775,6 +8866,7 @@ void sched_move_task(struct task_struct *tsk) + put_prev_task(rq, tsk); + + sched_change_group(tsk, group); ++ scx_move_task(tsk); + + if (queued) + enqueue_task(rq, tsk, queue_flags); +@@ -8789,11 +8881,6 @@ void sched_move_task(struct task_struct *tsk) } } @@ -1286,16 +1502,154 @@ index ebf21373f663..fb6276f74ee6 100644 static struct cgroup_subsys_state * cpu_cgroup_css_alloc(struct cgroup_subsys_state *parent_css) { -@@ -11293,29 +11403,27 @@ static int cpu_local_stat_show(struct seq_file *sf, +@@ -8817,6 +8904,11 @@ static int cpu_cgroup_css_online(struct cgroup_subsys_state *css) + { + struct task_group *tg = css_tg(css); + struct task_group *parent = css_tg(css->parent); ++ int ret; ++ ++ ret = scx_tg_online(tg); ++ if (ret) ++ return ret; + + if (parent) + sched_online_group(tg, parent); +@@ -8831,6 +8923,13 @@ static int cpu_cgroup_css_online(struct cgroup_subsys_state *css) + return 0; } - #ifdef CONFIG_FAIR_GROUP_SCHED ++static void cpu_cgroup_css_offline(struct cgroup_subsys_state *css) ++{ ++ struct task_group *tg = css_tg(css); ++ ++ scx_tg_offline(tg); ++} + + static void cpu_cgroup_css_released(struct cgroup_subsys_state *css) + { + struct task_group *tg = css_tg(css); +@@ -8848,9 +8947,9 @@ static void cpu_cgroup_css_free(struct cgroup_subsys_state *css) + sched_unregister_group(tg); + } + +-#ifdef CONFIG_RT_GROUP_SCHED + static int cpu_cgroup_can_attach(struct cgroup_taskset *tset) + { ++#ifdef CONFIG_RT_GROUP_SCHED + struct task_struct *task; + struct cgroup_subsys_state *css; + +@@ -8858,9 +8957,9 @@ static int cpu_cgroup_can_attach(struct cgroup_taskset *tset) + if (!sched_rt_can_attach(css_tg(css), task)) + return -EINVAL; + } +- return 0; +-} + #endif ++ return scx_cgroup_can_attach(tset); ++} + + static void cpu_cgroup_attach(struct cgroup_taskset *tset) + { +@@ -8869,6 +8968,13 @@ static void cpu_cgroup_attach(struct cgroup_taskset *tset) + + cgroup_taskset_for_each(task, css, tset) + sched_move_task(task); ++ ++ scx_cgroup_finish_attach(); ++} ++ ++static void cpu_cgroup_cancel_attach(struct cgroup_taskset *tset) ++{ ++ scx_cgroup_cancel_attach(tset); + } + + #ifdef CONFIG_UCLAMP_TASK_GROUP +@@ -9045,22 +9151,36 @@ static int cpu_uclamp_max_show(struct seq_file *sf, void *v) + } + #endif /* CONFIG_UCLAMP_TASK_GROUP */ + ++#ifdef CONFIG_GROUP_SCHED_WEIGHT +static unsigned long tg_weight(struct task_group *tg) +{ + #ifdef CONFIG_FAIR_GROUP_SCHED + return scale_load_down(tg->shares); ++#else ++ return sched_weight_from_cgroup(tg->scx_weight); ++#endif +} + + static int cpu_shares_write_u64(struct cgroup_subsys_state *css, + struct cftype *cftype, u64 shareval) + { ++ int ret; ++ + if (shareval > scale_load_down(ULONG_MAX)) + shareval = MAX_SHARES; +- return sched_group_set_shares(css_tg(css), scale_load(shareval)); ++ ret = sched_group_set_shares(css_tg(css), scale_load(shareval)); ++ if (!ret) ++ scx_group_set_weight(css_tg(css), ++ sched_weight_to_cgroup(shareval)); ++ return ret; + } + + static u64 cpu_shares_read_u64(struct cgroup_subsys_state *css, + struct cftype *cft) + { +- struct task_group *tg = css_tg(css); +- +- return (u64) scale_load_down(tg->shares); ++ return tg_weight(css_tg(css)); + } ++#endif /* CONFIG_GROUP_SCHED_WEIGHT */ + + #ifdef CONFIG_CFS_BANDWIDTH + static DEFINE_MUTEX(cfs_constraints_mutex); +@@ -9406,7 +9526,6 @@ static int cpu_cfs_local_stat_show(struct seq_file *sf, void *v) + return 0; + } + #endif /* CONFIG_CFS_BANDWIDTH */ +-#endif /* CONFIG_FAIR_GROUP_SCHED */ + + #ifdef CONFIG_RT_GROUP_SCHED + static int cpu_rt_runtime_write(struct cgroup_subsys_state *css, +@@ -9434,7 +9553,7 @@ static u64 cpu_rt_period_read_uint(struct cgroup_subsys_state *css, + } + #endif /* CONFIG_RT_GROUP_SCHED */ + +-#ifdef CONFIG_FAIR_GROUP_SCHED ++#ifdef CONFIG_GROUP_SCHED_WEIGHT + static s64 cpu_idle_read_s64(struct cgroup_subsys_state *css, + struct cftype *cft) + { +@@ -9444,12 +9563,17 @@ static s64 cpu_idle_read_s64(struct cgroup_subsys_state *css, + static int cpu_idle_write_s64(struct cgroup_subsys_state *css, + struct cftype *cft, s64 idle) + { +- return sched_group_set_idle(css_tg(css), idle); ++ int ret; ++ ++ ret = sched_group_set_idle(css_tg(css), idle); ++ if (!ret) ++ scx_group_set_idle(css_tg(css), idle); ++ return ret; + } + #endif + + static struct cftype cpu_legacy_files[] = { +-#ifdef CONFIG_FAIR_GROUP_SCHED ++#ifdef CONFIG_GROUP_SCHED_WEIGHT + { + .name = "shares", + .read_u64 = cpu_shares_read_u64, +@@ -9559,38 +9683,35 @@ static int cpu_local_stat_show(struct seq_file *sf, + return 0; + } + +-#ifdef CONFIG_FAIR_GROUP_SCHED ++#ifdef CONFIG_GROUP_SCHED_WEIGHT ++ static u64 cpu_weight_read_u64(struct cgroup_subsys_state *css, struct cftype *cft) { @@ -1319,6 +1673,7 @@ index ebf21373f663..fb6276f74ee6 100644 - */ - if (weight < CGROUP_WEIGHT_MIN || weight > CGROUP_WEIGHT_MAX) + unsigned long weight; ++ int ret; + + if (cgrp_weight < CGROUP_WEIGHT_MIN || cgrp_weight > CGROUP_WEIGHT_MAX) return -ERANGE; @@ -1326,9 +1681,13 @@ index ebf21373f663..fb6276f74ee6 100644 - weight = DIV_ROUND_CLOSEST_ULL(weight * 1024, CGROUP_WEIGHT_DFL); + weight = sched_weight_from_cgroup(cgrp_weight); - return sched_group_set_shares(css_tg(css), scale_load(weight)); +- return sched_group_set_shares(css_tg(css), scale_load(weight)); ++ ret = sched_group_set_shares(css_tg(css), scale_load(weight)); ++ if (!ret) ++ scx_group_set_weight(css_tg(css), cgrp_weight); ++ return ret; } -@@ -11323,7 +11431,7 @@ static int cpu_weight_write_u64(struct cgroup_subsys_state *css, + static s64 cpu_weight_nice_read_s64(struct cgroup_subsys_state *css, struct cftype *cft) { @@ -1337,7 +1696,58 @@ index ebf21373f663..fb6276f74ee6 100644 int last_delta = INT_MAX; int prio, delta; -@@ -12064,3 +12172,38 @@ void sched_mm_cid_fork(struct task_struct *t) +@@ -9609,7 +9730,7 @@ static int cpu_weight_nice_write_s64(struct cgroup_subsys_state *css, + struct cftype *cft, s64 nice) + { + unsigned long weight; +- int idx; ++ int idx, ret; + + if (nice < MIN_NICE || nice > MAX_NICE) + return -ERANGE; +@@ -9618,9 +9739,13 @@ static int cpu_weight_nice_write_s64(struct cgroup_subsys_state *css, + idx = array_index_nospec(idx, 40); + weight = sched_prio_to_weight[idx]; + +- return sched_group_set_shares(css_tg(css), scale_load(weight)); ++ ret = sched_group_set_shares(css_tg(css), scale_load(weight)); ++ if (!ret) ++ scx_group_set_weight(css_tg(css), ++ sched_weight_to_cgroup(weight)); ++ return ret; + } +-#endif ++#endif /* CONFIG_GROUP_SCHED_WEIGHT */ + + static void __maybe_unused cpu_period_quota_print(struct seq_file *sf, + long period, long quota) +@@ -9680,7 +9805,7 @@ static ssize_t cpu_max_write(struct kernfs_open_file *of, + #endif + + static struct cftype cpu_files[] = { +-#ifdef CONFIG_FAIR_GROUP_SCHED ++#ifdef CONFIG_GROUP_SCHED_WEIGHT + { + .name = "weight", + .flags = CFTYPE_NOT_ON_ROOT, +@@ -9734,14 +9859,14 @@ static struct cftype cpu_files[] = { + struct cgroup_subsys cpu_cgrp_subsys = { + .css_alloc = cpu_cgroup_css_alloc, + .css_online = cpu_cgroup_css_online, ++ .css_offline = cpu_cgroup_css_offline, + .css_released = cpu_cgroup_css_released, + .css_free = cpu_cgroup_css_free, + .css_extra_stat_show = cpu_extra_stat_show, + .css_local_stat_show = cpu_local_stat_show, +-#ifdef CONFIG_RT_GROUP_SCHED + .can_attach = cpu_cgroup_can_attach, +-#endif + .attach = cpu_cgroup_attach, ++ .cancel_attach = cpu_cgroup_cancel_attach, + .legacy_cftypes = cpu_legacy_files, + .dfl_cftypes = cpu_files, + .early_init = true, +@@ -10331,3 +10456,38 @@ void sched_mm_cid_fork(struct task_struct *t) t->mm_cid_active = 1; } #endif @@ -1481,10 +1891,10 @@ index c1eb9a1afd13..c057ef46c5f8 100644 diff --git a/kernel/sched/ext.c b/kernel/sched/ext.c new file mode 100644 -index 000000000000..0dac88d0e578 +index 000000000000..25fadfaace33 --- /dev/null +++ b/kernel/sched/ext.c -@@ -0,0 +1,6532 @@ +@@ -0,0 +1,7262 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * BPF extensible scheduler class: Documentation/scheduler/sched-ext.rst @@ -1603,10 +2013,16 @@ index 000000000000..0dac88d0e578 + */ + SCX_OPS_SWITCH_PARTIAL = 1LLU << 3, + ++ /* ++ * CPU cgroup support flags ++ */ ++ SCX_OPS_HAS_CGROUP_WEIGHT = 1LLU << 16, /* cpu.weight */ ++ + SCX_OPS_ALL_FLAGS = SCX_OPS_KEEP_BUILTIN_IDLE | + SCX_OPS_ENQ_LAST | + SCX_OPS_ENQ_EXITING | -+ SCX_OPS_SWITCH_PARTIAL, ++ SCX_OPS_SWITCH_PARTIAL | ++ SCX_OPS_HAS_CGROUP_WEIGHT, +}; + +/* argument container for ops.init_task() */ @@ -1616,6 +2032,10 @@ index 000000000000..0dac88d0e578 + * to the scheduler transition path. + */ + bool fork; ++#ifdef CONFIG_EXT_GROUP_SCHED ++ /* the cgroup the task is joining */ ++ struct cgroup *cgroup; ++#endif +}; + +/* argument container for ops.exit_task() */ @@ -1624,6 +2044,12 @@ index 000000000000..0dac88d0e578 + bool cancelled; +}; + ++/* argument container for ops->cgroup_init() */ ++struct scx_cgroup_init_args { ++ /* the weight of the cgroup [1..10000] */ ++ u32 weight; ++}; ++ +enum scx_cpu_preempt_reason { + /* next task is being scheduled by &sched_class_rt */ + SCX_CPU_PREEMPT_RT, @@ -1988,6 +2414,79 @@ index 000000000000..0dac88d0e578 + */ + void (*dump_task)(struct scx_dump_ctx *ctx, struct task_struct *p); + ++#ifdef CONFIG_EXT_GROUP_SCHED ++ /** ++ * cgroup_init - Initialize a cgroup ++ * @cgrp: cgroup being initialized ++ * @args: init arguments, see the struct definition ++ * ++ * Either the BPF scheduler is being loaded or @cgrp created, initialize ++ * @cgrp for sched_ext. This operation may block. ++ * ++ * Return 0 for success, -errno for failure. An error return while ++ * loading will abort loading of the BPF scheduler. During cgroup ++ * creation, it will abort the specific cgroup creation. ++ */ ++ s32 (*cgroup_init)(struct cgroup *cgrp, ++ struct scx_cgroup_init_args *args); ++ ++ /** ++ * cgroup_exit - Exit a cgroup ++ * @cgrp: cgroup being exited ++ * ++ * Either the BPF scheduler is being unloaded or @cgrp destroyed, exit ++ * @cgrp for sched_ext. This operation my block. ++ */ ++ void (*cgroup_exit)(struct cgroup *cgrp); ++ ++ /** ++ * cgroup_prep_move - Prepare a task to be moved to a different cgroup ++ * @p: task being moved ++ * @from: cgroup @p is being moved from ++ * @to: cgroup @p is being moved to ++ * ++ * Prepare @p for move from cgroup @from to @to. This operation may ++ * block and can be used for allocations. ++ * ++ * Return 0 for success, -errno for failure. An error return aborts the ++ * migration. ++ */ ++ s32 (*cgroup_prep_move)(struct task_struct *p, ++ struct cgroup *from, struct cgroup *to); ++ ++ /** ++ * cgroup_move - Commit cgroup move ++ * @p: task being moved ++ * @from: cgroup @p is being moved from ++ * @to: cgroup @p is being moved to ++ * ++ * Commit the move. @p is dequeued during this operation. ++ */ ++ void (*cgroup_move)(struct task_struct *p, ++ struct cgroup *from, struct cgroup *to); ++ ++ /** ++ * cgroup_cancel_move - Cancel cgroup move ++ * @p: task whose cgroup move is being canceled ++ * @from: cgroup @p was being moved from ++ * @to: cgroup @p was being moved to ++ * ++ * @p was cgroup_prep_move()'d but failed before reaching cgroup_move(). ++ * Undo the preparation. ++ */ ++ void (*cgroup_cancel_move)(struct task_struct *p, ++ struct cgroup *from, struct cgroup *to); ++ ++ /** ++ * cgroup_set_weight - A cgroup's weight is being changed ++ * @cgrp: cgroup whose weight is being updated ++ * @weight: new weight [1..10000] ++ * ++ * Update @tg's weight to @weight. ++ */ ++ void (*cgroup_set_weight)(struct cgroup *cgrp, u32 weight); ++#endif /* CONFIG_CGROUPS */ ++ + /* + * All online ops must come before ops.cpu_online(). + */ @@ -2173,8 +2672,12 @@ index 000000000000..0dac88d0e578 + SCX_KICK_WAIT = 1LLU << 2, +}; + ++enum scx_tg_flags { ++ SCX_TG_ONLINE = 1U << 0, ++ SCX_TG_INITED = 1U << 1, ++}; ++ +enum scx_ops_enable_state { -+ SCX_OPS_PREPPING, + SCX_OPS_ENABLING, + SCX_OPS_ENABLED, + SCX_OPS_DISABLING, @@ -2182,7 +2685,6 @@ index 000000000000..0dac88d0e578 +}; + +static const char *scx_ops_enable_state_str[] = { -+ [SCX_OPS_PREPPING] = "prepping", + [SCX_OPS_ENABLING] = "enabling", + [SCX_OPS_ENABLED] = "enabled", + [SCX_OPS_DISABLING] = "disabling", @@ -2250,6 +2752,7 @@ index 000000000000..0dac88d0e578 +DEFINE_STATIC_PERCPU_RWSEM(scx_fork_rwsem); +static atomic_t scx_ops_enable_state_var = ATOMIC_INIT(SCX_OPS_DISABLED); +static atomic_t scx_ops_bypass_depth = ATOMIC_INIT(0); ++static bool scx_ops_init_task_enabled; +static bool scx_switching_all; +DEFINE_STATIC_KEY_FALSE(__scx_switched_all); + @@ -2261,7 +2764,7 @@ index 000000000000..0dac88d0e578 +static DEFINE_STATIC_KEY_FALSE(scx_ops_cpu_preempt); +static DEFINE_STATIC_KEY_FALSE(scx_builtin_idle_enabled); + -+struct static_key_false scx_has_op[SCX_OPI_END] = ++static struct static_key_false scx_has_op[SCX_OPI_END] = + { [0 ... SCX_OPI_END-1] = STATIC_KEY_FALSE_INIT }; + +static atomic_t scx_exit_kind = ATOMIC_INIT(SCX_EXIT_DONE); @@ -2271,6 +2774,13 @@ index 000000000000..0dac88d0e578 +static atomic_long_t scx_hotplug_seq = ATOMIC_LONG_INIT(0); + +/* ++ * A monotically increasing sequence number that is incremented every time a ++ * scheduler is enabled. This can be used by to check if any custom sched_ext ++ * scheduler has ever been used in the system. ++ */ ++static atomic_long_t scx_enable_seq = ATOMIC_LONG_INIT(0); ++ ++/* + * The maximum amount of time in jiffies that a task may be runnable without + * being scheduled on a CPU. If this timeout is exceeded, it will trigger + * scx_ops_error(). @@ -2314,8 +2824,15 @@ index 000000000000..0dac88d0e578 + */ +static DEFINE_PER_CPU(struct task_struct *, direct_dispatch_task); + -+/* dispatch queues */ -+static struct scx_dispatch_q __cacheline_aligned_in_smp scx_dsq_global; ++/* ++ * Dispatch queues. ++ * ++ * The global DSQ (%SCX_DSQ_GLOBAL) is split per-node for scalability. This is ++ * to avoid live-locking in bypass mode where all tasks are dispatched to ++ * %SCX_DSQ_GLOBAL and all CPUs consume from it. If per-node split isn't ++ * sufficient, it can be further split. ++ */ ++static struct scx_dispatch_q **global_dsqs; + +static const struct rhashtable_params dsq_hash_params = { + .key_len = 8, @@ -2364,7 +2881,7 @@ index 000000000000..0dac88d0e578 + struct scx_bstr_buf buf; +}; + -+struct scx_dump_data scx_dump_data = { ++static struct scx_dump_data scx_dump_data = { + .cpu = -1, +}; + @@ -2418,6 +2935,16 @@ index 000000000000..0dac88d0e578 + return (s32)(a - b) < 0; +} + ++static struct scx_dispatch_q *find_global_dsq(struct task_struct *p) ++{ ++ return global_dsqs[cpu_to_node(task_cpu(p))]; ++} ++ ++static struct scx_dispatch_q *find_user_dsq(u64 dsq_id) ++{ ++ return rhashtable_lookup_fast(&dsq_hash, &dsq_id, dsq_hash_params); ++} ++ +/* + * scx_kf_mask enforcement. Some kfuncs can only be called from specific SCX + * ops. When invoking SCX ops, SCX_CALL_OP[_RET]() should be used to indicate @@ -2554,6 +3081,11 @@ index 000000000000..0dac88d0e578 + return true; +} + ++static bool scx_kf_allowed_if_unlocked(void) ++{ ++ return !current->scx.kf_mask; ++} ++ +/** + * nldsq_next_task - Iterate to the next task in a non-local DSQ + * @dsq: user dsq being interated @@ -2587,7 +3119,7 @@ index 000000000000..0dac88d0e578 + + dsq_lnode = container_of(list_node, struct scx_dsq_list_node, + node); -+ } while (dsq_lnode->is_bpf_iter_cursor); ++ } while (dsq_lnode->flags & SCX_DSQ_LNODE_ITER_CURSOR); + + return container_of(dsq_lnode, struct task_struct, scx.dsq_list); +} @@ -2605,16 +3137,22 @@ index 000000000000..0dac88d0e578 + */ +enum scx_dsq_iter_flags { + /* iterate in the reverse dispatch order */ -+ SCX_DSQ_ITER_REV = 1U << 0, ++ SCX_DSQ_ITER_REV = 1U << 16, + -+ __SCX_DSQ_ITER_ALL_FLAGS = SCX_DSQ_ITER_REV, ++ __SCX_DSQ_ITER_HAS_SLICE = 1U << 30, ++ __SCX_DSQ_ITER_HAS_VTIME = 1U << 31, ++ ++ __SCX_DSQ_ITER_USER_FLAGS = SCX_DSQ_ITER_REV, ++ __SCX_DSQ_ITER_ALL_FLAGS = __SCX_DSQ_ITER_USER_FLAGS | ++ __SCX_DSQ_ITER_HAS_SLICE | ++ __SCX_DSQ_ITER_HAS_VTIME, +}; + +struct bpf_iter_scx_dsq_kern { + struct scx_dsq_list_node cursor; + struct scx_dispatch_q *dsq; -+ u32 dsq_seq; -+ u32 flags; ++ u64 slice; ++ u64 vtime; +} __attribute__((aligned(8))); + +struct bpf_iter_scx_dsq { @@ -2652,6 +3190,9 @@ index 000000000000..0dac88d0e578 +{ + lockdep_assert_held(&scx_tasks_lock); + ++ BUILD_BUG_ON(__SCX_DSQ_ITER_ALL_FLAGS & ++ ((1U << __SCX_DSQ_LNODE_PRIV_SHIFT) - 1)); ++ + iter->cursor = (struct sched_ext_entity){ .flags = SCX_TASK_CURSOR }; + list_add(&iter->cursor.tasks_node, &scx_tasks); + iter->locked = NULL; @@ -2730,17 +3271,37 @@ index 000000000000..0dac88d0e578 + * whether they would like to filter out dead tasks. See scx_task_iter_init() + * for details. + */ -+static struct task_struct * -+scx_task_iter_next_locked(struct scx_task_iter *iter, bool include_dead) ++static struct task_struct *scx_task_iter_next_locked(struct scx_task_iter *iter) +{ + struct task_struct *p; -+retry: ++ + scx_task_iter_rq_unlock(iter); + + while ((p = scx_task_iter_next(iter))) { + /* -+ * is_idle_task() tests %PF_IDLE which may not be set for CPUs -+ * which haven't yet been onlined. Test sched_class directly. ++ * scx_task_iter is used to prepare and move tasks into SCX ++ * while loading the BPF scheduler and vice-versa while ++ * unloading. The init_tasks ("swappers") should be excluded ++ * from the iteration because: ++ * ++ * - It's unsafe to use __setschduler_prio() on an init_task to ++ * determine the sched_class to use as it won't preserve its ++ * idle_sched_class. ++ * ++ * - ops.init/exit_task() can easily be confused if called with ++ * init_tasks as they, e.g., share PID 0. ++ * ++ * As init_tasks are never scheduled through SCX, they can be ++ * skipped safely. Note that is_idle_task() which tests %PF_IDLE ++ * doesn't work here: ++ * ++ * - %PF_IDLE may not be set for an init_task whose CPU hasn't ++ * yet been onlined. ++ * ++ * - %PF_IDLE can be set on tasks that are not init_tasks. See ++ * play_idle_precise() used by CONFIG_IDLE_INJECT. ++ * ++ * Test for idle_sched_class as only init_tasks are on it. + */ + if (p->sched_class != &idle_sched_class) + break; @@ -2751,16 +3312,6 @@ index 000000000000..0dac88d0e578 + iter->rq = task_rq_lock(p, &iter->rf); + iter->locked = p; + -+ /* -+ * If we see %TASK_DEAD, @p already disabled preemption, is about to do -+ * the final __schedule(), won't ever need to be scheduled again and can -+ * thus be safely ignored. If we don't see %TASK_DEAD, @p can't enter -+ * the final __schedle() while we're locking its rq and thus will stay -+ * alive until the rq is unlocked. -+ */ -+ if (!include_dead && READ_ONCE(p->__state) == TASK_DEAD) -+ goto retry; -+ + return p; +} + @@ -2783,9 +3334,9 @@ index 000000000000..0dac88d0e578 + return atomic_try_cmpxchg(&scx_ops_enable_state_var, &from_v, to); +} + -+static bool scx_ops_bypassing(void) ++static bool scx_rq_bypassing(struct rq *rq) +{ -+ return unlikely(atomic_read(&scx_ops_bypass_depth)); ++ return unlikely(rq->scx.flags & SCX_RQ_BYPASSING); +} + +/** @@ -2919,13 +3470,18 @@ index 000000000000..0dac88d0e578 + */ +static void touch_core_sched(struct rq *rq, struct task_struct *p) +{ ++ lockdep_assert_rq_held(rq); ++ +#ifdef CONFIG_SCHED_CORE + /* + * It's okay to update the timestamp spuriously. Use + * sched_core_disabled() which is cheaper than enabled(). ++ * ++ * As this is used to determine ordering between tasks of sibling CPUs, ++ * it may be better to use per-core dispatch sequence instead. + */ + if (!sched_core_disabled()) -+ p->scx.core_sched_at = rq_clock_task(rq); ++ p->scx.core_sched_at = sched_clock_cpu(cpu_of(rq)); +#endif +} + @@ -2942,7 +3498,6 @@ index 000000000000..0dac88d0e578 +static void touch_core_sched_dispatch(struct rq *rq, struct task_struct *p) +{ + lockdep_assert_rq_held(rq); -+ assert_clock_updated(rq); + +#ifdef CONFIG_SCHED_CORE + if (SCX_HAS_OP(core_sched_before)) @@ -2953,20 +3508,14 @@ index 000000000000..0dac88d0e578 +static void update_curr_scx(struct rq *rq) +{ + struct task_struct *curr = rq->curr; -+ u64 now = rq_clock_task(rq); -+ u64 delta_exec; ++ s64 delta_exec; + -+ if (time_before_eq64(now, curr->se.exec_start)) ++ delta_exec = update_curr_common(rq); ++ if (unlikely(delta_exec <= 0)) + return; + -+ delta_exec = now - curr->se.exec_start; -+ curr->se.exec_start = now; -+ curr->se.sum_exec_runtime += delta_exec; -+ account_group_exec_runtime(curr, delta_exec); -+ cgroup_account_cputime(curr, delta_exec); -+ + if (curr->scx.slice != SCX_SLICE_INF) { -+ curr->scx.slice -= min(curr->scx.slice, delta_exec); ++ curr->scx.slice -= min_t(u64, curr->scx.slice, delta_exec); + if (!curr->scx.slice) + touch_core_sched(rq, curr); + } @@ -3004,7 +3553,7 @@ index 000000000000..0dac88d0e578 + scx_ops_error("attempting to dispatch to a destroyed dsq"); + /* fall back to the global dsq */ + raw_spin_unlock(&dsq->lock); -+ dsq = &scx_dsq_global; ++ dsq = find_global_dsq(p); + raw_spin_lock(&dsq->lock); + } + } @@ -3107,6 +3656,8 @@ index 000000000000..0dac88d0e578 +static void task_unlink_from_dsq(struct task_struct *p, + struct scx_dispatch_q *dsq) +{ ++ WARN_ON_ONCE(list_empty(&p->scx.dsq_list.node)); ++ + if (p->scx.dsq_flags & SCX_TASK_DSQ_ON_PRIQ) { + rb_erase(&p->scx.dsq_priq, &dsq->priq); + RB_CLEAR_NODE(&p->scx.dsq_priq); @@ -3114,6 +3665,7 @@ index 000000000000..0dac88d0e578 + } + + list_del_init(&p->scx.dsq_list.node); ++ dsq_mod_nr(dsq, -1); +} + +static void dispatch_dequeue(struct rq *rq, struct task_struct *p) @@ -3150,9 +3702,7 @@ index 000000000000..0dac88d0e578 + */ + if (p->scx.holding_cpu < 0) { + /* @p must still be on @dsq, dequeue */ -+ WARN_ON_ONCE(list_empty(&p->scx.dsq_list.node)); + task_unlink_from_dsq(p, dsq); -+ dsq_mod_nr(dsq, -1); + } else { + /* + * We're racing against dispatch_to_local_dsq() which already @@ -3169,21 +3719,6 @@ index 000000000000..0dac88d0e578 + raw_spin_unlock(&dsq->lock); +} + -+static struct scx_dispatch_q *find_user_dsq(u64 dsq_id) -+{ -+ return rhashtable_lookup_fast(&dsq_hash, &dsq_id, dsq_hash_params); -+} -+ -+static struct scx_dispatch_q *find_non_local_dsq(u64 dsq_id) -+{ -+ lockdep_assert(rcu_read_lock_any_held()); -+ -+ if (dsq_id == SCX_DSQ_GLOBAL) -+ return &scx_dsq_global; -+ else -+ return find_user_dsq(dsq_id); -+} -+ +static struct scx_dispatch_q *find_dsq_for_dispatch(struct rq *rq, u64 dsq_id, + struct task_struct *p) +{ @@ -3192,11 +3727,24 @@ index 000000000000..0dac88d0e578 + if (dsq_id == SCX_DSQ_LOCAL) + return &rq->scx.local_dsq; + -+ dsq = find_non_local_dsq(dsq_id); ++ if ((dsq_id & SCX_DSQ_LOCAL_ON) == SCX_DSQ_LOCAL_ON) { ++ s32 cpu = dsq_id & SCX_DSQ_LOCAL_CPU_MASK; ++ ++ if (!ops_cpu_valid(cpu, "in SCX_DSQ_LOCAL_ON dispatch verdict")) ++ return find_global_dsq(p); ++ ++ return &cpu_rq(cpu)->scx.local_dsq; ++ } ++ ++ if (dsq_id == SCX_DSQ_GLOBAL) ++ dsq = find_global_dsq(p); ++ else ++ dsq = find_user_dsq(dsq_id); ++ + if (unlikely(!dsq)) { + scx_ops_error("non-existent DSQ 0x%llx for %s[%d]", + dsq_id, p->comm, p->pid); -+ return &scx_dsq_global; ++ return find_global_dsq(p); + } + + return dsq; @@ -3235,8 +3783,8 @@ index 000000000000..0dac88d0e578 +static void direct_dispatch(struct task_struct *p, u64 enq_flags) +{ + struct rq *rq = task_rq(p); -+ struct scx_dispatch_q *dsq; -+ u64 dsq_id = p->scx.ddsp_dsq_id; ++ struct scx_dispatch_q *dsq = ++ find_dsq_for_dispatch(rq, p->scx.ddsp_dsq_id, p); + + touch_core_sched_dispatch(rq, p); + @@ -3248,15 +3796,9 @@ index 000000000000..0dac88d0e578 + * DSQ_LOCAL_ON verdicts targeting the local DSQ of a remote CPU, defer + * the enqueue so that it's executed when @rq can be unlocked. + */ -+ if ((dsq_id & SCX_DSQ_LOCAL_ON) == SCX_DSQ_LOCAL_ON) { -+ s32 cpu = dsq_id & SCX_DSQ_LOCAL_CPU_MASK; ++ if (dsq->id == SCX_DSQ_LOCAL && dsq != &rq->scx.local_dsq) { + unsigned long opss; + -+ if (cpu == cpu_of(rq)) { -+ dsq_id = SCX_DSQ_LOCAL; -+ goto dispatch; -+ } -+ + opss = atomic_long_read(&p->scx.ops_state) & SCX_OPSS_STATE_MASK; + + switch (opss & SCX_OPSS_STATE_MASK) { @@ -3283,14 +3825,19 @@ index 000000000000..0dac88d0e578 + return; + } + -+dispatch: -+ dsq = find_dsq_for_dispatch(rq, dsq_id, p); + dispatch_enqueue(dsq, p, p->scx.ddsp_enq_flags | SCX_ENQ_CLEAR_OPSS); +} + +static bool scx_rq_online(struct rq *rq) +{ -+ return likely(rq->scx.flags & SCX_RQ_ONLINE); ++ /* ++ * Test both cpu_active() and %SCX_RQ_ONLINE. %SCX_RQ_ONLINE indicates ++ * the online state as seen from the BPF scheduler. cpu_active() test ++ * guarantees that, if this function returns %true, %SCX_RQ_ONLINE will ++ * stay set until the current scheduling operation is complete even if ++ * we aren't locking @rq. ++ */ ++ return likely((rq->scx.flags & SCX_RQ_ONLINE) && cpu_active(cpu_of(rq))); +} + +static void do_enqueue_task(struct rq *rq, struct task_struct *p, u64 enq_flags, @@ -3313,7 +3860,7 @@ index 000000000000..0dac88d0e578 + if (!scx_rq_online(rq)) + goto local; + -+ if (scx_ops_bypassing()) { ++ if (scx_rq_bypassing(rq)) { + if (enq_flags & SCX_ENQ_LAST) + goto local; + else @@ -3378,7 +3925,7 @@ index 000000000000..0dac88d0e578 +global: + touch_core_sched(rq, p); /* see the comment in local: */ + p->scx.slice = SCX_SLICE_DFL; -+ dispatch_enqueue(&scx_dsq_global, p, enq_flags); ++ dispatch_enqueue(find_global_dsq(p), p, enq_flags); +} + +static bool task_runnable(const struct task_struct *p) @@ -3440,7 +3987,7 @@ index 000000000000..0dac88d0e578 + rq->scx.nr_running++; + add_nr_running(rq, 1); + -+ if (SCX_HAS_OP(runnable)) ++ if (SCX_HAS_OP(runnable) && !task_on_rq_migrating(p)) + SCX_CALL_OP_TASK(SCX_KF_REST, runnable, p, enq_flags); + + if (enq_flags & SCX_ENQ_WAKEUP) @@ -3524,7 +4071,7 @@ index 000000000000..0dac88d0e578 + SCX_CALL_OP_TASK(SCX_KF_REST, stopping, p, false); + } + -+ if (SCX_HAS_OP(quiescent)) ++ if (SCX_HAS_OP(quiescent) && !task_on_rq_migrating(p)) + SCX_CALL_OP_TASK(SCX_KF_REST, quiescent, p, deq_flags); + + if (deq_flags & SCX_DEQ_SLEEP) @@ -3559,193 +4106,173 @@ index 000000000000..0dac88d0e578 + return false; +} + ++static void move_local_task_to_local_dsq(struct task_struct *p, u64 enq_flags, ++ struct scx_dispatch_q *src_dsq, ++ struct rq *dst_rq) ++{ ++ struct scx_dispatch_q *dst_dsq = &dst_rq->scx.local_dsq; ++ ++ /* @dsq is locked and @p is on @dst_rq */ ++ lockdep_assert_held(&src_dsq->lock); ++ lockdep_assert_rq_held(dst_rq); ++ ++ WARN_ON_ONCE(p->scx.holding_cpu >= 0); ++ ++ if (enq_flags & (SCX_ENQ_HEAD | SCX_ENQ_PREEMPT)) ++ list_add(&p->scx.dsq_list.node, &dst_dsq->list); ++ else ++ list_add_tail(&p->scx.dsq_list.node, &dst_dsq->list); ++ ++ dsq_mod_nr(dst_dsq, 1); ++ p->scx.dsq = dst_dsq; ++} ++ +#ifdef CONFIG_SMP +/** -+ * move_task_to_local_dsq - Move a task from a different rq to a local DSQ -+ * @rq: rq to move the task into, currently locked ++ * move_remote_task_to_local_dsq - Move a task from a foreign rq to a local DSQ + * @p: task to move + * @enq_flags: %SCX_ENQ_* ++ * @src_rq: rq to move the task from, locked on entry, released on return ++ * @dst_rq: rq to move the task into, locked on return + * -+ * Move @p which is currently on a different rq to @rq's local DSQ. The caller -+ * must: -+ * -+ * 1. Start with exclusive access to @p either through its DSQ lock or -+ * %SCX_OPSS_DISPATCHING flag. -+ * -+ * 2. Set @p->scx.holding_cpu to raw_smp_processor_id(). -+ * -+ * 3. Remember task_rq(@p). Release the exclusive access so that we don't -+ * deadlock with dequeue. -+ * -+ * 4. Lock @rq and the task_rq from #3. -+ * -+ * 5. Call this function. -+ * -+ * Returns %true if @p was successfully moved. %false after racing dequeue and -+ * losing. ++ * Move @p which is currently on @src_rq to @dst_rq's local DSQ. + */ -+static bool move_task_to_local_dsq(struct rq *rq, struct task_struct *p, -+ u64 enq_flags) ++static void move_remote_task_to_local_dsq(struct task_struct *p, u64 enq_flags, ++ struct rq *src_rq, struct rq *dst_rq) +{ -+ struct rq *task_rq; -+ -+ lockdep_assert_rq_held(rq); -+ -+ /* -+ * If dequeue got to @p while we were trying to lock both rq's, it'd -+ * have cleared @p->scx.holding_cpu to -1. While other cpus may have -+ * updated it to different values afterwards, as this operation can't be -+ * preempted or recurse, @p->scx.holding_cpu can never become -+ * raw_smp_processor_id() again before we're done. Thus, we can tell -+ * whether we lost to dequeue by testing whether @p->scx.holding_cpu is -+ * still raw_smp_processor_id(). -+ * -+ * See dispatch_dequeue() for the counterpart. -+ */ -+ if (unlikely(p->scx.holding_cpu != raw_smp_processor_id())) -+ return false; ++ lockdep_assert_rq_held(src_rq); + -+ /* @p->rq couldn't have changed if we're still the holding cpu */ -+ task_rq = task_rq(p); -+ lockdep_assert_rq_held(task_rq); ++ /* the following marks @p MIGRATING which excludes dequeue */ ++ deactivate_task(src_rq, p, 0); ++ set_task_cpu(p, cpu_of(dst_rq)); ++ p->scx.sticky_cpu = cpu_of(dst_rq); + -+ WARN_ON_ONCE(!cpumask_test_cpu(cpu_of(rq), p->cpus_ptr)); -+ deactivate_task(task_rq, p, 0); -+ set_task_cpu(p, cpu_of(rq)); -+ p->scx.sticky_cpu = cpu_of(rq); ++ raw_spin_rq_unlock(src_rq); ++ raw_spin_rq_lock(dst_rq); + + /* + * We want to pass scx-specific enq_flags but activate_task() will + * truncate the upper 32 bit. As we own @rq, we can pass them through + * @rq->scx.extra_enq_flags instead. + */ -+ WARN_ON_ONCE(rq->scx.extra_enq_flags); -+ rq->scx.extra_enq_flags = enq_flags; -+ activate_task(rq, p, 0); -+ rq->scx.extra_enq_flags = 0; -+ -+ return true; ++ WARN_ON_ONCE(!cpumask_test_cpu(cpu_of(dst_rq), p->cpus_ptr)); ++ WARN_ON_ONCE(dst_rq->scx.extra_enq_flags); ++ dst_rq->scx.extra_enq_flags = enq_flags; ++ activate_task(dst_rq, p, 0); ++ dst_rq->scx.extra_enq_flags = 0; +} + -+/** -+ * dispatch_to_local_dsq_lock - Ensure source and destination rq's are locked -+ * @rq: current rq which is locked -+ * @src_rq: rq to move task from -+ * @dst_rq: rq to move task to ++/* ++ * Similar to kernel/sched/core.c::is_cpu_allowed(). However, there are two ++ * differences: + * -+ * We're holding @rq lock and trying to dispatch a task from @src_rq to -+ * @dst_rq's local DSQ and thus need to lock both @src_rq and @dst_rq. Whether -+ * @rq stays locked isn't important as long as the state is restored after -+ * dispatch_to_local_dsq_unlock(). -+ */ -+static void dispatch_to_local_dsq_lock(struct rq *rq, struct rq *src_rq, -+ struct rq *dst_rq) -+{ -+ if (src_rq == dst_rq) { -+ raw_spin_rq_unlock(rq); -+ raw_spin_rq_lock(dst_rq); -+ } else if (rq == src_rq) { -+ double_lock_balance(rq, dst_rq); -+ } else if (rq == dst_rq) { -+ double_lock_balance(rq, src_rq); -+ } else { -+ raw_spin_rq_unlock(rq); -+ double_rq_lock(src_rq, dst_rq); -+ } -+} -+ -+/** -+ * dispatch_to_local_dsq_unlock - Undo dispatch_to_local_dsq_lock() -+ * @rq: current rq which is locked -+ * @src_rq: rq to move task from -+ * @dst_rq: rq to move task to ++ * - is_cpu_allowed() asks "Can this task run on this CPU?" while ++ * task_can_run_on_remote_rq() asks "Can the BPF scheduler migrate the task to ++ * this CPU?". + * -+ * Unlock @src_rq and @dst_rq and ensure that @rq is locked on return. -+ */ -+static void dispatch_to_local_dsq_unlock(struct rq *rq, struct rq *src_rq, -+ struct rq *dst_rq) -+{ -+ if (src_rq == dst_rq) { -+ raw_spin_rq_unlock(dst_rq); -+ raw_spin_rq_lock(rq); -+ } else if (rq == src_rq) { -+ double_unlock_balance(rq, dst_rq); -+ } else if (rq == dst_rq) { -+ double_unlock_balance(rq, src_rq); -+ } else { -+ double_rq_unlock(src_rq, dst_rq); -+ raw_spin_rq_lock(rq); -+ } -+} -+#endif /* CONFIG_SMP */ -+ -+static void consume_local_task(struct rq *rq, struct scx_dispatch_q *dsq, -+ struct task_struct *p) -+{ -+ lockdep_assert_held(&dsq->lock); /* released on return */ -+ -+ /* @dsq is locked and @p is on this rq */ -+ WARN_ON_ONCE(p->scx.holding_cpu >= 0); -+ task_unlink_from_dsq(p, dsq); -+ list_add_tail(&p->scx.dsq_list.node, &rq->scx.local_dsq.list); -+ dsq_mod_nr(dsq, -1); -+ dsq_mod_nr(&rq->scx.local_dsq, 1); -+ p->scx.dsq = &rq->scx.local_dsq; -+ raw_spin_unlock(&dsq->lock); -+} -+ -+#ifdef CONFIG_SMP -+/* -+ * Similar to kernel/sched/core.c::is_cpu_allowed() but we're testing whether @p -+ * can be pulled to @rq. ++ * While migration is disabled, is_cpu_allowed() has to say "yes" as the task ++ * must be allowed to finish on the CPU that it's currently on regardless of ++ * the CPU state. However, task_can_run_on_remote_rq() must say "no" as the ++ * BPF scheduler shouldn't attempt to migrate a task which has migration ++ * disabled. ++ * ++ * - The BPF scheduler is bypassed while the rq is offline and we can always say ++ * no to the BPF scheduler initiated migrations while offline. + */ -+static bool task_can_run_on_remote_rq(struct task_struct *p, struct rq *rq) ++static bool task_can_run_on_remote_rq(struct task_struct *p, struct rq *rq, ++ bool trigger_error) +{ + int cpu = cpu_of(rq); + -+ if (!cpumask_test_cpu(cpu, p->cpus_ptr)) ++ /* ++ * We don't require the BPF scheduler to avoid dispatching to offline ++ * CPUs mostly for convenience but also because CPUs can go offline ++ * between scx_bpf_dispatch() calls and here. Trigger error iff the ++ * picked CPU is outside the allowed mask. ++ */ ++ if (!task_allowed_on_cpu(p, cpu)) { ++ if (trigger_error) ++ scx_ops_error("SCX_DSQ_LOCAL[_ON] verdict target cpu %d not allowed for %s[%d]", ++ cpu_of(rq), p->comm, p->pid); + return false; ++ } ++ + if (unlikely(is_migration_disabled(p))) + return false; -+ if (!(p->flags & PF_KTHREAD) && unlikely(!task_cpu_possible(cpu, p))) -+ return false; ++ + if (!scx_rq_online(rq)) + return false; ++ + return true; +} + -+static bool consume_remote_task(struct rq *rq, struct scx_dispatch_q *dsq, -+ struct task_struct *p, struct rq *task_rq) ++/** ++ * unlink_dsq_and_lock_src_rq() - Unlink task from its DSQ and lock its task_rq ++ * @p: target task ++ * @dsq: locked DSQ @p is currently on ++ * @src_rq: rq @p is currently on, stable with @dsq locked ++ * ++ * Called with @dsq locked but no rq's locked. We want to move @p to a different ++ * DSQ, including any local DSQ, but are not locking @src_rq. Locking @src_rq is ++ * required when transferring into a local DSQ. Even when transferring into a ++ * non-local DSQ, it's better to use the same mechanism to protect against ++ * dequeues and maintain the invariant that @p->scx.dsq can only change while ++ * @src_rq is locked, which e.g. scx_dump_task() depends on. ++ * ++ * We want to grab @src_rq but that can deadlock if we try while locking @dsq, ++ * so we want to unlink @p from @dsq, drop its lock and then lock @src_rq. As ++ * this may race with dequeue, which can't drop the rq lock or fail, do a little ++ * dancing from our side. ++ * ++ * @p->scx.holding_cpu is set to this CPU before @dsq is unlocked. If @p gets ++ * dequeued after we unlock @dsq but before locking @src_rq, the holding_cpu ++ * would be cleared to -1. While other cpus may have updated it to different ++ * values afterwards, as this operation can't be preempted or recurse, the ++ * holding_cpu can never become this CPU again before we're done. Thus, we can ++ * tell whether we lost to dequeue by testing whether the holding_cpu still ++ * points to this CPU. See dispatch_dequeue() for the counterpart. ++ * ++ * On return, @dsq is unlocked and @src_rq is locked. Returns %true if @p is ++ * still valid. %false if lost to dequeue. ++ */ ++static bool unlink_dsq_and_lock_src_rq(struct task_struct *p, ++ struct scx_dispatch_q *dsq, ++ struct rq *src_rq) +{ -+ bool moved = false; ++ s32 cpu = raw_smp_processor_id(); + -+ lockdep_assert_held(&dsq->lock); /* released on return */ ++ lockdep_assert_held(&dsq->lock); + -+ /* -+ * @dsq is locked and @p is on a remote rq. @p is currently protected by -+ * @dsq->lock. We want to pull @p to @rq but may deadlock if we grab -+ * @task_rq while holding @dsq and @rq locks. As dequeue can't drop the -+ * rq lock or fail, do a little dancing from our side. See -+ * move_task_to_local_dsq(). -+ */ + WARN_ON_ONCE(p->scx.holding_cpu >= 0); + task_unlink_from_dsq(p, dsq); -+ dsq_mod_nr(dsq, -1); -+ p->scx.holding_cpu = raw_smp_processor_id(); -+ raw_spin_unlock(&dsq->lock); ++ p->scx.holding_cpu = cpu; + -+ double_lock_balance(rq, task_rq); ++ raw_spin_unlock(&dsq->lock); ++ raw_spin_rq_lock(src_rq); + -+ moved = move_task_to_local_dsq(rq, p, 0); ++ /* task_rq couldn't have changed if we're still the holding cpu */ ++ return likely(p->scx.holding_cpu == cpu) && ++ !WARN_ON_ONCE(src_rq != task_rq(p)); ++} + -+ double_unlock_balance(rq, task_rq); ++static bool consume_remote_task(struct rq *this_rq, struct task_struct *p, ++ struct scx_dispatch_q *dsq, struct rq *src_rq) ++{ ++ raw_spin_rq_unlock(this_rq); + -+ return moved; ++ if (unlink_dsq_and_lock_src_rq(p, dsq, src_rq)) { ++ move_remote_task_to_local_dsq(p, 0, src_rq, this_rq); ++ return true; ++ } else { ++ raw_spin_rq_unlock(src_rq); ++ raw_spin_rq_lock(this_rq); ++ return false; ++ } +} +#else /* CONFIG_SMP */ -+static bool task_can_run_on_remote_rq(struct task_struct *p, struct rq *rq) { return false; } -+static bool consume_remote_task(struct rq *rq, struct scx_dispatch_q *dsq, -+ struct task_struct *p, struct rq *task_rq) { return false; } ++static inline void move_remote_task_to_local_dsq(struct task_struct *p, u64 enq_flags, struct rq *src_rq, struct rq *dst_rq) { WARN_ON_ONCE(1); } ++static inline bool task_can_run_on_remote_rq(struct task_struct *p, struct rq *rq, bool trigger_error) { return false; } ++static inline bool consume_remote_task(struct rq *this_rq, struct task_struct *p, struct scx_dispatch_q *dsq, struct rq *task_rq) { return false; } +#endif /* CONFIG_SMP */ + +static bool consume_dispatch_q(struct rq *rq, struct scx_dispatch_q *dsq) @@ -3766,12 +4293,14 @@ index 000000000000..0dac88d0e578 + struct rq *task_rq = task_rq(p); + + if (rq == task_rq) { -+ consume_local_task(rq, dsq, p); ++ task_unlink_from_dsq(p, dsq); ++ move_local_task_to_local_dsq(p, 0, dsq, rq); ++ raw_spin_unlock(&dsq->lock); + return true; + } + -+ if (task_can_run_on_remote_rq(p, rq)) { -+ if (likely(consume_remote_task(rq, dsq, p, task_rq))) ++ if (task_can_run_on_remote_rq(p, rq, false)) { ++ if (likely(consume_remote_task(rq, p, dsq, task_rq))) + return true; + goto retry; + } @@ -3781,122 +4310,102 @@ index 000000000000..0dac88d0e578 + return false; +} + -+enum dispatch_to_local_dsq_ret { -+ DTL_DISPATCHED, /* successfully dispatched */ -+ DTL_LOST, /* lost race to dequeue */ -+ DTL_NOT_LOCAL, /* destination is not a local DSQ */ -+ DTL_INVALID, /* invalid local dsq_id */ -+}; ++static bool consume_global_dsq(struct rq *rq) ++{ ++ int node = cpu_to_node(cpu_of(rq)); ++ ++ return consume_dispatch_q(rq, global_dsqs[node]); ++} + +/** + * dispatch_to_local_dsq - Dispatch a task to a local dsq + * @rq: current rq which is locked -+ * @dsq_id: destination dsq ID ++ * @dst_dsq: destination DSQ + * @p: task to dispatch + * @enq_flags: %SCX_ENQ_* + * -+ * We're holding @rq lock and want to dispatch @p to the local DSQ identified by -+ * @dsq_id. This function performs all the synchronization dancing needed -+ * because local DSQs are protected with rq locks. ++ * We're holding @rq lock and want to dispatch @p to @dst_dsq which is a local ++ * DSQ. This function performs all the synchronization dancing needed because ++ * local DSQs are protected with rq locks. + * + * The caller must have exclusive ownership of @p (e.g. through + * %SCX_OPSS_DISPATCHING). + */ -+static enum dispatch_to_local_dsq_ret -+dispatch_to_local_dsq(struct rq *rq, u64 dsq_id, struct task_struct *p, -+ u64 enq_flags) ++static void dispatch_to_local_dsq(struct rq *rq, struct scx_dispatch_q *dst_dsq, ++ struct task_struct *p, u64 enq_flags) +{ + struct rq *src_rq = task_rq(p); -+ struct rq *dst_rq; ++ struct rq *dst_rq = container_of(dst_dsq, struct rq, scx.local_dsq); + + /* + * We're synchronized against dequeue through DISPATCHING. As @p can't + * be dequeued, its task_rq and cpus_allowed are stable too. ++ * ++ * If dispatching to @rq that @p is already on, no lock dancing needed. + */ -+ if (dsq_id == SCX_DSQ_LOCAL) { -+ dst_rq = rq; -+ } else if ((dsq_id & SCX_DSQ_LOCAL_ON) == SCX_DSQ_LOCAL_ON) { -+ s32 cpu = dsq_id & SCX_DSQ_LOCAL_CPU_MASK; -+ -+ if (!ops_cpu_valid(cpu, "in SCX_DSQ_LOCAL_ON dispatch verdict")) -+ return DTL_INVALID; -+ dst_rq = cpu_rq(cpu); -+ } else { -+ return DTL_NOT_LOCAL; -+ } -+ -+ /* if dispatching to @rq that @p is already on, no lock dancing needed */ + if (rq == src_rq && rq == dst_rq) { -+ dispatch_enqueue(&dst_rq->scx.local_dsq, p, -+ enq_flags | SCX_ENQ_CLEAR_OPSS); -+ return DTL_DISPATCHED; ++ dispatch_enqueue(dst_dsq, p, enq_flags | SCX_ENQ_CLEAR_OPSS); ++ return; + } + +#ifdef CONFIG_SMP -+ if (cpumask_test_cpu(cpu_of(dst_rq), p->cpus_ptr)) { -+ struct rq *locked_dst_rq = dst_rq; -+ bool dsp; ++ if (unlikely(!task_can_run_on_remote_rq(p, dst_rq, true))) { ++ dispatch_enqueue(find_global_dsq(p), p, ++ enq_flags | SCX_ENQ_CLEAR_OPSS); ++ return; ++ } + -+ /* -+ * @p is on a possibly remote @src_rq which we need to lock to -+ * move the task. If dequeue is in progress, it'd be locking -+ * @src_rq and waiting on DISPATCHING, so we can't grab @src_rq -+ * lock while holding DISPATCHING. -+ * -+ * As DISPATCHING guarantees that @p is wholly ours, we can -+ * pretend that we're moving from a DSQ and use the same -+ * mechanism - mark the task under transfer with holding_cpu, -+ * release DISPATCHING and then follow the same protocol. -+ */ -+ p->scx.holding_cpu = raw_smp_processor_id(); ++ /* ++ * @p is on a possibly remote @src_rq which we need to lock to move the ++ * task. If dequeue is in progress, it'd be locking @src_rq and waiting ++ * on DISPATCHING, so we can't grab @src_rq lock while holding ++ * DISPATCHING. ++ * ++ * As DISPATCHING guarantees that @p is wholly ours, we can pretend that ++ * we're moving from a DSQ and use the same mechanism - mark the task ++ * under transfer with holding_cpu, release DISPATCHING and then follow ++ * the same protocol. See unlink_dsq_and_lock_src_rq(). ++ */ ++ p->scx.holding_cpu = raw_smp_processor_id(); + -+ /* store_release ensures that dequeue sees the above */ -+ atomic_long_set_release(&p->scx.ops_state, SCX_OPSS_NONE); ++ /* store_release ensures that dequeue sees the above */ ++ atomic_long_set_release(&p->scx.ops_state, SCX_OPSS_NONE); + -+ dispatch_to_local_dsq_lock(rq, src_rq, locked_dst_rq); ++ /* switch to @src_rq lock */ ++ if (rq != src_rq) { ++ raw_spin_rq_unlock(rq); ++ raw_spin_rq_lock(src_rq); ++ } + ++ /* task_rq couldn't have changed if we're still the holding cpu */ ++ if (likely(p->scx.holding_cpu == raw_smp_processor_id()) && ++ !WARN_ON_ONCE(src_rq != task_rq(p))) { + /* -+ * We don't require the BPF scheduler to avoid dispatching to -+ * offline CPUs mostly for convenience but also because CPUs can -+ * go offline between scx_bpf_dispatch() calls and here. If @p -+ * is destined to an offline CPU, queue it on its current CPU -+ * instead, which should always be safe. As this is an allowed -+ * behavior, don't trigger an ops error. ++ * If @p is staying on the same rq, there's no need to go ++ * through the full deactivate/activate cycle. Optimize by ++ * abbreviating move_remote_task_to_local_dsq(). + */ -+ if (!scx_rq_online(dst_rq)) -+ dst_rq = src_rq; -+ + if (src_rq == dst_rq) { -+ /* -+ * As @p is staying on the same rq, there's no need to -+ * go through the full deactivate/activate cycle. -+ * Optimize by abbreviating the operations in -+ * move_task_to_local_dsq(). -+ */ -+ dsp = p->scx.holding_cpu == raw_smp_processor_id(); -+ if (likely(dsp)) { -+ p->scx.holding_cpu = -1; -+ dispatch_enqueue(&dst_rq->scx.local_dsq, p, -+ enq_flags); -+ } ++ p->scx.holding_cpu = -1; ++ dispatch_enqueue(&dst_rq->scx.local_dsq, p, enq_flags); + } else { -+ dsp = move_task_to_local_dsq(dst_rq, p, enq_flags); ++ move_remote_task_to_local_dsq(p, enq_flags, ++ src_rq, dst_rq); + } + + /* if the destination CPU is idle, wake it up */ -+ if (dsp && sched_class_above(p->sched_class, -+ dst_rq->curr->sched_class)) ++ if (sched_class_above(p->sched_class, dst_rq->curr->sched_class)) + resched_curr(dst_rq); ++ } + -+ dispatch_to_local_dsq_unlock(rq, src_rq, locked_dst_rq); -+ -+ return dsp ? DTL_DISPATCHED : DTL_LOST; ++ /* switch back to @rq lock */ ++ if (rq != dst_rq) { ++ raw_spin_rq_unlock(dst_rq); ++ raw_spin_rq_lock(rq); + } ++#else /* CONFIG_SMP */ ++ BUG(); /* control can not reach here on UP */ +#endif /* CONFIG_SMP */ -+ -+ scx_ops_error("SCX_DSQ_LOCAL[_ON] verdict target cpu %d not allowed for %s[%d]", -+ cpu_of(dst_rq), p->comm, p->pid); -+ return DTL_INVALID; +} + +/** @@ -3971,20 +4480,12 @@ index 000000000000..0dac88d0e578 + + BUG_ON(!(p->scx.flags & SCX_TASK_QUEUED)); + -+ switch (dispatch_to_local_dsq(rq, dsq_id, p, enq_flags)) { -+ case DTL_DISPATCHED: -+ break; -+ case DTL_LOST: -+ break; -+ case DTL_INVALID: -+ dsq_id = SCX_DSQ_GLOBAL; -+ fallthrough; -+ case DTL_NOT_LOCAL: -+ dsq = find_dsq_for_dispatch(cpu_rq(raw_smp_processor_id()), -+ dsq_id, p); ++ dsq = find_dsq_for_dispatch(this_rq(), dsq_id, p); ++ ++ if (dsq->id == SCX_DSQ_LOCAL) ++ dispatch_to_local_dsq(rq, dsq, p, enq_flags); ++ else + dispatch_enqueue(dsq, p, enq_flags | SCX_ENQ_CLEAR_OPSS); -+ break; -+ } +} + +static void flush_dispatch_buf(struct rq *rq) @@ -4046,7 +4547,7 @@ index 000000000000..0dac88d0e578 + * same conditions later and pick @rq->curr accordingly. + */ + if ((prev->scx.flags & SCX_TASK_QUEUED) && -+ prev->scx.slice && !scx_ops_bypassing()) { ++ prev->scx.slice && !scx_rq_bypassing(rq)) { + if (local) + prev->scx.flags |= SCX_TASK_BAL_KEEP; + goto has_tasks; @@ -4057,10 +4558,10 @@ index 000000000000..0dac88d0e578 + if (rq->scx.local_dsq.nr) + goto has_tasks; + -+ if (consume_dispatch_q(rq, &scx_dsq_global)) ++ if (consume_global_dsq(rq)) + goto has_tasks; + -+ if (!SCX_HAS_OP(dispatch) || scx_ops_bypassing() || !scx_rq_online(rq)) ++ if (!SCX_HAS_OP(dispatch) || scx_rq_bypassing(rq) || !scx_rq_online(rq)) + goto out; + + dspc->rq = rq; @@ -4082,7 +4583,7 @@ index 000000000000..0dac88d0e578 + + if (rq->scx.local_dsq.nr) + goto has_tasks; -+ if (consume_dispatch_q(rq, &scx_dsq_global)) ++ if (consume_global_dsq(rq)) + goto has_tasks; + + /* @@ -4109,7 +4610,6 @@ index 000000000000..0dac88d0e578 + return has_tasks; +} + -+#ifdef CONFIG_SMP +static int balance_scx(struct rq *rq, struct task_struct *prev, + struct rq_flags *rf) +{ @@ -4143,7 +4643,31 @@ index 000000000000..0dac88d0e578 + + return ret; +} -+#endif ++ ++static void process_ddsp_deferred_locals(struct rq *rq) ++{ ++ struct task_struct *p; ++ ++ lockdep_assert_rq_held(rq); ++ ++ /* ++ * Now that @rq can be unlocked, execute the deferred enqueueing of ++ * tasks directly dispatched to the local DSQs of other CPUs. See ++ * direct_dispatch(). Keep popping from the head instead of using ++ * list_for_each_entry_safe() as dispatch_local_dsq() may unlock @rq ++ * temporarily. ++ */ ++ while ((p = list_first_entry_or_null(&rq->scx.ddsp_deferred_locals, ++ struct task_struct, scx.dsq_list.node))) { ++ struct scx_dispatch_q *dsq; ++ ++ list_del_init(&p->scx.dsq_list.node); ++ ++ dsq = find_dsq_for_dispatch(rq, p->scx.ddsp_dsq_id, p); ++ if (!WARN_ON_ONCE(dsq->id != SCX_DSQ_LOCAL)) ++ dispatch_to_local_dsq(rq, dsq, p, p->scx.ddsp_enq_flags); ++ } ++} + +static void set_next_task_scx(struct rq *rq, struct task_struct *p, bool first) +{ @@ -4187,62 +4711,71 @@ index 000000000000..0dac88d0e578 + } +} + -+static void process_ddsp_deferred_locals(struct rq *rq) ++static enum scx_cpu_preempt_reason ++preempt_reason_from_class(const struct sched_class *class) ++{ ++#ifdef CONFIG_SMP ++ if (class == &stop_sched_class) ++ return SCX_CPU_PREEMPT_STOP; ++#endif ++ if (class == &dl_sched_class) ++ return SCX_CPU_PREEMPT_DL; ++ if (class == &rt_sched_class) ++ return SCX_CPU_PREEMPT_RT; ++ return SCX_CPU_PREEMPT_UNKNOWN; ++} ++ ++static void switch_class_scx(struct rq *rq, struct task_struct *next) +{ -+ struct task_struct *p, *tmp; ++ const struct sched_class *next_class = next->sched_class; + -+ lockdep_assert_rq_held(rq); ++ if (!scx_enabled()) ++ return; ++#ifdef CONFIG_SMP ++ /* ++ * Pairs with the smp_load_acquire() issued by a CPU in ++ * kick_cpus_irq_workfn() who is waiting for this CPU to perform a ++ * resched. ++ */ ++ smp_store_release(&rq->scx.pnt_seq, rq->scx.pnt_seq + 1); ++#endif ++ if (!static_branch_unlikely(&scx_ops_cpu_preempt)) ++ return; + + /* -+ * Now that @rq can be unlocked, execute the deferred enqueueing of -+ * tasks directly dispatched to the local DSQs of other CPUs. See -+ * direct_dispatch(). ++ * The callback is conceptually meant to convey that the CPU is no ++ * longer under the control of SCX. Therefore, don't invoke the callback ++ * if the next class is below SCX (in which case the BPF scheduler has ++ * actively decided not to schedule any tasks on the CPU). + */ -+ list_for_each_entry_safe(p, tmp, &rq->scx.ddsp_deferred_locals, -+ scx.dsq_list.node) { -+ s32 ret; ++ if (sched_class_above(&ext_sched_class, next_class)) ++ return; + -+ list_del_init(&p->scx.dsq_list.node); ++ /* ++ * At this point we know that SCX was preempted by a higher priority ++ * sched_class, so invoke the ->cpu_release() callback if we have not ++ * done so already. We only send the callback once between SCX being ++ * preempted, and it regaining control of the CPU. ++ * ++ * ->cpu_release() complements ->cpu_acquire(), which is emitted the ++ * next time that balance_scx() is invoked. ++ */ ++ if (!rq->scx.cpu_released) { ++ if (SCX_HAS_OP(cpu_release)) { ++ struct scx_cpu_release_args args = { ++ .reason = preempt_reason_from_class(next_class), ++ .task = next, ++ }; + -+ ret = dispatch_to_local_dsq(rq, p->scx.ddsp_dsq_id, p, -+ p->scx.ddsp_enq_flags); -+ WARN_ON_ONCE(ret == DTL_NOT_LOCAL); ++ SCX_CALL_OP(SCX_KF_CPU_RELEASE, ++ cpu_release, cpu_of(rq), &args); ++ } ++ rq->scx.cpu_released = true; + } +} + +static void put_prev_task_scx(struct rq *rq, struct task_struct *p) +{ -+#ifndef CONFIG_SMP -+ /* -+ * UP workaround. -+ * -+ * Because SCX may transfer tasks across CPUs during dispatch, dispatch -+ * is performed from its balance operation which isn't called in UP. -+ * Let's work around by calling it from the operations which come right -+ * after. -+ * -+ * 1. If the prev task is on SCX, pick_next_task() calls -+ * .put_prev_task() right after. As .put_prev_task() is also called -+ * from other places, we need to distinguish the calls which can be -+ * done by looking at the previous task's state - if still queued or -+ * dequeued with %SCX_DEQ_SLEEP, the caller must be pick_next_task(). -+ * This case is handled here. -+ * -+ * 2. If the prev task is not on SCX, the first following call into SCX -+ * will be .pick_next_task(), which is covered by calling -+ * balance_scx() from pick_next_task_scx(). -+ * -+ * Note that we can't merge the first case into the second as -+ * balance_scx() must be called before the previous SCX task goes -+ * through put_prev_task_scx(). -+ * -+ * @rq is pinned and can't be unlocked. As UP doesn't transfer tasks -+ * around, balance_one() doesn't need to. -+ */ -+ if (p->scx.flags & (SCX_TASK_QUEUED | SCX_TASK_DEQD_FOR_SLEEP)) -+ balance_one(rq, p, true); -+#endif -+ + update_curr_scx(rq); + + /* see dequeue_task_scx() on why we skip when !QUEUED */ @@ -4269,7 +4802,7 @@ index 000000000000..0dac88d0e578 + * scheduler class or core-sched forcing a different task. Leave + * it at the head of the local DSQ. + */ -+ if (p->scx.slice && !scx_ops_bypassing()) { ++ if (p->scx.slice && !scx_rq_bypassing(rq)) { + dispatch_enqueue(&rq->scx.local_dsq, p, SCX_ENQ_HEAD); + return; + } @@ -4300,12 +4833,6 @@ index 000000000000..0dac88d0e578 +{ + struct task_struct *p; + -+#ifndef CONFIG_SMP -+ /* UP workaround - see the comment at the head of put_prev_task_scx() */ -+ if (unlikely(rq->curr->sched_class != &ext_sched_class)) -+ balance_one(rq, rq->curr, true); -+#endif -+ + p = first_local_task(rq); + if (!p) + return NULL; @@ -4313,7 +4840,7 @@ index 000000000000..0dac88d0e578 + set_next_task_scx(rq, p, true); + + if (unlikely(!p->scx.slice)) { -+ if (!scx_ops_bypassing() && !scx_warned_zero_slice) { ++ if (!scx_rq_bypassing(rq) && !scx_warned_zero_slice) { + printk_deferred(KERN_WARNING "sched_ext: %s[%d] has zero slice in pick_next_task_scx()\n", + p->comm, p->pid); + scx_warned_zero_slice = true; @@ -4350,7 +4877,7 @@ index 000000000000..0dac88d0e578 + * calling ops.core_sched_before(). Accesses are controlled by the + * verifier. + */ -+ if (SCX_HAS_OP(core_sched_before) && !scx_ops_bypassing()) ++ if (SCX_HAS_OP(core_sched_before) && !scx_rq_bypassing(task_rq(a))) + return SCX_CALL_OP_2TASKS_RET(SCX_KF_REST, core_sched_before, + (struct task_struct *)a, + (struct task_struct *)b); @@ -4402,69 +4929,6 @@ index 000000000000..0dac88d0e578 +} +#endif /* CONFIG_SCHED_CORE */ + -+static enum scx_cpu_preempt_reason -+preempt_reason_from_class(const struct sched_class *class) -+{ -+#ifdef CONFIG_SMP -+ if (class == &stop_sched_class) -+ return SCX_CPU_PREEMPT_STOP; -+#endif -+ if (class == &dl_sched_class) -+ return SCX_CPU_PREEMPT_DL; -+ if (class == &rt_sched_class) -+ return SCX_CPU_PREEMPT_RT; -+ return SCX_CPU_PREEMPT_UNKNOWN; -+} -+ -+static void switch_class_scx(struct rq *rq, struct task_struct *next) -+{ -+ const struct sched_class *next_class = next->sched_class; -+ -+ if (!scx_enabled()) -+ return; -+#ifdef CONFIG_SMP -+ /* -+ * Pairs with the smp_load_acquire() issued by a CPU in -+ * kick_cpus_irq_workfn() who is waiting for this CPU to perform a -+ * resched. -+ */ -+ smp_store_release(&rq->scx.pnt_seq, rq->scx.pnt_seq + 1); -+#endif -+ if (!static_branch_unlikely(&scx_ops_cpu_preempt)) -+ return; -+ -+ /* -+ * The callback is conceptually meant to convey that the CPU is no -+ * longer under the control of SCX. Therefore, don't invoke the callback -+ * if the next class is below SCX (in which case the BPF scheduler has -+ * actively decided not to schedule any tasks on the CPU). -+ */ -+ if (sched_class_above(&ext_sched_class, next_class)) -+ return; -+ -+ /* -+ * At this point we know that SCX was preempted by a higher priority -+ * sched_class, so invoke the ->cpu_release() callback if we have not -+ * done so already. We only send the callback once between SCX being -+ * preempted, and it regaining control of the CPU. -+ * -+ * ->cpu_release() complements ->cpu_acquire(), which is emitted the -+ * next time that balance_scx() is invoked. -+ */ -+ if (!rq->scx.cpu_released) { -+ if (SCX_HAS_OP(cpu_release)) { -+ struct scx_cpu_release_args args = { -+ .reason = preempt_reason_from_class(next_class), -+ .task = next, -+ }; -+ -+ SCX_CALL_OP(SCX_KF_CPU_RELEASE, -+ cpu_release, cpu_of(rq), &args); -+ } -+ rq->scx.cpu_released = true; -+ } -+} -+ +#ifdef CONFIG_SMP + +static bool test_and_clear_cpu_idle(int cpu) @@ -4815,7 +5279,7 @@ index 000000000000..0dac88d0e578 + * While disabling, always resched and refresh core-sched timestamp as + * we can't trust the slice management or ops.core_sched_before(). + */ -+ if (scx_ops_bypassing()) { ++ if (scx_rq_bypassing(rq)) { + curr->scx.slice = 0; + touch_core_sched(rq, curr); + } else if (SCX_HAS_OP(tick)) { @@ -4826,6 +5290,28 @@ index 000000000000..0dac88d0e578 + resched_curr(rq); +} + ++#ifdef CONFIG_EXT_GROUP_SCHED ++static struct cgroup *tg_cgrp(struct task_group *tg) ++{ ++ /* ++ * If CGROUP_SCHED is disabled, @tg is NULL. If @tg is an autogroup, ++ * @tg->css.cgroup is NULL. In both cases, @tg can be treated as the ++ * root cgroup. ++ */ ++ if (tg && tg->css.cgroup) ++ return tg->css.cgroup; ++ else ++ return &cgrp_dfl_root.cgrp; ++} ++ ++#define SCX_INIT_TASK_ARGS_CGROUP(tg) .cgroup = tg_cgrp(tg), ++ ++#else /* CONFIG_EXT_GROUP_SCHED */ ++ ++#define SCX_INIT_TASK_ARGS_CGROUP(tg) ++ ++#endif /* CONFIG_EXT_GROUP_SCHED */ ++ +static enum scx_task_state scx_get_task_state(const struct task_struct *p) +{ + return (p->scx.flags & SCX_TASK_STATE_MASK) >> SCX_TASK_STATE_SHIFT; @@ -4870,6 +5356,7 @@ index 000000000000..0dac88d0e578 + + if (SCX_HAS_OP(init_task)) { + struct scx_init_task_args args = { ++ SCX_INIT_TASK_ARGS_CGROUP(tg) + .fork = fork, + }; + @@ -4883,24 +5370,29 @@ index 000000000000..0dac88d0e578 + scx_set_task_state(p, SCX_TASK_INIT); + + if (p->scx.disallow) { -+ struct rq *rq; -+ struct rq_flags rf; ++ if (!fork) { ++ struct rq *rq; ++ struct rq_flags rf; + -+ rq = task_rq_lock(p, &rf); ++ rq = task_rq_lock(p, &rf); + -+ /* -+ * We're either in fork or load path and @p->policy will be -+ * applied right after. Reverting @p->policy here and rejecting -+ * %SCHED_EXT transitions from scx_check_setscheduler() -+ * guarantees that if ops.init_task() sets @p->disallow, @p can -+ * never be in SCX. -+ */ -+ if (p->policy == SCHED_EXT) { -+ p->policy = SCHED_NORMAL; -+ atomic_long_inc(&scx_nr_rejected); -+ } ++ /* ++ * We're in the load path and @p->policy will be applied ++ * right after. Reverting @p->policy here and rejecting ++ * %SCHED_EXT transitions from scx_check_setscheduler() ++ * guarantees that if ops.init_task() sets @p->disallow, ++ * @p can never be in SCX. ++ */ ++ if (p->policy == SCHED_EXT) { ++ p->policy = SCHED_NORMAL; ++ atomic_long_inc(&scx_nr_rejected); ++ } + -+ task_rq_unlock(rq, p, &rf); ++ task_rq_unlock(rq, p, &rf); ++ } else if (p->policy == SCHED_EXT) { ++ scx_ops_error("ops.init_task() set task->scx.disallow for %s[%d] during fork", ++ p->comm, p->pid); ++ } + } + + p->scx.flags |= SCX_TASK_RESET_RUNNABLE_AT; @@ -4929,7 +5421,7 @@ index 000000000000..0dac88d0e578 + scx_set_task_state(p, SCX_TASK_ENABLED); + + if (SCX_HAS_OP(set_weight)) -+ SCX_CALL_OP(SCX_KF_REST, set_weight, p, p->scx.weight); ++ SCX_CALL_OP_TASK(SCX_KF_REST, set_weight, p, p->scx.weight); +} + +static void scx_ops_disable_task(struct task_struct *p) @@ -5004,7 +5496,7 @@ index 000000000000..0dac88d0e578 +{ + percpu_rwsem_assert_held(&scx_fork_rwsem); + -+ if (scx_enabled()) ++ if (scx_ops_init_task_enabled) + return scx_ops_init_task(p, task_group(p), true); + else + return 0; @@ -5012,7 +5504,7 @@ index 000000000000..0dac88d0e578 + +void scx_post_fork(struct task_struct *p) +{ -+ if (scx_enabled()) { ++ if (scx_ops_init_task_enabled) { + scx_set_task_state(p, SCX_TASK_READY); + + /* @@ -5126,7 +5618,7 @@ index 000000000000..0dac88d0e578 +{ + struct task_struct *p = rq->curr; + -+ if (scx_ops_bypassing()) ++ if (scx_rq_bypassing(rq)) + return false; + + if (p->sched_class != &ext_sched_class) @@ -5141,6 +5633,222 @@ index 000000000000..0dac88d0e578 +} +#endif + ++#ifdef CONFIG_EXT_GROUP_SCHED ++ ++DEFINE_STATIC_PERCPU_RWSEM(scx_cgroup_rwsem); ++static bool scx_cgroup_enabled; ++static bool cgroup_warned_missing_weight; ++static bool cgroup_warned_missing_idle; ++ ++static void scx_cgroup_warn_missing_weight(struct task_group *tg) ++{ ++ if (scx_ops_enable_state() == SCX_OPS_DISABLED || ++ cgroup_warned_missing_weight) ++ return; ++ ++ if ((scx_ops.flags & SCX_OPS_HAS_CGROUP_WEIGHT) || !tg->css.parent) ++ return; ++ ++ pr_warn("sched_ext: \"%s\" does not implement cgroup cpu.weight\n", ++ scx_ops.name); ++ cgroup_warned_missing_weight = true; ++} ++ ++static void scx_cgroup_warn_missing_idle(struct task_group *tg) ++{ ++ if (!scx_cgroup_enabled || cgroup_warned_missing_idle) ++ return; ++ ++ if (!tg->idle) ++ return; ++ ++ pr_warn("sched_ext: \"%s\" does not implement cgroup cpu.idle\n", ++ scx_ops.name); ++ cgroup_warned_missing_idle = true; ++} ++ ++int scx_tg_online(struct task_group *tg) ++{ ++ int ret = 0; ++ ++ WARN_ON_ONCE(tg->scx_flags & (SCX_TG_ONLINE | SCX_TG_INITED)); ++ ++ percpu_down_read(&scx_cgroup_rwsem); ++ ++ scx_cgroup_warn_missing_weight(tg); ++ ++ if (scx_cgroup_enabled) { ++ if (SCX_HAS_OP(cgroup_init)) { ++ struct scx_cgroup_init_args args = ++ { .weight = tg->scx_weight }; ++ ++ ret = SCX_CALL_OP_RET(SCX_KF_UNLOCKED, cgroup_init, ++ tg->css.cgroup, &args); ++ if (ret) ++ ret = ops_sanitize_err("cgroup_init", ret); ++ } ++ if (ret == 0) ++ tg->scx_flags |= SCX_TG_ONLINE | SCX_TG_INITED; ++ } else { ++ tg->scx_flags |= SCX_TG_ONLINE; ++ } ++ ++ percpu_up_read(&scx_cgroup_rwsem); ++ return ret; ++} ++ ++void scx_tg_offline(struct task_group *tg) ++{ ++ WARN_ON_ONCE(!(tg->scx_flags & SCX_TG_ONLINE)); ++ ++ percpu_down_read(&scx_cgroup_rwsem); ++ ++ if (SCX_HAS_OP(cgroup_exit) && (tg->scx_flags & SCX_TG_INITED)) ++ SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_exit, tg->css.cgroup); ++ tg->scx_flags &= ~(SCX_TG_ONLINE | SCX_TG_INITED); ++ ++ percpu_up_read(&scx_cgroup_rwsem); ++} ++ ++int scx_cgroup_can_attach(struct cgroup_taskset *tset) ++{ ++ struct cgroup_subsys_state *css; ++ struct task_struct *p; ++ int ret; ++ ++ /* released in scx_finish/cancel_attach() */ ++ percpu_down_read(&scx_cgroup_rwsem); ++ ++ if (!scx_cgroup_enabled) ++ return 0; ++ ++ cgroup_taskset_for_each(p, css, tset) { ++ struct cgroup *from = tg_cgrp(task_group(p)); ++ struct cgroup *to = tg_cgrp(css_tg(css)); ++ ++ WARN_ON_ONCE(p->scx.cgrp_moving_from); ++ ++ /* ++ * sched_move_task() omits identity migrations. Let's match the ++ * behavior so that ops.cgroup_prep_move() and ops.cgroup_move() ++ * always match one-to-one. ++ */ ++ if (from == to) ++ continue; ++ ++ if (SCX_HAS_OP(cgroup_prep_move)) { ++ ret = SCX_CALL_OP_RET(SCX_KF_UNLOCKED, cgroup_prep_move, ++ p, from, css->cgroup); ++ if (ret) ++ goto err; ++ } ++ ++ p->scx.cgrp_moving_from = from; ++ } ++ ++ return 0; ++ ++err: ++ cgroup_taskset_for_each(p, css, tset) { ++ if (SCX_HAS_OP(cgroup_cancel_move) && p->scx.cgrp_moving_from) ++ SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_cancel_move, p, ++ p->scx.cgrp_moving_from, css->cgroup); ++ p->scx.cgrp_moving_from = NULL; ++ } ++ ++ percpu_up_read(&scx_cgroup_rwsem); ++ return ops_sanitize_err("cgroup_prep_move", ret); ++} ++ ++void scx_move_task(struct task_struct *p) ++{ ++ if (!scx_cgroup_enabled) ++ return; ++ ++ /* ++ * We're called from sched_move_task() which handles both cgroup and ++ * autogroup moves. Ignore the latter. ++ * ++ * Also ignore exiting tasks, because in the exit path tasks transition ++ * from the autogroup to the root group, so task_group_is_autogroup() ++ * alone isn't able to catch exiting autogroup tasks. This is safe for ++ * cgroup_move(), because cgroup migrations never happen for PF_EXITING ++ * tasks. ++ */ ++ if (task_group_is_autogroup(task_group(p)) || (p->flags & PF_EXITING)) ++ return; ++ ++ /* ++ * @p must have ops.cgroup_prep_move() called on it and thus ++ * cgrp_moving_from set. ++ */ ++ if (SCX_HAS_OP(cgroup_move) && !WARN_ON_ONCE(!p->scx.cgrp_moving_from)) ++ SCX_CALL_OP_TASK(SCX_KF_UNLOCKED, cgroup_move, p, ++ p->scx.cgrp_moving_from, tg_cgrp(task_group(p))); ++ p->scx.cgrp_moving_from = NULL; ++} ++ ++void scx_cgroup_finish_attach(void) ++{ ++ percpu_up_read(&scx_cgroup_rwsem); ++} ++ ++void scx_cgroup_cancel_attach(struct cgroup_taskset *tset) ++{ ++ struct cgroup_subsys_state *css; ++ struct task_struct *p; ++ ++ if (!scx_cgroup_enabled) ++ goto out_unlock; ++ ++ cgroup_taskset_for_each(p, css, tset) { ++ if (SCX_HAS_OP(cgroup_cancel_move) && p->scx.cgrp_moving_from) ++ SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_cancel_move, p, ++ p->scx.cgrp_moving_from, css->cgroup); ++ p->scx.cgrp_moving_from = NULL; ++ } ++out_unlock: ++ percpu_up_read(&scx_cgroup_rwsem); ++} ++ ++void scx_group_set_weight(struct task_group *tg, unsigned long weight) ++{ ++ percpu_down_read(&scx_cgroup_rwsem); ++ ++ if (scx_cgroup_enabled && tg->scx_weight != weight) { ++ if (SCX_HAS_OP(cgroup_set_weight)) ++ SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_set_weight, ++ tg_cgrp(tg), weight); ++ tg->scx_weight = weight; ++ } ++ ++ percpu_up_read(&scx_cgroup_rwsem); ++} ++ ++void scx_group_set_idle(struct task_group *tg, bool idle) ++{ ++ percpu_down_read(&scx_cgroup_rwsem); ++ scx_cgroup_warn_missing_idle(tg); ++ percpu_up_read(&scx_cgroup_rwsem); ++} ++ ++static void scx_cgroup_lock(void) ++{ ++ percpu_down_write(&scx_cgroup_rwsem); ++} ++ ++static void scx_cgroup_unlock(void) ++{ ++ percpu_up_write(&scx_cgroup_rwsem); ++} ++ ++#else /* CONFIG_EXT_GROUP_SCHED */ ++ ++static inline void scx_cgroup_lock(void) {} ++static inline void scx_cgroup_unlock(void) {} ++ ++#endif /* CONFIG_EXT_GROUP_SCHED */ ++ +/* + * Omitted operations: + * @@ -5161,6 +5869,7 @@ index 000000000000..0dac88d0e578 + + .wakeup_preempt = wakeup_preempt_scx, + ++ .balance = balance_scx, + .pick_next_task = pick_next_task_scx, + + .put_prev_task = put_prev_task_scx, @@ -5169,7 +5878,6 @@ index 000000000000..0dac88d0e578 + .switch_class = switch_class_scx, + +#ifdef CONFIG_SMP -+ .balance = balance_scx, + .select_task_rq = select_task_rq_scx, + .task_woken = task_woken_scx, + .set_cpus_allowed = set_cpus_allowed_scx, @@ -5278,6 +5986,102 @@ index 000000000000..0dac88d0e578 + rcu_read_unlock(); +} + ++#ifdef CONFIG_EXT_GROUP_SCHED ++static void scx_cgroup_exit(void) ++{ ++ struct cgroup_subsys_state *css; ++ ++ percpu_rwsem_assert_held(&scx_cgroup_rwsem); ++ ++ WARN_ON_ONCE(!scx_cgroup_enabled); ++ scx_cgroup_enabled = false; ++ ++ /* ++ * scx_tg_on/offline() are excluded through scx_cgroup_rwsem. If we walk ++ * cgroups and exit all the inited ones, all online cgroups are exited. ++ */ ++ rcu_read_lock(); ++ css_for_each_descendant_post(css, &root_task_group.css) { ++ struct task_group *tg = css_tg(css); ++ ++ if (!(tg->scx_flags & SCX_TG_INITED)) ++ continue; ++ tg->scx_flags &= ~SCX_TG_INITED; ++ ++ if (!scx_ops.cgroup_exit) ++ continue; ++ ++ if (WARN_ON_ONCE(!css_tryget(css))) ++ continue; ++ rcu_read_unlock(); ++ ++ SCX_CALL_OP(SCX_KF_UNLOCKED, cgroup_exit, css->cgroup); ++ ++ rcu_read_lock(); ++ css_put(css); ++ } ++ rcu_read_unlock(); ++} ++ ++static int scx_cgroup_init(void) ++{ ++ struct cgroup_subsys_state *css; ++ int ret; ++ ++ percpu_rwsem_assert_held(&scx_cgroup_rwsem); ++ ++ cgroup_warned_missing_weight = false; ++ cgroup_warned_missing_idle = false; ++ ++ /* ++ * scx_tg_on/offline() are excluded thorugh scx_cgroup_rwsem. If we walk ++ * cgroups and init, all online cgroups are initialized. ++ */ ++ rcu_read_lock(); ++ css_for_each_descendant_pre(css, &root_task_group.css) { ++ struct task_group *tg = css_tg(css); ++ struct scx_cgroup_init_args args = { .weight = tg->scx_weight }; ++ ++ scx_cgroup_warn_missing_weight(tg); ++ scx_cgroup_warn_missing_idle(tg); ++ ++ if ((tg->scx_flags & ++ (SCX_TG_ONLINE | SCX_TG_INITED)) != SCX_TG_ONLINE) ++ continue; ++ ++ if (!scx_ops.cgroup_init) { ++ tg->scx_flags |= SCX_TG_INITED; ++ continue; ++ } ++ ++ if (WARN_ON_ONCE(!css_tryget(css))) ++ continue; ++ rcu_read_unlock(); ++ ++ ret = SCX_CALL_OP_RET(SCX_KF_UNLOCKED, cgroup_init, ++ css->cgroup, &args); ++ if (ret) { ++ css_put(css); ++ return ret; ++ } ++ tg->scx_flags |= SCX_TG_INITED; ++ ++ rcu_read_lock(); ++ css_put(css); ++ } ++ rcu_read_unlock(); ++ ++ WARN_ON_ONCE(scx_cgroup_enabled); ++ scx_cgroup_enabled = true; ++ ++ return 0; ++} ++ ++#else ++static void scx_cgroup_exit(void) {} ++static int scx_cgroup_init(void) { return 0; } ++#endif ++ + +/******************************************************************************** + * Sysfs interface and ops enable/disable. @@ -5318,11 +6122,19 @@ index 000000000000..0dac88d0e578 +} +SCX_ATTR(hotplug_seq); + ++static ssize_t scx_attr_enable_seq_show(struct kobject *kobj, ++ struct kobj_attribute *ka, char *buf) ++{ ++ return sysfs_emit(buf, "%ld\n", atomic_long_read(&scx_enable_seq)); ++} ++SCX_ATTR(enable_seq); ++ +static struct attribute *scx_global_attrs[] = { + &scx_attr_state.attr, + &scx_attr_switch_all.attr, + &scx_attr_nr_rejected.attr, + &scx_attr_hotplug_seq.attr, ++ &scx_attr_enable_seq.attr, + NULL, +}; + @@ -5421,16 +6233,8 @@ index 000000000000..0dac88d0e578 + } + + /* -+ * We need to guarantee that no tasks are on the BPF scheduler while -+ * bypassing. Either we see enabled or the enable path sees the -+ * increased bypass_depth before moving tasks to SCX. -+ */ -+ if (!scx_enabled()) -+ return; -+ -+ /* + * No task property is changing. We just need to make sure all currently -+ * queued tasks are re-queued according to the new scx_ops_bypassing() ++ * queued tasks are re-queued according to the new scx_rq_bypassing() + * state. As an optimization, walk each rq's runnable_list instead of + * the scx_tasks list. + * @@ -5444,6 +6248,24 @@ index 000000000000..0dac88d0e578 + + rq_lock_irqsave(rq, &rf); + ++ if (bypass) { ++ WARN_ON_ONCE(rq->scx.flags & SCX_RQ_BYPASSING); ++ rq->scx.flags |= SCX_RQ_BYPASSING; ++ } else { ++ WARN_ON_ONCE(!(rq->scx.flags & SCX_RQ_BYPASSING)); ++ rq->scx.flags &= ~SCX_RQ_BYPASSING; ++ } ++ ++ /* ++ * We need to guarantee that no tasks are on the BPF scheduler ++ * while bypassing. Either we see enabled or the enable path ++ * sees scx_rq_bypassing() before moving tasks to SCX. ++ */ ++ if (!scx_enabled()) { ++ rq_unlock_irqrestore(rq, &rf); ++ continue; ++ } ++ + /* + * The use of list_for_each_entry_safe_reverse() is required + * because each task is going to be removed from and added back @@ -5499,11 +6321,11 @@ index 000000000000..0dac88d0e578 +{ + switch (kind) { + case SCX_EXIT_UNREG: -+ return "Scheduler unregistered from user space"; ++ return "unregistered from user space"; + case SCX_EXIT_UNREG_BPF: -+ return "Scheduler unregistered from BPF"; ++ return "unregistered from BPF"; + case SCX_EXIT_UNREG_KERN: -+ return "Scheduler unregistered from the main kernel"; ++ return "unregistered from the main kernel"; + case SCX_EXIT_SYSRQ: + return "disabled by sysrq-S"; + case SCX_EXIT_ERROR: @@ -5569,66 +6391,64 @@ index 000000000000..0dac88d0e578 + WRITE_ONCE(scx_switching_all, false); + + /* -+ * Avoid racing against fork. See scx_ops_enable() for explanation on -+ * the locking order. ++ * Shut down cgroup support before tasks so that the cgroup attach path ++ * doesn't race against scx_ops_exit_task(). ++ */ ++ scx_cgroup_lock(); ++ scx_cgroup_exit(); ++ scx_cgroup_unlock(); ++ ++ /* ++ * The BPF scheduler is going away. All tasks including %TASK_DEAD ones ++ * must be switched out and exited synchronously. + */ + percpu_down_write(&scx_fork_rwsem); -+ cpus_read_lock(); ++ ++ scx_ops_init_task_enabled = false; + + spin_lock_irq(&scx_tasks_lock); + scx_task_iter_init(&sti); -+ /* -+ * Invoke scx_ops_exit_task() on all non-idle tasks, including -+ * TASK_DEAD tasks. Because dead tasks may have a nonzero refcount, -+ * we may not have invoked sched_ext_free() on them by the time a -+ * scheduler is disabled. We must therefore exit the task here, or we'd -+ * fail to invoke ops.exit_task(), as the scheduler will have been -+ * unloaded by the time the task is subsequently exited on the -+ * sched_ext_free() path. -+ */ -+ while ((p = scx_task_iter_next_locked(&sti, true))) { ++ while ((p = scx_task_iter_next_locked(&sti))) { + const struct sched_class *old_class = p->sched_class; + struct sched_enq_and_set_ctx ctx; + -+ if (READ_ONCE(p->__state) != TASK_DEAD) { -+ sched_deq_and_put_task(p, DEQUEUE_SAVE | DEQUEUE_MOVE, -+ &ctx); ++ sched_deq_and_put_task(p, DEQUEUE_SAVE | DEQUEUE_MOVE, &ctx); + -+ p->scx.slice = min_t(u64, p->scx.slice, SCX_SLICE_DFL); -+ __setscheduler_prio(p, p->prio); -+ check_class_changing(task_rq(p), p, old_class); ++ p->scx.slice = min_t(u64, p->scx.slice, SCX_SLICE_DFL); ++ __setscheduler_prio(p, p->prio); ++ check_class_changing(task_rq(p), p, old_class); + -+ sched_enq_and_set_task(&ctx); ++ sched_enq_and_set_task(&ctx); + -+ check_class_changed(task_rq(p), p, old_class, p->prio); -+ } ++ check_class_changed(task_rq(p), p, old_class, p->prio); + scx_ops_exit_task(p); + } + scx_task_iter_exit(&sti); + spin_unlock_irq(&scx_tasks_lock); ++ percpu_up_write(&scx_fork_rwsem); + + /* no task is on scx, turn off all the switches and flush in-progress calls */ -+ static_branch_disable_cpuslocked(&__scx_ops_enabled); ++ static_branch_disable(&__scx_ops_enabled); + for (i = SCX_OPI_BEGIN; i < SCX_OPI_END; i++) -+ static_branch_disable_cpuslocked(&scx_has_op[i]); -+ static_branch_disable_cpuslocked(&scx_ops_enq_last); -+ static_branch_disable_cpuslocked(&scx_ops_enq_exiting); -+ static_branch_disable_cpuslocked(&scx_ops_cpu_preempt); -+ static_branch_disable_cpuslocked(&scx_builtin_idle_enabled); ++ static_branch_disable(&scx_has_op[i]); ++ static_branch_disable(&scx_ops_enq_last); ++ static_branch_disable(&scx_ops_enq_exiting); ++ static_branch_disable(&scx_ops_cpu_preempt); ++ static_branch_disable(&scx_builtin_idle_enabled); + synchronize_rcu(); + -+ cpus_read_unlock(); -+ percpu_up_write(&scx_fork_rwsem); -+ + if (ei->kind >= SCX_EXIT_ERROR) { -+ printk(KERN_ERR "sched_ext: BPF scheduler \"%s\" errored, disabling\n", scx_ops.name); -+ -+ if (ei->msg[0] == '\0') -+ printk(KERN_ERR "sched_ext: %s\n", ei->reason); -+ else -+ printk(KERN_ERR "sched_ext: %s (%s)\n", ei->reason, ei->msg); ++ pr_err("sched_ext: BPF scheduler \"%s\" disabled (%s)\n", ++ scx_ops.name, ei->reason); + ++ if (ei->msg[0] != '\0') ++ pr_err("sched_ext: %s: %s\n", scx_ops.name, ei->msg); ++#ifdef CONFIG_STACKTRACE + stack_trace_print(ei->bt, ei->bt_len, 2); ++#endif ++ } else { ++ pr_info("sched_ext: BPF scheduler \"%s\" disabled (%s)\n", ++ scx_ops.name, ei->reason); + } + + if (scx_ops.exit) @@ -5817,7 +6637,7 @@ index 000000000000..0dac88d0e578 + static unsigned long bt[SCX_EXIT_BT_LEN]; + char dsq_id_buf[19] = "(n/a)"; + unsigned long ops_state = atomic_long_read(&p->scx.ops_state); -+ unsigned int bt_len; ++ unsigned int bt_len = 0; + + if (p->scx.dsq) + scnprintf(dsq_id_buf, sizeof(dsq_id_buf), "0x%llx", @@ -5842,7 +6662,9 @@ index 000000000000..0dac88d0e578 + ops_dump_exit(); + } + ++#ifdef CONFIG_STACKTRACE + bt_len = stack_trace_save_tsk(p, bt, SCX_EXIT_BT_LEN, 1); ++#endif + if (bt_len) { + dump_newline(s); + dump_stack_trace(s, " ", bt, bt_len); @@ -6000,10 +6822,10 @@ index 000000000000..0dac88d0e578 + return; + + ei->exit_code = exit_code; -+ ++#ifdef CONFIG_STACKTRACE + if (kind >= SCX_EXIT_ERROR) + ei->bt_len = stack_trace_save(ei->bt, SCX_EXIT_BT_LEN, 1); -+ ++#endif + va_start(args, fmt); + vscnprintf(ei->msg, SCX_EXIT_MSG_LEN, fmt, args); + va_end(args); @@ -6061,12 +6883,12 @@ index 000000000000..0dac88d0e578 + return 0; +} + -+static int scx_ops_enable(struct sched_ext_ops *ops) ++static int scx_ops_enable(struct sched_ext_ops *ops, struct bpf_link *link) +{ + struct scx_task_iter sti; + struct task_struct *p; + unsigned long timeout; -+ int i, cpu, ret; ++ int i, cpu, node, ret; + + if (!cpumask_equal(housekeeping_cpumask(HK_TYPE_DOMAIN), + cpu_possible_mask)) { @@ -6085,6 +6907,34 @@ index 000000000000..0dac88d0e578 + } + } + ++ if (!global_dsqs) { ++ struct scx_dispatch_q **dsqs; ++ ++ dsqs = kcalloc(nr_node_ids, sizeof(dsqs[0]), GFP_KERNEL); ++ if (!dsqs) { ++ ret = -ENOMEM; ++ goto err_unlock; ++ } ++ ++ for_each_node_state(node, N_POSSIBLE) { ++ struct scx_dispatch_q *dsq; ++ ++ dsq = kzalloc_node(sizeof(*dsq), GFP_KERNEL, node); ++ if (!dsq) { ++ for_each_node_state(node, N_POSSIBLE) ++ kfree(dsqs[node]); ++ kfree(dsqs); ++ ret = -ENOMEM; ++ goto err_unlock; ++ } ++ ++ init_dsq(dsq, SCX_DSQ_GLOBAL); ++ dsqs[node] = dsq; ++ } ++ ++ global_dsqs = dsqs; ++ } ++ + if (scx_ops_enable_state() != SCX_OPS_DISABLED) { + ret = -EBUSY; + goto err_unlock; @@ -6108,12 +6958,12 @@ index 000000000000..0dac88d0e578 + } + + /* -+ * Set scx_ops, transition to PREPPING and clear exit info to arm the ++ * Set scx_ops, transition to ENABLING and clear exit info to arm the + * disable path. Failure triggers full disabling from here on. + */ + scx_ops = *ops; + -+ WARN_ON_ONCE(scx_ops_set_enable_state(SCX_OPS_PREPPING) != ++ WARN_ON_ONCE(scx_ops_set_enable_state(SCX_OPS_ENABLING) != + SCX_OPS_DISABLED); + + atomic_set(&scx_exit_kind, SCX_EXIT_NONE); @@ -6134,7 +6984,8 @@ index 000000000000..0dac88d0e578 + ret = SCX_CALL_OP_RET(SCX_KF_UNLOCKED, init); + if (ret) { + ret = ops_sanitize_err("init", ret); -+ goto err_disable_unlock_cpus; ++ cpus_read_unlock(); ++ goto err_disable; + } + } + @@ -6142,6 +6993,7 @@ index 000000000000..0dac88d0e578 + if (((void (**)(void))ops)[i]) + static_branch_enable_cpuslocked(&scx_has_op[i]); + ++ check_hotplug_seq(ops); + cpus_read_unlock(); + + ret = validate_ops(ops); @@ -6169,42 +7021,40 @@ index 000000000000..0dac88d0e578 + scx_watchdog_timeout / 2); + + /* -+ * Lock out forks before opening the floodgate so that they don't wander -+ * into the operations prematurely. -+ * -+ * We don't need to keep the CPUs stable but grab cpus_read_lock() to -+ * ease future locking changes for cgroup suport. -+ * -+ * Note that cpu_hotplug_lock must nest inside scx_fork_rwsem due to the -+ * following dependency chain: -+ * -+ * scx_fork_rwsem --> pernet_ops_rwsem --> cpu_hotplug_lock ++ * Once __scx_ops_enabled is set, %current can be switched to SCX ++ * anytime. This can lead to stalls as some BPF schedulers (e.g. ++ * userspace scheduling) may not function correctly before all tasks are ++ * switched. Init in bypass mode to guarantee forward progress. + */ -+ percpu_down_write(&scx_fork_rwsem); -+ cpus_read_lock(); -+ -+ check_hotplug_seq(ops); ++ scx_ops_bypass(true); + + for (i = SCX_OPI_NORMAL_BEGIN; i < SCX_OPI_NORMAL_END; i++) + if (((void (**)(void))ops)[i]) -+ static_branch_enable_cpuslocked(&scx_has_op[i]); ++ static_branch_enable(&scx_has_op[i]); + + if (ops->flags & SCX_OPS_ENQ_LAST) -+ static_branch_enable_cpuslocked(&scx_ops_enq_last); ++ static_branch_enable(&scx_ops_enq_last); + + if (ops->flags & SCX_OPS_ENQ_EXITING) -+ static_branch_enable_cpuslocked(&scx_ops_enq_exiting); ++ static_branch_enable(&scx_ops_enq_exiting); + if (scx_ops.cpu_acquire || scx_ops.cpu_release) -+ static_branch_enable_cpuslocked(&scx_ops_cpu_preempt); ++ static_branch_enable(&scx_ops_cpu_preempt); + + if (!ops->update_idle || (ops->flags & SCX_OPS_KEEP_BUILTIN_IDLE)) { + reset_idle_masks(); -+ static_branch_enable_cpuslocked(&scx_builtin_idle_enabled); ++ static_branch_enable(&scx_builtin_idle_enabled); + } else { -+ static_branch_disable_cpuslocked(&scx_builtin_idle_enabled); ++ static_branch_disable(&scx_builtin_idle_enabled); + } + -+ static_branch_enable_cpuslocked(&__scx_ops_enabled); ++ /* ++ * Lock out forks, cgroup on/offlining and moves before opening the ++ * floodgate so that they don't wander into the operations prematurely. ++ */ ++ percpu_down_write(&scx_fork_rwsem); ++ ++ WARN_ON_ONCE(scx_ops_init_task_enabled); ++ scx_ops_init_task_enabled = true; + + /* + * Enable ops for every task. Fork is excluded by scx_fork_rwsem @@ -6212,12 +7062,29 @@ index 000000000000..0dac88d0e578 + * leaving as sched_ext_free() can handle both prepped and enabled + * tasks. Prep all tasks first and then enable them with preemption + * disabled. ++ * ++ * All cgroups should be initialized before scx_ops_init_task() so that ++ * the BPF scheduler can reliably track each task's cgroup membership ++ * from scx_ops_init_task(). Lock out cgroup on/offlining and task ++ * migrations while tasks are being initialized so that ++ * scx_cgroup_can_attach() never sees uninitialized tasks. + */ -+ spin_lock_irq(&scx_tasks_lock); ++ scx_cgroup_lock(); ++ ret = scx_cgroup_init(); ++ if (ret) ++ goto err_disable_unlock_all; + ++ spin_lock_irq(&scx_tasks_lock); + scx_task_iter_init(&sti); -+ while ((p = scx_task_iter_next_locked(&sti, false))) { -+ get_task_struct(p); ++ while ((p = scx_task_iter_next_locked(&sti))) { ++ /* ++ * @p may already be dead, have lost all its usages counts and ++ * be waiting for RCU grace period before being freed. @p can't ++ * be initialized for SCX in such cases and should be ignored. ++ */ ++ if (!tryget_task_struct(p)) ++ continue; ++ + scx_task_iter_rq_unlock(&sti); + spin_unlock_irq(&scx_tasks_lock); + @@ -6232,51 +7099,37 @@ index 000000000000..0dac88d0e578 + goto err_disable_unlock_all; + } + ++ scx_set_task_state(p, SCX_TASK_READY); ++ + put_task_struct(p); + spin_lock_irq(&scx_tasks_lock); + } + scx_task_iter_exit(&sti); ++ spin_unlock_irq(&scx_tasks_lock); ++ scx_cgroup_unlock(); ++ percpu_up_write(&scx_fork_rwsem); + + /* -+ * All tasks are prepped but are still ops-disabled. Ensure that -+ * %current can't be scheduled out and switch everyone. -+ * preempt_disable() is necessary because we can't guarantee that -+ * %current won't be starved if scheduled out while switching. -+ */ -+ preempt_disable(); -+ -+ /* -+ * From here on, the disable path must assume that tasks have ops -+ * enabled and need to be recovered. -+ * -+ * Transition to ENABLING fails iff the BPF scheduler has already -+ * triggered scx_bpf_error(). Returning an error code here would lose -+ * the recorded error information. Exit indicating success so that the -+ * error is notified through ops.exit() with all the details. ++ * All tasks are READY. It's safe to turn on scx_enabled() and switch ++ * all eligible tasks. + */ -+ if (!scx_ops_tryset_enable_state(SCX_OPS_ENABLING, SCX_OPS_PREPPING)) { -+ preempt_enable(); -+ spin_unlock_irq(&scx_tasks_lock); -+ WARN_ON_ONCE(atomic_read(&scx_exit_kind) == SCX_EXIT_NONE); -+ ret = 0; -+ goto err_disable_unlock_all; -+ } ++ WRITE_ONCE(scx_switching_all, !(ops->flags & SCX_OPS_SWITCH_PARTIAL)); ++ static_branch_enable(&__scx_ops_enabled); + + /* -+ * We're fully committed and can't fail. The PREPPED -> ENABLED ++ * We're fully committed and can't fail. The task READY -> ENABLED + * transitions here are synchronized against sched_ext_free() through + * scx_tasks_lock. + */ -+ WRITE_ONCE(scx_switching_all, !(ops->flags & SCX_OPS_SWITCH_PARTIAL)); -+ ++ percpu_down_write(&scx_fork_rwsem); ++ spin_lock_irq(&scx_tasks_lock); + scx_task_iter_init(&sti); -+ while ((p = scx_task_iter_next_locked(&sti, false))) { ++ while ((p = scx_task_iter_next_locked(&sti))) { + const struct sched_class *old_class = p->sched_class; + struct sched_enq_and_set_ctx ctx; + + sched_deq_and_put_task(p, DEQUEUE_SAVE | DEQUEUE_MOVE, &ctx); + -+ scx_set_task_state(p, SCX_TASK_READY); + __setscheduler_prio(p, p->prio); + check_class_changing(task_rq(p), p, old_class); + @@ -6285,13 +7138,16 @@ index 000000000000..0dac88d0e578 + check_class_changed(task_rq(p), p, old_class, p->prio); + } + scx_task_iter_exit(&sti); -+ + spin_unlock_irq(&scx_tasks_lock); -+ preempt_enable(); -+ cpus_read_unlock(); + percpu_up_write(&scx_fork_rwsem); + -+ /* see above ENABLING transition for the explanation on exiting with 0 */ ++ scx_ops_bypass(false); ++ ++ /* ++ * Returning an error code here would lose the recorded error ++ * information. Exit indicating success so that the error is notified ++ * through ops.exit() with all the details. ++ */ + if (!scx_ops_tryset_enable_state(SCX_OPS_ENABLED, SCX_OPS_ENABLING)) { + WARN_ON_ONCE(atomic_read(&scx_exit_kind) == SCX_EXIT_NONE); + ret = 0; @@ -6301,9 +7157,13 @@ index 000000000000..0dac88d0e578 + if (!(ops->flags & SCX_OPS_SWITCH_PARTIAL)) + static_branch_enable(&__scx_switched_all); + ++ pr_info("sched_ext: BPF scheduler \"%s\" enabled%s\n", ++ scx_ops.name, scx_switched_all() ? "" : " (partial)"); + kobject_uevent(scx_root_kobj, KOBJ_ADD); + mutex_unlock(&scx_ops_enable_mutex); + ++ atomic_long_inc(&scx_enable_seq); ++ + return 0; + +err_del: @@ -6320,9 +7180,9 @@ index 000000000000..0dac88d0e578 + return ret; + +err_disable_unlock_all: ++ scx_cgroup_unlock(); + percpu_up_write(&scx_fork_rwsem); -+err_disable_unlock_cpus: -+ cpus_read_unlock(); ++ scx_ops_bypass(false); +err_disable: + mutex_unlock(&scx_ops_enable_mutex); + /* must be fully disabled before returning */ @@ -6514,6 +7374,11 @@ index 000000000000..0dac88d0e578 + + switch (moff) { + case offsetof(struct sched_ext_ops, init_task): ++#ifdef CONFIG_EXT_GROUP_SCHED ++ case offsetof(struct sched_ext_ops, cgroup_init): ++ case offsetof(struct sched_ext_ops, cgroup_exit): ++ case offsetof(struct sched_ext_ops, cgroup_prep_move): ++#endif + case offsetof(struct sched_ext_ops, cpu_online): + case offsetof(struct sched_ext_ops, cpu_offline): + case offsetof(struct sched_ext_ops, init): @@ -6527,12 +7392,12 @@ index 000000000000..0dac88d0e578 + return 0; +} + -+static int bpf_scx_reg(void *kdata) ++static int bpf_scx_reg(void *kdata, struct bpf_link *link) +{ -+ return scx_ops_enable(kdata); ++ return scx_ops_enable(kdata, link); +} + -+static void bpf_scx_unreg(void *kdata) ++static void bpf_scx_unreg(void *kdata, struct bpf_link *link) +{ + scx_ops_disable(SCX_EXIT_UNREG); + kthread_flush_work(&scx_ops_disable_work); @@ -6551,7 +7416,7 @@ index 000000000000..0dac88d0e578 + return 0; +} + -+static int bpf_scx_update(void *kdata, void *old_kdata) ++static int bpf_scx_update(void *kdata, void *old_kdata, struct bpf_link *link) +{ + /* + * sched_ext does not support updating the actively-loaded BPF @@ -6572,6 +7437,7 @@ index 000000000000..0dac88d0e578 +static void enqueue_stub(struct task_struct *p, u64 enq_flags) {} +static void dequeue_stub(struct task_struct *p, u64 enq_flags) {} +static void dispatch_stub(s32 prev_cpu, struct task_struct *p) {} ++static void tick_stub(struct task_struct *p) {} +static void runnable_stub(struct task_struct *p, u64 enq_flags) {} +static void running_stub(struct task_struct *p) {} +static void stopping_stub(struct task_struct *p, bool runnable) {} @@ -6587,16 +7453,28 @@ index 000000000000..0dac88d0e578 +static void exit_task_stub(struct task_struct *p, struct scx_exit_task_args *args) {} +static void enable_stub(struct task_struct *p) {} +static void disable_stub(struct task_struct *p) {} ++#ifdef CONFIG_EXT_GROUP_SCHED ++static s32 cgroup_init_stub(struct cgroup *cgrp, struct scx_cgroup_init_args *args) { return -EINVAL; } ++static void cgroup_exit_stub(struct cgroup *cgrp) {} ++static s32 cgroup_prep_move_stub(struct task_struct *p, struct cgroup *from, struct cgroup *to) { return -EINVAL; } ++static void cgroup_move_stub(struct task_struct *p, struct cgroup *from, struct cgroup *to) {} ++static void cgroup_cancel_move_stub(struct task_struct *p, struct cgroup *from, struct cgroup *to) {} ++static void cgroup_set_weight_stub(struct cgroup *cgrp, u32 weight) {} ++#endif +static void cpu_online_stub(s32 cpu) {} +static void cpu_offline_stub(s32 cpu) {} +static s32 init_stub(void) { return -EINVAL; } +static void exit_stub(struct scx_exit_info *info) {} ++static void dump_stub(struct scx_dump_ctx *ctx) {} ++static void dump_cpu_stub(struct scx_dump_ctx *ctx, s32 cpu, bool idle) {} ++static void dump_task_stub(struct scx_dump_ctx *ctx, struct task_struct *p) {} + +static struct sched_ext_ops __bpf_ops_sched_ext_ops = { + .select_cpu = select_cpu_stub, + .enqueue = enqueue_stub, + .dequeue = dequeue_stub, + .dispatch = dispatch_stub, ++ .tick = tick_stub, + .runnable = runnable_stub, + .running = running_stub, + .stopping = stopping_stub, @@ -6612,10 +7490,21 @@ index 000000000000..0dac88d0e578 + .exit_task = exit_task_stub, + .enable = enable_stub, + .disable = disable_stub, ++#ifdef CONFIG_EXT_GROUP_SCHED ++ .cgroup_init = cgroup_init_stub, ++ .cgroup_exit = cgroup_exit_stub, ++ .cgroup_prep_move = cgroup_prep_move_stub, ++ .cgroup_move = cgroup_move_stub, ++ .cgroup_cancel_move = cgroup_cancel_move_stub, ++ .cgroup_set_weight = cgroup_set_weight_stub, ++#endif + .cpu_online = cpu_online_stub, + .cpu_offline = cpu_offline_stub, + .init = init_stub, + .exit = exit_stub, ++ .dump = dump_stub, ++ .dump_cpu = dump_cpu_stub, ++ .dump_task = dump_task_stub, +}; + +static struct bpf_struct_ops bpf_sched_ext_ops = { @@ -6858,10 +7747,10 @@ index 000000000000..0dac88d0e578 + * definitions so that BPF scheduler implementations can use them + * through the generated vmlinux.h. + */ -+ WRITE_ONCE(v, SCX_ENQ_WAKEUP | SCX_DEQ_SLEEP | SCX_KICK_PREEMPT); ++ WRITE_ONCE(v, SCX_ENQ_WAKEUP | SCX_DEQ_SLEEP | SCX_KICK_PREEMPT | ++ SCX_TG_ONLINE); + + BUG_ON(rhashtable_init(&dsq_hash, &dsq_hash_params)); -+ init_dsq(&scx_dsq_global, SCX_DSQ_GLOBAL); +#ifdef CONFIG_SMP + BUG_ON(!alloc_cpumask_var(&idle_masks.cpu, GFP_KERNEL)); + BUG_ON(!alloc_cpumask_var(&idle_masks.smt, GFP_KERNEL)); @@ -6903,35 +7792,6 @@ index 000000000000..0dac88d0e578 +__bpf_kfunc_start_defs(); + +/** -+ * scx_bpf_create_dsq - Create a custom DSQ -+ * @dsq_id: DSQ to create -+ * @node: NUMA node to allocate from -+ * -+ * Create a custom DSQ identified by @dsq_id. Can be called from any sleepable -+ * scx callback, and any BPF_PROG_TYPE_SYSCALL prog. -+ */ -+__bpf_kfunc s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) -+{ -+ if (unlikely(node >= (int)nr_node_ids || -+ (node < 0 && node != NUMA_NO_NODE))) -+ return -EINVAL; -+ return PTR_ERR_OR_ZERO(create_dsq(dsq_id, node)); -+} -+ -+__bpf_kfunc_end_defs(); -+ -+BTF_KFUNCS_START(scx_kfunc_ids_sleepable) -+BTF_ID_FLAGS(func, scx_bpf_create_dsq, KF_SLEEPABLE) -+BTF_KFUNCS_END(scx_kfunc_ids_sleepable) -+ -+static const struct btf_kfunc_id_set scx_kfunc_set_sleepable = { -+ .owner = THIS_MODULE, -+ .set = &scx_kfunc_ids_sleepable, -+}; -+ -+__bpf_kfunc_start_defs(); -+ -+/** + * scx_bpf_select_cpu_dfl - The default implementation of ops.select_cpu() + * @p: task_struct to select a CPU for + * @prev_cpu: CPU @p was on previously @@ -7021,7 +7881,7 @@ index 000000000000..0dac88d0e578 + * scx_bpf_dispatch - Dispatch a task into the FIFO queue of a DSQ + * @p: task_struct to dispatch + * @dsq_id: DSQ to dispatch to -+ * @slice: duration @p can run for in nsecs ++ * @slice: duration @p can run for in nsecs, 0 to keep the current value + * @enq_flags: SCX_ENQ_* + * + * Dispatch @p into the FIFO queue of the DSQ identified by @dsq_id. It is safe @@ -7071,7 +7931,7 @@ index 000000000000..0dac88d0e578 + * scx_bpf_dispatch_vtime - Dispatch a task into the vtime priority queue of a DSQ + * @p: task_struct to dispatch + * @dsq_id: DSQ to dispatch to -+ * @slice: duration @p can run for in nsecs ++ * @slice: duration @p can run for in nsecs, 0 to keep the current value + * @vtime: @p's ordering inside the vtime-sorted queue of the target DSQ + * @enq_flags: SCX_ENQ_* + * @@ -7112,6 +7972,118 @@ index 000000000000..0dac88d0e578 + .set = &scx_kfunc_ids_enqueue_dispatch, +}; + ++static bool scx_dispatch_from_dsq(struct bpf_iter_scx_dsq_kern *kit, ++ struct task_struct *p, u64 dsq_id, ++ u64 enq_flags) ++{ ++ struct scx_dispatch_q *src_dsq = kit->dsq, *dst_dsq; ++ struct rq *this_rq, *src_rq, *dst_rq, *locked_rq; ++ bool dispatched = false; ++ bool in_balance; ++ unsigned long flags; ++ ++ if (!scx_kf_allowed_if_unlocked() && !scx_kf_allowed(SCX_KF_DISPATCH)) ++ return false; ++ ++ /* ++ * Can be called from either ops.dispatch() locking this_rq() or any ++ * context where no rq lock is held. If latter, lock @p's task_rq which ++ * we'll likely need anyway. ++ */ ++ src_rq = task_rq(p); ++ ++ local_irq_save(flags); ++ this_rq = this_rq(); ++ in_balance = this_rq->scx.flags & SCX_RQ_IN_BALANCE; ++ ++ if (in_balance) { ++ if (this_rq != src_rq) { ++ raw_spin_rq_unlock(this_rq); ++ raw_spin_rq_lock(src_rq); ++ } ++ } else { ++ raw_spin_rq_lock(src_rq); ++ } ++ ++ locked_rq = src_rq; ++ raw_spin_lock(&src_dsq->lock); ++ ++ /* ++ * Did someone else get to it? @p could have already left $src_dsq, got ++ * re-enqueud, or be in the process of being consumed by someone else. ++ */ ++ if (unlikely(p->scx.dsq != src_dsq || ++ u32_before(kit->cursor.priv, p->scx.dsq_seq) || ++ p->scx.holding_cpu >= 0) || ++ WARN_ON_ONCE(src_rq != task_rq(p))) { ++ raw_spin_unlock(&src_dsq->lock); ++ goto out; ++ } ++ ++ /* @p is still on $src_dsq and stable, determine the destination */ ++ dst_dsq = find_dsq_for_dispatch(this_rq, dsq_id, p); ++ ++ if (dst_dsq->id == SCX_DSQ_LOCAL) { ++ dst_rq = container_of(dst_dsq, struct rq, scx.local_dsq); ++ if (!task_can_run_on_remote_rq(p, dst_rq, true)) { ++ dst_dsq = find_global_dsq(p); ++ dst_rq = src_rq; ++ } ++ } else { ++ /* no need to migrate if destination is a non-local DSQ */ ++ dst_rq = src_rq; ++ } ++ ++ /* ++ * Move @p into $dst_dsq. If $dst_dsq is the local DSQ of a different ++ * CPU, @p will be migrated. ++ */ ++ if (dst_dsq->id == SCX_DSQ_LOCAL) { ++ /* @p is going from a non-local DSQ to a local DSQ */ ++ if (src_rq == dst_rq) { ++ task_unlink_from_dsq(p, src_dsq); ++ move_local_task_to_local_dsq(p, enq_flags, ++ src_dsq, dst_rq); ++ raw_spin_unlock(&src_dsq->lock); ++ } else { ++ raw_spin_unlock(&src_dsq->lock); ++ move_remote_task_to_local_dsq(p, enq_flags, ++ src_rq, dst_rq); ++ locked_rq = dst_rq; ++ } ++ } else { ++ /* ++ * @p is going from a non-local DSQ to a non-local DSQ. As ++ * $src_dsq is already locked, do an abbreviated dequeue. ++ */ ++ task_unlink_from_dsq(p, src_dsq); ++ p->scx.dsq = NULL; ++ raw_spin_unlock(&src_dsq->lock); ++ ++ if (kit->cursor.flags & __SCX_DSQ_ITER_HAS_VTIME) ++ p->scx.dsq_vtime = kit->vtime; ++ dispatch_enqueue(dst_dsq, p, enq_flags); ++ } ++ ++ if (kit->cursor.flags & __SCX_DSQ_ITER_HAS_SLICE) ++ p->scx.slice = kit->slice; ++ ++ dispatched = true; ++out: ++ if (in_balance) { ++ if (this_rq != locked_rq) { ++ raw_spin_rq_unlock(locked_rq); ++ raw_spin_rq_lock(this_rq); ++ } ++ } else { ++ raw_spin_rq_unlock_irqrestore(locked_rq, flags); ++ } ++ ++ kit->cursor.flags &= ~(__SCX_DSQ_ITER_HAS_SLICE | ++ __SCX_DSQ_ITER_HAS_VTIME); ++ return dispatched; ++} ++ +__bpf_kfunc_start_defs(); + +/** @@ -7171,7 +8143,7 @@ index 000000000000..0dac88d0e578 + + flush_dispatch_buf(dspc->rq); + -+ dsq = find_non_local_dsq(dsq_id); ++ dsq = find_user_dsq(dsq_id); + if (unlikely(!dsq)) { + scx_ops_error("invalid DSQ ID 0x%016llx", dsq_id); + return false; @@ -7191,12 +8163,112 @@ index 000000000000..0dac88d0e578 + } +} + ++/** ++ * scx_bpf_dispatch_from_dsq_set_slice - Override slice when dispatching from DSQ ++ * @it__iter: DSQ iterator in progress ++ * @slice: duration the dispatched task can run for in nsecs ++ * ++ * Override the slice of the next task that will be dispatched from @it__iter ++ * using scx_bpf_dispatch_from_dsq[_vtime](). If this function is not called, ++ * the previous slice duration is kept. ++ */ ++__bpf_kfunc void scx_bpf_dispatch_from_dsq_set_slice( ++ struct bpf_iter_scx_dsq *it__iter, u64 slice) ++{ ++ struct bpf_iter_scx_dsq_kern *kit = (void *)it__iter; ++ ++ kit->slice = slice; ++ kit->cursor.flags |= __SCX_DSQ_ITER_HAS_SLICE; ++} ++ ++/** ++ * scx_bpf_dispatch_from_dsq_set_vtime - Override vtime when dispatching from DSQ ++ * @it__iter: DSQ iterator in progress ++ * @vtime: task's ordering inside the vtime-sorted queue of the target DSQ ++ * ++ * Override the vtime of the next task that will be dispatched from @it__iter ++ * using scx_bpf_dispatch_from_dsq_vtime(). If this function is not called, the ++ * previous slice vtime is kept. If scx_bpf_dispatch_from_dsq() is used to ++ * dispatch the next task, the override is ignored and cleared. ++ */ ++__bpf_kfunc void scx_bpf_dispatch_from_dsq_set_vtime( ++ struct bpf_iter_scx_dsq *it__iter, u64 vtime) ++{ ++ struct bpf_iter_scx_dsq_kern *kit = (void *)it__iter; ++ ++ kit->vtime = vtime; ++ kit->cursor.flags |= __SCX_DSQ_ITER_HAS_VTIME; ++} ++ ++/** ++ * scx_bpf_dispatch_from_dsq - Move a task from DSQ iteration to a DSQ ++ * @it__iter: DSQ iterator in progress ++ * @p: task to transfer ++ * @dsq_id: DSQ to move @p to ++ * @enq_flags: SCX_ENQ_* ++ * ++ * Transfer @p which is on the DSQ currently iterated by @it__iter to the DSQ ++ * specified by @dsq_id. All DSQs - local DSQs, global DSQ and user DSQs - can ++ * be the destination. ++ * ++ * For the transfer to be successful, @p must still be on the DSQ and have been ++ * queued before the DSQ iteration started. This function doesn't care whether ++ * @p was obtained from the DSQ iteration. @p just has to be on the DSQ and have ++ * been queued before the iteration started. ++ * ++ * @p's slice is kept by default. Use scx_bpf_dispatch_from_dsq_set_slice() to ++ * update. ++ * ++ * Can be called from ops.dispatch() or any BPF context which doesn't hold a rq ++ * lock (e.g. BPF timers or SYSCALL programs). ++ * ++ * Returns %true if @p has been consumed, %false if @p had already been consumed ++ * or dequeued. ++ */ ++__bpf_kfunc bool scx_bpf_dispatch_from_dsq(struct bpf_iter_scx_dsq *it__iter, ++ struct task_struct *p, u64 dsq_id, ++ u64 enq_flags) ++{ ++ return scx_dispatch_from_dsq((struct bpf_iter_scx_dsq_kern *)it__iter, ++ p, dsq_id, enq_flags); ++} ++ ++/** ++ * scx_bpf_dispatch_vtime_from_dsq - Move a task from DSQ iteration to a PRIQ DSQ ++ * @it__iter: DSQ iterator in progress ++ * @p: task to transfer ++ * @dsq_id: DSQ to move @p to ++ * @enq_flags: SCX_ENQ_* ++ * ++ * Transfer @p which is on the DSQ currently iterated by @it__iter to the ++ * priority queue of the DSQ specified by @dsq_id. The destination must be a ++ * user DSQ as only user DSQs support priority queue. ++ * ++ * @p's slice and vtime are kept by default. Use ++ * scx_bpf_dispatch_from_dsq_set_slice() and ++ * scx_bpf_dispatch_from_dsq_set_vtime() to update. ++ * ++ * All other aspects are identical to scx_bpf_dispatch_from_dsq(). See ++ * scx_bpf_dispatch_vtime() for more information on @vtime. ++ */ ++__bpf_kfunc bool scx_bpf_dispatch_vtime_from_dsq(struct bpf_iter_scx_dsq *it__iter, ++ struct task_struct *p, u64 dsq_id, ++ u64 enq_flags) ++{ ++ return scx_dispatch_from_dsq((struct bpf_iter_scx_dsq_kern *)it__iter, ++ p, dsq_id, enq_flags | SCX_ENQ_DSQ_PRIQ); ++} ++ +__bpf_kfunc_end_defs(); + +BTF_KFUNCS_START(scx_kfunc_ids_dispatch) +BTF_ID_FLAGS(func, scx_bpf_dispatch_nr_slots) +BTF_ID_FLAGS(func, scx_bpf_dispatch_cancel) +BTF_ID_FLAGS(func, scx_bpf_consume) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_from_dsq_set_slice) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_from_dsq_set_vtime) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_from_dsq, KF_RCU) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_vtime_from_dsq, KF_RCU) +BTF_KFUNCS_END(scx_kfunc_ids_dispatch) + +static const struct btf_kfunc_id_set scx_kfunc_set_dispatch = { @@ -7274,6 +8346,37 @@ index 000000000000..0dac88d0e578 +__bpf_kfunc_start_defs(); + +/** ++ * scx_bpf_create_dsq - Create a custom DSQ ++ * @dsq_id: DSQ to create ++ * @node: NUMA node to allocate from ++ * ++ * Create a custom DSQ identified by @dsq_id. Can be called from any sleepable ++ * scx callback, and any BPF_PROG_TYPE_SYSCALL prog. ++ */ ++__bpf_kfunc s32 scx_bpf_create_dsq(u64 dsq_id, s32 node) ++{ ++ if (unlikely(node >= (int)nr_node_ids || ++ (node < 0 && node != NUMA_NO_NODE))) ++ return -EINVAL; ++ return PTR_ERR_OR_ZERO(create_dsq(dsq_id, node)); ++} ++ ++__bpf_kfunc_end_defs(); ++ ++BTF_KFUNCS_START(scx_kfunc_ids_unlocked) ++BTF_ID_FLAGS(func, scx_bpf_create_dsq, KF_SLEEPABLE) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_from_dsq, KF_RCU) ++BTF_ID_FLAGS(func, scx_bpf_dispatch_vtime_from_dsq, KF_RCU) ++BTF_KFUNCS_END(scx_kfunc_ids_unlocked) ++ ++static const struct btf_kfunc_id_set scx_kfunc_set_unlocked = { ++ .owner = THIS_MODULE, ++ .set = &scx_kfunc_ids_unlocked, ++}; ++ ++__bpf_kfunc_start_defs(); ++ ++/** + * scx_bpf_kick_cpu - Trigger reschedule on a CPU + * @cpu: cpu to kick + * @flags: %SCX_KICK_* flags @@ -7291,17 +8394,17 @@ index 000000000000..0dac88d0e578 + if (!ops_cpu_valid(cpu, NULL)) + return; + ++ local_irq_save(irq_flags); ++ ++ this_rq = this_rq(); ++ + /* + * While bypassing for PM ops, IRQ handling may not be online which can + * lead to irq_work_queue() malfunction such as infinite busy wait for + * IRQ status update. Suppress kicking. + */ -+ if (scx_ops_bypassing()) -+ return; -+ -+ local_irq_save(irq_flags); -+ -+ this_rq = this_rq(); ++ if (scx_rq_bypassing(this_rq)) ++ goto out; + + /* + * Actual kicking is bounced to kick_cpus_irq_workfn() to avoid nesting @@ -7361,7 +8464,7 @@ index 000000000000..0dac88d0e578 + goto out; + } + } else { -+ dsq = find_non_local_dsq(dsq_id); ++ dsq = find_user_dsq(dsq_id); + if (dsq) { + ret = READ_ONCE(dsq->nr); + goto out; @@ -7407,17 +8510,16 @@ index 000000000000..0dac88d0e578 + BUILD_BUG_ON(__alignof__(struct bpf_iter_scx_dsq_kern) != + __alignof__(struct bpf_iter_scx_dsq)); + -+ if (flags & ~__SCX_DSQ_ITER_ALL_FLAGS) ++ if (flags & ~__SCX_DSQ_ITER_USER_FLAGS) + return -EINVAL; + -+ kit->dsq = find_non_local_dsq(dsq_id); ++ kit->dsq = find_user_dsq(dsq_id); + if (!kit->dsq) + return -ENOENT; + + INIT_LIST_HEAD(&kit->cursor.node); -+ kit->cursor.is_bpf_iter_cursor = true; -+ kit->dsq_seq = READ_ONCE(kit->dsq->seq); -+ kit->flags = flags; ++ kit->cursor.flags |= SCX_DSQ_LNODE_ITER_CURSOR | flags; ++ kit->cursor.priv = READ_ONCE(kit->dsq->seq); + + return 0; +} @@ -7431,7 +8533,7 @@ index 000000000000..0dac88d0e578 +__bpf_kfunc struct task_struct *bpf_iter_scx_dsq_next(struct bpf_iter_scx_dsq *it) +{ + struct bpf_iter_scx_dsq_kern *kit = (void *)it; -+ bool rev = kit->flags & SCX_DSQ_ITER_REV; ++ bool rev = kit->cursor.flags & SCX_DSQ_ITER_REV; + struct task_struct *p; + unsigned long flags; + @@ -7452,7 +8554,7 @@ index 000000000000..0dac88d0e578 + */ + do { + p = nldsq_next_task(kit->dsq, p, rev); -+ } while (p && unlikely(u32_before(kit->dsq_seq, p->scx.dsq_seq))); ++ } while (p && unlikely(u32_before(kit->cursor.priv, p->scx.dsq_seq))); + + if (p) { + if (rev) @@ -7918,6 +9020,41 @@ index 000000000000..0dac88d0e578 + return cpu_rq(cpu); +} + ++/** ++ * scx_bpf_task_cgroup - Return the sched cgroup of a task ++ * @p: task of interest ++ * ++ * @p->sched_task_group->css.cgroup represents the cgroup @p is associated with ++ * from the scheduler's POV. SCX operations should use this function to ++ * determine @p's current cgroup as, unlike following @p->cgroups, ++ * @p->sched_task_group is protected by @p's rq lock and thus atomic w.r.t. all ++ * rq-locked operations. Can be called on the parameter tasks of rq-locked ++ * operations. The restriction guarantees that @p's rq is locked by the caller. ++ */ ++#ifdef CONFIG_CGROUP_SCHED ++__bpf_kfunc struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) ++{ ++ struct task_group *tg = p->sched_task_group; ++ struct cgroup *cgrp = &cgrp_dfl_root.cgrp; ++ ++ if (!scx_kf_allowed_on_arg_tasks(__SCX_KF_RQ_LOCKED, p)) ++ goto out; ++ ++ /* ++ * A task_group may either be a cgroup or an autogroup. In the latter ++ * case, @tg->css.cgroup is %NULL. A task_group can't become the other ++ * kind once created. ++ */ ++ if (tg && tg->css.cgroup) ++ cgrp = tg->css.cgroup; ++ else ++ cgrp = &cgrp_dfl_root.cgrp; ++out: ++ cgroup_get(cgrp); ++ return cgrp; ++} ++#endif ++ +__bpf_kfunc_end_defs(); + +BTF_KFUNCS_START(scx_kfunc_ids_any) @@ -7946,6 +9083,9 @@ index 000000000000..0dac88d0e578 +BTF_ID_FLAGS(func, scx_bpf_task_running, KF_RCU) +BTF_ID_FLAGS(func, scx_bpf_task_cpu, KF_RCU) +BTF_ID_FLAGS(func, scx_bpf_cpu_rq) ++#ifdef CONFIG_CGROUP_SCHED ++BTF_ID_FLAGS(func, scx_bpf_task_cgroup, KF_RCU | KF_ACQUIRE) ++#endif +BTF_KFUNCS_END(scx_kfunc_ids_any) + +static const struct btf_kfunc_id_set scx_kfunc_set_any = { @@ -7969,10 +9109,6 @@ index 000000000000..0dac88d0e578 + * check using scx_kf_allowed(). + */ + if ((ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, -+ &scx_kfunc_set_sleepable)) || -+ (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_SYSCALL, -+ &scx_kfunc_set_sleepable)) || -+ (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, + &scx_kfunc_set_select_cpu)) || + (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, + &scx_kfunc_set_enqueue_dispatch)) || @@ -7981,6 +9117,10 @@ index 000000000000..0dac88d0e578 + (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, + &scx_kfunc_set_cpu_release)) || + (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, ++ &scx_kfunc_set_unlocked)) || ++ (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_SYSCALL, ++ &scx_kfunc_set_unlocked)) || ++ (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_STRUCT_OPS, + &scx_kfunc_set_any)) || + (ret = register_btf_kfunc_id_set(BPF_PROG_TYPE_TRACING, + &scx_kfunc_set_any)) || @@ -8019,10 +9159,10 @@ index 000000000000..0dac88d0e578 +__initcall(scx_init); diff --git a/kernel/sched/ext.h b/kernel/sched/ext.h new file mode 100644 -index 000000000000..32d3a51f591a +index 000000000000..246019519231 --- /dev/null +++ b/kernel/sched/ext.h -@@ -0,0 +1,69 @@ +@@ -0,0 +1,91 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * BPF extensible scheduler class: Documentation/scheduler/sched-ext.rst @@ -8092,11 +9232,33 @@ index 000000000000..32d3a51f591a +#else +static inline void scx_update_idle(struct rq *rq, bool idle) {} +#endif ++ ++#ifdef CONFIG_CGROUP_SCHED ++#ifdef CONFIG_EXT_GROUP_SCHED ++int scx_tg_online(struct task_group *tg); ++void scx_tg_offline(struct task_group *tg); ++int scx_cgroup_can_attach(struct cgroup_taskset *tset); ++void scx_move_task(struct task_struct *p); ++void scx_cgroup_finish_attach(void); ++void scx_cgroup_cancel_attach(struct cgroup_taskset *tset); ++void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight); ++void scx_group_set_idle(struct task_group *tg, bool idle); ++#else /* CONFIG_EXT_GROUP_SCHED */ ++static inline int scx_tg_online(struct task_group *tg) { return 0; } ++static inline void scx_tg_offline(struct task_group *tg) {} ++static inline int scx_cgroup_can_attach(struct cgroup_taskset *tset) { return 0; } ++static inline void scx_move_task(struct task_struct *p) {} ++static inline void scx_cgroup_finish_attach(void) {} ++static inline void scx_cgroup_cancel_attach(struct cgroup_taskset *tset) {} ++static inline void scx_group_set_weight(struct task_group *tg, unsigned long cgrp_weight) {} ++static inline void scx_group_set_idle(struct task_group *tg, bool idle) {} ++#endif /* CONFIG_EXT_GROUP_SCHED */ ++#endif /* CONFIG_CGROUP_SCHED */ diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c -index 483c137b9d3d..ab17954001ae 100644 +index 91b242e47db7..a36e37a674e8 100644 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c -@@ -3835,7 +3835,8 @@ static void reweight_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, +@@ -3857,7 +3857,8 @@ static void reweight_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, } } @@ -8106,16 +9268,7 @@ index 483c137b9d3d..ab17954001ae 100644 { struct sched_entity *se = &p->se; struct cfs_rq *cfs_rq = cfs_rq_of(se); -@@ -8697,7 +8697,7 @@ - /* - * BATCH and IDLE tasks do not preempt others. - */ -- if (unlikely(p->policy != SCHED_NORMAL)) -+ if (unlikely(!normal_policy(p->policy))) - return; - - cfs_rq = cfs_rq_of(se); -@@ -9647,29 +9647,18 @@ +@@ -9365,29 +9366,18 @@ static inline void update_blocked_load_status(struct rq *rq, bool has_blocked) { static bool __update_blocked_others(struct rq *rq, bool *done) { @@ -8148,7 +9301,7 @@ index 483c137b9d3d..ab17954001ae 100644 } #ifdef CONFIG_FAIR_GROUP_SCHED -@@ -13207,6 +13198,7 @@ DEFINE_SCHED_CLASS(fair) = { +@@ -13233,6 +13223,7 @@ DEFINE_SCHED_CLASS(fair) = { .task_tick = task_tick_fair, .task_fork = task_fork_fair, @@ -8157,10 +9310,10 @@ index 483c137b9d3d..ab17954001ae 100644 .switched_from = switched_from_fair, .switched_to = switched_to_fair, diff --git a/kernel/sched/idle.c b/kernel/sched/idle.c -index 6135fbe83d68..3b6540cc436a 100644 +index 6e78d071beb5..c7a218123b7a 100644 --- a/kernel/sched/idle.c +++ b/kernel/sched/idle.c -@@ -458,11 +458,13 @@ static void wakeup_preempt_idle(struct rq *rq, struct task_struct *p, int flags) +@@ -452,11 +452,13 @@ static void wakeup_preempt_idle(struct rq *rq, struct task_struct *p, int flags) static void put_prev_task_idle(struct rq *rq, struct task_struct *prev) { @@ -8175,14 +9328,13 @@ index 6135fbe83d68..3b6540cc436a 100644 } diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h -index 38aeedd8a6cc..f952a4b99ead 100644 +index 432b43aa091c..48d893de632b 100644 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h -@@ -187,9 +187,19 @@ static inline int idle_policy(int policy) - { +@@ -192,9 +192,18 @@ static inline int idle_policy(int policy) return policy == SCHED_IDLE; } -+ + +static inline int normal_policy(int policy) +{ +#ifdef CONFIG_SCHED_CLASS_EXT @@ -8199,7 +9351,7 @@ index 38aeedd8a6cc..f952a4b99ead 100644 } static inline int rt_policy(int policy) -@@ -237,6 +247,24 @@ static inline void update_avg(u64 *avg, u64 sample) +@@ -244,6 +253,24 @@ static inline void update_avg(u64 *avg, u64 sample) #define shr_bound(val, shift) \ (val >> min_t(typeof(shift), shift, BITS_PER_TYPE(typeof(val)) - 1)) @@ -8224,7 +9376,50 @@ index 38aeedd8a6cc..f952a4b99ead 100644 /* * !! For sched_setattr_nocheck() (kernel) only !! * -@@ -475,6 +503,11 @@ static inline int walk_tg_tree(tg_visitor down, tg_visitor up, void *data) +@@ -397,16 +424,17 @@ struct cfs_bandwidth { + struct task_group { + struct cgroup_subsys_state css; + ++#ifdef CONFIG_GROUP_SCHED_WEIGHT ++ /* A positive value indicates that this is a SCHED_IDLE group. */ ++ int idle; ++#endif ++ + #ifdef CONFIG_FAIR_GROUP_SCHED + /* schedulable entities of this group on each CPU */ + struct sched_entity **se; + /* runqueue "owned" by this group on each CPU */ + struct cfs_rq **cfs_rq; + unsigned long shares; +- +- /* A positive value indicates that this is a SCHED_IDLE group. */ +- int idle; +- + #ifdef CONFIG_SMP + /* + * load_avg can be heavily contended at clock tick time, so put +@@ -424,6 +452,11 @@ struct task_group { + struct rt_bandwidth rt_bandwidth; + #endif + ++#ifdef CONFIG_EXT_GROUP_SCHED ++ u32 scx_flags; /* SCX_TG_* */ ++ u32 scx_weight; ++#endif ++ + struct rcu_head rcu; + struct list_head list; + +@@ -448,7 +481,7 @@ struct task_group { + + }; + +-#ifdef CONFIG_FAIR_GROUP_SCHED ++#ifdef CONFIG_GROUP_SCHED_WEIGHT + #define ROOT_TASK_GROUP_LOAD NICE_0_LOAD + + /* +@@ -479,6 +512,11 @@ static inline int walk_tg_tree(tg_visitor down, tg_visitor up, void *data) return walk_tg_tree_from(&root_task_group, down, up, data); } @@ -8236,11 +9431,20 @@ index 38aeedd8a6cc..f952a4b99ead 100644 extern int tg_nop(struct task_group *tg, void *data); #ifdef CONFIG_FAIR_GROUP_SCHED -@@ -583,6 +616,12 @@ do { \ - # define u64_u32_load(var) u64_u32_load_copy(var, var##_copy) - # define u64_u32_store(var, val) u64_u32_store_copy(var, var##_copy, val) +@@ -535,6 +573,9 @@ extern void set_task_rq_fair(struct sched_entity *se, + static inline void set_task_rq_fair(struct sched_entity *se, + struct cfs_rq *prev, struct cfs_rq *next) { } + #endif /* CONFIG_SMP */ ++#else /* !CONFIG_FAIR_GROUP_SCHED */ ++static inline int sched_group_set_shares(struct task_group *tg, unsigned long shares) { return 0; } ++static inline int sched_group_set_idle(struct task_group *tg, long idle) { return 0; } + #endif /* CONFIG_FAIR_GROUP_SCHED */ + + #else /* CONFIG_CGROUP_SCHED */ +@@ -588,6 +629,11 @@ do { \ + # define u64_u32_load(var) u64_u32_load_copy(var, var##_copy) + # define u64_u32_store(var, val) u64_u32_store_copy(var, var##_copy, val) -+struct rq; +struct balance_callback { + struct balance_callback *next; + void (*func)(struct rq *rq); @@ -8249,7 +9453,7 @@ index 38aeedd8a6cc..f952a4b99ead 100644 /* CFS-related fields in a runqueue */ struct cfs_rq { struct load_weight load; -@@ -691,6 +730,42 @@ struct cfs_rq { +@@ -696,6 +742,43 @@ struct cfs_rq { #endif /* CONFIG_FAIR_GROUP_SCHED */ }; @@ -8263,6 +9467,7 @@ index 38aeedd8a6cc..f952a4b99ead 100644 + */ + SCX_RQ_ONLINE = 1 << 0, + SCX_RQ_CAN_STOP_TICK = 1 << 1, ++ SCX_RQ_BYPASSING = 1 << 3, + + SCX_RQ_IN_WAKEUP = 1 << 16, + SCX_RQ_IN_BALANCE = 1 << 17, @@ -8292,11 +9497,10 @@ index 38aeedd8a6cc..f952a4b99ead 100644 static inline int rt_bandwidth_enabled(void) { return sysctl_sched_rt_runtime >= 0; -@@ -988,12 +1063,6 @@ struct uclamp_rq { +@@ -996,11 +1079,6 @@ struct uclamp_rq { DECLARE_STATIC_KEY_FALSE(sched_uclamp_used); #endif /* CONFIG_UCLAMP_TASK */ --struct rq; -struct balance_callback { - struct balance_callback *next; - void (*func)(struct rq *rq); @@ -8305,7 +9509,7 @@ index 38aeedd8a6cc..f952a4b99ead 100644 /* * This is the main, per-CPU runqueue data structure. * -@@ -1036,6 +1105,9 @@ struct rq { +@@ -1043,6 +1121,9 @@ struct rq { struct cfs_rq cfs; struct rt_rq rt; struct dl_rq dl; @@ -8315,16 +9519,24 @@ index 38aeedd8a6cc..f952a4b99ead 100644 #ifdef CONFIG_FAIR_GROUP_SCHED /* list of leaf cfs_rq on this CPU: */ -@@ -2278,6 +2350,8 @@ struct sched_class { +@@ -2291,13 +2372,15 @@ struct sched_class { + + void (*wakeup_preempt)(struct rq *rq, struct task_struct *p, int flags); + ++ int (*balance)(struct rq *rq, struct task_struct *prev, struct rq_flags *rf); + struct task_struct *(*pick_next_task)(struct rq *rq); + void (*put_prev_task)(struct rq *rq, struct task_struct *p); void (*set_next_task)(struct rq *rq, struct task_struct *p, bool first); + void (*switch_class)(struct rq *rq, struct task_struct *next); + #ifdef CONFIG_SMP - int (*balance)(struct rq *rq, struct task_struct *prev, struct rq_flags *rf); +- int (*balance)(struct rq *rq, struct task_struct *prev, struct rq_flags *rf); int (*select_task_rq)(struct task_struct *p, int task_cpu, int flags); -@@ -2305,8 +2379,11 @@ struct sched_class { + + struct task_struct * (*pick_task)(struct rq *rq); +@@ -2323,8 +2406,11 @@ struct sched_class { * cannot assume the switched_from/switched_to pair is serialized by * rq->lock. They are however serialized by p->pi_lock. */ @@ -8336,7 +9548,7 @@ index 38aeedd8a6cc..f952a4b99ead 100644 void (*prio_changed) (struct rq *this_rq, struct task_struct *task, int oldprio); -@@ -2355,19 +2432,54 @@ const struct sched_class name##_sched_class \ +@@ -2373,19 +2459,54 @@ const struct sched_class name##_sched_class \ extern struct sched_class __sched_class_highest[]; extern struct sched_class __sched_class_lowest[]; @@ -8397,50 +9609,77 @@ index 38aeedd8a6cc..f952a4b99ead 100644 static inline bool sched_stop_runnable(struct rq *rq) { -@@ -2464,7 +2576,7 @@ extern void init_sched_dl_class(void); +@@ -2424,6 +2545,19 @@ extern void sched_balance_trigger(struct rq *rq); + extern int __set_cpus_allowed_ptr(struct task_struct *p, struct affinity_context *ctx); + extern void set_cpus_allowed_common(struct task_struct *p, struct affinity_context *ctx); + ++static inline bool task_allowed_on_cpu(struct task_struct *p, int cpu) ++{ ++ /* When not in the task's cpumask, no point in looking further. */ ++ if (!cpumask_test_cpu(cpu, p->cpus_ptr)) ++ return false; ++ ++ /* Can @cpu run a user thread? */ ++ if (!(p->flags & PF_KTHREAD) && !task_cpu_possible(cpu, p)) ++ return false; ++ ++ return true; ++} ++ + static inline cpumask_t *alloc_user_cpus_ptr(int node) + { + /* +@@ -2457,6 +2591,11 @@ extern int push_cpu_stop(void *arg); + + #else /* !CONFIG_SMP: */ + ++static inline bool task_allowed_on_cpu(struct task_struct *p, int cpu) ++{ ++ return true; ++} ++ + static inline int __set_cpus_allowed_ptr(struct task_struct *p, + struct affinity_context *ctx) + { +@@ -2510,8 +2649,6 @@ extern void init_sched_dl_class(void); extern void init_sched_rt_class(void); extern void init_sched_fair_class(void); -extern void reweight_task(struct task_struct *p, const struct load_weight *lw); -+extern void __setscheduler_prio(struct task_struct *p, int prio); - +- extern void resched_curr(struct rq *rq); extern void resched_cpu(int cpu); -@@ -2542,6 +2654,12 @@ static inline void sub_nr_running(struct rq *rq, unsigned count) - extern void activate_task(struct rq *rq, struct task_struct *p, int flags); - extern void deactivate_task(struct rq *rq, struct task_struct *p, int flags); -+extern void check_class_changing(struct rq *rq, struct task_struct *p, -+ const struct sched_class *prev_class); -+extern void check_class_changed(struct rq *rq, struct task_struct *p, -+ const struct sched_class *prev_class, -+ int oldprio); -+ - extern void wakeup_preempt(struct rq *rq, struct task_struct *p, int flags); - - #ifdef CONFIG_PREEMPT_RT -@@ -3007,6 +3125,9 @@ static inline void cpufreq_update_util(struct rq *rq, unsigned int flags) {} - #endif +@@ -3056,6 +3193,8 @@ static inline void cpufreq_update_util(struct rq *rq, unsigned int flags) { } #ifdef CONFIG_SMP -+ + +bool update_other_load_avgs(struct rq *rq); + unsigned long effective_cpu_util(int cpu, unsigned long util_cfs, unsigned long *min, unsigned long *max); -@@ -3049,6 +3170,8 @@ static inline unsigned long cpu_util_rt(struct rq *rq) - { +@@ -3099,6 +3238,8 @@ static inline unsigned long cpu_util_rt(struct rq *rq) return READ_ONCE(rq->avg_rt.util_avg); } + +#else /* !CONFIG_SMP */ +static inline bool update_other_load_avgs(struct rq *rq) { return false; } - #endif + #endif /* CONFIG_SMP */ #ifdef CONFIG_UCLAMP_TASK -@@ -3481,4 +3604,24 @@ static inline void init_sched_mm_cid(struct task_struct *t) { } - extern u64 avg_vruntime(struct cfs_rq *cfs_rq); - extern int entity_eligible(struct cfs_rq *cfs_rq, struct sched_entity *se); +@@ -3609,6 +3750,8 @@ extern void set_load_weight(struct task_struct *p, bool update_load); + extern void enqueue_task(struct rq *rq, struct task_struct *p, int flags); + extern void dequeue_task(struct rq *rq, struct task_struct *p, int flags); + ++extern void check_class_changing(struct rq *rq, struct task_struct *p, ++ const struct sched_class *prev_class); + extern void check_class_changed(struct rq *rq, struct task_struct *p, + const struct sched_class *prev_class, + int oldprio); +@@ -3629,4 +3772,24 @@ static inline void balance_callbacks(struct rq *rq, struct balance_callback *hea + + #endif +#ifdef CONFIG_SCHED_CLASS_EXT +/* @@ -8463,11 +9702,76 @@ index 38aeedd8a6cc..f952a4b99ead 100644 +#include "ext.h" + #endif /* _KERNEL_SCHED_SCHED_H */ +diff --git a/kernel/sched/syscalls.c b/kernel/sched/syscalls.c +index ae1b42775ef9..4fa59c9f69ac 100644 +--- a/kernel/sched/syscalls.c ++++ b/kernel/sched/syscalls.c +@@ -259,6 +259,25 @@ int sched_core_idle_cpu(int cpu) + #endif + + #ifdef CONFIG_SMP ++/* ++ * Load avg and utiliztion metrics need to be updated periodically and before ++ * consumption. This function updates the metrics for all subsystems except for ++ * the fair class. @rq must be locked and have its clock updated. ++ */ ++bool update_other_load_avgs(struct rq *rq) ++{ ++ u64 now = rq_clock_pelt(rq); ++ const struct sched_class *curr_class = rq->curr->sched_class; ++ unsigned long hw_pressure = arch_scale_hw_pressure(cpu_of(rq)); ++ ++ lockdep_assert_rq_held(rq); ++ ++ return update_rt_rq_load_avg(now, rq, curr_class == &rt_sched_class) | ++ update_dl_rq_load_avg(now, rq, curr_class == &dl_sched_class) | ++ update_hw_load_avg(now, rq, hw_pressure) | ++ update_irq_load_avg(rq, 0); ++} ++ + /* + * This function computes an effective utilization for the given CPU, to be + * used for frequency selection given the linear relation: f = u * f_max. +@@ -695,6 +714,10 @@ int __sched_setscheduler(struct task_struct *p, + goto unlock; + } + ++ retval = scx_check_setscheduler(p, policy); ++ if (retval) ++ goto unlock; ++ + /* + * If not changing anything there's no need to proceed further, + * but store a possible modification of reset_on_fork. +@@ -797,6 +820,7 @@ int __sched_setscheduler(struct task_struct *p, + __setscheduler_prio(p, newprio); + } + __setscheduler_uclamp(p, attr); ++ check_class_changing(rq, p, prev_class); + + if (queued) { + /* +@@ -1602,6 +1626,7 @@ SYSCALL_DEFINE1(sched_get_priority_max, int, policy) + case SCHED_NORMAL: + case SCHED_BATCH: + case SCHED_IDLE: ++ case SCHED_EXT: + ret = 0; + break; + } +@@ -1629,6 +1654,7 @@ SYSCALL_DEFINE1(sched_get_priority_min, int, policy) + case SCHED_NORMAL: + case SCHED_BATCH: + case SCHED_IDLE: ++ case SCHED_EXT: + ret = 0; + } + return ret; diff --git a/lib/dump_stack.c b/lib/dump_stack.c -index 222c6d6c8281..9581ef4efec5 100644 +index 1a996fbbf50a..388da1aea14a 100644 --- a/lib/dump_stack.c +++ b/lib/dump_stack.c -@@ -68,6 +68,7 @@ void dump_stack_print_info(const char *log_lvl) +@@ -73,6 +73,7 @@ void dump_stack_print_info(const char *log_lvl) print_worker_info(log_lvl, current); print_stop_info(log_lvl, current); @@ -8479,7 +9783,7 @@ diff --git a/tools/Makefile b/tools/Makefile index 276f5d0d53a4..278d24723b74 100644 --- a/tools/Makefile +++ b/tools/Makefile -@@ -28,6 +28,7 @@ include scripts/Makefile.include +@@ -28,6 +28,7 @@ help: @echo ' pci - PCI tools' @echo ' perf - Linux performance measurement and analysis tool' @echo ' selftests - various kernel selftests' @@ -8497,7 +9801,7 @@ index 276f5d0d53a4..278d24723b74 100644 selftests: FORCE $(call descend,testing/$@) -@@ -184,6 +188,9 @@ install: acpi_install counter_install cpupower_install gpio_install \ +@@ -184,6 +188,9 @@ perf_clean: $(Q)mkdir -p $(PERF_O) . $(Q)$(MAKE) --no-print-directory -C perf O=$(PERF_O) subdir= clean @@ -8526,7 +9830,7 @@ index 000000000000..d6264fe1c8cd +build/ diff --git a/tools/sched_ext/Makefile b/tools/sched_ext/Makefile new file mode 100644 -index 000000000000..bf7e108f5ae1 +index 000000000000..ca3815e572d8 --- /dev/null +++ b/tools/sched_ext/Makefile @@ -0,0 +1,246 @@ @@ -8708,7 +10012,7 @@ index 000000000000..bf7e108f5ae1 + +SCX_COMMON_DEPS := include/scx/common.h include/scx/user_exit_info.h | $(BINDIR) + -+c-sched-targets = scx_simple scx_qmap scx_central ++c-sched-targets = scx_simple scx_qmap scx_central scx_flatcg + +$(addprefix $(BINDIR)/,$(c-sched-targets)): \ + $(BINDIR)/%: \ @@ -8778,10 +10082,10 @@ index 000000000000..bf7e108f5ae1 +.SECONDARY: diff --git a/tools/sched_ext/README.md b/tools/sched_ext/README.md new file mode 100644 -index 000000000000..8efe70cc4363 +index 000000000000..16a42e4060f6 --- /dev/null +++ b/tools/sched_ext/README.md -@@ -0,0 +1,258 @@ +@@ -0,0 +1,270 @@ +SCHED_EXT EXAMPLE SCHEDULERS +============================ + @@ -8976,6 +10280,18 @@ index 000000000000..8efe70cc4363 +infinite slices and no timer ticks allows the VM to avoid unnecessary expensive +vmexits. + ++## scx_flatcg ++ ++A flattened cgroup hierarchy scheduler. This scheduler implements hierarchical ++weight-based cgroup CPU control by flattening the cgroup hierarchy into a single ++layer, by compounding the active weight share at each level. The effect of this ++is a much more performant CPU controller, which does not need to descend down ++cgroup trees in order to properly compute a cgroup's share. ++ ++Similar to scx_simple, in limited scenarios, this scheduler can perform ++reasonably well on single socket-socket systems with a unified L3 cache and show ++significantly lowered hierarchical scheduling overhead. ++ + +# Troubleshooting + @@ -9059,10 +10375,10 @@ index 000000000000..ad7d139ce907 + */ diff --git a/tools/sched_ext/include/scx/common.bpf.h b/tools/sched_ext/include/scx/common.bpf.h new file mode 100644 -index 000000000000..20280df62857 +index 000000000000..225f61f9bfca --- /dev/null +++ b/tools/sched_ext/include/scx/common.bpf.h -@@ -0,0 +1,401 @@ +@@ -0,0 +1,427 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Meta Platforms, Inc. and affiliates. @@ -9072,7 +10388,13 @@ index 000000000000..20280df62857 +#ifndef __SCX_COMMON_BPF_H +#define __SCX_COMMON_BPF_H + ++#ifdef LSP ++#define __bpf__ ++#include "../vmlinux/vmlinux.h" ++#else +#include "vmlinux.h" ++#endif ++ +#include <bpf/bpf_helpers.h> +#include <bpf/bpf_tracing.h> +#include <asm-generic/errno.h> @@ -9100,6 +10422,10 @@ index 000000000000..20280df62857 +u32 scx_bpf_dispatch_nr_slots(void) __ksym; +void scx_bpf_dispatch_cancel(void) __ksym; +bool scx_bpf_consume(u64 dsq_id) __ksym; ++void scx_bpf_dispatch_from_dsq_set_slice(struct bpf_iter_scx_dsq *it__iter, u64 slice) __ksym; ++void scx_bpf_dispatch_from_dsq_set_vtime(struct bpf_iter_scx_dsq *it__iter, u64 vtime) __ksym; ++bool scx_bpf_dispatch_from_dsq(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak; ++bool scx_bpf_dispatch_vtime_from_dsq(struct bpf_iter_scx_dsq *it__iter, struct task_struct *p, u64 dsq_id, u64 enq_flags) __ksym __weak; +u32 scx_bpf_reenqueue_local(void) __ksym; +void scx_bpf_kick_cpu(s32 cpu, u64 flags) __ksym; +s32 scx_bpf_dsq_nr_queued(u64 dsq_id) __ksym; @@ -9126,6 +10452,13 @@ index 000000000000..20280df62857 +bool scx_bpf_task_running(const struct task_struct *p) __ksym; +s32 scx_bpf_task_cpu(const struct task_struct *p) __ksym; +struct rq *scx_bpf_cpu_rq(s32 cpu) __ksym; ++struct cgroup *scx_bpf_task_cgroup(struct task_struct *p) __ksym; ++ ++/* ++ * Use the following as @it__iter when calling ++ * scx_bpf_dispatch[_vtime]_from_dsq() from within bpf_for_each() loops. ++ */ ++#define BPF_FOR_EACH_ITER (&___it) + +static inline __attribute__((format(printf, 1, 2))) +void ___scx_bpf_bstr_format_checker(const char *fmt, ...) {} @@ -9363,6 +10696,15 @@ index 000000000000..20280df62857 +u32 bpf_cpumask_any_distribute(const struct cpumask *cpumask) __ksym; +u32 bpf_cpumask_any_and_distribute(const struct cpumask *src1, + const struct cpumask *src2) __ksym; ++u32 bpf_cpumask_weight(const struct cpumask *cpumask) __ksym; ++ ++/* ++ * Access a cpumask in read-only mode (typically to check bits). ++ */ ++const struct cpumask *cast_mask(struct bpf_cpumask *mask) ++{ ++ return (const struct cpumask *)mask; ++} + +/* rcu */ +void bpf_rcu_read_lock(void) __ksym; @@ -9547,10 +10889,10 @@ index 000000000000..5b0f90152152 +#endif /* __SCHED_EXT_COMMON_H */ diff --git a/tools/sched_ext/include/scx/compat.bpf.h b/tools/sched_ext/include/scx/compat.bpf.h new file mode 100644 -index 000000000000..3d2fe1208900 +index 000000000000..e5afe9efd3f3 --- /dev/null +++ b/tools/sched_ext/include/scx/compat.bpf.h -@@ -0,0 +1,28 @@ +@@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 Meta Platforms, Inc. and affiliates. @@ -9568,6 +10910,25 @@ index 000000000000..3d2fe1208900 + __ret; \ +}) + ++/* v6.12: 819513666966 ("sched_ext: Add cgroup support") */ ++#define __COMPAT_scx_bpf_task_cgroup(p) \ ++ (bpf_ksym_exists(scx_bpf_task_cgroup) ? \ ++ scx_bpf_task_cgroup((p)) : NULL) ++ ++/* v6.12: 4c30f5ce4f7a ("sched_ext: Implement scx_bpf_dispatch[_vtime]_from_dsq()") */ ++#define __COMPAT_scx_bpf_dispatch_from_dsq_set_slice(it, slice) \ ++ (bpf_ksym_exists(scx_bpf_dispatch_from_dsq_set_slice) ? \ ++ scx_bpf_dispatch_from_dsq_set_slice((it), (slice)) : (void)0) ++#define __COMPAT_scx_bpf_dispatch_from_dsq_set_vtime(it, vtime) \ ++ (bpf_ksym_exists(scx_bpf_dispatch_from_dsq_set_vtime) ? \ ++ scx_bpf_dispatch_from_dsq_set_vtime((it), (vtime)) : (void)0) ++#define __COMPAT_scx_bpf_dispatch_from_dsq(it, p, dsq_id, enq_flags) \ ++ (bpf_ksym_exists(scx_bpf_dispatch_from_dsq) ? \ ++ scx_bpf_dispatch_from_dsq((it), (p), (dsq_id), (enq_flags)) : false) ++#define __COMPAT_scx_bpf_dispatch_vtime_from_dsq(it, p, dsq_id, enq_flags) \ ++ (bpf_ksym_exists(scx_bpf_dispatch_vtime_from_dsq) ? \ ++ scx_bpf_dispatch_vtime_from_dsq((it), (p), (dsq_id), (enq_flags)) : false) ++ +/* + * Define sched_ext_ops. This may be expanded to define multiple variants for + * backward compatibility. See compat.h::SCX_OPS_LOAD/ATTACH(). @@ -9581,10 +10942,10 @@ index 000000000000..3d2fe1208900 +#endif /* __SCX_COMPAT_BPF_H */ diff --git a/tools/sched_ext/include/scx/compat.h b/tools/sched_ext/include/scx/compat.h new file mode 100644 -index 000000000000..1bf8eddf20c2 +index 000000000000..cc56ff9aa252 --- /dev/null +++ b/tools/sched_ext/include/scx/compat.h -@@ -0,0 +1,187 @@ +@@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2024 Meta Platforms, Inc. and affiliates. @@ -9753,14 +11114,13 @@ index 000000000000..1bf8eddf20c2 + * To maintain compatibility with older libbpf while avoiding trying to attach + * twice, disable the autoattach feature on newer libbpf. + */ -+/* BACKPORT - bpf_mpa__set_autoattach() not available yet, commented out */ -+/*#if LIBBPF_MAJOR_VERSION > 1 || \ ++#if LIBBPF_MAJOR_VERSION > 1 || \ + (LIBBPF_MAJOR_VERSION == 1 && LIBBPF_MINOR_VERSION >= 5) +#define __SCX_OPS_DISABLE_AUTOATTACH(__skel, __ops_name) \ + bpf_map__set_autoattach((__skel)->maps.__ops_name, false) -+#else*/ ++#else +#define __SCX_OPS_DISABLE_AUTOATTACH(__skel, __ops_name) do {} while (0) -+/*#endif*/ ++#endif + +#define SCX_OPS_ATTACH(__skel, __ops_name, __scx_name) ({ \ + struct bpf_link *__link; \ @@ -9774,10 +11134,10 @@ index 000000000000..1bf8eddf20c2 +#endif /* __SCX_COMPAT_H */ diff --git a/tools/sched_ext/include/scx/user_exit_info.h b/tools/sched_ext/include/scx/user_exit_info.h new file mode 100644 -index 000000000000..891693ee604e +index 000000000000..8ce2734402e1 --- /dev/null +++ b/tools/sched_ext/include/scx/user_exit_info.h -@@ -0,0 +1,111 @@ +@@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Define struct user_exit_info which is shared between BPF and userspace parts @@ -9805,7 +11165,11 @@ index 000000000000..891693ee604e + +#ifdef __bpf__ + ++#ifdef LSP ++#include "../vmlinux/vmlinux.h" ++#else +#include "vmlinux.h" ++#endif +#include <bpf/bpf_core_read.h> + +#define UEI_DEFINE(__name) \ @@ -9891,7 +11255,7 @@ index 000000000000..891693ee604e +#endif /* __USER_EXIT_INFO_H */ diff --git a/tools/sched_ext/scx_central.bpf.c b/tools/sched_ext/scx_central.bpf.c new file mode 100644 -index 000000000000..1d8fd570eaa7 +index 000000000000..8dd8eb73b6b8 --- /dev/null +++ b/tools/sched_ext/scx_central.bpf.c @@ -0,0 +1,361 @@ @@ -10095,7 +11459,7 @@ index 000000000000..1d8fd570eaa7 + + /* central's gimme is never set */ + gimme = ARRAY_ELEM_PTR(cpu_gimme_task, cpu, nr_cpu_ids); -+ if (gimme && !*gimme) ++ if (!gimme || !*gimme) + continue; + + if (dispatch_to_cpu(cpu)) @@ -10397,12 +11761,1271 @@ index 000000000000..21deea320bd7 + goto restart; + return 0; +} +diff --git a/tools/sched_ext/scx_flatcg.bpf.c b/tools/sched_ext/scx_flatcg.bpf.c +new file mode 100644 +index 000000000000..b722baf6da4b +--- /dev/null ++++ b/tools/sched_ext/scx_flatcg.bpf.c +@@ -0,0 +1,957 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * A demo sched_ext flattened cgroup hierarchy scheduler. It implements ++ * hierarchical weight-based cgroup CPU control by flattening the cgroup ++ * hierarchy into a single layer by compounding the active weight share at each ++ * level. Consider the following hierarchy with weights in parentheses: ++ * ++ * R + A (100) + B (100) ++ * | \ C (100) ++ * \ D (200) ++ * ++ * Ignoring the root and threaded cgroups, only B, C and D can contain tasks. ++ * Let's say all three have runnable tasks. The total share that each of these ++ * three cgroups is entitled to can be calculated by compounding its share at ++ * each level. ++ * ++ * For example, B is competing against C and in that competition its share is ++ * 100/(100+100) == 1/2. At its parent level, A is competing against D and A's ++ * share in that competition is 100/(200+100) == 1/3. B's eventual share in the ++ * system can be calculated by multiplying the two shares, 1/2 * 1/3 == 1/6. C's ++ * eventual shaer is the same at 1/6. D is only competing at the top level and ++ * its share is 200/(100+200) == 2/3. ++ * ++ * So, instead of hierarchically scheduling level-by-level, we can consider it ++ * as B, C and D competing each other with respective share of 1/6, 1/6 and 2/3 ++ * and keep updating the eventual shares as the cgroups' runnable states change. ++ * ++ * This flattening of hierarchy can bring a substantial performance gain when ++ * the cgroup hierarchy is nested multiple levels. in a simple benchmark using ++ * wrk[8] on apache serving a CGI script calculating sha1sum of a small file, it ++ * outperforms CFS by ~3% with CPU controller disabled and by ~10% with two ++ * apache instances competing with 2:1 weight ratio nested four level deep. ++ * ++ * However, the gain comes at the cost of not being able to properly handle ++ * thundering herd of cgroups. For example, if many cgroups which are nested ++ * behind a low priority parent cgroup wake up around the same time, they may be ++ * able to consume more CPU cycles than they are entitled to. In many use cases, ++ * this isn't a real concern especially given the performance gain. Also, there ++ * are ways to mitigate the problem further by e.g. introducing an extra ++ * scheduling layer on cgroup delegation boundaries. ++ * ++ * The scheduler first picks the cgroup to run and then schedule the tasks ++ * within by using nested weighted vtime scheduling by default. The ++ * cgroup-internal scheduling can be switched to FIFO with the -f option. ++ */ ++#include <scx/common.bpf.h> ++#include "scx_flatcg.h" ++ ++/* ++ * Maximum amount of retries to find a valid cgroup. ++ */ ++enum { ++ FALLBACK_DSQ = 0, ++ CGROUP_MAX_RETRIES = 1024, ++}; ++ ++char _license[] SEC("license") = "GPL"; ++ ++const volatile u32 nr_cpus = 32; /* !0 for veristat, set during init */ ++const volatile u64 cgrp_slice_ns = SCX_SLICE_DFL; ++const volatile bool fifo_sched; ++ ++u64 cvtime_now; ++UEI_DEFINE(uei); ++ ++struct { ++ __uint(type, BPF_MAP_TYPE_PERCPU_ARRAY); ++ __type(key, u32); ++ __type(value, u64); ++ __uint(max_entries, FCG_NR_STATS); ++} stats SEC(".maps"); ++ ++static void stat_inc(enum fcg_stat_idx idx) ++{ ++ u32 idx_v = idx; ++ ++ u64 *cnt_p = bpf_map_lookup_elem(&stats, &idx_v); ++ if (cnt_p) ++ (*cnt_p)++; ++} ++ ++struct fcg_cpu_ctx { ++ u64 cur_cgid; ++ u64 cur_at; ++}; ++ ++struct { ++ __uint(type, BPF_MAP_TYPE_PERCPU_ARRAY); ++ __type(key, u32); ++ __type(value, struct fcg_cpu_ctx); ++ __uint(max_entries, 1); ++} cpu_ctx SEC(".maps"); ++ ++struct { ++ __uint(type, BPF_MAP_TYPE_CGRP_STORAGE); ++ __uint(map_flags, BPF_F_NO_PREALLOC); ++ __type(key, int); ++ __type(value, struct fcg_cgrp_ctx); ++} cgrp_ctx SEC(".maps"); ++ ++struct cgv_node { ++ struct bpf_rb_node rb_node; ++ __u64 cvtime; ++ __u64 cgid; ++}; ++ ++private(CGV_TREE) struct bpf_spin_lock cgv_tree_lock; ++private(CGV_TREE) struct bpf_rb_root cgv_tree __contains(cgv_node, rb_node); ++ ++struct cgv_node_stash { ++ struct cgv_node __kptr *node; ++}; ++ ++struct { ++ __uint(type, BPF_MAP_TYPE_HASH); ++ __uint(max_entries, 16384); ++ __type(key, __u64); ++ __type(value, struct cgv_node_stash); ++} cgv_node_stash SEC(".maps"); ++ ++struct fcg_task_ctx { ++ u64 bypassed_at; ++}; ++ ++struct { ++ __uint(type, BPF_MAP_TYPE_TASK_STORAGE); ++ __uint(map_flags, BPF_F_NO_PREALLOC); ++ __type(key, int); ++ __type(value, struct fcg_task_ctx); ++} task_ctx SEC(".maps"); ++ ++/* gets inc'd on weight tree changes to expire the cached hweights */ ++u64 hweight_gen = 1; ++ ++static u64 div_round_up(u64 dividend, u64 divisor) ++{ ++ return (dividend + divisor - 1) / divisor; ++} ++ ++static bool vtime_before(u64 a, u64 b) ++{ ++ return (s64)(a - b) < 0; ++} ++ ++static bool cgv_node_less(struct bpf_rb_node *a, const struct bpf_rb_node *b) ++{ ++ struct cgv_node *cgc_a, *cgc_b; ++ ++ cgc_a = container_of(a, struct cgv_node, rb_node); ++ cgc_b = container_of(b, struct cgv_node, rb_node); ++ ++ return cgc_a->cvtime < cgc_b->cvtime; ++} ++ ++static struct fcg_cpu_ctx *find_cpu_ctx(void) ++{ ++ struct fcg_cpu_ctx *cpuc; ++ u32 idx = 0; ++ ++ cpuc = bpf_map_lookup_elem(&cpu_ctx, &idx); ++ if (!cpuc) { ++ scx_bpf_error("cpu_ctx lookup failed"); ++ return NULL; ++ } ++ return cpuc; ++} ++ ++static struct fcg_cgrp_ctx *find_cgrp_ctx(struct cgroup *cgrp) ++{ ++ struct fcg_cgrp_ctx *cgc; ++ ++ cgc = bpf_cgrp_storage_get(&cgrp_ctx, cgrp, 0, 0); ++ if (!cgc) { ++ scx_bpf_error("cgrp_ctx lookup failed for cgid %llu", cgrp->kn->id); ++ return NULL; ++ } ++ return cgc; ++} ++ ++static struct fcg_cgrp_ctx *find_ancestor_cgrp_ctx(struct cgroup *cgrp, int level) ++{ ++ struct fcg_cgrp_ctx *cgc; ++ ++ cgrp = bpf_cgroup_ancestor(cgrp, level); ++ if (!cgrp) { ++ scx_bpf_error("ancestor cgroup lookup failed"); ++ return NULL; ++ } ++ ++ cgc = find_cgrp_ctx(cgrp); ++ if (!cgc) ++ scx_bpf_error("ancestor cgrp_ctx lookup failed"); ++ bpf_cgroup_release(cgrp); ++ return cgc; ++} ++ ++static void cgrp_refresh_hweight(struct cgroup *cgrp, struct fcg_cgrp_ctx *cgc) ++{ ++ int level; ++ ++ if (!cgc->nr_active) { ++ stat_inc(FCG_STAT_HWT_SKIP); ++ return; ++ } ++ ++ if (cgc->hweight_gen == hweight_gen) { ++ stat_inc(FCG_STAT_HWT_CACHE); ++ return; ++ } ++ ++ stat_inc(FCG_STAT_HWT_UPDATES); ++ bpf_for(level, 0, cgrp->level + 1) { ++ struct fcg_cgrp_ctx *cgc; ++ bool is_active; ++ ++ cgc = find_ancestor_cgrp_ctx(cgrp, level); ++ if (!cgc) ++ break; ++ ++ if (!level) { ++ cgc->hweight = FCG_HWEIGHT_ONE; ++ cgc->hweight_gen = hweight_gen; ++ } else { ++ struct fcg_cgrp_ctx *pcgc; ++ ++ pcgc = find_ancestor_cgrp_ctx(cgrp, level - 1); ++ if (!pcgc) ++ break; ++ ++ /* ++ * We can be opportunistic here and not grab the ++ * cgv_tree_lock and deal with the occasional races. ++ * However, hweight updates are already cached and ++ * relatively low-frequency. Let's just do the ++ * straightforward thing. ++ */ ++ bpf_spin_lock(&cgv_tree_lock); ++ is_active = cgc->nr_active; ++ if (is_active) { ++ cgc->hweight_gen = pcgc->hweight_gen; ++ cgc->hweight = ++ div_round_up(pcgc->hweight * cgc->weight, ++ pcgc->child_weight_sum); ++ } ++ bpf_spin_unlock(&cgv_tree_lock); ++ ++ if (!is_active) { ++ stat_inc(FCG_STAT_HWT_RACE); ++ break; ++ } ++ } ++ } ++} ++ ++static void cgrp_cap_budget(struct cgv_node *cgv_node, struct fcg_cgrp_ctx *cgc) ++{ ++ u64 delta, cvtime, max_budget; ++ ++ /* ++ * A node which is on the rbtree can't be pointed to from elsewhere yet ++ * and thus can't be updated and repositioned. Instead, we collect the ++ * vtime deltas separately and apply it asynchronously here. ++ */ ++ delta = __sync_fetch_and_sub(&cgc->cvtime_delta, cgc->cvtime_delta); ++ cvtime = cgv_node->cvtime + delta; ++ ++ /* ++ * Allow a cgroup to carry the maximum budget proportional to its ++ * hweight such that a full-hweight cgroup can immediately take up half ++ * of the CPUs at the most while staying at the front of the rbtree. ++ */ ++ max_budget = (cgrp_slice_ns * nr_cpus * cgc->hweight) / ++ (2 * FCG_HWEIGHT_ONE); ++ if (vtime_before(cvtime, cvtime_now - max_budget)) ++ cvtime = cvtime_now - max_budget; ++ ++ cgv_node->cvtime = cvtime; ++} ++ ++static void cgrp_enqueued(struct cgroup *cgrp, struct fcg_cgrp_ctx *cgc) ++{ ++ struct cgv_node_stash *stash; ++ struct cgv_node *cgv_node; ++ u64 cgid = cgrp->kn->id; ++ ++ /* paired with cmpxchg in try_pick_next_cgroup() */ ++ if (__sync_val_compare_and_swap(&cgc->queued, 0, 1)) { ++ stat_inc(FCG_STAT_ENQ_SKIP); ++ return; ++ } ++ ++ stash = bpf_map_lookup_elem(&cgv_node_stash, &cgid); ++ if (!stash) { ++ scx_bpf_error("cgv_node lookup failed for cgid %llu", cgid); ++ return; ++ } ++ ++ /* NULL if the node is already on the rbtree */ ++ cgv_node = bpf_kptr_xchg(&stash->node, NULL); ++ if (!cgv_node) { ++ stat_inc(FCG_STAT_ENQ_RACE); ++ return; ++ } ++ ++ bpf_spin_lock(&cgv_tree_lock); ++ cgrp_cap_budget(cgv_node, cgc); ++ bpf_rbtree_add(&cgv_tree, &cgv_node->rb_node, cgv_node_less); ++ bpf_spin_unlock(&cgv_tree_lock); ++} ++ ++static void set_bypassed_at(struct task_struct *p, struct fcg_task_ctx *taskc) ++{ ++ /* ++ * Tell fcg_stopping() that this bypassed the regular scheduling path ++ * and should be force charged to the cgroup. 0 is used to indicate that ++ * the task isn't bypassing, so if the current runtime is 0, go back by ++ * one nanosecond. ++ */ ++ taskc->bypassed_at = p->se.sum_exec_runtime ?: (u64)-1; ++} ++ ++s32 BPF_STRUCT_OPS(fcg_select_cpu, struct task_struct *p, s32 prev_cpu, u64 wake_flags) ++{ ++ struct fcg_task_ctx *taskc; ++ bool is_idle = false; ++ s32 cpu; ++ ++ cpu = scx_bpf_select_cpu_dfl(p, prev_cpu, wake_flags, &is_idle); ++ ++ taskc = bpf_task_storage_get(&task_ctx, p, 0, 0); ++ if (!taskc) { ++ scx_bpf_error("task_ctx lookup failed"); ++ return cpu; ++ } ++ ++ /* ++ * If select_cpu_dfl() is recommending local enqueue, the target CPU is ++ * idle. Follow it and charge the cgroup later in fcg_stopping() after ++ * the fact. ++ */ ++ if (is_idle) { ++ set_bypassed_at(p, taskc); ++ stat_inc(FCG_STAT_LOCAL); ++ scx_bpf_dispatch(p, SCX_DSQ_LOCAL, SCX_SLICE_DFL, 0); ++ } ++ ++ return cpu; ++} ++ ++void BPF_STRUCT_OPS(fcg_enqueue, struct task_struct *p, u64 enq_flags) ++{ ++ struct fcg_task_ctx *taskc; ++ struct cgroup *cgrp; ++ struct fcg_cgrp_ctx *cgc; ++ ++ taskc = bpf_task_storage_get(&task_ctx, p, 0, 0); ++ if (!taskc) { ++ scx_bpf_error("task_ctx lookup failed"); ++ return; ++ } ++ ++ /* ++ * Use the direct dispatching and force charging to deal with tasks with ++ * custom affinities so that we don't have to worry about per-cgroup ++ * dq's containing tasks that can't be executed from some CPUs. ++ */ ++ if (p->nr_cpus_allowed != nr_cpus) { ++ set_bypassed_at(p, taskc); ++ ++ /* ++ * The global dq is deprioritized as we don't want to let tasks ++ * to boost themselves by constraining its cpumask. The ++ * deprioritization is rather severe, so let's not apply that to ++ * per-cpu kernel threads. This is ham-fisted. We probably wanna ++ * implement per-cgroup fallback dq's instead so that we have ++ * more control over when tasks with custom cpumask get issued. ++ */ ++ if (p->nr_cpus_allowed == 1 && (p->flags & PF_KTHREAD)) { ++ stat_inc(FCG_STAT_LOCAL); ++ scx_bpf_dispatch(p, SCX_DSQ_LOCAL, SCX_SLICE_DFL, enq_flags); ++ } else { ++ stat_inc(FCG_STAT_GLOBAL); ++ scx_bpf_dispatch(p, FALLBACK_DSQ, SCX_SLICE_DFL, enq_flags); ++ } ++ return; ++ } ++ ++ cgrp = __COMPAT_scx_bpf_task_cgroup(p); ++ cgc = find_cgrp_ctx(cgrp); ++ if (!cgc) ++ goto out_release; ++ ++ if (fifo_sched) { ++ scx_bpf_dispatch(p, cgrp->kn->id, SCX_SLICE_DFL, enq_flags); ++ } else { ++ u64 tvtime = p->scx.dsq_vtime; ++ ++ /* ++ * Limit the amount of budget that an idling task can accumulate ++ * to one slice. ++ */ ++ if (vtime_before(tvtime, cgc->tvtime_now - SCX_SLICE_DFL)) ++ tvtime = cgc->tvtime_now - SCX_SLICE_DFL; ++ ++ scx_bpf_dispatch_vtime(p, cgrp->kn->id, SCX_SLICE_DFL, ++ tvtime, enq_flags); ++ } ++ ++ cgrp_enqueued(cgrp, cgc); ++out_release: ++ bpf_cgroup_release(cgrp); ++} ++ ++/* ++ * Walk the cgroup tree to update the active weight sums as tasks wake up and ++ * sleep. The weight sums are used as the base when calculating the proportion a ++ * given cgroup or task is entitled to at each level. ++ */ ++static void update_active_weight_sums(struct cgroup *cgrp, bool runnable) ++{ ++ struct fcg_cgrp_ctx *cgc; ++ bool updated = false; ++ int idx; ++ ++ cgc = find_cgrp_ctx(cgrp); ++ if (!cgc) ++ return; ++ ++ /* ++ * In most cases, a hot cgroup would have multiple threads going to ++ * sleep and waking up while the whole cgroup stays active. In leaf ++ * cgroups, ->nr_runnable which is updated with __sync operations gates ++ * ->nr_active updates, so that we don't have to grab the cgv_tree_lock ++ * repeatedly for a busy cgroup which is staying active. ++ */ ++ if (runnable) { ++ if (__sync_fetch_and_add(&cgc->nr_runnable, 1)) ++ return; ++ stat_inc(FCG_STAT_ACT); ++ } else { ++ if (__sync_sub_and_fetch(&cgc->nr_runnable, 1)) ++ return; ++ stat_inc(FCG_STAT_DEACT); ++ } ++ ++ /* ++ * If @cgrp is becoming runnable, its hweight should be refreshed after ++ * it's added to the weight tree so that enqueue has the up-to-date ++ * value. If @cgrp is becoming quiescent, the hweight should be ++ * refreshed before it's removed from the weight tree so that the usage ++ * charging which happens afterwards has access to the latest value. ++ */ ++ if (!runnable) ++ cgrp_refresh_hweight(cgrp, cgc); ++ ++ /* propagate upwards */ ++ bpf_for(idx, 0, cgrp->level) { ++ int level = cgrp->level - idx; ++ struct fcg_cgrp_ctx *cgc, *pcgc = NULL; ++ bool propagate = false; ++ ++ cgc = find_ancestor_cgrp_ctx(cgrp, level); ++ if (!cgc) ++ break; ++ if (level) { ++ pcgc = find_ancestor_cgrp_ctx(cgrp, level - 1); ++ if (!pcgc) ++ break; ++ } ++ ++ /* ++ * We need the propagation protected by a lock to synchronize ++ * against weight changes. There's no reason to drop the lock at ++ * each level but bpf_spin_lock() doesn't want any function ++ * calls while locked. ++ */ ++ bpf_spin_lock(&cgv_tree_lock); ++ ++ if (runnable) { ++ if (!cgc->nr_active++) { ++ updated = true; ++ if (pcgc) { ++ propagate = true; ++ pcgc->child_weight_sum += cgc->weight; ++ } ++ } ++ } else { ++ if (!--cgc->nr_active) { ++ updated = true; ++ if (pcgc) { ++ propagate = true; ++ pcgc->child_weight_sum -= cgc->weight; ++ } ++ } ++ } ++ ++ bpf_spin_unlock(&cgv_tree_lock); ++ ++ if (!propagate) ++ break; ++ } ++ ++ if (updated) ++ __sync_fetch_and_add(&hweight_gen, 1); ++ ++ if (runnable) ++ cgrp_refresh_hweight(cgrp, cgc); ++} ++ ++void BPF_STRUCT_OPS(fcg_runnable, struct task_struct *p, u64 enq_flags) ++{ ++ struct cgroup *cgrp; ++ ++ cgrp = __COMPAT_scx_bpf_task_cgroup(p); ++ update_active_weight_sums(cgrp, true); ++ bpf_cgroup_release(cgrp); ++} ++ ++void BPF_STRUCT_OPS(fcg_running, struct task_struct *p) ++{ ++ struct cgroup *cgrp; ++ struct fcg_cgrp_ctx *cgc; ++ ++ if (fifo_sched) ++ return; ++ ++ cgrp = __COMPAT_scx_bpf_task_cgroup(p); ++ cgc = find_cgrp_ctx(cgrp); ++ if (cgc) { ++ /* ++ * @cgc->tvtime_now always progresses forward as tasks start ++ * executing. The test and update can be performed concurrently ++ * from multiple CPUs and thus racy. Any error should be ++ * contained and temporary. Let's just live with it. ++ */ ++ if (vtime_before(cgc->tvtime_now, p->scx.dsq_vtime)) ++ cgc->tvtime_now = p->scx.dsq_vtime; ++ } ++ bpf_cgroup_release(cgrp); ++} ++ ++void BPF_STRUCT_OPS(fcg_stopping, struct task_struct *p, bool runnable) ++{ ++ struct fcg_task_ctx *taskc; ++ struct cgroup *cgrp; ++ struct fcg_cgrp_ctx *cgc; ++ ++ /* ++ * Scale the execution time by the inverse of the weight and charge. ++ * ++ * Note that the default yield implementation yields by setting ++ * @p->scx.slice to zero and the following would treat the yielding task ++ * as if it has consumed all its slice. If this penalizes yielding tasks ++ * too much, determine the execution time by taking explicit timestamps ++ * instead of depending on @p->scx.slice. ++ */ ++ if (!fifo_sched) ++ p->scx.dsq_vtime += ++ (SCX_SLICE_DFL - p->scx.slice) * 100 / p->scx.weight; ++ ++ taskc = bpf_task_storage_get(&task_ctx, p, 0, 0); ++ if (!taskc) { ++ scx_bpf_error("task_ctx lookup failed"); ++ return; ++ } ++ ++ if (!taskc->bypassed_at) ++ return; ++ ++ cgrp = __COMPAT_scx_bpf_task_cgroup(p); ++ cgc = find_cgrp_ctx(cgrp); ++ if (cgc) { ++ __sync_fetch_and_add(&cgc->cvtime_delta, ++ p->se.sum_exec_runtime - taskc->bypassed_at); ++ taskc->bypassed_at = 0; ++ } ++ bpf_cgroup_release(cgrp); ++} ++ ++void BPF_STRUCT_OPS(fcg_quiescent, struct task_struct *p, u64 deq_flags) ++{ ++ struct cgroup *cgrp; ++ ++ cgrp = __COMPAT_scx_bpf_task_cgroup(p); ++ update_active_weight_sums(cgrp, false); ++ bpf_cgroup_release(cgrp); ++} ++ ++void BPF_STRUCT_OPS(fcg_cgroup_set_weight, struct cgroup *cgrp, u32 weight) ++{ ++ struct fcg_cgrp_ctx *cgc, *pcgc = NULL; ++ ++ cgc = find_cgrp_ctx(cgrp); ++ if (!cgc) ++ return; ++ ++ if (cgrp->level) { ++ pcgc = find_ancestor_cgrp_ctx(cgrp, cgrp->level - 1); ++ if (!pcgc) ++ return; ++ } ++ ++ bpf_spin_lock(&cgv_tree_lock); ++ if (pcgc && cgc->nr_active) ++ pcgc->child_weight_sum += (s64)weight - cgc->weight; ++ cgc->weight = weight; ++ bpf_spin_unlock(&cgv_tree_lock); ++} ++ ++static bool try_pick_next_cgroup(u64 *cgidp) ++{ ++ struct bpf_rb_node *rb_node; ++ struct cgv_node_stash *stash; ++ struct cgv_node *cgv_node; ++ struct fcg_cgrp_ctx *cgc; ++ struct cgroup *cgrp; ++ u64 cgid; ++ ++ /* pop the front cgroup and wind cvtime_now accordingly */ ++ bpf_spin_lock(&cgv_tree_lock); ++ ++ rb_node = bpf_rbtree_first(&cgv_tree); ++ if (!rb_node) { ++ bpf_spin_unlock(&cgv_tree_lock); ++ stat_inc(FCG_STAT_PNC_NO_CGRP); ++ *cgidp = 0; ++ return true; ++ } ++ ++ rb_node = bpf_rbtree_remove(&cgv_tree, rb_node); ++ bpf_spin_unlock(&cgv_tree_lock); ++ ++ if (!rb_node) { ++ /* ++ * This should never happen. bpf_rbtree_first() was called ++ * above while the tree lock was held, so the node should ++ * always be present. ++ */ ++ scx_bpf_error("node could not be removed"); ++ return true; ++ } ++ ++ cgv_node = container_of(rb_node, struct cgv_node, rb_node); ++ cgid = cgv_node->cgid; ++ ++ if (vtime_before(cvtime_now, cgv_node->cvtime)) ++ cvtime_now = cgv_node->cvtime; ++ ++ /* ++ * If lookup fails, the cgroup's gone. Free and move on. See ++ * fcg_cgroup_exit(). ++ */ ++ cgrp = bpf_cgroup_from_id(cgid); ++ if (!cgrp) { ++ stat_inc(FCG_STAT_PNC_GONE); ++ goto out_free; ++ } ++ ++ cgc = bpf_cgrp_storage_get(&cgrp_ctx, cgrp, 0, 0); ++ if (!cgc) { ++ bpf_cgroup_release(cgrp); ++ stat_inc(FCG_STAT_PNC_GONE); ++ goto out_free; ++ } ++ ++ if (!scx_bpf_consume(cgid)) { ++ bpf_cgroup_release(cgrp); ++ stat_inc(FCG_STAT_PNC_EMPTY); ++ goto out_stash; ++ } ++ ++ /* ++ * Successfully consumed from the cgroup. This will be our current ++ * cgroup for the new slice. Refresh its hweight. ++ */ ++ cgrp_refresh_hweight(cgrp, cgc); ++ ++ bpf_cgroup_release(cgrp); ++ ++ /* ++ * As the cgroup may have more tasks, add it back to the rbtree. Note ++ * that here we charge the full slice upfront and then exact later ++ * according to the actual consumption. This prevents lowpri thundering ++ * herd from saturating the machine. ++ */ ++ bpf_spin_lock(&cgv_tree_lock); ++ cgv_node->cvtime += cgrp_slice_ns * FCG_HWEIGHT_ONE / (cgc->hweight ?: 1); ++ cgrp_cap_budget(cgv_node, cgc); ++ bpf_rbtree_add(&cgv_tree, &cgv_node->rb_node, cgv_node_less); ++ bpf_spin_unlock(&cgv_tree_lock); ++ ++ *cgidp = cgid; ++ stat_inc(FCG_STAT_PNC_NEXT); ++ return true; ++ ++out_stash: ++ stash = bpf_map_lookup_elem(&cgv_node_stash, &cgid); ++ if (!stash) { ++ stat_inc(FCG_STAT_PNC_GONE); ++ goto out_free; ++ } ++ ++ /* ++ * Paired with cmpxchg in cgrp_enqueued(). If they see the following ++ * transition, they'll enqueue the cgroup. If they are earlier, we'll ++ * see their task in the dq below and requeue the cgroup. ++ */ ++ __sync_val_compare_and_swap(&cgc->queued, 1, 0); ++ ++ if (scx_bpf_dsq_nr_queued(cgid)) { ++ bpf_spin_lock(&cgv_tree_lock); ++ bpf_rbtree_add(&cgv_tree, &cgv_node->rb_node, cgv_node_less); ++ bpf_spin_unlock(&cgv_tree_lock); ++ stat_inc(FCG_STAT_PNC_RACE); ++ } else { ++ cgv_node = bpf_kptr_xchg(&stash->node, cgv_node); ++ if (cgv_node) { ++ scx_bpf_error("unexpected !NULL cgv_node stash"); ++ goto out_free; ++ } ++ } ++ ++ return false; ++ ++out_free: ++ bpf_obj_drop(cgv_node); ++ return false; ++} ++ ++void BPF_STRUCT_OPS(fcg_dispatch, s32 cpu, struct task_struct *prev) ++{ ++ struct fcg_cpu_ctx *cpuc; ++ struct fcg_cgrp_ctx *cgc; ++ struct cgroup *cgrp; ++ u64 now = bpf_ktime_get_ns(); ++ bool picked_next = false; ++ ++ cpuc = find_cpu_ctx(); ++ if (!cpuc) ++ return; ++ ++ if (!cpuc->cur_cgid) ++ goto pick_next_cgroup; ++ ++ if (vtime_before(now, cpuc->cur_at + cgrp_slice_ns)) { ++ if (scx_bpf_consume(cpuc->cur_cgid)) { ++ stat_inc(FCG_STAT_CNS_KEEP); ++ return; ++ } ++ stat_inc(FCG_STAT_CNS_EMPTY); ++ } else { ++ stat_inc(FCG_STAT_CNS_EXPIRE); ++ } ++ ++ /* ++ * The current cgroup is expiring. It was already charged a full slice. ++ * Calculate the actual usage and accumulate the delta. ++ */ ++ cgrp = bpf_cgroup_from_id(cpuc->cur_cgid); ++ if (!cgrp) { ++ stat_inc(FCG_STAT_CNS_GONE); ++ goto pick_next_cgroup; ++ } ++ ++ cgc = bpf_cgrp_storage_get(&cgrp_ctx, cgrp, 0, 0); ++ if (cgc) { ++ /* ++ * We want to update the vtime delta and then look for the next ++ * cgroup to execute but the latter needs to be done in a loop ++ * and we can't keep the lock held. Oh well... ++ */ ++ bpf_spin_lock(&cgv_tree_lock); ++ __sync_fetch_and_add(&cgc->cvtime_delta, ++ (cpuc->cur_at + cgrp_slice_ns - now) * ++ FCG_HWEIGHT_ONE / (cgc->hweight ?: 1)); ++ bpf_spin_unlock(&cgv_tree_lock); ++ } else { ++ stat_inc(FCG_STAT_CNS_GONE); ++ } ++ ++ bpf_cgroup_release(cgrp); ++ ++pick_next_cgroup: ++ cpuc->cur_at = now; ++ ++ if (scx_bpf_consume(FALLBACK_DSQ)) { ++ cpuc->cur_cgid = 0; ++ return; ++ } ++ ++ bpf_repeat(CGROUP_MAX_RETRIES) { ++ if (try_pick_next_cgroup(&cpuc->cur_cgid)) { ++ picked_next = true; ++ break; ++ } ++ } ++ ++ /* ++ * This only happens if try_pick_next_cgroup() races against enqueue ++ * path for more than CGROUP_MAX_RETRIES times, which is extremely ++ * unlikely and likely indicates an underlying bug. There shouldn't be ++ * any stall risk as the race is against enqueue. ++ */ ++ if (!picked_next) ++ stat_inc(FCG_STAT_PNC_FAIL); ++} ++ ++s32 BPF_STRUCT_OPS(fcg_init_task, struct task_struct *p, ++ struct scx_init_task_args *args) ++{ ++ struct fcg_task_ctx *taskc; ++ struct fcg_cgrp_ctx *cgc; ++ ++ /* ++ * @p is new. Let's ensure that its task_ctx is available. We can sleep ++ * in this function and the following will automatically use GFP_KERNEL. ++ */ ++ taskc = bpf_task_storage_get(&task_ctx, p, 0, ++ BPF_LOCAL_STORAGE_GET_F_CREATE); ++ if (!taskc) ++ return -ENOMEM; ++ ++ taskc->bypassed_at = 0; ++ ++ if (!(cgc = find_cgrp_ctx(args->cgroup))) ++ return -ENOENT; ++ ++ p->scx.dsq_vtime = cgc->tvtime_now; ++ ++ return 0; ++} ++ ++int BPF_STRUCT_OPS_SLEEPABLE(fcg_cgroup_init, struct cgroup *cgrp, ++ struct scx_cgroup_init_args *args) ++{ ++ struct fcg_cgrp_ctx *cgc; ++ struct cgv_node *cgv_node; ++ struct cgv_node_stash empty_stash = {}, *stash; ++ u64 cgid = cgrp->kn->id; ++ int ret; ++ ++ /* ++ * Technically incorrect as cgroup ID is full 64bit while dsq ID is ++ * 63bit. Should not be a problem in practice and easy to spot in the ++ * unlikely case that it breaks. ++ */ ++ ret = scx_bpf_create_dsq(cgid, -1); ++ if (ret) ++ return ret; ++ ++ cgc = bpf_cgrp_storage_get(&cgrp_ctx, cgrp, 0, ++ BPF_LOCAL_STORAGE_GET_F_CREATE); ++ if (!cgc) { ++ ret = -ENOMEM; ++ goto err_destroy_dsq; ++ } ++ ++ cgc->weight = args->weight; ++ cgc->hweight = FCG_HWEIGHT_ONE; ++ ++ ret = bpf_map_update_elem(&cgv_node_stash, &cgid, &empty_stash, ++ BPF_NOEXIST); ++ if (ret) { ++ if (ret != -ENOMEM) ++ scx_bpf_error("unexpected stash creation error (%d)", ++ ret); ++ goto err_destroy_dsq; ++ } ++ ++ stash = bpf_map_lookup_elem(&cgv_node_stash, &cgid); ++ if (!stash) { ++ scx_bpf_error("unexpected cgv_node stash lookup failure"); ++ ret = -ENOENT; ++ goto err_destroy_dsq; ++ } ++ ++ cgv_node = bpf_obj_new(struct cgv_node); ++ if (!cgv_node) { ++ ret = -ENOMEM; ++ goto err_del_cgv_node; ++ } ++ ++ cgv_node->cgid = cgid; ++ cgv_node->cvtime = cvtime_now; ++ ++ cgv_node = bpf_kptr_xchg(&stash->node, cgv_node); ++ if (cgv_node) { ++ scx_bpf_error("unexpected !NULL cgv_node stash"); ++ ret = -EBUSY; ++ goto err_drop; ++ } ++ ++ return 0; ++ ++err_drop: ++ bpf_obj_drop(cgv_node); ++err_del_cgv_node: ++ bpf_map_delete_elem(&cgv_node_stash, &cgid); ++err_destroy_dsq: ++ scx_bpf_destroy_dsq(cgid); ++ return ret; ++} ++ ++void BPF_STRUCT_OPS(fcg_cgroup_exit, struct cgroup *cgrp) ++{ ++ u64 cgid = cgrp->kn->id; ++ ++ /* ++ * For now, there's no way find and remove the cgv_node if it's on the ++ * cgv_tree. Let's drain them in the dispatch path as they get popped ++ * off the front of the tree. ++ */ ++ bpf_map_delete_elem(&cgv_node_stash, &cgid); ++ scx_bpf_destroy_dsq(cgid); ++} ++ ++void BPF_STRUCT_OPS(fcg_cgroup_move, struct task_struct *p, ++ struct cgroup *from, struct cgroup *to) ++{ ++ struct fcg_cgrp_ctx *from_cgc, *to_cgc; ++ s64 vtime_delta; ++ ++ /* find_cgrp_ctx() triggers scx_ops_error() on lookup failures */ ++ if (!(from_cgc = find_cgrp_ctx(from)) || !(to_cgc = find_cgrp_ctx(to))) ++ return; ++ ++ vtime_delta = p->scx.dsq_vtime - from_cgc->tvtime_now; ++ p->scx.dsq_vtime = to_cgc->tvtime_now + vtime_delta; ++} ++ ++s32 BPF_STRUCT_OPS_SLEEPABLE(fcg_init) ++{ ++ return scx_bpf_create_dsq(FALLBACK_DSQ, -1); ++} ++ ++void BPF_STRUCT_OPS(fcg_exit, struct scx_exit_info *ei) ++{ ++ UEI_RECORD(uei, ei); ++} ++ ++SCX_OPS_DEFINE(flatcg_ops, ++ .select_cpu = (void *)fcg_select_cpu, ++ .enqueue = (void *)fcg_enqueue, ++ .dispatch = (void *)fcg_dispatch, ++ .runnable = (void *)fcg_runnable, ++ .running = (void *)fcg_running, ++ .stopping = (void *)fcg_stopping, ++ .quiescent = (void *)fcg_quiescent, ++ .init_task = (void *)fcg_init_task, ++ .cgroup_set_weight = (void *)fcg_cgroup_set_weight, ++ .cgroup_init = (void *)fcg_cgroup_init, ++ .cgroup_exit = (void *)fcg_cgroup_exit, ++ .cgroup_move = (void *)fcg_cgroup_move, ++ .init = (void *)fcg_init, ++ .exit = (void *)fcg_exit, ++ .flags = SCX_OPS_HAS_CGROUP_WEIGHT | SCX_OPS_ENQ_EXITING, ++ .name = "flatcg"); +diff --git a/tools/sched_ext/scx_flatcg.c b/tools/sched_ext/scx_flatcg.c +new file mode 100644 +index 000000000000..5d24ca9c29d9 +--- /dev/null ++++ b/tools/sched_ext/scx_flatcg.c +@@ -0,0 +1,233 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (c) 2023 Meta Platforms, Inc. and affiliates. ++ * Copyright (c) 2023 Tejun Heo <tj@kernel.org> ++ * Copyright (c) 2023 David Vernet <dvernet@meta.com> ++ */ ++#include <stdio.h> ++#include <signal.h> ++#include <unistd.h> ++#include <libgen.h> ++#include <limits.h> ++#include <inttypes.h> ++#include <fcntl.h> ++#include <time.h> ++#include <bpf/bpf.h> ++#include <scx/common.h> ++#include "scx_flatcg.h" ++#include "scx_flatcg.bpf.skel.h" ++ ++#ifndef FILEID_KERNFS ++#define FILEID_KERNFS 0xfe ++#endif ++ ++const char help_fmt[] = ++"A flattened cgroup hierarchy sched_ext scheduler.\n" ++"\n" ++"See the top-level comment in .bpf.c for more details.\n" ++"\n" ++"Usage: %s [-s SLICE_US] [-i INTERVAL] [-f] [-v]\n" ++"\n" ++" -s SLICE_US Override slice duration\n" ++" -i INTERVAL Report interval\n" ++" -f Use FIFO scheduling instead of weighted vtime scheduling\n" ++" -v Print libbpf debug messages\n" ++" -h Display this help and exit\n"; ++ ++static bool verbose; ++static volatile int exit_req; ++ ++static int libbpf_print_fn(enum libbpf_print_level level, const char *format, va_list args) ++{ ++ if (level == LIBBPF_DEBUG && !verbose) ++ return 0; ++ return vfprintf(stderr, format, args); ++} ++ ++static void sigint_handler(int dummy) ++{ ++ exit_req = 1; ++} ++ ++static float read_cpu_util(__u64 *last_sum, __u64 *last_idle) ++{ ++ FILE *fp; ++ char buf[4096]; ++ char *line, *cur = NULL, *tok; ++ __u64 sum = 0, idle = 0; ++ __u64 delta_sum, delta_idle; ++ int idx; ++ ++ fp = fopen("/proc/stat", "r"); ++ if (!fp) { ++ perror("fopen(\"/proc/stat\")"); ++ return 0.0; ++ } ++ ++ if (!fgets(buf, sizeof(buf), fp)) { ++ perror("fgets(\"/proc/stat\")"); ++ fclose(fp); ++ return 0.0; ++ } ++ fclose(fp); ++ ++ line = buf; ++ for (idx = 0; (tok = strtok_r(line, " \n", &cur)); idx++) { ++ char *endp = NULL; ++ __u64 v; ++ ++ if (idx == 0) { ++ line = NULL; ++ continue; ++ } ++ v = strtoull(tok, &endp, 0); ++ if (!endp || *endp != '\0') { ++ fprintf(stderr, "failed to parse %dth field of /proc/stat (\"%s\")\n", ++ idx, tok); ++ continue; ++ } ++ sum += v; ++ if (idx == 4) ++ idle = v; ++ } ++ ++ delta_sum = sum - *last_sum; ++ delta_idle = idle - *last_idle; ++ *last_sum = sum; ++ *last_idle = idle; ++ ++ return delta_sum ? (float)(delta_sum - delta_idle) / delta_sum : 0.0; ++} ++ ++static void fcg_read_stats(struct scx_flatcg *skel, __u64 *stats) ++{ ++ __u64 cnts[FCG_NR_STATS][skel->rodata->nr_cpus]; ++ __u32 idx; ++ ++ memset(stats, 0, sizeof(stats[0]) * FCG_NR_STATS); ++ ++ for (idx = 0; idx < FCG_NR_STATS; idx++) { ++ int ret, cpu; ++ ++ ret = bpf_map_lookup_elem(bpf_map__fd(skel->maps.stats), ++ &idx, cnts[idx]); ++ if (ret < 0) ++ continue; ++ for (cpu = 0; cpu < skel->rodata->nr_cpus; cpu++) ++ stats[idx] += cnts[idx][cpu]; ++ } ++} ++ ++int main(int argc, char **argv) ++{ ++ struct scx_flatcg *skel; ++ struct bpf_link *link; ++ struct timespec intv_ts = { .tv_sec = 2, .tv_nsec = 0 }; ++ bool dump_cgrps = false; ++ __u64 last_cpu_sum = 0, last_cpu_idle = 0; ++ __u64 last_stats[FCG_NR_STATS] = {}; ++ unsigned long seq = 0; ++ __s32 opt; ++ __u64 ecode; ++ ++ libbpf_set_print(libbpf_print_fn); ++ signal(SIGINT, sigint_handler); ++ signal(SIGTERM, sigint_handler); ++restart: ++ skel = SCX_OPS_OPEN(flatcg_ops, scx_flatcg); ++ ++ skel->rodata->nr_cpus = libbpf_num_possible_cpus(); ++ ++ while ((opt = getopt(argc, argv, "s:i:dfvh")) != -1) { ++ double v; ++ ++ switch (opt) { ++ case 's': ++ v = strtod(optarg, NULL); ++ skel->rodata->cgrp_slice_ns = v * 1000; ++ break; ++ case 'i': ++ v = strtod(optarg, NULL); ++ intv_ts.tv_sec = v; ++ intv_ts.tv_nsec = (v - (float)intv_ts.tv_sec) * 1000000000; ++ break; ++ case 'd': ++ dump_cgrps = true; ++ break; ++ case 'f': ++ skel->rodata->fifo_sched = true; ++ break; ++ case 'v': ++ verbose = true; ++ break; ++ case 'h': ++ default: ++ fprintf(stderr, help_fmt, basename(argv[0])); ++ return opt != 'h'; ++ } ++ } ++ ++ printf("slice=%.1lfms intv=%.1lfs dump_cgrps=%d", ++ (double)skel->rodata->cgrp_slice_ns / 1000000.0, ++ (double)intv_ts.tv_sec + (double)intv_ts.tv_nsec / 1000000000.0, ++ dump_cgrps); ++ ++ SCX_OPS_LOAD(skel, flatcg_ops, scx_flatcg, uei); ++ link = SCX_OPS_ATTACH(skel, flatcg_ops, scx_flatcg); ++ ++ while (!exit_req && !UEI_EXITED(skel, uei)) { ++ __u64 acc_stats[FCG_NR_STATS]; ++ __u64 stats[FCG_NR_STATS]; ++ float cpu_util; ++ int i; ++ ++ cpu_util = read_cpu_util(&last_cpu_sum, &last_cpu_idle); ++ ++ fcg_read_stats(skel, acc_stats); ++ for (i = 0; i < FCG_NR_STATS; i++) ++ stats[i] = acc_stats[i] - last_stats[i]; ++ ++ memcpy(last_stats, acc_stats, sizeof(acc_stats)); ++ ++ printf("\n[SEQ %6lu cpu=%5.1lf hweight_gen=%" PRIu64 "]\n", ++ seq++, cpu_util * 100.0, skel->data->hweight_gen); ++ printf(" act:%6llu deact:%6llu global:%6llu local:%6llu\n", ++ stats[FCG_STAT_ACT], ++ stats[FCG_STAT_DEACT], ++ stats[FCG_STAT_GLOBAL], ++ stats[FCG_STAT_LOCAL]); ++ printf("HWT cache:%6llu update:%6llu skip:%6llu race:%6llu\n", ++ stats[FCG_STAT_HWT_CACHE], ++ stats[FCG_STAT_HWT_UPDATES], ++ stats[FCG_STAT_HWT_SKIP], ++ stats[FCG_STAT_HWT_RACE]); ++ printf("ENQ skip:%6llu race:%6llu\n", ++ stats[FCG_STAT_ENQ_SKIP], ++ stats[FCG_STAT_ENQ_RACE]); ++ printf("CNS keep:%6llu expire:%6llu empty:%6llu gone:%6llu\n", ++ stats[FCG_STAT_CNS_KEEP], ++ stats[FCG_STAT_CNS_EXPIRE], ++ stats[FCG_STAT_CNS_EMPTY], ++ stats[FCG_STAT_CNS_GONE]); ++ printf("PNC next:%6llu empty:%6llu nocgrp:%6llu gone:%6llu race:%6llu fail:%6llu\n", ++ stats[FCG_STAT_PNC_NEXT], ++ stats[FCG_STAT_PNC_EMPTY], ++ stats[FCG_STAT_PNC_NO_CGRP], ++ stats[FCG_STAT_PNC_GONE], ++ stats[FCG_STAT_PNC_RACE], ++ stats[FCG_STAT_PNC_FAIL]); ++ printf("BAD remove:%6llu\n", ++ acc_stats[FCG_STAT_BAD_REMOVAL]); ++ fflush(stdout); ++ ++ nanosleep(&intv_ts, NULL); ++ } ++ ++ bpf_link__destroy(link); ++ ecode = UEI_REPORT(skel, uei); ++ scx_flatcg__destroy(skel); ++ ++ if (UEI_ECODE_RESTART(ecode)) ++ goto restart; ++ return 0; ++} +diff --git a/tools/sched_ext/scx_flatcg.h b/tools/sched_ext/scx_flatcg.h +new file mode 100644 +index 000000000000..6f2ea50acb1c +--- /dev/null ++++ b/tools/sched_ext/scx_flatcg.h +@@ -0,0 +1,51 @@ ++#ifndef __SCX_EXAMPLE_FLATCG_H ++#define __SCX_EXAMPLE_FLATCG_H ++ ++enum { ++ FCG_HWEIGHT_ONE = 1LLU << 16, ++}; ++ ++enum fcg_stat_idx { ++ FCG_STAT_ACT, ++ FCG_STAT_DEACT, ++ FCG_STAT_LOCAL, ++ FCG_STAT_GLOBAL, ++ ++ FCG_STAT_HWT_UPDATES, ++ FCG_STAT_HWT_CACHE, ++ FCG_STAT_HWT_SKIP, ++ FCG_STAT_HWT_RACE, ++ ++ FCG_STAT_ENQ_SKIP, ++ FCG_STAT_ENQ_RACE, ++ ++ FCG_STAT_CNS_KEEP, ++ FCG_STAT_CNS_EXPIRE, ++ FCG_STAT_CNS_EMPTY, ++ FCG_STAT_CNS_GONE, ++ ++ FCG_STAT_PNC_NO_CGRP, ++ FCG_STAT_PNC_NEXT, ++ FCG_STAT_PNC_EMPTY, ++ FCG_STAT_PNC_GONE, ++ FCG_STAT_PNC_RACE, ++ FCG_STAT_PNC_FAIL, ++ ++ FCG_STAT_BAD_REMOVAL, ++ ++ FCG_NR_STATS, ++}; ++ ++struct fcg_cgrp_ctx { ++ u32 nr_active; ++ u32 nr_runnable; ++ u32 queued; ++ u32 weight; ++ u32 hweight; ++ u64 child_weight_sum; ++ u64 hweight_gen; ++ s64 cvtime_delta; ++ u64 tvtime_now; ++}; ++ ++#endif /* __SCX_EXAMPLE_FLATCG_H */ diff --git a/tools/sched_ext/scx_qmap.bpf.c b/tools/sched_ext/scx_qmap.bpf.c new file mode 100644 -index 000000000000..892278f12dce +index 000000000000..5b39bee9eb23 --- /dev/null +++ b/tools/sched_ext/scx_qmap.bpf.c -@@ -0,0 +1,706 @@ +@@ -0,0 +1,813 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * A simple five-level FIFO queue scheduler. @@ -10432,6 +13055,8 @@ index 000000000000..892278f12dce +enum consts { + ONE_SEC_IN_NS = 1000000000, + SHARED_DSQ = 0, ++ HIGHPRI_DSQ = 1, ++ HIGHPRI_WEIGHT = 8668, /* this is what -20 maps to */ +}; + +char _license[] SEC("license") = "GPL"; @@ -10441,10 +13066,12 @@ index 000000000000..892278f12dce +const volatile u32 stall_kernel_nth; +const volatile u32 dsp_inf_loop_after; +const volatile u32 dsp_batch; ++const volatile bool highpri_boosting; +const volatile bool print_shared_dsq; +const volatile s32 disallow_tgid; +const volatile bool suppress_dump; + ++u64 nr_highpri_queued; +u32 test_error_cnt; + +UEI_DEFINE(uei); @@ -10500,6 +13127,7 @@ index 000000000000..892278f12dce +/* Per-task scheduling context */ +struct task_ctx { + bool force_local; /* Dispatch directly to local_dsq */ ++ bool highpri; + u64 core_sched_seq; +}; + @@ -10527,6 +13155,7 @@ index 000000000000..892278f12dce +/* Statistics */ +u64 nr_enqueued, nr_dispatched, nr_reenqueued, nr_dequeued, nr_ddsp_from_enq; +u64 nr_core_sched_execed; ++u64 nr_expedited_local, nr_expedited_remote, nr_expedited_lost, nr_expedited_from_timer; +u32 cpuperf_min, cpuperf_avg, cpuperf_max; +u32 cpuperf_target_min, cpuperf_target_avg, cpuperf_target_max; + @@ -10545,17 +13174,25 @@ index 000000000000..892278f12dce + return -1; +} + ++static struct task_ctx *lookup_task_ctx(struct task_struct *p) ++{ ++ struct task_ctx *tctx; ++ ++ if (!(tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0))) { ++ scx_bpf_error("task_ctx lookup failed"); ++ return NULL; ++ } ++ return tctx; ++} ++ +s32 BPF_STRUCT_OPS(qmap_select_cpu, struct task_struct *p, + s32 prev_cpu, u64 wake_flags) +{ + struct task_ctx *tctx; + s32 cpu; + -+ tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0); -+ if (!tctx) { -+ scx_bpf_error("task_ctx lookup failed"); ++ if (!(tctx = lookup_task_ctx(p))) + return -ESRCH; -+ } + + cpu = pick_direct_dispatch_cpu(p, prev_cpu); + @@ -10602,11 +13239,8 @@ index 000000000000..892278f12dce + if (test_error_cnt && !--test_error_cnt) + scx_bpf_error("test triggering error"); + -+ tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0); -+ if (!tctx) { -+ scx_bpf_error("task_ctx lookup failed"); ++ if (!(tctx = lookup_task_ctx(p))) + return; -+ } + + /* + * All enqueued tasks must have their core_sched_seq updated for correct @@ -10661,6 +13295,10 @@ index 000000000000..892278f12dce + return; + } + ++ if (highpri_boosting && p->scx.weight >= HIGHPRI_WEIGHT) { ++ tctx->highpri = true; ++ __sync_fetch_and_add(&nr_highpri_queued, 1); ++ } + __sync_fetch_and_add(&nr_enqueued, 1); +} + @@ -10677,13 +13315,80 @@ index 000000000000..892278f12dce + +static void update_core_sched_head_seq(struct task_struct *p) +{ -+ struct task_ctx *tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0); + int idx = weight_to_idx(p->scx.weight); ++ struct task_ctx *tctx; + -+ if (tctx) ++ if ((tctx = lookup_task_ctx(p))) + core_sched_head_seqs[idx] = tctx->core_sched_seq; -+ else -+ scx_bpf_error("task_ctx lookup failed"); ++} ++ ++/* ++ * To demonstrate the use of scx_bpf_dispatch_from_dsq(), implement silly ++ * selective priority boosting mechanism by scanning SHARED_DSQ looking for ++ * highpri tasks, moving them to HIGHPRI_DSQ and then consuming them first. This ++ * makes minor difference only when dsp_batch is larger than 1. ++ * ++ * scx_bpf_dispatch[_vtime]_from_dsq() are allowed both from ops.dispatch() and ++ * non-rq-lock holding BPF programs. As demonstration, this function is called ++ * from qmap_dispatch() and monitor_timerfn(). ++ */ ++static bool dispatch_highpri(bool from_timer) ++{ ++ struct task_struct *p; ++ s32 this_cpu = bpf_get_smp_processor_id(); ++ ++ /* scan SHARED_DSQ and move highpri tasks to HIGHPRI_DSQ */ ++ bpf_for_each(scx_dsq, p, SHARED_DSQ, 0) { ++ static u64 highpri_seq; ++ struct task_ctx *tctx; ++ ++ if (!(tctx = lookup_task_ctx(p))) ++ return false; ++ ++ if (tctx->highpri) { ++ /* exercise the set_*() and vtime interface too */ ++ __COMPAT_scx_bpf_dispatch_from_dsq_set_slice( ++ BPF_FOR_EACH_ITER, slice_ns * 2); ++ __COMPAT_scx_bpf_dispatch_from_dsq_set_vtime( ++ BPF_FOR_EACH_ITER, highpri_seq++); ++ __COMPAT_scx_bpf_dispatch_vtime_from_dsq( ++ BPF_FOR_EACH_ITER, p, HIGHPRI_DSQ, 0); ++ } ++ } ++ ++ /* ++ * Scan HIGHPRI_DSQ and dispatch until a task that can run on this CPU ++ * is found. ++ */ ++ bpf_for_each(scx_dsq, p, HIGHPRI_DSQ, 0) { ++ bool dispatched = false; ++ s32 cpu; ++ ++ if (bpf_cpumask_test_cpu(this_cpu, p->cpus_ptr)) ++ cpu = this_cpu; ++ else ++ cpu = scx_bpf_pick_any_cpu(p->cpus_ptr, 0); ++ ++ if (__COMPAT_scx_bpf_dispatch_from_dsq(BPF_FOR_EACH_ITER, p, ++ SCX_DSQ_LOCAL_ON | cpu, ++ SCX_ENQ_PREEMPT)) { ++ if (cpu == this_cpu) { ++ dispatched = true; ++ __sync_fetch_and_add(&nr_expedited_local, 1); ++ } else { ++ __sync_fetch_and_add(&nr_expedited_remote, 1); ++ } ++ if (from_timer) ++ __sync_fetch_and_add(&nr_expedited_from_timer, 1); ++ } else { ++ __sync_fetch_and_add(&nr_expedited_lost, 1); ++ } ++ ++ if (dispatched) ++ return true; ++ } ++ ++ return false; +} + +void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev) @@ -10694,7 +13399,10 @@ index 000000000000..892278f12dce + void *fifo; + s32 i, pid; + -+ if (scx_bpf_consume(SHARED_DSQ)) ++ if (dispatch_highpri(false)) ++ return; ++ ++ if (!nr_highpri_queued && scx_bpf_consume(SHARED_DSQ)) + return; + + if (dsp_inf_loop_after && nr_dispatched > dsp_inf_loop_after) { @@ -10731,6 +13439,8 @@ index 000000000000..892278f12dce + + /* Dispatch or advance. */ + bpf_repeat(BPF_MAX_LOOPS) { ++ struct task_ctx *tctx; ++ + if (bpf_map_pop_elem(fifo, &pid)) + break; + @@ -10738,13 +13448,25 @@ index 000000000000..892278f12dce + if (!p) + continue; + ++ if (!(tctx = lookup_task_ctx(p))) { ++ bpf_task_release(p); ++ return; ++ } ++ ++ if (tctx->highpri) ++ __sync_fetch_and_sub(&nr_highpri_queued, 1); ++ + update_core_sched_head_seq(p); + __sync_fetch_and_add(&nr_dispatched, 1); ++ + scx_bpf_dispatch(p, SHARED_DSQ, slice_ns, 0); + bpf_task_release(p); ++ + batch--; + cpuc->dsp_cnt--; + if (!batch || !scx_bpf_dispatch_nr_slots()) { ++ if (dispatch_highpri(false)) ++ return; + scx_bpf_consume(SHARED_DSQ); + return; + } @@ -11054,6 +13776,10 @@ index 000000000000..892278f12dce + +static int monitor_timerfn(void *map, int *key, struct bpf_timer *timer) +{ ++ bpf_rcu_read_lock(); ++ dispatch_highpri(true); ++ bpf_rcu_read_unlock(); ++ + monitor_cpuperf(); + + if (print_shared_dsq) @@ -11075,6 +13801,10 @@ index 000000000000..892278f12dce + if (ret) + return ret; + ++ ret = scx_bpf_create_dsq(HIGHPRI_DSQ, -1); ++ if (ret) ++ return ret; ++ + timer = bpf_map_lookup_elem(&monitor_timer, &key); + if (!timer) + return -ESRCH; @@ -11111,10 +13841,10 @@ index 000000000000..892278f12dce + .name = "qmap"); diff --git a/tools/sched_ext/scx_qmap.c b/tools/sched_ext/scx_qmap.c new file mode 100644 -index 000000000000..c9ca30d62b2b +index 000000000000..ac45a02b4055 --- /dev/null +++ b/tools/sched_ext/scx_qmap.c -@@ -0,0 +1,144 @@ +@@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2022 Meta Platforms, Inc. and affiliates. @@ -11146,6 +13876,7 @@ index 000000000000..c9ca30d62b2b +" -l COUNT Trigger dispatch infinite looping after COUNT dispatches\n" +" -b COUNT Dispatch upto COUNT tasks together\n" +" -P Print out DSQ content to trace_pipe every second, use with -b\n" ++" -H Boost nice -20 tasks in SHARED_DSQ, use with -b\n" +" -d PID Disallow a process from switching into SCHED_EXT (-1 for self)\n" +" -D LEN Set scx_exit_info.dump buffer length\n" +" -S Suppress qmap-specific debug dump\n" @@ -11180,7 +13911,7 @@ index 000000000000..c9ca30d62b2b + + skel = SCX_OPS_OPEN(qmap_ops, scx_qmap); + -+ while ((opt = getopt(argc, argv, "s:e:t:T:l:b:Pd:D:Spvh")) != -1) { ++ while ((opt = getopt(argc, argv, "s:e:t:T:l:b:PHd:D:Spvh")) != -1) { + switch (opt) { + case 's': + skel->rodata->slice_ns = strtoull(optarg, NULL, 0) * 1000; @@ -11203,6 +13934,9 @@ index 000000000000..c9ca30d62b2b + case 'P': + skel->rodata->print_shared_dsq = true; + break; ++ case 'H': ++ skel->rodata->highpri_boosting = true; ++ break; + case 'd': + skel->rodata->disallow_tgid = strtol(optarg, NULL, 0); + if (skel->rodata->disallow_tgid < 0) @@ -11238,6 +13972,11 @@ index 000000000000..c9ca30d62b2b + skel->bss->nr_reenqueued, skel->bss->nr_dequeued, + skel->bss->nr_core_sched_execed, + skel->bss->nr_ddsp_from_enq); ++ printf(" exp_local=%"PRIu64" exp_remote=%"PRIu64" exp_timer=%"PRIu64" exp_lost=%"PRIu64"\n", ++ skel->bss->nr_expedited_local, ++ skel->bss->nr_expedited_remote, ++ skel->bss->nr_expedited_from_timer, ++ skel->bss->nr_expedited_lost); + if (__COMPAT_has_ksym("scx_bpf_cpuperf_cur")) + printf("cpuperf: cur min/avg/max=%u/%u/%u target min/avg/max=%u/%u/%u\n", + skel->bss->cpuperf_min, @@ -11261,10 +14000,10 @@ index 000000000000..c9ca30d62b2b +} diff --git a/tools/sched_ext/scx_show_state.py b/tools/sched_ext/scx_show_state.py new file mode 100644 -index 000000000000..d457d2a74e1e +index 000000000000..8bc626ede1c4 --- /dev/null +++ b/tools/sched_ext/scx_show_state.py -@@ -0,0 +1,39 @@ +@@ -0,0 +1,40 @@ +#!/usr/bin/env drgn +# +# Copyright (C) 2024 Tejun Heo <tj@kernel.org> @@ -11304,6 +14043,7 @@ index 000000000000..d457d2a74e1e +print(f'enable_state : {ops_state_str(enable_state)} ({enable_state})') +print(f'bypass_depth : {read_atomic("scx_ops_bypass_depth")}') +print(f'nr_rejected : {read_atomic("scx_nr_rejected")}') ++print(f'enable_seq : {read_atomic("scx_enable_seq")}') diff --git a/tools/sched_ext/scx_simple.bpf.c b/tools/sched_ext/scx_simple.bpf.c new file mode 100644 index 000000000000..ed7e8d535fc5 @@ -13191,10 +15931,10 @@ index 000000000000..97d45f1e5597 +REGISTER_SCX_TEST(&init_enable_count) diff --git a/tools/testing/selftests/sched_ext/maximal.bpf.c b/tools/testing/selftests/sched_ext/maximal.bpf.c new file mode 100644 -index 000000000000..44612fdaf399 +index 000000000000..00bfa9cb95d3 --- /dev/null +++ b/tools/testing/selftests/sched_ext/maximal.bpf.c -@@ -0,0 +1,132 @@ +@@ -0,0 +1,164 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * A scheduler with every callback defined. @@ -13292,6 +16032,32 @@ index 000000000000..44612fdaf399 +void BPF_STRUCT_OPS(maximal_disable, struct task_struct *p) +{} + ++s32 BPF_STRUCT_OPS(maximal_cgroup_init, struct cgroup *cgrp, ++ struct scx_cgroup_init_args *args) ++{ ++ return 0; ++} ++ ++void BPF_STRUCT_OPS(maximal_cgroup_exit, struct cgroup *cgrp) ++{} ++ ++s32 BPF_STRUCT_OPS(maximal_cgroup_prep_move, struct task_struct *p, ++ struct cgroup *from, struct cgroup *to) ++{ ++ return 0; ++} ++ ++void BPF_STRUCT_OPS(maximal_cgroup_move, struct task_struct *p, ++ struct cgroup *from, struct cgroup *to) ++{} ++ ++void BPF_STRUCT_OPS(maximal_cgroup_cancel_move, struct task_struct *p, ++ struct cgroup *from, struct cgroup *to) ++{} ++ ++void BPF_STRUCT_OPS(maximal_cgroup_set_weight, struct cgroup *cgrp, u32 weight) ++{} ++ +s32 BPF_STRUCT_OPS_SLEEPABLE(maximal_init) +{ + return 0; @@ -13323,6 +16089,12 @@ index 000000000000..44612fdaf399 + .enable = maximal_enable, + .exit_task = maximal_exit_task, + .disable = maximal_disable, ++ .cgroup_init = maximal_cgroup_init, ++ .cgroup_exit = maximal_cgroup_exit, ++ .cgroup_prep_move = maximal_cgroup_prep_move, ++ .cgroup_move = maximal_cgroup_move, ++ .cgroup_cancel_move = maximal_cgroup_cancel_move, ++ .cgroup_set_weight = maximal_cgroup_set_weight, + .init = maximal_init, + .exit = maximal_exit, + .name = "maximal", @@ -15130,3 +17902,6 @@ index 000000000000..bc13dfec1267 +int file_write_long(const char *path, long val); + +#endif // __SCX_TEST_H__ +-- +2.47.0.rc0 + diff --git a/SOURCES/steam-deck.patch b/SOURCES/steam-deck.patch index fb06952..03946df 100644 --- a/SOURCES/steam-deck.patch +++ b/SOURCES/steam-deck.patch @@ -225,10 +225,10 @@ diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile index 11d076cad8a2..d03c1e1d339f 100644 --- a/drivers/hwmon/Makefile +++ b/drivers/hwmon/Makefile -@@ -200,6 +200,7 @@ - obj-$(CONFIG_SENSORS_SMSC47M1) += smsc47m1.o +@@ -207,6 +207,7 @@ obj-$(CONFIG_SENSORS_SMSC47M192)+= smsc47m192.o obj-$(CONFIG_SENSORS_SPARX5) += sparx5-temp.o + obj-$(CONFIG_SENSORS_SPD5118) += spd5118.o +obj-$(CONFIG_SENSORS_STEAMDECK) += steamdeck-hwmon.o obj-$(CONFIG_SENSORS_STTS751) += stts751.o obj-$(CONFIG_SENSORS_SURFACE_FAN)+= surface_fan.o diff --git a/SOURCES/tkg-misc-additions.patch b/SOURCES/tkg-misc-additions.patch index 3056a1c..c6065b8 100644 --- a/SOURCES/tkg-misc-additions.patch +++ b/SOURCES/tkg-misc-additions.patch @@ -1,68 +1,3 @@ -From e5e77ad2223f662e1615266d8ef39a8db7e65a70 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Felix=20H=C3=A4dicke?= <felixhaedicke@web.de> -Date: Thu, 19 Nov 2020 09:22:32 +0100 -Subject: HID: quirks: Add Apple Magic Trackpad 2 to hid_have_special_driver - list -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The Apple Magic Trackpad 2 is handled by the magicmouse driver. And -there were severe stability issues when both drivers (hid-generic and -hid-magicmouse) were loaded for this device. - -Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=210241 - -Signed-off-by: Felix Hädicke <felixhaedicke@web.de> ---- - drivers/hid/hid-quirks.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/drivers/hid/hid-quirks.c b/drivers/hid/hid-quirks.c -index bf7ecab5d9e5..142e9dae2837 100644 ---- a/drivers/hid/hid-quirks.c -+++ b/drivers/hid/hid-quirks.c -@@ -478,6 +478,8 @@ static const struct hid_device_id hid_have_special_driver[] = { - #if IS_ENABLED(CONFIG_HID_MAGICMOUSE) - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICMOUSE) }, - { HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD) }, -+ { HID_BLUETOOTH_DEVICE(BT_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD2) }, -+ { HID_USB_DEVICE(USB_VENDOR_ID_APPLE, USB_DEVICE_ID_APPLE_MAGICTRACKPAD2) }, - #endif - #if IS_ENABLED(CONFIG_HID_MAYFLASH) - { HID_USB_DEVICE(USB_VENDOR_ID_DRAGONRISE, USB_DEVICE_ID_DRAGONRISE_PS3) }, --- -cgit v1.2.3-1-gf6bb5 - -From f7f49141a5dbe9c99d78196b58c44307fb2e6be3 Mon Sep 17 00:00:00 2001 -From: Tk-Glitch <ti3nou@gmail.com> -Date: Wed, 3 Feb 2021 11:20:12 +0200 -Subject: Revert "cpufreq: Avoid configuring old governors as default with intel_pstate" - -This is an undesirable behavior for us since our aggressive ondemand performs -better than schedutil for gaming when using intel_pstate in passive mode. -Also it interferes with the option to select the desired default governor we have. - -diff --git a/drivers/cpufreq/Kconfig b/drivers/cpufreq/Kconfig -index 2c7171e0b0010..85de313ddec29 100644 ---- a/drivers/cpufreq/Kconfig -+++ b/drivers/cpufreq/Kconfig -@@ -71,7 +71,6 @@ config CPU_FREQ_DEFAULT_GOV_USERSPACE - - config CPU_FREQ_DEFAULT_GOV_ONDEMAND - bool "ondemand" -- depends on !(X86_INTEL_PSTATE && SMP) - select CPU_FREQ_GOV_ONDEMAND - select CPU_FREQ_GOV_PERFORMANCE - help -@@ -83,7 +84,6 @@ config CPU_FREQ_DEFAULT_GOV_ONDEMAND - - config CPU_FREQ_DEFAULT_GOV_CONSERVATIVE - bool "conservative" -- depends on !(X86_INTEL_PSTATE && SMP) - select CPU_FREQ_GOV_CONSERVATIVE - select CPU_FREQ_GOV_PERFORMANCE - help From 3a88b77d3cb9f9cd8a8aee052ab479b73aeb2e80 Mon Sep 17 00:00:00 2001 From: "Jan Alexander Steffens (heftig)" <heftig@archlinux.org> @@ -98,125 +33,6 @@ index f4b210ab061291..837d0dbb28ea08 100644 help This value can be used to select the number of bits to use to -From 299b81f3e619aea3ceda77d7c42842a496b34a53 Mon Sep 17 00:00:00 2001 -From: Peter Jung <admin@ptr1337.dev> -Date: Thu, 21 Mar 2024 19:00:50 +0100 -Subject: [PATCH] cachy: move AMD_PRIVATE_COLOR to Kconfig - -Co-authored-by: PedroHLC <root@pedrohlc.com> -Signed-off-by: Peter Jung <admin@ptr1337.dev> ---- - drivers/gpu/drm/amd/display/Kconfig | 6 ++++++ - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 +- - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 +++--- - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- - 5 files changed, 14 insertions(+), 8 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig -index 901d1961b73927..05c49141f5802f 100644 ---- a/drivers/gpu/drm/amd/display/Kconfig -+++ b/drivers/gpu/drm/amd/display/Kconfig -@@ -51,4 +51,10 @@ config DRM_AMD_SECURE_DISPLAY - This option enables the calculation of crc of specific region via - debugfs. Cooperate with specific DMCU FW. - -+config AMD_PRIVATE_COLOR -+ bool "Enable KMS color management by AMD for AMD" -+ default n -+ help -+ This option extends the KMS color management API with AMD driver-specific properties to enhance the color management support on AMD Steam Deck. -+ - endmenu -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -index 59d2eee72a3297..0a4e75de95c257 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -@@ -4078,7 +4078,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) - return r; - } - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - if (amdgpu_dm_create_color_properties(adev)) { - dc_state_release(state->context); - kfree(state); -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c -index c87b64e464ed5c..6fe07243adc3d5 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c -@@ -97,7 +97,7 @@ static inline struct fixed31_32 amdgpu_dm_fixpt_from_s3132(__u64 x) - return val; - } - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - /* Pre-defined Transfer Functions (TF) - * - * AMD driver supports pre-defined mathematical functions for transferring -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c -index 6e715ef3a5566e..11c7199ec3b348 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c -@@ -290,7 +290,7 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) - } - #endif - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - /** - * dm_crtc_additional_color_mgmt - enable additional color properties - * @crtc: DRM CRTC -@@ -372,7 +372,7 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { - #if defined(CONFIG_DEBUG_FS) - .late_register = amdgpu_dm_crtc_late_register, - #endif --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, - .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, - #endif -@@ -551,7 +551,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, - - drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - dm_crtc_additional_color_mgmt(&acrtc->base); - #endif - return 0; -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -index 8a4c40b4c27e4f..779880c6457553 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -@@ -1468,7 +1468,7 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, - drm_atomic_helper_plane_destroy_state(plane, state); - } - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - static void - dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, - struct drm_plane *plane) -@@ -1659,7 +1659,7 @@ static const struct drm_plane_funcs dm_plane_funcs = { - .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, - .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, - .format_mod_supported = amdgpu_dm_plane_format_mod_supported, --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - .atomic_set_property = dm_atomic_plane_set_property, - .atomic_get_property = dm_atomic_plane_get_property, - #endif -@@ -1742,7 +1742,7 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - - drm_plane_helper_add(plane, &dm_plane_helper_funcs); - --#ifdef AMD_PRIVATE_COLOR -+#ifdef CONFIG_AMD_PRIVATE_COLOR - dm_atomic_plane_attach_color_mgmt_properties(dm, plane); - #endif - /* Create (reset) the plane state */ - From f1807682de0edbff6c1e46b19642a517d2e15c57 Mon Sep 17 00:00:00 2001 From: Tk-Glitch <ti3nou@gmail.com> Date: Sat, 13 Apr 2024 18:25:35 +0530 @@ -235,6 +51,222 @@ index a54663f2e2ab9f..7ffad3eb0a0150 100644 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { case IP_VERSION(13, 0, 2): - case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): case IP_VERSION(11, 0, 7): case IP_VERSION(11, 0, 11): - case IP_VERSION(11, 0, 12): +From 5863404999cd2cada56e454b1b3a33c43b3c0806 Mon Sep 17 00:00:00 2001 +From: Thomas Gleixner <tglx@linutronix.de> +Date: Sun, 28 Jul 2024 13:06:10 +0200 +Subject: [PATCH] x86/apic: Remove logical destination mode for 64-bit + +Logical destination mode of the local APIC is used for systems with up to +8 CPUs. It has an advantage over physical destination mode as it allows to +target multiple CPUs at once with IPIs. + +That advantage was definitely worth it when systems with up to 8 CPUs +were state of the art for servers and workstations, but that's history. + +Aside of that there are systems which fail to work with logical destination +mode as the ACPI/DMI quirks show and there are AMD Zen1 systems out there +which fail when interrupt remapping is enabled. The latter can be cured by +firmware updates, but not all OEMs distribute the required changes. + +Physical destination mode is guaranteed to work because it is the only way +to get a CPU up and running via the INIT/INIT/STARTUP sequence. + +As the number of CPUs keeps increasing, logical destination mode becomes a +less used code path so there is no real good reason to keep it around. + +Therefore remove logical destination mode support for 64-bit and default to +physical destination mode. + +Signed-off-by: Thomas Gleixner <tglx@linutronix.de> +Cherry-picked-for: https://gitlab.archlinux.org/archlinux/packaging/packages/linux/-/issues/64 +--- + arch/x86/include/asm/apic.h | 8 -- + arch/x86/kernel/apic/apic_flat_64.c | 119 ++-------------------------- + 2 files changed, 7 insertions(+), 120 deletions(-) + +diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h +index 9327eb00e96d09..be2045a18e69b9 100644 +--- a/arch/x86/include/asm/apic.h ++++ b/arch/x86/include/asm/apic.h +@@ -345,20 +345,12 @@ extern struct apic *apic; + * APIC drivers are probed based on how they are listed in the .apicdrivers + * section. So the order is important and enforced by the ordering + * of different apic driver files in the Makefile. +- * +- * For the files having two apic drivers, we use apic_drivers() +- * to enforce the order with in them. + */ + #define apic_driver(sym) \ + static const struct apic *__apicdrivers_##sym __used \ + __aligned(sizeof(struct apic *)) \ + __section(".apicdrivers") = { &sym } + +-#define apic_drivers(sym1, sym2) \ +- static struct apic *__apicdrivers_##sym1##sym2[2] __used \ +- __aligned(sizeof(struct apic *)) \ +- __section(".apicdrivers") = { &sym1, &sym2 } +- + extern struct apic *__apicdrivers[], *__apicdrivers_end[]; + + /* +diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c +index f37ad3392fec91..e0308d8c4e6c27 100644 +--- a/arch/x86/kernel/apic/apic_flat_64.c ++++ b/arch/x86/kernel/apic/apic_flat_64.c +@@ -8,129 +8,25 @@ + * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and + * James Cleverdon. + */ +-#include <linux/cpumask.h> + #include <linux/export.h> +-#include <linux/acpi.h> + +-#include <asm/jailhouse_para.h> + #include <asm/apic.h> + + #include "local.h" + +-static struct apic apic_physflat; +-static struct apic apic_flat; +- +-struct apic *apic __ro_after_init = &apic_flat; +-EXPORT_SYMBOL_GPL(apic); +- +-static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) +-{ +- return 1; +-} +- +-static void _flat_send_IPI_mask(unsigned long mask, int vector) +-{ +- unsigned long flags; +- +- local_irq_save(flags); +- __default_send_IPI_dest_field(mask, vector, APIC_DEST_LOGICAL); +- local_irq_restore(flags); +-} +- +-static void flat_send_IPI_mask(const struct cpumask *cpumask, int vector) +-{ +- unsigned long mask = cpumask_bits(cpumask)[0]; +- +- _flat_send_IPI_mask(mask, vector); +-} +- +-static void +-flat_send_IPI_mask_allbutself(const struct cpumask *cpumask, int vector) +-{ +- unsigned long mask = cpumask_bits(cpumask)[0]; +- int cpu = smp_processor_id(); +- +- if (cpu < BITS_PER_LONG) +- __clear_bit(cpu, &mask); +- +- _flat_send_IPI_mask(mask, vector); +-} +- +-static u32 flat_get_apic_id(u32 x) ++static u32 physflat_get_apic_id(u32 x) + { + return (x >> 24) & 0xFF; + } + +-static int flat_probe(void) ++static int physflat_probe(void) + { + return 1; + } + +-static struct apic apic_flat __ro_after_init = { +- .name = "flat", +- .probe = flat_probe, +- .acpi_madt_oem_check = flat_acpi_madt_oem_check, +- +- .dest_mode_logical = true, +- +- .disable_esr = 0, +- +- .init_apic_ldr = default_init_apic_ldr, +- .cpu_present_to_apicid = default_cpu_present_to_apicid, +- +- .max_apic_id = 0xFE, +- .get_apic_id = flat_get_apic_id, +- +- .calc_dest_apicid = apic_flat_calc_apicid, +- +- .send_IPI = default_send_IPI_single, +- .send_IPI_mask = flat_send_IPI_mask, +- .send_IPI_mask_allbutself = flat_send_IPI_mask_allbutself, +- .send_IPI_allbutself = default_send_IPI_allbutself, +- .send_IPI_all = default_send_IPI_all, +- .send_IPI_self = default_send_IPI_self, +- .nmi_to_offline_cpu = true, +- +- .read = native_apic_mem_read, +- .write = native_apic_mem_write, +- .eoi = native_apic_mem_eoi, +- .icr_read = native_apic_icr_read, +- .icr_write = native_apic_icr_write, +- .wait_icr_idle = apic_mem_wait_icr_idle, +- .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, +-}; +- +-/* +- * Physflat mode is used when there are more than 8 CPUs on a system. +- * We cannot use logical delivery in this case because the mask +- * overflows, so use physical mode. +- */ + static int physflat_acpi_madt_oem_check(char *oem_id, char *oem_table_id) + { +-#ifdef CONFIG_ACPI +- /* +- * Quirk: some x86_64 machines can only use physical APIC mode +- * regardless of how many processors are present (x86_64 ES7000 +- * is an example). +- */ +- if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID && +- (acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL)) { +- printk(KERN_DEBUG "system APIC only can use physical flat"); +- return 1; +- } +- +- if (!strncmp(oem_id, "IBM", 3) && !strncmp(oem_table_id, "EXA", 3)) { +- printk(KERN_DEBUG "IBM Summit detected, will use apic physical"); +- return 1; +- } +-#endif +- +- return 0; +-} +- +-static int physflat_probe(void) +-{ +- return apic == &apic_physflat || num_possible_cpus() > 8 || jailhouse_paravirt(); ++ return 1; + } + + static struct apic apic_physflat __ro_after_init = { +@@ -146,7 +42,7 @@ static struct apic apic_physflat __ro_after_init = { + .cpu_present_to_apicid = default_cpu_present_to_apicid, + + .max_apic_id = 0xFE, +- .get_apic_id = flat_get_apic_id, ++ .get_apic_id = physflat_get_apic_id, + + .calc_dest_apicid = apic_default_calc_apicid, + +@@ -166,8 +62,7 @@ static struct apic apic_physflat __ro_after_init = { + .wait_icr_idle = apic_mem_wait_icr_idle, + .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout, + }; ++apic_driver(apic_physflat); + +-/* +- * We need to check for physflat first, so this order is important. +- */ +-apic_drivers(apic_physflat, apic_flat); ++struct apic *apic __ro_after_init = &apic_physflat; ++EXPORT_SYMBOL_GPL(apic); diff --git a/SOURCES/tkg-unprivileged-CLONE_NEWUSER.patch b/SOURCES/tkg-unprivileged-CLONE_NEWUSER.patch deleted file mode 100644 index 4d8146c..0000000 --- a/SOURCES/tkg-unprivileged-CLONE_NEWUSER.patch +++ /dev/null @@ -1,151 +0,0 @@ -From d50977b164e708bf523a35ef53315355528c3ca6 Mon Sep 17 00:00:00 2001 -From: "Jan Alexander Steffens (heftig)" <jan.steffens@gmail.com> -Date: Mon, 16 Sep 2019 04:53:20 +0200 -Subject: [PATCH] ZEN: Add sysctl and CONFIG to disallow unprivileged - CLONE_NEWUSER - -Our default behavior continues to match the vanilla kernel. ---- - include/linux/user_namespace.h | 4 ++++ - init/Kconfig | 16 ++++++++++++++++ - kernel/fork.c | 14 ++++++++++++++ - kernel/sysctl.c | 12 ++++++++++++ - kernel/user_namespace.c | 7 +++++++ - 5 files changed, 53 insertions(+) - -diff --git a/include/linux/user_namespace.h b/include/linux/user_namespace.h -index 45f09bec02c485..87b20e2ee27445 100644 ---- a/include/linux/user_namespace.h -+++ b/include/linux/user_namespace.h -@@ -148,6 +148,8 @@ static inline void set_userns_rlimit_max(struct user_namespace *ns, - - #ifdef CONFIG_USER_NS - -+extern int unprivileged_userns_clone; -+ - static inline struct user_namespace *get_user_ns(struct user_namespace *ns) - { - if (ns) -@@ -181,6 +183,8 @@ extern bool current_in_userns(const struct user_namespace *target_ns); - struct ns_common *ns_get_owner(struct ns_common *ns); - #else - -+#define unprivileged_userns_clone 0 -+ - static inline struct user_namespace *get_user_ns(struct user_namespace *ns) - { - return &init_user_ns; -diff --git a/init/Kconfig b/init/Kconfig -index 94125d3b6893c7..9f7139b536f638 100644 ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -1247,6 +1247,22 @@ config USER_NS - - If unsure, say N. - -+config USER_NS_UNPRIVILEGED -+ bool "Allow unprivileged users to create namespaces" -+ default y -+ depends on USER_NS -+ help -+ When disabled, unprivileged users will not be able to create -+ new namespaces. Allowing users to create their own namespaces -+ has been part of several recent local privilege escalation -+ exploits, so if you need user namespaces but are -+ paranoid^Wsecurity-conscious you want to disable this. -+ -+ This setting can be overridden at runtime via the -+ kernel.unprivileged_userns_clone sysctl. -+ -+ If unsure, say Y. -+ - config PID_NS - bool "PID Namespaces" - default y -diff --git a/kernel/fork.c b/kernel/fork.c -index 08969f5aa38d59..ff601cb7a1fae0 100644 ---- a/kernel/fork.c -+++ b/kernel/fork.c -@@ -104,6 +104,10 @@ - #include <uapi/linux/pidfd.h> - #include <linux/pidfs.h> - -+#ifdef CONFIG_USER_NS -+#include <linux/user_namespace.h> -+#endif -+ - #include <asm/pgalloc.h> - #include <linux/uaccess.h> - #include <asm/mmu_context.h> -@@ -2008,6 +2012,10 @@ static __latent_entropy struct task_struct *copy_process( - if ((clone_flags & (CLONE_NEWUSER|CLONE_FS)) == (CLONE_NEWUSER|CLONE_FS)) - return ERR_PTR(-EINVAL); - -+ if ((clone_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) -+ if (!capable(CAP_SYS_ADMIN)) -+ return ERR_PTR(-EPERM); -+ - /* - * Thread groups must share signals as well, and detached threads - * can only be started up within the thread group. -@@ -3166,6 +3174,12 @@ int ksys_unshare(unsigned long unshare_flags) - if (unshare_flags & CLONE_NEWNS) - unshare_flags |= CLONE_FS; - -+ if ((unshare_flags & CLONE_NEWUSER) && !unprivileged_userns_clone) { -+ err = -EPERM; -+ if (!capable(CAP_SYS_ADMIN)) -+ goto bad_unshare_out; -+ } -+ - err = check_unshare_flags(unshare_flags); - if (err) - goto bad_unshare_out; -diff --git a/kernel/sysctl.c b/kernel/sysctl.c -index c6d9dec11b749d..9a4514ad481b21 100644 ---- a/kernel/sysctl.c -+++ b/kernel/sysctl.c -@@ -81,6 +81,9 @@ - #ifdef CONFIG_RT_MUTEXES - #include <linux/rtmutex.h> - #endif -+#ifdef CONFIG_USER_NS -+#include <linux/user_namespace.h> -+#endif - - /* shared constants to be used in various sysctls */ - const int sysctl_vals[] = { 0, 1, 2, 3, 4, 100, 200, 1000, 3000, INT_MAX, 65535, -1 }; -@@ -1659,6 +1662,15 @@ static struct ctl_table kern_table[] = { - .mode = 0644, - .proc_handler = proc_dointvec, - }, -+#ifdef CONFIG_USER_NS -+ { -+ .procname = "unprivileged_userns_clone", -+ .data = &unprivileged_userns_clone, -+ .maxlen = sizeof(int), -+ .mode = 0644, -+ .proc_handler = proc_dointvec, -+ }, -+#endif - #ifdef CONFIG_PROC_SYSCTL - { - .procname = "tainted", -diff --git a/kernel/user_namespace.c b/kernel/user_namespace.c -index 54211dbd516c57..16ca0c1516298d 100644 ---- a/kernel/user_namespace.c -+++ b/kernel/user_namespace.c -@@ -22,6 +22,13 @@ - #include <linux/bsearch.h> - #include <linux/sort.h> - -+/* sysctl */ -+#ifdef CONFIG_USER_NS_UNPRIVILEGED -+int unprivileged_userns_clone = 1; -+#else -+int unprivileged_userns_clone; -+#endif -+ - static struct kmem_cache *user_ns_cachep __ro_after_init; - static DEFINE_MUTEX(userns_state_mutex); - diff --git a/SOURCES/tkg.patch b/SOURCES/tkg.patch deleted file mode 100644 index f29c409..0000000 --- a/SOURCES/tkg.patch +++ /dev/null @@ -1,428 +0,0 @@ -From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 -From: Jan200101 <sentrycraft123@gmail.com> -Date: Tue, 6 Aug 2024 19:20:54 +0200 -Subject: [PATCH] tkg glitched base - -Signed-off-by: Jan200101 <sentrycraft123@gmail.com> ---- - .../admin-guide/kernel-parameters.txt | 3 ++ - Makefile | 3 ++ - block/elevator.c | 6 ++-- - drivers/cpufreq/intel_pstate.c | 2 ++ - drivers/infiniband/core/addr.c | 1 + - drivers/input/evdev.c | 19 ++++++----- - drivers/md/dm-crypt.c | 5 +++ - fs/dcache.c | 2 +- - include/linux/mm.h | 3 +- - include/linux/pageblock-flags.h | 2 +- - include/linux/pagemap.h | 2 +- - init/Kconfig | 32 +++++++++++++++++++ - init/Makefile | 2 +- - kernel/sched/rt.c | 4 +-- - mm/huge_memory.c | 4 +++ - mm/page_alloc.c | 9 +++--- - net/ipv4/Kconfig | 4 +++ - net/sched/Kconfig | 4 +++ - scripts/setlocalversion | 14 ++++---- - 19 files changed, 91 insertions(+), 30 deletions(-) - -diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt -index 2569e7f19b47..5b79a61afd6d 100644 ---- a/Documentation/admin-guide/kernel-parameters.txt -+++ b/Documentation/admin-guide/kernel-parameters.txt -@@ -355,6 +355,9 @@ - disable - Do not enable amd_pstate as the default - scaling driver for the supported processors -+ enable -+ Enable intel_pstate in-case "disable" was passed -+ previously in the kernel boot parameters - passive - Use amd_pstate with passive mode as a scaling driver. - In this mode autonomous selection is disabled. -diff --git a/Makefile b/Makefile -index c0af6d8aeb05..94d76f300914 100644 ---- a/Makefile -+++ b/Makefile -@@ -999,6 +999,9 @@ KBUILD_CFLAGS += $(call cc-option, -fstrict-flex-arrays=3) - KBUILD_CFLAGS-$(CONFIG_CC_NO_STRINGOP_OVERFLOW) += $(call cc-option, -Wno-stringop-overflow) - KBUILD_CFLAGS-$(CONFIG_CC_STRINGOP_OVERFLOW) += $(call cc-option, -Wstringop-overflow) - -+# disable GCC vectorization on trees -+KBUILD_CFLAGS += $(call cc-option, -fno-tree-vectorize) -+ - # disable invalid "can't wrap" optimizations for signed / pointers - KBUILD_CFLAGS += -fno-strict-overflow - -diff --git a/block/elevator.c b/block/elevator.c -index f64ebd726e58..73227b97162b 100644 ---- a/block/elevator.c -+++ b/block/elevator.c -@@ -557,8 +557,8 @@ static inline bool elv_support_iosched(struct request_queue *q) - } - - /* -- * For single queue devices, default to using mq-deadline. If we have multiple -- * queues or mq-deadline is not available, default to "none". -+ * For single queue devices, default to using bfq. If we have multiple -+ * queues or bfq is not available, default to "none". - */ - static struct elevator_type *elevator_get_default(struct request_queue *q) - { -@@ -569,7 +569,7 @@ static struct elevator_type *elevator_get_default(struct request_queue *q) - !blk_mq_is_shared_tags(q->tag_set->flags)) - return NULL; - -- return elevator_find_get(q, "mq-deadline"); -+ return elevator_find_get(q, "bfq"); - } - - /* -diff --git a/drivers/cpufreq/intel_pstate.c b/drivers/cpufreq/intel_pstate.c -index c31914a9876f..d6ed90b3c930 100644 ---- a/drivers/cpufreq/intel_pstate.c -+++ b/drivers/cpufreq/intel_pstate.c -@@ -3558,6 +3558,8 @@ static int __init intel_pstate_setup(char *str) - if (!strcmp(str, "no_hwp")) - no_hwp = 1; - -+ if (!strcmp(str, "enable")) -+ no_load = 0; - if (!strcmp(str, "force")) - force_load = 1; - if (!strcmp(str, "hwp_only")) -diff --git a/drivers/infiniband/core/addr.c b/drivers/infiniband/core/addr.c -index be0743dac3ff..358eb15e1d69 100644 ---- a/drivers/infiniband/core/addr.c -+++ b/drivers/infiniband/core/addr.c -@@ -814,6 +814,7 @@ int rdma_addr_find_l2_eth_by_grh(const union ib_gid *sgid, - union { - struct sockaddr_in _sockaddr_in; - struct sockaddr_in6 _sockaddr_in6; -+ struct sockaddr_ib _sockaddr_ib; - } sgid_addr, dgid_addr; - int ret; - -diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c -index 51e0c4954600..35c3ad741870 100644 ---- a/drivers/input/evdev.c -+++ b/drivers/input/evdev.c -@@ -46,6 +46,7 @@ struct evdev_client { - struct fasync_struct *fasync; - struct evdev *evdev; - struct list_head node; -+ struct rcu_head rcu; - enum input_clock_type clk_type; - bool revoked; - unsigned long *evmasks[EV_CNT]; -@@ -377,13 +378,22 @@ static void evdev_attach_client(struct evdev *evdev, - spin_unlock(&evdev->client_lock); - } - -+static void evdev_reclaim_client(struct rcu_head *rp) -+{ -+ struct evdev_client *client = container_of(rp, struct evdev_client, rcu); -+ unsigned int i; -+ for (i = 0; i < EV_CNT; ++i) -+ bitmap_free(client->evmasks[i]); -+ kvfree(client); -+} -+ - static void evdev_detach_client(struct evdev *evdev, - struct evdev_client *client) - { - spin_lock(&evdev->client_lock); - list_del_rcu(&client->node); - spin_unlock(&evdev->client_lock); -- synchronize_rcu(); -+ call_rcu(&client->rcu, evdev_reclaim_client); - } - - static int evdev_open_device(struct evdev *evdev) -@@ -436,7 +446,6 @@ static int evdev_release(struct inode *inode, struct file *file) - { - struct evdev_client *client = file->private_data; - struct evdev *evdev = client->evdev; -- unsigned int i; - - mutex_lock(&evdev->mutex); - -@@ -448,11 +457,6 @@ static int evdev_release(struct inode *inode, struct file *file) - - evdev_detach_client(evdev, client); - -- for (i = 0; i < EV_CNT; ++i) -- bitmap_free(client->evmasks[i]); -- -- kvfree(client); -- - evdev_close_device(evdev); - - return 0; -@@ -495,7 +499,6 @@ static int evdev_open(struct inode *inode, struct file *file) - - err_free_client: - evdev_detach_client(evdev, client); -- kvfree(client); - return error; - } - -diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c -index 1b7a97cc3779..bed9d9588b87 100644 ---- a/drivers/md/dm-crypt.c -+++ b/drivers/md/dm-crypt.c -@@ -3284,6 +3284,11 @@ static int crypt_ctr(struct dm_target *ti, unsigned int argc, char **argv) - goto bad; - } - -+#ifdef CONFIG_ZENIFY -+ set_bit(DM_CRYPT_NO_READ_WORKQUEUE, &cc->flags); -+ set_bit(DM_CRYPT_NO_WRITE_WORKQUEUE, &cc->flags); -+#endif -+ - ret = crypt_ctr_cipher(ti, argv[0], argv[1]); - if (ret < 0) - goto bad; -diff --git a/fs/dcache.c b/fs/dcache.c -index 4c144519aa70..fb0f9a1368c8 100644 ---- a/fs/dcache.c -+++ b/fs/dcache.c -@@ -71,7 +71,7 @@ - * If no ancestor relationship: - * arbitrary, since it's serialized on rename_lock - */ --int sysctl_vfs_cache_pressure __read_mostly = 100; -+int sysctl_vfs_cache_pressure __read_mostly = 50; - EXPORT_SYMBOL_GPL(sysctl_vfs_cache_pressure); - - __cacheline_aligned_in_smp DEFINE_SEQLOCK(rename_lock); -diff --git a/include/linux/mm.h b/include/linux/mm.h -index b58bad248eef..dbae141dc3ce 100644 ---- a/include/linux/mm.h -+++ b/include/linux/mm.h -@@ -192,8 +192,7 @@ static inline void __mm_zero_struct_page(struct page *page) - * not a hard limit any more. Although some userspace tools can be surprised by - * that. - */ --#define MAPCOUNT_ELF_CORE_MARGIN (5) --#define DEFAULT_MAX_MAP_COUNT (USHRT_MAX - MAPCOUNT_ELF_CORE_MARGIN) -+#define DEFAULT_MAX_MAP_COUNT (16777216) - - extern int sysctl_max_map_count; - -diff --git a/include/linux/pageblock-flags.h b/include/linux/pageblock-flags.h -index 547e82cdc89a..67a999944cdb 100644 ---- a/include/linux/pageblock-flags.h -+++ b/include/linux/pageblock-flags.h -@@ -52,7 +52,7 @@ extern unsigned int pageblock_order; - #else /* CONFIG_TRANSPARENT_HUGEPAGE */ - - /* If huge pages are not used, group by MAX_ORDER_NR_PAGES */ --#define pageblock_order MAX_PAGE_ORDER -+#define pageblock_order PAGE_ALLOC_COSTLY_ORDER - - #endif /* CONFIG_HUGETLB_PAGE */ - -diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h -index a0a026d2d244..4d2e7d8512d1 100644 ---- a/include/linux/pagemap.h -+++ b/include/linux/pagemap.h -@@ -1281,7 +1281,7 @@ struct readahead_control { - ._index = i, \ - } - --#define VM_READAHEAD_PAGES (SZ_128K / PAGE_SIZE) -+#define VM_READAHEAD_PAGES (SZ_2M / PAGE_SIZE) - - void page_cache_ra_unbounded(struct readahead_control *, - unsigned long nr_to_read, unsigned long lookahead_count); -diff --git a/init/Kconfig b/init/Kconfig -index febdea2afc3b..c8c6671c9549 100644 ---- a/init/Kconfig -+++ b/init/Kconfig -@@ -132,6 +132,38 @@ config THREAD_INFO_IN_TASK - - menu "General setup" - -+config ZENIFY -+ bool "A selection of patches from Zen/Liquorix kernel and additional tweaks for a better gaming experience" -+ default y -+ help -+ Tunes the kernel for responsiveness at the cost of throughput and power usage. -+ -+ --- Virtual Memory Subsystem --------------------------- -+ -+ Mem dirty before bg writeback..: 10 % -> 20 % -+ Mem dirty before sync writeback: 20 % -> 50 % -+ -+ --- Block Layer ---------------------------------------- -+ -+ Queue depth...............: 128 -> 512 -+ Default MQ scheduler......: mq-deadline -> bfq -+ -+ --- CFS CPU Scheduler ---------------------------------- -+ -+ Scheduling latency.............: 6 -> 3 ms -+ Minimal granularity............: 0.75 -> 0.3 ms -+ Wakeup granularity.............: 1 -> 0.5 ms -+ CPU migration cost.............: 0.5 -> 0.25 ms -+ Bandwidth slice size...........: 5 -> 3 ms -+ Ondemand fine upscaling limit..: 95 % -> 85 % -+ -+ --- MuQSS CPU Scheduler -------------------------------- -+ -+ Scheduling interval............: 6 -> 3 ms -+ ISO task max realtime use......: 70 % -> 25 % -+ Ondemand coarse upscaling limit: 80 % -> 45 % -+ Ondemand fine upscaling limit..: 95 % -> 45 % -+ - config BROKEN - bool - -diff --git a/init/Makefile b/init/Makefile -index ab71cedc5fd6..eafc4ef50ab5 100644 ---- a/init/Makefile -+++ b/init/Makefile -@@ -33,7 +33,7 @@ build-timestamp = $(or $(KBUILD_BUILD_TIMESTAMP), $(build-timestamp-auto)) - - # Maximum length of UTS_VERSION is 64 chars - filechk_uts_version = \ -- utsver=$$(echo '$(pound)'"$(build-version)" $(smp-flag-y) $(preempt-flag-y) "$(build-timestamp)" | cut -b -64); \ -+ utsver=$$(echo '$(pound)'"$(build-version)" $(smp-flag-y) $(preempt-flag-y) "TKG" "$(build-timestamp)" | cut -b -64); \ - echo '$(pound)'define UTS_VERSION \""$${utsver}"\" - - # -diff --git a/kernel/sched/rt.c b/kernel/sched/rt.c -index aa4c1c874fa4..cd58198e990f 100644 ---- a/kernel/sched/rt.c -+++ b/kernel/sched/rt.c -@@ -20,9 +20,9 @@ int sysctl_sched_rt_period = 1000000; - - /* - * part of the period that we allow rt tasks to run in us. -- * default: 0.95s -+ * XanMod default: 0.98s - */ --int sysctl_sched_rt_runtime = 950000; -+int sysctl_sched_rt_runtime = 980000; - - #ifdef CONFIG_SYSCTL - static int sysctl_sched_rr_timeslice = (MSEC_PER_SEC * RR_TIMESLICE) / HZ; -diff --git a/mm/huge_memory.c b/mm/huge_memory.c -index 374a0d54b08d..1d4efe9df1a6 100644 ---- a/mm/huge_memory.c -+++ b/mm/huge_memory.c -@@ -63,7 +63,11 @@ unsigned long transparent_hugepage_flags __read_mostly = - #ifdef CONFIG_TRANSPARENT_HUGEPAGE_MADVISE - (1<<TRANSPARENT_HUGEPAGE_REQ_MADV_FLAG)| - #endif -+#ifdef CONFIG_ZENIFY -+ (1<<TRANSPARENT_HUGEPAGE_DEFRAG_KSWAPD_OR_MADV_FLAG)| -+#else - (1<<TRANSPARENT_HUGEPAGE_DEFRAG_REQ_MADV_FLAG)| -+#endif - (1<<TRANSPARENT_HUGEPAGE_DEFRAG_KHUGEPAGED_FLAG)| - (1<<TRANSPARENT_HUGEPAGE_USE_ZERO_PAGE_FLAG); - -diff --git a/mm/page_alloc.c b/mm/page_alloc.c -index df2c442f1c47..d8d83c503419 100644 ---- a/mm/page_alloc.c -+++ b/mm/page_alloc.c -@@ -2228,16 +2228,17 @@ __rmqueue(struct zone *zone, unsigned int order, int migratetype, - } - - /* -- * Obtain a specified number of elements from the buddy allocator, all under -- * a single hold of the lock, for efficiency. Add them to the supplied list. -- * Returns the number of new pages which were placed at *list. -+ * Obtain a specified number of elements from the buddy allocator, and relax the -+ * zone lock when needed. Add them to the supplied list. Returns the number of -+ * new pages which were placed at *list. - */ - static int rmqueue_bulk(struct zone *zone, unsigned int order, - unsigned long count, struct list_head *list, - int migratetype, unsigned int alloc_flags) - { - unsigned long flags; -- int i; -+ const bool can_resched = !preempt_count() && !irqs_disabled(); -+ int i, allocated = 0, last_mod = 0; - - spin_lock_irqsave(&zone->lock, flags); - for (i = 0; i < count; ++i) { -diff --git a/net/ipv4/Kconfig b/net/ipv4/Kconfig -index 8e94ed7c56a0..c103bc45c900 100644 ---- a/net/ipv4/Kconfig -+++ b/net/ipv4/Kconfig -@@ -700,6 +700,9 @@ choice - config DEFAULT_VEGAS - bool "Vegas" if TCP_CONG_VEGAS=y - -+ config DEFAULT_YEAH -+ bool "YeAH" if TCP_CONG_YEAH=y -+ - config DEFAULT_VENO - bool "Veno" if TCP_CONG_VENO=y - -@@ -733,6 +736,7 @@ config DEFAULT_TCP_CONG - default "htcp" if DEFAULT_HTCP - default "hybla" if DEFAULT_HYBLA - default "vegas" if DEFAULT_VEGAS -+ default "yeah" if DEFAULT_YEAH - default "westwood" if DEFAULT_WESTWOOD - default "veno" if DEFAULT_VENO - default "reno" if DEFAULT_RENO -diff --git a/net/sched/Kconfig b/net/sched/Kconfig -index 8180d0c12fce..22c5a59d5058 100644 ---- a/net/sched/Kconfig -+++ b/net/sched/Kconfig -@@ -438,6 +438,9 @@ choice - config DEFAULT_SFQ - bool "Stochastic Fair Queue" if NET_SCH_SFQ - -+ config DEFAULT_CAKE -+ bool "Common Applications Kept Enhanced" if NET_SCH_CAKE -+ - config DEFAULT_PFIFO_FAST - bool "Priority FIFO Fast" - endchoice -@@ -449,6 +452,7 @@ config DEFAULT_NET_SCH - default "fq_codel" if DEFAULT_FQ_CODEL - default "fq_pie" if DEFAULT_FQ_PIE - default "sfq" if DEFAULT_SFQ -+ default "cake" if DEFAULT_CAKE - default "pfifo_fast" - endif - -diff --git a/scripts/setlocalversion b/scripts/setlocalversion -index 38b96c6797f4..e22768e0e875 100755 ---- a/scripts/setlocalversion -+++ b/scripts/setlocalversion -@@ -92,7 +92,7 @@ scm_version() - # If only the short version is requested, don't bother - # running further git commands - if $short; then -- echo "+" -+ #echo "+" - return - fi - # If we are past the tagged commit, we pretty print it. -@@ -119,12 +119,12 @@ scm_version() - # git-diff-index does not refresh the index, so it may give misleading - # results. - # See git-update-index(1), git-diff-index(1), and git-status(1). -- if { -- git --no-optional-locks status -uno --porcelain 2>/dev/null || -- git diff-index --name-only HEAD -- } | read dummy; then -- printf '%s' -dirty -- fi -+ #if { -+ # git --no-optional-locks status -uno --porcelain 2>/dev/null || -+ # git diff-index --name-only HEAD -+ #} | read dummy; then -+ # printf '%s' -dirty -+ #fi - } - - collect_files() diff --git a/SOURCES/uki_addons.json b/SOURCES/uki_addons.json new file mode 100644 index 0000000..d82dc87 --- /dev/null +++ b/SOURCES/uki_addons.json @@ -0,0 +1,12 @@ +{ + "virt": { + "common": { + "fips-disable.addon": [ + "fips=0\n" + ], + "fips-enable.addon": [ + "fips=1\n" + ] + } + } +}
\ No newline at end of file diff --git a/SOURCES/uki_create_addons.py b/SOURCES/uki_create_addons.py new file mode 100755 index 0000000..e30d43b --- /dev/null +++ b/SOURCES/uki_create_addons.py @@ -0,0 +1,151 @@ +#!/usr/bin/env python3 +# +# This script inspects a given json proving a list of addons, and +# creates an addon for each key/value pair matching the given uki, distro and +# arch provided in input. +# +# Usage: python uki_create_addons.py input_json out_dir uki distro arch +# +# This tool requires the systemd-ukify and systemd-boot packages. +# +# Addon file +#----------- +# Each addon terminates with .addon +# Each addon contains only two types of lines: +# Lines beginning with '#' are description and thus ignored +# All other lines are command line to be added. +# The name of the end resulting addon is taken from the json hierarchy. +# For example, and addon in json['virt']['rhel']['x86_64']['hello.addon'] will +# result in an UKI addon file generated in out_dir called +# hello-virt.rhel.x86_64.addon.efi +# +# The common key, present in any sub-dict in the provided json (except the leaf dict) +# is used as place for default addons when the same addon is not defined deep +# in the hierarchy. For example, if we define test.addon (text: 'test1\n') in +# json['common']['test.addon'] = ['test1\n'] and another test.addon (text: test2) in +# json['virt']['common']['test.addon'] = ['test2'], any other uki except virt +# will have a test.addon.efi with text "test1", and virt will have a +# test.addon.efi with "test2" +# +# sbat.conf +#---------- +# This dict is containing the sbat string for *all* addons being created. +# This dict is optional, but when used has to be put in a sub-dict with +# { 'sbat' : { 'sbat.conf' : ['your text here'] }} +# It follows the same syntax as the addon files, meaning '#' is comment and +# the rest is taken as sbat string and feed to ukify. + +import os +import sys +import json +import collections +import subprocess + + +UKIFY_PATH = '/usr/lib/systemd/ukify' + +def usage(err): + print(f'Usage: {os.path.basename(__file__)} input_json output_dir uki distro arch') + print(f'Error:{err}') + sys.exit(1) + +def check_clean_arguments(input_json, out_dir): + # Remove end '/' + if out_dir[-1:] == '/': + out_dir = out_dir[:-1] + if not os.path.isfile(input_json): + usage(f'input_json {input_json} is not a file, or does not exist!') + if not os.path.isdir(out_dir): + usage(f'out_dir_dir {out_dir} is not a dir, or does not exist!') + return out_dir + +UKICmdlineAddon = collections.namedtuple('UKICmdlineAddon', ['name', 'cmdline']) +uki_addons_list = [] +uki_addons = {} +addon_sbat_string = None + +def parse_lines(lines, rstrip=True): + cmdline = '' + for l in lines: + l = l.lstrip() + if not l: + continue + if l[0] == '#': + continue + # rstrip is used only for addons cmdline, not sbat.conf, as it replaces + # return lines with spaces. + if rstrip: + l = l.rstrip() + ' ' + cmdline += l + if cmdline == '': + return '' + return cmdline + +def parse_all_addons(in_obj): + global addon_sbat_string + + for el in in_obj.keys(): + # addon found: copy it in our global dict uki_addons + if el.endswith('.addon'): + uki_addons[el] = in_obj[el] + + if 'sbat' in in_obj and 'sbat.conf' in in_obj['sbat']: + # sbat.conf found: override sbat with the most specific one found + addon_sbat_string = parse_lines(in_obj['sbat']['sbat.conf'], rstrip=False) + +def recursively_find_addons(in_obj, folder_list): + # end of recursion, leaf directory. Search all addons here + if len(folder_list) == 0: + parse_all_addons(in_obj) + return + + # first, check for common folder + if 'common' in in_obj: + parse_all_addons(in_obj['common']) + + # second, check if there is a match with the searched folder + if folder_list[0] in in_obj: + folder_next = in_obj[folder_list[0]] + folder_list = folder_list[1:] + recursively_find_addons(folder_next, folder_list) + +def parse_in_json(in_json, uki_name, distro, arch): + with open(in_json, 'r') as f: + in_obj = json.load(f) + recursively_find_addons(in_obj, [uki_name, distro, arch]) + + for addon_name, cmdline in uki_addons.items(): + addon_name = addon_name.replace(".addon","") + addon_full_name = f'{addon_name}-{uki_name}.{distro}.{arch}.addon.efi' + cmdline = parse_lines(cmdline).rstrip() + if cmdline: + uki_addons_list.append(UKICmdlineAddon(addon_full_name, cmdline)) + +def create_addons(out_dir): + for uki_addon in uki_addons_list: + out_path = os.path.join(out_dir, uki_addon.name) + cmd = [ + f'{UKIFY_PATH}', 'build', + f'--cmdline="{uki_addon.cmdline}"', + f'--output={out_path}'] + if addon_sbat_string: + cmd.append('--sbat="' + addon_sbat_string.rstrip() +'"') + + subprocess.check_call(cmd, text=True) + +if __name__ == "__main__": + argc = len(sys.argv) - 1 + if argc != 5: + usage('too few or too many parameters!') + + input_json = sys.argv[1] + out_dir = sys.argv[2] + uki_name = sys.argv[3] + distro = sys.argv[4] + arch = sys.argv[5] + + out_dir = check_clean_arguments(input_json, out_dir) + parse_in_json(input_json, uki_name, distro, arch) + create_addons(out_dir) + + diff --git a/SOURCES/v0-oxp-sensors.patch b/SOURCES/v0-oxp-sensors.patch index 4b42d51..098119f 100644 --- a/SOURCES/v0-oxp-sensors.patch +++ b/SOURCES/v0-oxp-sensors.patch @@ -1,54 +1,152 @@ -From b75680974fe91faa5fcc1bbe39156b1e2e134238 Mon Sep 17 00:00:00 2001 -From: "Derek J. Clark" <derekjohn.clark@gmail.com> -Date: Wed, 27 Mar 2024 18:47:00 -0700 -Subject: [PATCH 1/4] oxp-sensors: hwmon: Add OrangePi Neo PWM fan control +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jan200101 <sentrycraft123@gmail.com> +Date: Sat, 21 Sep 2024 09:44:41 +0200 +Subject: [PATCH] backport oxp-sensors -Add OrangePi NEO handheld device. The OrangePi Neo uses different registers -for PWM manual mode, set PWM, and read fan speed than previous devices. Valid -PWM input and duty cycle is 1-244, we scale this to 1-155 to maintain -compatibility with existing userspace tools. +Signed-off-by: Jan200101 <sentrycraft123@gmail.com> --- - drivers/hwmon/oxp-sensors.c | 112 ++++++++++++++++++++++++++++++++---- - 1 file changed, 100 insertions(+), 12 deletions(-) + drivers/hwmon/oxp-sensors.c | 301 ++++++++++++++++++++++++++++++------ + 1 file changed, 257 insertions(+), 44 deletions(-) diff --git a/drivers/hwmon/oxp-sensors.c b/drivers/hwmon/oxp-sensors.c -index 8d3b0f86c..ebca28b4a 100644 +index 8d3b0f86cc57..83730d931824 100644 --- a/drivers/hwmon/oxp-sensors.c +++ b/drivers/hwmon/oxp-sensors.c -@@ -46,6 +46,7 @@ enum oxp_board { +@@ -1,18 +1,21 @@ + // SPDX-License-Identifier: GPL-2.0+ + /* +- * Platform driver for OneXPlayer, AOK ZOE, and Aya Neo Handhelds that expose +- * fan reading and control via hwmon sysfs. ++ * Platform driver for OneXPlayer, AOKZOE, AYANEO, and OrangePi Handhelds ++ * that expose fan reading and control via hwmon sysfs. + * + * Old OXP boards have the same DMI strings and they are told apart by +- * the boot cpu vendor (Intel/AMD). Currently only AMD boards are +- * supported but the code is made to be simple to add other handheld +- * boards in the future. ++ * the boot cpu vendor (Intel/AMD). Of these older models only AMD is ++ * supported. ++ * + * Fan control is provided via pwm interface in the range [0-255]. + * Old AMD boards use [0-100] as range in the EC, the written value is + * scaled to accommodate for that. Newer boards like the mini PRO and +- * AOK ZOE are not scaled but have the same EC layout. ++ * AOKZOE are not scaled but have the same EC layout. Newer models ++ * like the 2 and X1 are [0-184] and are scaled to 0-255. OrangePi ++ * are [1-244] and scaled to 0-255. + * + * Copyright (C) 2022 JoaquÃn I. AramendÃa <samsagax@gmail.com> ++ * Copyright (C) 2024 Derek J. Clark <derekjohn.clark@gmail.com> + */ + + #include <linux/acpi.h> +@@ -43,32 +46,48 @@ enum oxp_board { + aok_zoe_a1 = 1, + aya_neo_2, + aya_neo_air, ++ aya_neo_air_1s, aya_neo_air_plus_mendo, aya_neo_air_pro, ++ aya_neo_flip, aya_neo_geek, ++ aya_neo_kun, + orange_pi_neo, ++ oxp_2, ++ oxp_fly, oxp_mini_amd, oxp_mini_amd_a07, oxp_mini_amd_pro, -@@ -54,10 +55,16 @@ enum oxp_board { ++ oxp_x1, + }; + static enum oxp_board board; /* Fan reading and PWM */ -#define OXP_SENSOR_FAN_REG 0x76 /* Fan reading is 2 registers long */ -#define OXP_SENSOR_PWM_ENABLE_REG 0x4A /* PWM enable is 1 register long */ -#define OXP_SENSOR_PWM_REG 0x4B /* PWM reading is 1 register long */ -+#define OXP_SENSOR_FAN_REG 0x76 /* Fan reading is 2 registers long */ -+#define OXP_SENSOR_PWM_ENABLE_REG 0x4A /* PWM enable is 1 register long */ -+#define OXP_SENSOR_PWM_REG 0x4B /* PWM reading is 1 register long */ - -+#define ORANGEPI_SENSOR_FAN_REG 0x78 /* Fan reading is 2 registers long */ -+#define ORANGEPI_SENSOR_PWM_ENABLE_REG 0x40 /* PWM enable is 1 register long */ -+#define ORANGEPI_SENSOR_PWM_REG 0x38 /* PWM reading is 1 register long */ ++#define OXP_SENSOR_FAN_REG 0x76 /* Fan reading is 2 registers long */ ++#define OXP_2_SENSOR_FAN_REG 0x58 /* Fan reading is 2 registers long */ ++#define OXP_SENSOR_PWM_ENABLE_REG 0x4A /* PWM enable is 1 register long */ ++#define OXP_SENSOR_PWM_REG 0x4B /* PWM reading is 1 register long */ ++#define PWM_MODE_AUTO 0x00 ++#define PWM_MODE_MANUAL 0x01 + -+#define PWM_MODE_AUTO 0x00 -+#define PWM_MODE_MANUAL 0x01 ++/* OrangePi fan reading and PWM */ ++#define ORANGEPI_SENSOR_FAN_REG 0x78 /* Fan reading is 2 registers long */ ++#define ORANGEPI_SENSOR_PWM_ENABLE_REG 0x40 /* PWM enable is 1 register long */ ++#define ORANGEPI_SENSOR_PWM_REG 0x38 /* PWM reading is 1 register long */ + /* Turbo button takeover function - * Older boards have different values and EC registers +- * Older boards have different values and EC registers ++ * Different boards have different values and EC registers * for the same function -@@ -120,6 +127,13 @@ static const struct dmi_system_id dmi_table[] = { + */ +-#define OXP_OLD_TURBO_SWITCH_REG 0x1E +-#define OXP_OLD_TURBO_TAKE_VAL 0x01 +-#define OXP_OLD_TURBO_RETURN_VAL 0x00 ++#define OXP_TURBO_SWITCH_REG 0xF1 /* Mini Pro, OneXFly, AOKZOE */ ++#define OXP_2_TURBO_SWITCH_REG 0xEB /* OXP2 and X1 */ ++#define OXP_MINI_TURBO_SWITCH_REG 0x1E /* Mini AO7 */ ++ ++#define OXP_MINI_TURBO_TAKE_VAL 0x01 /* Mini AO7 */ ++#define OXP_TURBO_TAKE_VAL 0x40 /* All other models */ + +-#define OXP_TURBO_SWITCH_REG 0xF1 +-#define OXP_TURBO_TAKE_VAL 0x40 +-#define OXP_TURBO_RETURN_VAL 0x00 ++#define OXP_TURBO_RETURN_VAL 0x00 /* Common return val */ + + static const struct dmi_system_id dmi_table[] = { + { +@@ -88,7 +107,7 @@ static const struct dmi_system_id dmi_table[] = { + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "AYANEO 2"), ++ DMI_MATCH(DMI_BOARD_NAME, "AYANEO 2"), + }, + .driver_data = (void *)aya_neo_2, + }, +@@ -99,6 +118,13 @@ static const struct dmi_system_id dmi_table[] = { + }, + .driver_data = (void *)aya_neo_air, + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "AIR 1S"), ++ }, ++ .driver_data = (void *)aya_neo_air_1s, ++ }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), +@@ -116,10 +142,31 @@ static const struct dmi_system_id dmi_table[] = { + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), +- DMI_EXACT_MATCH(DMI_BOARD_NAME, "GEEK"), ++ DMI_MATCH(DMI_BOARD_NAME, "FLIP"), ++ }, ++ .driver_data = (void *)aya_neo_flip, ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), ++ DMI_MATCH(DMI_BOARD_NAME, "GEEK"), }, .driver_data = (void *)aya_neo_geek, }, + { + .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "KUN"), ++ }, ++ .driver_data = (void *)aya_neo_kun, ++ }, ++ { ++ .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "OrangePi"), + DMI_EXACT_MATCH(DMI_BOARD_NAME, "NEO-01"), + }, @@ -57,7 +155,122 @@ index 8d3b0f86c..ebca28b4a 100644 { .matches = { DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -@@ -295,12 +309,42 @@ static DEVICE_ATTR_RW(tt_toggle); +@@ -127,6 +174,20 @@ static const struct dmi_system_id dmi_table[] = { + }, + .driver_data = (void *)oxp_mini_amd, + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_MATCH(DMI_BOARD_NAME, "ONEXPLAYER 2"), ++ }, ++ .driver_data = (void *)oxp_2, ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER F1"), ++ }, ++ .driver_data = (void *)oxp_fly, ++ }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), +@@ -141,6 +202,13 @@ static const struct dmi_system_id dmi_table[] = { + }, + .driver_data = (void *)oxp_mini_amd_pro, + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_MATCH(DMI_BOARD_NAME, "ONEXPLAYER X1"), ++ }, ++ .driver_data = (void *)oxp_x1, ++ }, + {}, + }; + +@@ -192,14 +260,20 @@ static int tt_toggle_enable(void) + + switch (board) { + case oxp_mini_amd_a07: +- reg = OXP_OLD_TURBO_SWITCH_REG; +- val = OXP_OLD_TURBO_TAKE_VAL; ++ reg = OXP_MINI_TURBO_SWITCH_REG; ++ val = OXP_MINI_TURBO_TAKE_VAL; + break; +- case oxp_mini_amd_pro: + case aok_zoe_a1: ++ case oxp_fly: ++ case oxp_mini_amd_pro: + reg = OXP_TURBO_SWITCH_REG; + val = OXP_TURBO_TAKE_VAL; + break; ++ case oxp_2: ++ case oxp_x1: ++ reg = OXP_2_TURBO_SWITCH_REG; ++ val = OXP_TURBO_TAKE_VAL; ++ break; + default: + return -EINVAL; + } +@@ -213,14 +287,20 @@ static int tt_toggle_disable(void) + + switch (board) { + case oxp_mini_amd_a07: +- reg = OXP_OLD_TURBO_SWITCH_REG; +- val = OXP_OLD_TURBO_RETURN_VAL; ++ reg = OXP_MINI_TURBO_SWITCH_REG; ++ val = OXP_TURBO_RETURN_VAL; + break; +- case oxp_mini_amd_pro: + case aok_zoe_a1: ++ case oxp_fly: ++ case oxp_mini_amd_pro: + reg = OXP_TURBO_SWITCH_REG; + val = OXP_TURBO_RETURN_VAL; + break; ++ case oxp_2: ++ case oxp_x1: ++ reg = OXP_2_TURBO_SWITCH_REG; ++ val = OXP_TURBO_RETURN_VAL; ++ break; + default: + return -EINVAL; + } +@@ -233,8 +313,11 @@ static umode_t tt_toggle_is_visible(struct kobject *kobj, + { + switch (board) { + case aok_zoe_a1: ++ case oxp_2: ++ case oxp_fly: + case oxp_mini_amd_a07: + case oxp_mini_amd_pro: ++ case oxp_x1: + return attr->mode; + default: + break; +@@ -273,12 +356,17 @@ static ssize_t tt_toggle_show(struct device *dev, + + switch (board) { + case oxp_mini_amd_a07: +- reg = OXP_OLD_TURBO_SWITCH_REG; ++ reg = OXP_MINI_TURBO_SWITCH_REG; + break; +- case oxp_mini_amd_pro: + case aok_zoe_a1: ++ case oxp_fly: ++ case oxp_mini_amd_pro: + reg = OXP_TURBO_SWITCH_REG; + break; ++ case oxp_2: ++ case oxp_x1: ++ reg = OXP_2_TURBO_SWITCH_REG; ++ break; + default: + return -EINVAL; + } +@@ -295,12 +383,53 @@ static DEVICE_ATTR_RW(tt_toggle); /* PWM enable/disable functions */ static int oxp_pwm_enable(void) { @@ -70,10 +283,15 @@ index 8d3b0f86c..ebca28b4a 100644 + case aya_neo_air: + case aya_neo_air_plus_mendo: + case aya_neo_air_pro: ++ case aya_neo_flip: + case aya_neo_geek: ++ case aya_neo_kun: ++ case oxp_2: ++ case oxp_fly: + case oxp_mini_amd: + case oxp_mini_amd_a07: + case oxp_mini_amd_pro: ++ case oxp_x1: + return write_to_ec(OXP_SENSOR_PWM_ENABLE_REG, PWM_MODE_MANUAL); + default: + return -EINVAL; @@ -89,12 +307,18 @@ index 8d3b0f86c..ebca28b4a 100644 + case aok_zoe_a1: + case aya_neo_2: + case aya_neo_air: ++ case aya_neo_air_1s: + case aya_neo_air_plus_mendo: + case aya_neo_air_pro: ++ case aya_neo_flip: + case aya_neo_geek: ++ case aya_neo_kun: ++ case oxp_2: ++ case oxp_fly: + case oxp_mini_amd: + case oxp_mini_amd_a07: + case oxp_mini_amd_pro: ++ case oxp_x1: + return write_to_ec(OXP_SENSOR_PWM_ENABLE_REG, PWM_MODE_AUTO); + default: + return -EINVAL; @@ -102,7 +326,7 @@ index 8d3b0f86c..ebca28b4a 100644 } /* Callbacks for hwmon interface */ -@@ -326,7 +370,22 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, +@@ -326,7 +455,30 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, case hwmon_fan: switch (attr) { case hwmon_fan_input: @@ -110,12 +334,19 @@ index 8d3b0f86c..ebca28b4a 100644 + switch (board) { + case orange_pi_neo: + return read_from_ec(ORANGEPI_SENSOR_FAN_REG, 2, val); ++ case oxp_2: ++ case oxp_x1: ++ return read_from_ec(OXP_2_SENSOR_FAN_REG, 2, val); + case aok_zoe_a1: + case aya_neo_2: + case aya_neo_air: ++ case aya_neo_air_1s: + case aya_neo_air_plus_mendo: + case aya_neo_air_pro: ++ case aya_neo_flip: + case aya_neo_geek: ++ case aya_neo_kun: ++ case oxp_fly: + case oxp_mini_amd: + case oxp_mini_amd_a07: + case oxp_mini_amd_pro: @@ -123,10 +354,11 @@ index 8d3b0f86c..ebca28b4a 100644 + default: + break; + } ++ break; default: break; } -@@ -334,10 +393,14 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, +@@ -334,27 +486,72 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, case hwmon_pwm: switch (attr) { case hwmon_pwm_input: @@ -141,20 +373,34 @@ index 8d3b0f86c..ebca28b4a 100644 + /* scale from range [1-244] */ + *val = ((*val - 1) * 254 / 243) + 1; + break; ++ case oxp_2: ++ case oxp_x1: ++ ret = read_from_ec(OXP_SENSOR_PWM_REG, 1, val); ++ if (ret) ++ return ret; ++ /* scale from range [0-184] */ ++ *val = (*val * 255) / 184; ++ break; case aya_neo_2: case aya_neo_air: ++ case aya_neo_air_1s: case aya_neo_air_plus_mendo: -@@ -345,16 +408,37 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, + case aya_neo_air_pro: ++ case aya_neo_flip: case aya_neo_geek: ++ case aya_neo_kun: case oxp_mini_amd: case oxp_mini_amd_a07: + ret = read_from_ec(OXP_SENSOR_PWM_REG, 1, val); + if (ret) + return ret; ++ /* scale from range [0-100] */ *val = (*val * 255) / 100; break; - case oxp_mini_amd_pro: +- case oxp_mini_amd_pro: case aok_zoe_a1: ++ case oxp_fly: ++ case oxp_mini_amd_pro: default: + ret = read_from_ec(OXP_SENSOR_PWM_REG, 1, val); + if (ret) @@ -170,20 +416,27 @@ index 8d3b0f86c..ebca28b4a 100644 + case aok_zoe_a1: + case aya_neo_2: + case aya_neo_air: ++ case aya_neo_air_1s: + case aya_neo_air_plus_mendo: + case aya_neo_air_pro: ++ case aya_neo_flip: + case aya_neo_geek: ++ case aya_neo_kun: ++ case oxp_2: ++ case oxp_fly: + case oxp_mini_amd: + case oxp_mini_amd_a07: + case oxp_mini_amd_pro: ++ case oxp_x1: + return read_from_ec(OXP_SENSOR_PWM_ENABLE_REG, 1, val); + default: + break; + } ++ break; default: break; } -@@ -381,6 +465,10 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, +@@ -381,21 +578,36 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, if (val < 0 || val > 255) return -EINVAL; switch (board) { @@ -191,420 +444,98 @@ index 8d3b0f86c..ebca28b4a 100644 + /* scale to range [1-244] */ + val = ((val - 1) * 243 / 254) + 1; + return write_to_ec(ORANGEPI_SENSOR_PWM_REG, val); ++ case oxp_2: ++ case oxp_x1: ++ /* scale to range [0-184] */ ++ val = (val * 184) / 255; ++ return write_to_ec(OXP_SENSOR_PWM_REG, val); case aya_neo_2: case aya_neo_air: ++ case aya_neo_air_1s: case aya_neo_air_plus_mendo: -@@ -389,13 +477,13 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, + case aya_neo_air_pro: ++ case aya_neo_flip: + case aya_neo_geek: ++ case aya_neo_kun: case oxp_mini_amd: case oxp_mini_amd_a07: ++ /* scale to range [0-100] */ val = (val * 100) / 255; - break; + return write_to_ec(OXP_SENSOR_PWM_REG, val); case aok_zoe_a1: ++ case oxp_fly: case oxp_mini_amd_pro: + return write_to_ec(OXP_SENSOR_PWM_REG, val); default: break; } - return write_to_ec(OXP_SENSOR_PWM_REG, val); ++ break; default: break; } --- -2.45.2 - - -From 78c8501d4c2dc4dcc2125dcf130723b1fbe72e1c Mon Sep 17 00:00:00 2001 -From: "Derek J. Clark" <derekjohn.clark@gmail.com> -Date: Wed, 27 Mar 2024 18:50:22 -0700 -Subject: [PATCH 2/4] oxp-sensors: hwmon: Add OneXPlayer 2 and OneXFly - -Add OneXPlayer 2 series and OneXFly handhelds. The 2 series uses a new register -for turbo button takeover. While at it, adjust formatting of some constants and -reorder all cases alphabetically for consistency. Rename some constants for -disambiguation. ---- - drivers/hwmon/oxp-sensors.c | 90 ++++++++++++++++++++++++++++++------- - 1 file changed, 74 insertions(+), 16 deletions(-) - -diff --git a/drivers/hwmon/oxp-sensors.c b/drivers/hwmon/oxp-sensors.c -index ebca28b4a..cf8ba1cc6 100644 ---- a/drivers/hwmon/oxp-sensors.c -+++ b/drivers/hwmon/oxp-sensors.c -@@ -47,6 +47,8 @@ enum oxp_board { - aya_neo_air_pro, - aya_neo_geek, - orange_pi_neo, -+ oxp_2, -+ oxp_fly, - oxp_mini_amd, - oxp_mini_amd_a07, - oxp_mini_amd_pro, -@@ -66,16 +68,16 @@ static enum oxp_board board; - #define PWM_MODE_AUTO 0x00 - #define PWM_MODE_MANUAL 0x01 - /* Turbo button takeover function -- * Older boards have different values and EC registers -+ * Different boards have different values and EC registers - * for the same function - */ --#define OXP_OLD_TURBO_SWITCH_REG 0x1E --#define OXP_OLD_TURBO_TAKE_VAL 0x01 --#define OXP_OLD_TURBO_RETURN_VAL 0x00 -+#define OXP_TURBO_SWITCH_REG 0xF1 -+#define OXP_TURBO_TAKE_VAL 0x40 -+#define OXP_TURBO_RETURN_VAL 0x00 /* Common return val */ - --#define OXP_TURBO_SWITCH_REG 0xF1 --#define OXP_TURBO_TAKE_VAL 0x40 --#define OXP_TURBO_RETURN_VAL 0x00 -+#define OXP_2_TURBO_SWITCH_REG 0xEB /* OXP2 and OXP2 Pro */ -+#define OXP_MINI_TURBO_SWITCH_REG 0x1E /* Mini AO7 */ -+#define OXP_MINI_TURBO_TAKE_VAL 0x01 - - static const struct dmi_system_id dmi_table[] = { - { -@@ -141,6 +143,34 @@ static const struct dmi_system_id dmi_table[] = { - }, - .driver_data = (void *)oxp_mini_amd, - }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER 2 ARP23"), -+ }, -+ .driver_data = (void *)oxp_2, -+ }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER 2 PRO ARP23P"), -+ }, -+ .driver_data = (void *)oxp_2, -+ }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER 2 PRO ARP23P EVA-01"), -+ }, -+ .driver_data = (void *)oxp_2, -+ }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER F1"), -+ }, -+ .driver_data = (void *)oxp_fly, -+ }, - { - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), -@@ -206,14 +236,19 @@ static int tt_toggle_enable(void) +@@ -467,19 +679,20 @@ static int __init oxp_platform_init(void) + { + const struct dmi_system_id *dmi_entry; - switch (board) { - case oxp_mini_amd_a07: -- reg = OXP_OLD_TURBO_SWITCH_REG; -- val = OXP_OLD_TURBO_TAKE_VAL; -+ reg = OXP_MINI_TURBO_SWITCH_REG; -+ val = OXP_MINI_TURBO_TAKE_VAL; - break; -- case oxp_mini_amd_pro: - case aok_zoe_a1: -+ case oxp_fly: -+ case oxp_mini_amd_pro: - reg = OXP_TURBO_SWITCH_REG; - val = OXP_TURBO_TAKE_VAL; - break; -+ case oxp_2: -+ reg = OXP_2_TURBO_SWITCH_REG; -+ val = OXP_TURBO_TAKE_VAL; -+ break; - default: - return -EINVAL; - } -@@ -227,14 +262,19 @@ static int tt_toggle_disable(void) +- /* +- * Have to check for AMD processor here because DMI strings are the +- * same between Intel and AMD boards, the only way to tell them apart +- * is the CPU. +- * Intel boards seem to have different EC registers and values to +- * read/write. +- */ + dmi_entry = dmi_first_match(dmi_table); +- if (!dmi_entry || boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ++ if (!dmi_entry) + return -ENODEV; - switch (board) { - case oxp_mini_amd_a07: -- reg = OXP_OLD_TURBO_SWITCH_REG; -- val = OXP_OLD_TURBO_RETURN_VAL; -+ reg = OXP_MINI_TURBO_SWITCH_REG; -+ val = OXP_TURBO_RETURN_VAL; - break; -- case oxp_mini_amd_pro: - case aok_zoe_a1: -+ case oxp_fly: -+ case oxp_mini_amd_pro: - reg = OXP_TURBO_SWITCH_REG; - val = OXP_TURBO_RETURN_VAL; - break; -+ case oxp_2: -+ reg = OXP_2_TURBO_SWITCH_REG; -+ val = OXP_TURBO_RETURN_VAL; -+ break; - default: - return -EINVAL; - } -@@ -247,6 +287,8 @@ static umode_t tt_toggle_is_visible(struct kobject *kobj, - { - switch (board) { - case aok_zoe_a1: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_a07: - case oxp_mini_amd_pro: - return attr->mode; -@@ -287,12 +329,16 @@ static ssize_t tt_toggle_show(struct device *dev, + board = (enum oxp_board)(unsigned long)dmi_entry->driver_data; - switch (board) { - case oxp_mini_amd_a07: -- reg = OXP_OLD_TURBO_SWITCH_REG; -+ reg = OXP_MINI_TURBO_SWITCH_REG; - break; -- case oxp_mini_amd_pro: - case aok_zoe_a1: -+ case oxp_fly: -+ case oxp_mini_amd_pro: - reg = OXP_TURBO_SWITCH_REG; - break; -+ case oxp_2: -+ reg = OXP_2_TURBO_SWITCH_REG; -+ break; - default: - return -EINVAL; - } -@@ -320,6 +366,8 @@ static int oxp_pwm_enable(void) - case aya_neo_geek: - case oxp_mini_amd: - case oxp_mini_amd_a07: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_pro: - return write_to_ec(OXP_SENSOR_PWM_ENABLE_REG, PWM_MODE_MANUAL); - default: -@@ -340,6 +388,8 @@ static int oxp_pwm_disable(void) - case aya_neo_geek: - case oxp_mini_amd: - case oxp_mini_amd_a07: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_pro: - return write_to_ec(OXP_SENSOR_PWM_ENABLE_REG, PWM_MODE_AUTO); - default: -@@ -381,6 +431,8 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, - case aya_neo_geek: - case oxp_mini_amd: - case oxp_mini_amd_a07: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_pro: - return read_from_ec(OXP_SENSOR_FAN_REG, 2, val); - default: -@@ -413,8 +465,10 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, - return ret; - *val = (*val * 255) / 100; - break; -- case oxp_mini_amd_pro: - case aok_zoe_a1: -+ case oxp_2: -+ case oxp_fly: -+ case oxp_mini_amd_pro: - default: - ret = read_from_ec(OXP_SENSOR_PWM_REG, 1, val); - if (ret) -@@ -434,6 +488,8 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, - case aya_neo_geek: - case oxp_mini_amd: - case oxp_mini_amd_a07: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_pro: - return read_from_ec(OXP_SENSOR_PWM_ENABLE_REG, 1, val); - default: -@@ -479,6 +535,8 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, - val = (val * 100) / 255; - return write_to_ec(OXP_SENSOR_PWM_REG, val); - case aok_zoe_a1: -+ case oxp_2: -+ case oxp_fly: - case oxp_mini_amd_pro: - return write_to_ec(OXP_SENSOR_PWM_REG, val); - default: --- -2.45.2 - - -From f12bdbb992c66b8f1320372892da116e95a7f104 Mon Sep 17 00:00:00 2001 -From: "Derek J. Clark" <derekjohn.clark@gmail.com> -Date: Thu, 28 Mar 2024 19:50:40 +0100 -Subject: [PATCH 3/4] oxp-sensors: hwmon: Add support for AYANEO 2s, air 1s, - geek 1s and kun models - ---- - drivers/hwmon/oxp-sensors.c | 48 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 48 insertions(+) - -diff --git a/drivers/hwmon/oxp-sensors.c b/drivers/hwmon/oxp-sensors.c -index cf8ba1cc6..e8d9fea9d 100644 ---- a/drivers/hwmon/oxp-sensors.c -+++ b/drivers/hwmon/oxp-sensors.c -@@ -42,10 +42,14 @@ static bool unlock_global_acpi_lock(void) - enum oxp_board { - aok_zoe_a1 = 1, - aya_neo_2, -+ aya_neo_2s, - aya_neo_air, -+ aya_neo_air_1s, - aya_neo_air_plus_mendo, - aya_neo_air_pro, - aya_neo_geek, -+ aya_neo_geek_1s, -+ aya_neo_kun, - orange_pi_neo, - oxp_2, - oxp_fly, -@@ -101,6 +105,13 @@ static const struct dmi_system_id dmi_table[] = { - }, - .driver_data = (void *)aya_neo_2, - }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "AYANEO 2S"), -+ }, -+ .driver_data = (void *)aya_neo_2s, -+ }, - { - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -@@ -115,6 +126,13 @@ static const struct dmi_system_id dmi_table[] = { - }, - .driver_data = (void *)aya_neo_air_plus_mendo, - }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "AIR 1S"), -+ }, -+ .driver_data = (void *)aya_neo_air_1s, -+ }, - { - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -@@ -129,6 +147,20 @@ static const struct dmi_system_id dmi_table[] = { - }, - .driver_data = (void *)aya_neo_geek, - }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "GEEK 1S"), -+ }, -+ .driver_data = (void *)aya_neo_geek_1s, -+ }, -+ { -+ .matches = { -+ DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), -+ DMI_EXACT_MATCH(DMI_BOARD_NAME, "KUN"), -+ }, -+ .driver_data = (void *)aya_neo_kun, -+ }, - { - .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "OrangePi"), -@@ -360,10 +392,14 @@ static int oxp_pwm_enable(void) - return write_to_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, PWM_MODE_MANUAL); - case aok_zoe_a1: - case aya_neo_2: -+ case aya_neo_2s: - case aya_neo_air: -+ case aya_neo_air_1s: - case aya_neo_air_plus_mendo: - case aya_neo_air_pro: - case aya_neo_geek: -+ case aya_neo_geek_1s: -+ case aya_neo_kun: - case oxp_mini_amd: - case oxp_mini_amd_a07: - case oxp_2: -@@ -382,10 +418,14 @@ static int oxp_pwm_disable(void) - return write_to_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, PWM_MODE_AUTO); - case aok_zoe_a1: - case aya_neo_2: -+ case aya_neo_2s: - case aya_neo_air: -+ case aya_neo_air_1s: - case aya_neo_air_plus_mendo: - case aya_neo_air_pro: - case aya_neo_geek: -+ case aya_neo_geek_1s: -+ case aya_neo_kun: - case oxp_mini_amd: - case oxp_mini_amd_a07: - case oxp_2: -@@ -425,10 +465,14 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, - return read_from_ec(ORANGEPI_SENSOR_FAN_REG, 2, val); - case aok_zoe_a1: - case aya_neo_2: -+ case aya_neo_2s: - case aya_neo_air: -+ case aya_neo_air_1s: - case aya_neo_air_plus_mendo: - case aya_neo_air_pro: - case aya_neo_geek: -+ case aya_neo_geek_1s: -+ case aya_neo_kun: - case oxp_mini_amd: - case oxp_mini_amd_a07: - case oxp_2: -@@ -482,10 +526,14 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, - return read_from_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, 1, val); - case aok_zoe_a1: - case aya_neo_2: -+ case aya_neo_2s: - case aya_neo_air: -+ case aya_neo_air_1s: - case aya_neo_air_plus_mendo: - case aya_neo_air_pro: - case aya_neo_geek: -+ case aya_neo_geek_1s: -+ case aya_neo_kun: - case oxp_mini_amd: - case oxp_mini_amd_a07: - case oxp_2: --- -2.45.2 - ++ /* ++ * Have to check for AMD processor here because DMI strings are the same ++ * between Intel and AMD boards on older OneXPlayer devices, the only way ++ * to tell them apart is the CPU. Old Intel boards have an unsupported EC. ++ */ ++ if (board == oxp_mini_amd && boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ++ return -ENODEV; ++ + oxp_platform_device = + platform_create_bundle(&oxp_platform_driver, + oxp_platform_probe, NULL, 0, NULL, 0); -From 61740ea3d49721fa86f6a0085029f8f4f68ae916 Mon Sep 17 00:00:00 2001 -From: "Derek J. Clark" <derekjohn.clark@gmail.com> -Date: Wed, 27 Mar 2024 18:58:59 -0700 -Subject: [PATCH 4/4] oxp-sensors: hwmon: Add GPD Win Mini +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jan200101 <sentrycraft123@gmail.com> +Date: Sat, 21 Sep 2024 10:01:30 +0200 +Subject: [PATCH] oxp-sensors: hwmon: Add GPD Win Mini Add GPD Win Mini. GPD devices don't have a separate enable register, the PWM register is used for this purpose. A write value of 0 puts the PWM into auto mode, writing anything 1-244 puts the PWM into manual mode, and 245-255 are undefined. We scale to 1-255 and handle manual by writing a value to 70% as a common sense default. + +Signed-off-by: Jan200101 <sentrycraft123@gmail.com> --- - drivers/hwmon/oxp-sensors.c | 43 +++++++++++++++++++++++++++++++++++++ - 1 file changed, 43 insertions(+) + drivers/hwmon/oxp-sensors.c | 42 +++++++++++++++++++++++++++++++++++++ + 1 file changed, 42 insertions(+) diff --git a/drivers/hwmon/oxp-sensors.c b/drivers/hwmon/oxp-sensors.c -index e8d9fea9d..11dec1b31 100644 +index 83730d931824..e6ae932c11c5 100644 --- a/drivers/hwmon/oxp-sensors.c +++ b/drivers/hwmon/oxp-sensors.c -@@ -50,6 +50,7 @@ enum oxp_board { +@@ -52,6 +52,7 @@ enum oxp_board { + aya_neo_flip, aya_neo_geek, - aya_neo_geek_1s, aya_neo_kun, + gpd_win_mini, orange_pi_neo, oxp_2, oxp_fly, -@@ -69,8 +70,19 @@ static enum oxp_board board; - #define ORANGEPI_SENSOR_PWM_ENABLE_REG 0x40 /* PWM enable is 1 register long */ - #define ORANGEPI_SENSOR_PWM_REG 0x38 /* PWM reading is 1 register long */ +@@ -89,6 +90,16 @@ static enum oxp_board board; + + #define OXP_TURBO_RETURN_VAL 0x00 /* Common return val */ +/* GPD devices don't have a separate enable register for the fan. + * For the PWM register, 0 is auto, 1+ is a manual value, up to 255 @@ -613,18 +544,15 @@ index e8d9fea9d..11dec1b31 100644 + * The mini uses the same fan register as the OrangePi NEO. + */ +#define GPD_MINI_SENSOR_PWM_REG 0x7A /* PWM reading is 1 register long */ -+/* Values for fan auto mode */ - #define PWM_MODE_AUTO 0x00 -+ -+ /* Values for fan manual mode */ - #define PWM_MODE_MANUAL 0x01 ++/* Common sense default for manual mode */ +#define GPD_MINI_PWM_MODE_MANUAL 0xAA /* 70% */ - /* Turbo button takeover function - * Different boards have different values and EC registers - * for the same function -@@ -161,6 +173,13 @@ static const struct dmi_system_id dmi_table[] = { ++ + static const struct dmi_system_id dmi_table[] = { + { + .matches = { +@@ -153,6 +164,13 @@ static const struct dmi_system_id dmi_table[] = { }, - .driver_data = (void *)aya_neo_kun, + .driver_data = (void *)aya_neo_geek, }, + { + .matches = { @@ -635,8 +563,8 @@ index e8d9fea9d..11dec1b31 100644 + }, { .matches = { - DMI_MATCH(DMI_BOARD_VENDOR, "OrangePi"), -@@ -388,6 +407,11 @@ static DEVICE_ATTR_RW(tt_toggle); + DMI_MATCH(DMI_BOARD_VENDOR, "AYANEO"), +@@ -384,6 +402,11 @@ static DEVICE_ATTR_RW(tt_toggle); static int oxp_pwm_enable(void) { switch (board) { @@ -648,7 +576,7 @@ index e8d9fea9d..11dec1b31 100644 case orange_pi_neo: return write_to_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, PWM_MODE_MANUAL); case aok_zoe_a1: -@@ -414,6 +438,8 @@ static int oxp_pwm_enable(void) +@@ -409,6 +432,8 @@ static int oxp_pwm_enable(void) static int oxp_pwm_disable(void) { switch (board) { @@ -657,15 +585,15 @@ index e8d9fea9d..11dec1b31 100644 case orange_pi_neo: return write_to_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, PWM_MODE_AUTO); case aok_zoe_a1: -@@ -461,6 +487,7 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, +@@ -456,6 +481,7 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, switch (attr) { case hwmon_fan_input: switch (board) { + case gpd_win_mini: case orange_pi_neo: return read_from_ec(ORANGEPI_SENSOR_FAN_REG, 2, val); - case aok_zoe_a1: -@@ -490,6 +517,14 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, + case oxp_2: +@@ -487,6 +513,14 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, switch (attr) { case hwmon_pwm_input: switch (board) { @@ -680,7 +608,7 @@ index e8d9fea9d..11dec1b31 100644 case orange_pi_neo: ret = read_from_ec(ORANGEPI_SENSOR_PWM_REG, 1, val); if (ret) -@@ -522,6 +557,10 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, +@@ -530,6 +564,10 @@ static int oxp_platform_read(struct device *dev, enum hwmon_sensor_types type, return 0; case hwmon_pwm_enable: switch (board) { @@ -691,7 +619,7 @@ index e8d9fea9d..11dec1b31 100644 case orange_pi_neo: return read_from_ec(ORANGEPI_SENSOR_PWM_ENABLE_REG, 1, val); case aok_zoe_a1: -@@ -569,6 +608,10 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, +@@ -578,6 +616,10 @@ static int oxp_platform_write(struct device *dev, enum hwmon_sensor_types type, if (val < 0 || val > 255) return -EINVAL; switch (board) { @@ -702,6 +630,3 @@ index e8d9fea9d..11dec1b31 100644 case orange_pi_neo: /* scale to range [1-244] */ val = ((val - 1) * 243 / 254) + 1; --- -2.45.2 - diff --git a/SOURCES/v0-speaker-multifix.patch b/SOURCES/v0-speaker-multifix.patch deleted file mode 100644 index 014985e..0000000 --- a/SOURCES/v0-speaker-multifix.patch +++ /dev/null @@ -1,23729 +0,0 @@ -From dbe14cbae955a033bff0c83b7341cc722b476bda Mon Sep 17 00:00:00 2001 -From: Matthew Anderson <ruinairas1992@gmail.com> -Date: Thu, 25 Apr 2024 09:39:40 -0500 -Subject: [PATCH 1/8] Codec: Add aw87xxx codec with partial acpi implementation - Contribution by CVMagic (https://github.com/CVMagic) - -aw87xxx: Use strscpy instead of strlcpy - -awinic: i2c_driver cleanup and fixes -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/soc/codecs/Kconfig | 2 + - sound/soc/codecs/Makefile | 1 + - sound/soc/codecs/aw87xxx/Kconfig | 5 + - sound/soc/codecs/aw87xxx/Makefile | 4 + - sound/soc/codecs/aw87xxx/aw87xxx.c | 1457 +++++ - sound/soc/codecs/aw87xxx/aw87xxx.h | 121 + - sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.c | 1558 +++++ - sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.h | 191 + - sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.c | 515 ++ - sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.h | 73 + - sound/soc/codecs/aw87xxx/aw87xxx_device.c | 977 +++ - sound/soc/codecs/aw87xxx/aw87xxx_device.h | 149 + - sound/soc/codecs/aw87xxx/aw87xxx_dsp.c | 355 ++ - sound/soc/codecs/aw87xxx/aw87xxx_dsp.h | 65 + - sound/soc/codecs/aw87xxx/aw87xxx_log.h | 33 + - sound/soc/codecs/aw87xxx/aw87xxx_monitor.c | 1208 ++++ - sound/soc/codecs/aw87xxx/aw87xxx_monitor.h | 96 + - sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h | 2315 ++++++++ - sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h | 67 + - .../codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h | 93 + - .../codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h | 94 + - sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h | 4124 +++++++++++++ - sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h | 5246 +++++++++++++++++ - sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h | 1205 ++++ - sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h | 81 + - 25 files changed, 20035 insertions(+) - create mode 100644 sound/soc/codecs/aw87xxx/Kconfig - create mode 100644 sound/soc/codecs/aw87xxx/Makefile - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_device.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_device.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_dsp.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_dsp.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_log.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_monitor.c - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_monitor.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h - create mode 100644 sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h - -diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig -index f78ea2f86..34d6b290f 100644 ---- a/sound/soc/codecs/Kconfig -+++ b/sound/soc/codecs/Kconfig -@@ -2497,4 +2497,6 @@ config SND_SOC_LPASS_TX_MACRO - select SND_SOC_LPASS_MACRO_COMMON - tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)" - -+source "sound/soc/codecs/aw87xxx/Kconfig" -+ - endmenu -diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile -index 7c075539d..23f6d3b75 100644 ---- a/sound/soc/codecs/Makefile -+++ b/sound/soc/codecs/Makefile -@@ -781,6 +781,7 @@ obj-$(CONFIG_SND_SOC_WSA884X) += snd-soc-wsa884x.o - obj-$(CONFIG_SND_SOC_ZL38060) += snd-soc-zl38060.o - - # Amp -+obj-$(CONFIG_SND_SOC_AW87XXX) += aw87xxx/ - obj-$(CONFIG_SND_SOC_MAX9877) += snd-soc-max9877.o - obj-$(CONFIG_SND_SOC_MAX98504) += snd-soc-max98504.o - obj-$(CONFIG_SND_SOC_SIMPLE_AMPLIFIER) += snd-soc-simple-amplifier.o -diff --git a/sound/soc/codecs/aw87xxx/Kconfig b/sound/soc/codecs/aw87xxx/Kconfig -new file mode 100644 -index 000000000..bd0f208e2 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/Kconfig -@@ -0,0 +1,5 @@ -+config SND_SOC_AW87XXX -+ tristate "SoC Audio for awinic AW87XXX Smart K PA" -+ depends on I2C -+ help -+ This option enables support for AW87XXX Smart K PA. -diff --git a/sound/soc/codecs/aw87xxx/Makefile b/sound/soc/codecs/aw87xxx/Makefile -new file mode 100644 -index 000000000..d32f319a5 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/Makefile -@@ -0,0 +1,4 @@ -+#for AWINIC AW87XXX Smart K PA -+snd-soc-aw87xxx-objs := aw87xxx.o aw87xxx_device.o aw87xxx_monitor.o aw87xxx_bin_parse.o aw87xxx_dsp.o aw87xxx_acf_bin.o -+obj-$(CONFIG_SND_SOC_AW87XXX) += snd-soc-aw87xxx.o -+ -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx.c b/sound/soc/codecs/aw87xxx/aw87xxx.c -new file mode 100644 -index 000000000..eddb01695 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx.c -@@ -0,0 +1,1457 @@ -+/* -+ * aw87xxx.c aw87xxx pa module -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#include <linux/i2c.h> -+#include <sound/pcm.h> -+#include <sound/pcm_params.h> -+#include <linux/gpio.h> -+#include <linux/of_gpio.h> -+#include <linux/gpio/consumer.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/device.h> -+#include <linux/irq.h> -+#include <linux/firmware.h> -+#include <linux/platform_device.h> -+#include <linux/slab.h> -+#include <linux/fs.h> -+#include <linux/proc_fs.h> -+#include <linux/uaccess.h> -+#include <linux/io.h> -+#include <linux/init.h> -+#include <linux/pci.h> -+#include <linux/dma-mapping.h> -+#include <linux/gameport.h> -+#include <linux/moduleparam.h> -+#include <linux/mutex.h> -+#include <linux/timer.h> -+#include <linux/workqueue.h> -+#include <linux/hrtimer.h> -+#include <linux/ktime.h> -+#include <linux/kthread.h> -+#include <uapi/sound/asound.h> -+#include <sound/control.h> -+#include <sound/soc.h> -+#include "aw87xxx.h" -+#include "aw87xxx_device.h" -+#include "aw87xxx_log.h" -+#include "aw87xxx_monitor.h" -+#include "aw87xxx_acf_bin.h" -+#include "aw87xxx_bin_parse.h" -+#include "aw87xxx_dsp.h" -+ -+/***************************************************************** -+* aw87xxx marco -+******************************************************************/ -+#define AW87XXX_I2C_NAME "aw87xxx_pa" -+#define AW87XXX_DRIVER_VERSION "v2.7.0" -+#define AW87XXX_FW_BIN_NAME "aw87xxx_acf.bin" -+#define AW87XXX_PROF_MUSIC "Music" -+/************************************************************************* -+ * aw87xxx variable -+ ************************************************************************/ -+static LIST_HEAD(g_aw87xxx_list); -+static DEFINE_MUTEX(g_aw87xxx_mutex_lock); -+unsigned int g_aw87xxx_dev_cnt = 0; -+ -+static const char *const aw87xxx_monitor_switch[] = {"Disable", "Enable"}; -+static const char *const aw87xxx_spin_switch[] = {"spin_0", "spin_90", -+ "spin_180", "spin_270"}; -+#ifdef AW_KERNEL_VER_OVER_4_19_1 -+static struct aw_componet_codec_ops aw_componet_codec_ops = { -+ .add_codec_controls = snd_soc_add_component_controls, -+ .unregister_codec = snd_soc_unregister_component, -+}; -+#else -+static struct aw_componet_codec_ops aw_componet_codec_ops = { -+ .add_codec_controls = snd_soc_add_codec_controls, -+ .unregister_codec = snd_soc_unregister_codec, -+}; -+#endif -+ -+ -+/************************************************************************ -+ * -+ * aw87xxx device update profile -+ * -+ ************************************************************************/ -+static int aw87xxx_power_down(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = 0; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ struct aw_data_container *data_container = NULL; -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!prof_info->status) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -+ if (prof_desc == NULL) -+ goto no_bin_pwr_off; -+ -+ if (!prof_desc->prof_st) -+ goto no_bin_pwr_off; -+ -+ -+ data_container = &prof_desc->data_container; -+ AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -+ profile, data_container->len); -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGI(aw87xxx->dev, "profile[%s] has already load ", profile); -+ } else { -+ if (aw_dev->ops.pwr_off_func) { -+ ret = aw_dev->ops.pwr_off_func(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -+ goto pwr_off_failed; -+ } -+ } else { -+ ret = aw87xxx_dev_default_pwr_off(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -+ goto pwr_off_failed; -+ } -+ } -+ } -+ -+ aw87xxx->current_profile = prof_desc->prof_name; -+ return 0; -+ -+pwr_off_failed: -+no_bin_pwr_off: -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ aw87xxx->current_profile = aw87xxx->prof_off_name; -+ return ret; -+} -+ -+static int aw87xxx_power_on(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -EINVAL; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ struct aw_data_container *data_container = NULL; -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!prof_info->status) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -+ return aw87xxx_power_down(aw87xxx, profile); -+ -+ prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -+ if (prof_desc == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found [%s] parameter", profile); -+ return -EINVAL; -+ } -+ -+ if (!prof_desc->prof_st) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found data container"); -+ return -EINVAL; -+ } -+ -+ data_container = &prof_desc->data_container; -+ AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -+ profile, data_container->len); -+ -+ if (aw_dev->ops.pwr_on_func) { -+ ret = aw_dev->ops.pwr_on_func(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -+ profile); -+ return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -+ } -+ } else { -+ ret = aw87xxx_dev_default_pwr_on(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -+ profile); -+ return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -+ } -+ } -+ -+ aw87xxx->current_profile = prof_desc->prof_name; -+ AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] succeed", profile); -+ -+ return 0; -+} -+ -+ -+ -+int aw87xxx_update_profile(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] enter", profile); -+ mutex_lock(&aw87xxx->reg_lock); -+ aw87xxx_monitor_stop(&aw87xxx->monitor); -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) { -+ ret = aw87xxx_power_down(aw87xxx, profile); -+ } else { -+ ret = aw87xxx_power_on(aw87xxx, profile); -+ if (!ret) -+ aw87xxx_monitor_start(&aw87xxx->monitor); -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return ret; -+} -+ -+int aw87xxx_update_profile_esd(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -1; -+ -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -+ ret = aw87xxx_power_down(aw87xxx, profile); -+ else -+ ret = aw87xxx_power_on(aw87xxx, profile); -+ -+ return ret; -+} -+ -+char *aw87xxx_show_current_profile(int dev_index) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ if (aw87xxx->dev_index == dev_index) { -+ AW_DEV_LOGI(aw87xxx->dev, "current profile is [%s]", -+ aw87xxx->current_profile); -+ return aw87xxx->current_profile; -+ } -+ } -+ -+ AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -+ return NULL; -+} -+EXPORT_SYMBOL(aw87xxx_show_current_profile); -+ -+int aw87xxx_set_profile(int dev_index, char *profile) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ if (profile && aw87xxx->dev_index == dev_index) { -+ AW_DEV_LOGD(aw87xxx->dev, "set dev_index = %d, profile = %s", -+ dev_index, profile); -+ return aw87xxx_update_profile(aw87xxx, profile); -+ } -+ } -+ -+ AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(aw87xxx_set_profile); -+ -+int aw87xxx_set_profile_by_id(int dev_index, int profile_id) -+{ -+ char *profile = NULL; -+ -+ profile = aw87xxx_ctos_get_prof_name(profile_id); -+ if (profile == NULL) { -+ AW_LOGE("aw87xxx, dev_index[%d] profile[%d] not support!", -+ dev_index, profile_id); -+ return -EINVAL; -+ } -+ -+ AW_LOGI("aw87xxx, dev_index[%d] set profile[%s] by id[%d]", -+ dev_index, profile, profile_id); -+ return aw87xxx_set_profile(dev_index, profile); -+} -+EXPORT_SYMBOL(aw87xxx_set_profile_by_id); -+ -+/**************************************************************************** -+ * -+ * aw87xxx Kcontrols -+ * -+ ****************************************************************************/ -+static int aw87xxx_profile_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count = 0; -+ char *name = NULL; -+ char *profile_name = NULL; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ -+ /*make sure have prof */ -+ count = aw87xxx_acf_get_profile_count(aw87xxx->dev, &aw87xxx->acf_info); -+ if (count <= 0) { -+ uinfo->value.enumerated.items = 0; -+ AW_DEV_LOGE(aw87xxx->dev, "get count[%d] failed", count); -+ return 0; -+ } -+ -+ uinfo->value.enumerated.items = count; -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ name = uinfo->value.enumerated.name; -+ count = uinfo->value.enumerated.item; -+ profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, -+ &aw87xxx->acf_info, count); -+ if (profile_name == NULL) { -+ strscpy(uinfo->value.enumerated.name, "NULL", -+ strlen("NULL") + 1); -+ return 0; -+ } -+ -+ strscpy(name, profile_name, sizeof(uinfo->value.enumerated.name)); -+ -+ return 0; -+} -+ -+static int aw87xxx_profile_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int ret = -1; -+ char *profile_name = NULL; -+ int index = ucontrol->value.integer.value[0]; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct acf_bin_info *acf_info = NULL; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ acf_info = &aw87xxx->acf_info; -+ -+ profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, acf_info, index); -+ if (!profile_name) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found profile name,index=[%d]", -+ index); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "set profile [%s]", profile_name); -+ -+ ret = aw87xxx_update_profile(aw87xxx, profile_name); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "set dev_index[%d] profile failed, profile = %s", -+ aw87xxx->dev_index, profile_name); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int aw87xxx_profile_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int index = 0; -+ char *profile; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ if (!aw87xxx->current_profile) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile not init"); -+ return -EINVAL; -+ } -+ -+ profile = aw87xxx->current_profile; -+ AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", -+ aw87xxx->current_profile); -+ -+ -+ index = aw87xxx_acf_get_prof_index_form_name(aw87xxx->dev, -+ &aw87xxx->acf_info, aw87xxx->current_profile); -+ if (index < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "get profile index failed"); -+ return index; -+ } -+ -+ ucontrol->value.integer.value[0] = index; -+ -+ return 0; -+} -+ -+static int aw87xxx_vmax_get_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; -+ uinfo->count = 1; -+ uinfo->value.integer.min = INT_MIN; -+ uinfo->value.integer.max = AW_VMAX_MAX; -+ -+ return 0; -+} -+ -+static int aw87xxx_vmax_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int ret = -1; -+ int vmax_val = 0; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_monitor_no_dsp_get_vmax(&aw87xxx->monitor, &vmax_val); -+ if (ret < 0) -+ return ret; -+ -+ ucontrol->value.integer.value[0] = vmax_val; -+ AW_DEV_LOGI(aw87xxx->dev, "get vmax = [0x%x]", vmax_val); -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count; -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ count = ARRAY_SIZE(aw87xxx_monitor_switch); -+ -+ uinfo->value.enumerated.items = count; -+ -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ strscpy(uinfo->value.enumerated.name, -+ aw87xxx_monitor_switch[uinfo->value.enumerated.item], -+ strlen(aw87xxx_monitor_switch[uinfo->value.enumerated.item]) + 1); -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ uint32_t ctrl_value = ucontrol->value.integer.value[0]; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct aw_monitor *aw_monitor = &aw87xxx->monitor; -+ int ret = -1; -+ -+ ret = aw87xxx_dev_monitor_switch_set(aw_monitor, ctrl_value); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct aw_monitor *aw_monitor = &aw87xxx->monitor; -+ -+ ucontrol->value.integer.value[0] = aw_monitor->monitor_hdr.monitor_switch; -+ -+ AW_DEV_LOGI(aw87xxx->dev, "monitor switch is %ld", ucontrol->value.integer.value[0]); -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count; -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ count = ARRAY_SIZE(aw87xxx_spin_switch); -+ -+ uinfo->value.enumerated.items = count; -+ -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ strscpy(uinfo->value.enumerated.name, -+ aw87xxx_spin_switch[uinfo->value.enumerated.item], -+ strlen(aw87xxx_spin_switch[uinfo->value.enumerated.item]) + 1); -+ -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ uint32_t ctrl_value = 0; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ ctrl_value = ucontrol->value.integer.value[0]; -+ -+ ret = aw87xxx_dsp_set_spin(ctrl_value); -+ if (ret) { -+ AW_DEV_LOGE(aw87xxx->dev, "write spin failed"); -+ return ret; -+ } -+ AW_DEV_LOGD(aw87xxx->dev, "write spin done ctrl_value=%d", ctrl_value); -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ ucontrol->value.integer.value[0] = aw87xxx_dsp_get_spin(); -+ AW_DEV_LOGD(aw87xxx->dev, "current spin is %ld", ucontrol->value.integer.value[0]); -+ -+ return 0; -+} -+ -+ -+static int aw87xxx_kcontrol_dynamic_create(struct aw87xxx *aw87xxx, -+ void *codec) -+{ -+ struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -+ aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -+ char *kctl_name[AW87XXX_PRIVATE_KCONTROL_NUM]; -+ int kcontrol_num = AW87XXX_PRIVATE_KCONTROL_NUM; -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx->codec = soc_codec; -+ -+ aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -+ sizeof(struct snd_kcontrol_new) * kcontrol_num, -+ GFP_KERNEL); -+ if (aw87xxx_kcontrol == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[0] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_profile_switch_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[0].name = kctl_name[0]; -+ aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[0].info = aw87xxx_profile_switch_info; -+ aw87xxx_kcontrol[0].get = aw87xxx_profile_switch_get; -+ aw87xxx_kcontrol[0].put = aw87xxx_profile_switch_put; -+ aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -+ -+ kctl_name[1] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[1] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[1], AW_NAME_BUF_MAX, "aw87xxx_vmax_get_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[1].name = kctl_name[1]; -+ aw87xxx_kcontrol[1].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[1].access = SNDRV_CTL_ELEM_ACCESS_READ; -+ aw87xxx_kcontrol[1].info = aw87xxx_vmax_get_info; -+ aw87xxx_kcontrol[1].get = aw87xxx_vmax_get; -+ aw87xxx_kcontrol[1].private_value = (unsigned long)aw87xxx; -+ -+ kctl_name[2] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[2] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[2], AW_NAME_BUF_MAX, "aw87xxx_monitor_switch_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[2].name = kctl_name[2]; -+ aw87xxx_kcontrol[2].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[2].info = aw87xxx_monitor_switch_info; -+ aw87xxx_kcontrol[2].get = aw87xxx_monitor_switch_get; -+ aw87xxx_kcontrol[2].put = aw87xxx_monitor_switch_put; -+ aw87xxx_kcontrol[2].private_value = (unsigned long)aw87xxx; -+ -+ ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -+ aw87xxx_kcontrol, kcontrol_num); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -+ ret); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "add codec controls[%s,%s,%s]", -+ aw87xxx_kcontrol[0].name, -+ aw87xxx_kcontrol[1].name, -+ aw87xxx_kcontrol[2].name); -+ -+ return 0; -+} -+ -+static int aw87xxx_public_kcontrol_create(struct aw87xxx *aw87xxx, -+ void *codec) -+{ -+ struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -+ aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -+ char *kctl_name[AW87XXX_PUBLIC_KCONTROL_NUM]; -+ int kcontrol_num = AW87XXX_PUBLIC_KCONTROL_NUM; -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx->codec = soc_codec; -+ -+ aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -+ sizeof(struct snd_kcontrol_new) * kcontrol_num, -+ GFP_KERNEL); -+ if (aw87xxx_kcontrol == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[0] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_spin_switch"); -+ -+ aw87xxx_kcontrol[0].name = kctl_name[0]; -+ aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[0].info = aw87xxx_spin_switch_info; -+ aw87xxx_kcontrol[0].get = aw87xxx_spin_switch_get; -+ aw87xxx_kcontrol[0].put = aw87xxx_spin_switch_put; -+ aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -+ -+ ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -+ aw87xxx_kcontrol, kcontrol_num); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -+ ret); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "add public codec controls[%s]", -+ aw87xxx_kcontrol[0].name); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+ * -+ *aw87xxx kcontrol create -+ * -+ ****************************************************************************/ -+int aw87xxx_add_codec_controls(void *codec) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ int ret = -1; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ ret = aw87xxx_kcontrol_dynamic_create(aw87xxx, codec); -+ if (ret < 0) -+ return ret; -+ -+ if (aw87xxx->dev_index == 0) { -+ ret = aw87xxx_public_kcontrol_create(aw87xxx, codec); -+ if (ret < 0) -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(aw87xxx_add_codec_controls); -+ -+ -+/**************************************************************************** -+ * -+ * aw87xxx firmware cfg load -+ * -+ ***************************************************************************/ -+static void aw87xxx_fw_cfg_free(struct aw87xxx *aw87xxx) -+{ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx_acf_profile_free(aw87xxx->dev, &aw87xxx->acf_info); -+ aw87xxx_monitor_cfg_free(&aw87xxx->monitor); -+} -+ -+static int aw87xxx_init_default_prof(struct aw87xxx *aw87xxx) -+{ -+ char *profile = NULL; -+ -+ profile = aw87xxx_acf_get_prof_off_name(aw87xxx->dev, &aw87xxx->acf_info); -+ if (profile == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "get profile off name failed"); -+ return -EINVAL; -+ } -+ -+ snprintf(aw87xxx->prof_off_name, AW_PROFILE_STR_MAX, "%s", profile); -+ aw87xxx->current_profile = profile; -+ AW_DEV_LOGI(aw87xxx->dev, "init profile name [%s]", -+ aw87xxx->current_profile); -+ -+ return 0; -+} -+ -+static void aw87xxx_fw_load_retry(struct aw87xxx *aw87xxx) -+{ -+ struct acf_bin_info *acf_info = &aw87xxx->acf_info; -+ int ram_timer_val = 2000; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "failed to read [%s]", -+ aw87xxx->fw_name); -+ -+ if (acf_info->load_count < AW_LOAD_FW_RETRIES) { -+ AW_DEV_LOGD(aw87xxx->dev, -+ "restart hrtimer to load firmware"); -+ schedule_delayed_work(&aw87xxx->fw_load_work, -+ msecs_to_jiffies(ram_timer_val)); -+ } else { -+ acf_info->load_count = 0; -+ AW_DEV_LOGE(aw87xxx->dev, -+ "can not load firmware,please check name or file exists"); -+ return; -+ } -+ acf_info->load_count++; -+} -+ -+static void aw87xxx_fw_load(const struct firmware *fw, void *context) -+{ -+ int ret = -1; -+ struct aw87xxx *aw87xxx = context; -+ struct acf_bin_info *acf_info = &aw87xxx->acf_info; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!fw) { -+ aw87xxx_fw_load_retry(aw87xxx); -+ return; -+ } -+ -+ AW_DEV_LOGD(aw87xxx->dev, "loaded %s - size: %ld", -+ aw87xxx->fw_name, (u_long)(fw ? fw->size : 0)); -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ acf_info->fw_data = vmalloc(fw->size); -+ if (!acf_info->fw_data) { -+ AW_DEV_LOGE(aw87xxx->dev, "fw_data kzalloc memory failed"); -+ goto exit_vmalloc_failed; -+ } -+ memset(acf_info->fw_data, 0, fw->size); -+ memcpy(acf_info->fw_data, fw->data, fw->size); -+ acf_info->fw_size = fw->size; -+ -+ ret = aw87xxx_acf_parse(aw87xxx->dev, &aw87xxx->acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "fw_data parse failed"); -+ goto exit_acf_parse_failed; -+ } -+ -+ ret = aw87xxx_init_default_prof(aw87xxx); -+ if (ret < 0) { -+ aw87xxx_fw_cfg_free(aw87xxx); -+ goto exit_acf_parse_failed; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "acf parse succeed"); -+ mutex_unlock(&aw87xxx->reg_lock); -+ release_firmware(fw); -+ // Updating profile to "Music" because the firmware is set to "off" during init -+ aw87xxx_update_profile(aw87xxx, AW87XXX_PROF_MUSIC); -+ -+ return; -+ -+exit_acf_parse_failed: -+exit_vmalloc_failed: -+ release_firmware(fw); -+ mutex_unlock(&aw87xxx->reg_lock); -+} -+ -+static void aw87xxx_fw_load_work_routine(struct work_struct *work) -+{ -+ struct aw87xxx *aw87xxx = container_of(work, -+ struct aw87xxx, fw_load_work.work); -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (prof_info->status == AW_ACF_WAIT) { -+ request_firmware_nowait(THIS_MODULE, -+// FW_ACTION_HOTPLUG, -+ FW_ACTION_UEVENT, -+ aw87xxx->fw_name, -+ aw87xxx->dev, -+ GFP_KERNEL, aw87xxx, -+ aw87xxx_fw_load); -+ } -+} -+ -+static void aw87xxx_fw_load_init(struct aw87xxx *aw87xxx) -+{ -+#ifdef AW_CFG_UPDATE_DELAY -+ int cfg_timer_val = AW_CFG_UPDATE_DELAY_TIMER; -+#else -+ int cfg_timer_val = 0; -+#endif -+ AW_DEV_LOGI(aw87xxx->dev, "enter"); -+ snprintf(aw87xxx->fw_name, AW87XXX_FW_NAME_MAX, "%s", AW87XXX_FW_BIN_NAME); -+ aw87xxx_acf_init(&aw87xxx->aw_dev, &aw87xxx->acf_info, aw87xxx->dev_index); -+ -+ INIT_DELAYED_WORK(&aw87xxx->fw_load_work, aw87xxx_fw_load_work_routine); -+ schedule_delayed_work(&aw87xxx->fw_load_work, -+ msecs_to_jiffies(cfg_timer_val)); -+} -+ -+/**************************************************************************** -+ * -+ *aw87xxx attribute node -+ * -+ ****************************************************************************/ -+static ssize_t aw87xxx_attr_get_reg(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int ret = 0; -+ unsigned int i = 0; -+ unsigned char reg_val = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ for (i = 0; i < aw_dev->reg_max_addr; i++) { -+ if (!(aw_dev->reg_access[i] & AW_DEV_REG_RD_ACCESS)) -+ continue; -+ ret = aw87xxx_dev_i2c_read_byte(&aw87xxx->aw_dev, i, ®_val); -+ if (ret < 0) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "read reg [0x%x] failed\n", i); -+ AW_DEV_LOGE(aw87xxx->dev, "read reg [0x%x] failed", i); -+ } else { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "reg:0x%02X=0x%02X\n", i, reg_val); -+ AW_DEV_LOGD(aw87xxx->dev, "reg:0x%02X=0x%02X", -+ i, reg_val); -+ } -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_reg(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ unsigned int databuf[2] = { 0 }; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ if (sscanf(buf, "0x%x 0x%x", &databuf[0], &databuf[1]) == 2) { -+ if (databuf[0] >= aw87xxx->aw_dev.reg_max_addr) { -+ AW_DEV_LOGE(aw87xxx->dev, "set reg[0x%x] error,is out of reg_addr_max[0x%x]", -+ databuf[0], aw87xxx->aw_dev.reg_max_addr); -+ mutex_unlock(&aw87xxx->reg_lock); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_dev_i2c_write_byte(&aw87xxx->aw_dev, -+ databuf[0], databuf[1]); -+ if (ret < 0) -+ AW_DEV_LOGE(aw87xxx->dev, "set [0x%x]=0x%x failed", -+ databuf[0], databuf[1]); -+ else -+ AW_DEV_LOGD(aw87xxx->dev, "set [0x%x]=0x%x succeed", -+ databuf[0], databuf[1]); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "i2c write cmd input error"); -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_get_profile(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ unsigned int i = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ -+ if (!prof_info->status) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "profile_cfg not load\n"); -+ return len; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", aw87xxx->current_profile); -+ -+ for (i = 0; i < prof_info->count; i++) { -+ if (!strncmp(aw87xxx->current_profile, prof_info->prof_name_list[i], -+ AW_PROFILE_STR_MAX)) -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ ">%s\n", prof_info->prof_name_list[i]); -+ else -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ " %s\n", prof_info->prof_name_list[i]); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_profile(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ char profile[AW_PROFILE_STR_MAX] = {0}; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ if (strlen(buf) > AW_PROFILE_STR_MAX) { -+ AW_DEV_LOGE(aw87xxx->dev, "input profile_str_len is out of max[%d]", -+ AW_PROFILE_STR_MAX); -+ return -EINVAL; -+ } -+ -+ if (sscanf(buf, "%s", profile) == 1) { -+ AW_DEV_LOGD(aw87xxx->dev, "set profile [%s]", profile); -+ ret = aw87xxx_update_profile(aw87xxx, profile); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "set profile[%s] failed", -+ profile); -+ return ret; -+ } -+ } -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_get_hwen(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ int hwen = aw87xxx->aw_dev.hwen_status; -+ -+ if (hwen >= AW_DEV_HWEN_INVALID) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: invalid\n"); -+ else if (hwen == AW_DEV_HWEN_ON) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: on\n"); -+ else if (hwen == AW_DEV_HWEN_OFF) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: off\n"); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_hwen(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ int ret = -1; -+ unsigned int state; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ ret = kstrtouint(buf, 0, &state); -+ if (ret) { -+ AW_DEV_LOGE(aw87xxx->dev, "fail to channelge str to int"); -+ return ret; -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ if (state == AW_DEV_HWEN_OFF) -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); /*OFF*/ -+ else if (state == AW_DEV_HWEN_ON) -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); /*ON*/ -+ else -+ AW_DEV_LOGE(aw87xxx->dev, "input [%d] error, hwen_on=[%d],hwen_off=[%d]", -+ state, AW_DEV_HWEN_ON, AW_DEV_HWEN_OFF); -+ mutex_unlock(&aw87xxx->reg_lock); -+ return len; -+} -+ -+int aw87xxx_awrw_write(struct aw87xxx *aw87xxx, -+ const char *buf, size_t count) -+{ -+ int i = 0, ret = -1; -+ char *data_buf = NULL; -+ int buf_len = 0; -+ int temp_data = 0; -+ int data_str_size = 0; -+ char *reg_data; -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ /* one addr or one data string Composition of Contains two bytes of symbol(0X)*/ -+ /* and two byte of hexadecimal data*/ -+ data_str_size = 2 + 2 * AWRW_DATA_BYTES; -+ -+ /* The buf includes the first address of the register to be written and all data */ -+ buf_len = AWRW_ADDR_BYTES + packet->reg_num * AWRW_DATA_BYTES; -+ AW_DEV_LOGI(aw87xxx->dev, "buf_len = %d,reg_num = %d", buf_len, packet->reg_num); -+ data_buf = vmalloc(buf_len); -+ if (data_buf == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "alloc memory failed"); -+ return -ENOMEM; -+ } -+ memset(data_buf, 0, buf_len); -+ -+ data_buf[0] = packet->reg_addr; -+ reg_data = data_buf + 1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "reg_addr: 0x%02x", data_buf[0]); -+ -+ /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -+ for (i = 0; i < packet->reg_num; i++) { -+ ret = sscanf(buf + AWRW_HDR_LEN + 1 + i * (data_str_size + 1), -+ "0x%x", &temp_data); -+ if (ret != 1) { -+ AW_DEV_LOGE(aw87xxx->dev, "sscanf failed,ret=%d", ret); -+ vfree(data_buf); -+ data_buf = NULL; -+ return ret; -+ } -+ reg_data[i] = temp_data; -+ AW_DEV_LOGD(aw87xxx->dev, "[%d] : 0x%02x", i, reg_data[i]); -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ ret = i2c_master_send(aw87xxx->aw_dev.i2c, data_buf, buf_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "write failed"); -+ vfree(data_buf); -+ data_buf = NULL; -+ return -EFAULT; -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ vfree(data_buf); -+ data_buf = NULL; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "down"); -+ return 0; -+} -+ -+static int aw87xxx_awrw_data_check(struct aw87xxx *aw87xxx, -+ int *data, size_t count) -+{ -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int req_data_len = 0; -+ int act_data_len = 0; -+ int data_str_size = 0; -+ -+ if ((data[AWRW_HDR_ADDR_BYTES] != AWRW_ADDR_BYTES) || -+ (data[AWRW_HDR_DATA_BYTES] != AWRW_DATA_BYTES)) { -+ AW_DEV_LOGE(aw87xxx->dev, "addr_bytes [%d] or data_bytes [%d] unsupport", -+ data[AWRW_HDR_ADDR_BYTES], data[AWRW_HDR_DATA_BYTES]); -+ return -EINVAL; -+ } -+ -+ /* one data string Composition of Contains two bytes of symbol(0x)*/ -+ /* and two byte of hexadecimal data*/ -+ data_str_size = 2 + 2 * AWRW_DATA_BYTES; -+ act_data_len = count - AWRW_HDR_LEN - 1; -+ -+ /* There is a comma(,) or space between each piece of data */ -+ if (data[AWRW_HDR_WR_FLAG] == AWRW_FLAG_WRITE) { -+ /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -+ req_data_len = (data_str_size + 1) * packet->reg_num; -+ if (req_data_len > act_data_len) { -+ AW_DEV_LOGE(aw87xxx->dev, "data_len checkfailed,requeset data_len [%d],actaul data_len [%d]", -+ req_data_len, act_data_len); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+/* flag addr_bytes data_bytes reg_num reg_addr*/ -+static int aw87xxx_awrw_parse_buf(struct aw87xxx *aw87xxx, -+ const char *buf, size_t count, int *wr_status) -+{ -+ int data[AWRW_HDR_MAX] = {0}; -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int ret = -1; -+ -+ if (sscanf(buf, "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", -+ &data[AWRW_HDR_WR_FLAG], &data[AWRW_HDR_ADDR_BYTES], -+ &data[AWRW_HDR_DATA_BYTES], &data[AWRW_HDR_REG_NUM], -+ &data[AWRW_HDR_REG_ADDR]) == 5) { -+ -+ packet->reg_addr = data[AWRW_HDR_REG_ADDR]; -+ packet->reg_num = data[AWRW_HDR_REG_NUM]; -+ *wr_status = data[AWRW_HDR_WR_FLAG]; -+ ret = aw87xxx_awrw_data_check(aw87xxx, data, count); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+static ssize_t aw87xxx_attr_awrw_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int wr_status = 0; -+ int ret = -1; -+ -+ if (count < AWRW_HDR_LEN) { -+ AW_DEV_LOGE(aw87xxx->dev, "data count too smaller, please check write format"); -+ AW_DEV_LOGE(aw87xxx->dev, "string %s,count=%ld", -+ buf, (u_long)count); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "string:[%s],count=%ld", buf, (u_long)count); -+ ret = aw87xxx_awrw_parse_buf(aw87xxx, buf, count, &wr_status); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "can not parse string"); -+ return ret; -+ } -+ -+ if (wr_status == AWRW_FLAG_WRITE) { -+ ret = aw87xxx_awrw_write(aw87xxx, buf, count); -+ if (ret < 0) -+ return ret; -+ } else if (wr_status == AWRW_FLAG_READ) { -+ packet->status = AWRW_I2C_ST_READ; -+ AW_DEV_LOGI(aw87xxx->dev, "read_cmd:reg_addr[0x%02x], reg_num[%d]", -+ packet->reg_addr, packet->reg_num); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "please check str format, unsupport read_write_status: %d", -+ wr_status); -+ return -EINVAL; -+ } -+ -+ return count; -+} -+ -+static ssize_t aw87xxx_attr_awrw_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int data_len = 0; -+ size_t len = 0; -+ int ret = -1, i = 0; -+ char *reg_data = NULL; -+ -+ if (packet->status != AWRW_I2C_ST_READ) { -+ AW_DEV_LOGE(aw87xxx->dev, "please write read cmd first"); -+ return -EINVAL; -+ } -+ -+ data_len = AWRW_DATA_BYTES * packet->reg_num; -+ reg_data = (char *)vmalloc(data_len); -+ if (reg_data == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "memory alloc failed"); -+ ret = -EINVAL; -+ goto exit; -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ ret = aw87xxx_dev_i2c_read_msg(&aw87xxx->aw_dev, packet->reg_addr, -+ (char *)reg_data, data_len); -+ if (ret < 0) { -+ ret = -EFAULT; -+ mutex_unlock(&aw87xxx->reg_lock); -+ goto exit; -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ AW_DEV_LOGI(aw87xxx->dev, "reg_addr 0x%02x, reg_num %d", -+ packet->reg_addr, packet->reg_num); -+ -+ for (i = 0; i < data_len; i++) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "0x%02x,", reg_data[i]); -+ AW_DEV_LOGI(aw87xxx->dev, "0x%02x", reg_data[i]); -+ } -+ -+ ret = len; -+ -+exit: -+ if (reg_data) { -+ vfree(reg_data); -+ reg_data = NULL; -+ } -+ packet->status = AWRW_I2C_ST_NONE; -+ return ret; -+} -+ -+static ssize_t aw87xxx_drv_ver_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "driver_ver: %s \n", AW87XXX_DRIVER_VERSION); -+ -+ return len; -+} -+ -+static DEVICE_ATTR(reg, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_reg, aw87xxx_attr_set_reg); -+static DEVICE_ATTR(profile, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_profile, aw87xxx_attr_set_profile); -+static DEVICE_ATTR(hwen, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_hwen, aw87xxx_attr_set_hwen); -+static DEVICE_ATTR(awrw, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_awrw_show, aw87xxx_attr_awrw_store); -+static DEVICE_ATTR(drv_ver, S_IRUGO, aw87xxx_drv_ver_show, NULL); -+ -+static struct attribute *aw87xxx_attributes[] = { -+ &dev_attr_reg.attr, -+ &dev_attr_profile.attr, -+ &dev_attr_hwen.attr, -+ &dev_attr_awrw.attr, -+ &dev_attr_drv_ver.attr, -+ NULL -+}; -+ -+static struct attribute_group aw87xxx_attribute_group = { -+ .attrs = aw87xxx_attributes -+}; -+ -+/**************************************************************************** -+ * -+ *aw87xxx device probe -+ * -+ ****************************************************************************/ -+static const struct acpi_gpio_params reset_gpio = { 0, 0, false }; -+static const struct acpi_gpio_mapping reset_acpi_gpios[] = { -+ { "reset-gpios", &reset_gpio, 1 }, -+ { } -+}; -+ -+static struct aw87xxx *aw87xxx_malloc_init(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = NULL; -+ -+ aw87xxx = devm_kzalloc(&client->dev, sizeof(struct aw87xxx), -+ GFP_KERNEL); -+ if (aw87xxx == NULL) { -+ AW_DEV_LOGE(&client->dev, "failed to devm_kzalloc aw87xxx"); -+ return NULL; -+ } -+ memset(aw87xxx, 0, sizeof(struct aw87xxx)); -+ -+ aw87xxx->dev = &client->dev; -+ aw87xxx->aw_dev.dev = &client->dev; -+ aw87xxx->aw_dev.i2c_bus = client->adapter->nr; -+ aw87xxx->aw_dev.i2c_addr = client->addr; -+ aw87xxx->aw_dev.i2c = client; -+ aw87xxx->aw_dev.hwen_status = false; -+ aw87xxx->aw_dev.reg_access = NULL; -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -+ aw87xxx->off_bin_status = AW87XXX_NO_OFF_BIN; -+ aw87xxx->codec = NULL; -+ aw87xxx->current_profile = aw87xxx->prof_off_name; -+ -+ mutex_init(&aw87xxx->reg_lock); -+ -+ AW_DEV_LOGI(&client->dev, "struct aw87xxx devm_kzalloc and init down"); -+ return aw87xxx; -+} -+ -+static int aw87xxx_i2c_probe(struct i2c_client *client) -+{ -+ struct device_node *dev_node = client->dev.of_node; -+ struct aw87xxx *aw87xxx = NULL; -+ struct gpio_desc *gpiod = NULL; -+ int ret = -1; -+ -+ -+// To do, add this function -+//acpi_dev_add_driver_gpios() -+ -+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { -+ AW_DEV_LOGE(&client->dev, "check_functionality failed"); -+ ret = -ENODEV; -+ goto exit_check_functionality_failed; -+ } -+ -+ /* aw87xxx i2c_dev struct init */ -+ aw87xxx = aw87xxx_malloc_init(client); -+ if (aw87xxx == NULL) -+ goto exit_malloc_init_failed; -+ -+ i2c_set_clientdata(client, aw87xxx); -+ -+ aw87xxx_device_parse_port_id_dt(&aw87xxx->aw_dev); -+ aw87xxx_device_parse_topo_id_dt(&aw87xxx->aw_dev); -+ -+ /* aw87xxx Get ACPI GPIO */ -+/* -+ ret = devm_acpi_dev_add_driver_gpios(aw87xxx->dev, reset_acpi_gpios); -+ if(ret){ -+ AW_DEV_LOGE(aw87xxx->dev, "Unable to add GPIO mapping table"); -+ goto exit_device_init_failed; -+ } -+ -+ gpiod = gpiod_get_optional(aw87xxx->dev, "reset", GPIOD_OUT_LOW); -+ if (IS_ERR(gpiod)){ -+ AW_DEV_LOGE(aw87xxx->dev, "Get gpiod failed"); -+ goto exit_device_init_failed; -+ } -+ -+ aw87xxx->aw_dev.rst_gpio = desc_to_gpio(gpiod); -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_OFF; -+ AW_DEV_LOGI(aw87xxx->dev, "reset gpio[%d] parse succeed", aw87xxx->aw_dev.rst_gpio); -+ if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio)) { -+ ret = devm_gpio_request_one(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio, GPIOF_OUT_INIT_LOW, "aw87xxx_reset"); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "reset request failed"); -+ goto exit_device_init_failed; -+ } -+ } -+*/ -+ -+ /*Disabling RESET GPIO*/ -+ AW_DEV_LOGI(aw87xxx->dev, "no reset gpio provided, hardware reset unavailable"); -+ aw87xxx->aw_dev.rst_gpio = AW_NO_RESET_GPIO; -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -+ -+ -+ /*hw power on PA*/ -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ -+ /* aw87xxx devices private attributes init */ -+ ret = aw87xxx_dev_init(&aw87xxx->aw_dev); -+ if (ret < 0) -+ goto exit_device_init_failed; -+ -+ /*product register reset */ -+ aw87xxx_dev_soft_reset(&aw87xxx->aw_dev); -+ -+ /*hw power off */ -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ -+ /* create debug attrbute nodes */ -+ ret = sysfs_create_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -+ if (ret < 0) -+ AW_DEV_LOGE(aw87xxx->dev, "failed to create sysfs nodes, will not allowed to use"); -+ -+ /* cfg_load init */ -+ aw87xxx_fw_load_init(aw87xxx); -+ -+ /*monitor init*/ -+ aw87xxx_monitor_init(aw87xxx->dev, &aw87xxx->monitor, dev_node); -+ -+ /*add device to total list */ -+ mutex_lock(&g_aw87xxx_mutex_lock); -+ g_aw87xxx_dev_cnt++; -+ list_add(&aw87xxx->list, &g_aw87xxx_list); -+ aw87xxx->dev_index = g_aw87xxx_dev_cnt; -+ -+ mutex_unlock(&g_aw87xxx_mutex_lock); -+ AW_DEV_LOGI(aw87xxx->dev, "succeed, dev_index=[%d], g_aw87xxx_dev_cnt= [%d]", -+ aw87xxx->dev_index, g_aw87xxx_dev_cnt); -+ -+ return 0; -+ -+exit_device_init_failed: -+ AW_DEV_LOGE(aw87xxx->dev, "pa init failed"); -+ -+ devm_kfree(&client->dev, aw87xxx); -+ aw87xxx = NULL; -+exit_malloc_init_failed: -+exit_check_functionality_failed: -+ return ret; -+} -+ -+static void aw87xxx_i2c_remove(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -+ -+ aw87xxx_monitor_exit(&aw87xxx->monitor); -+ -+ /*rm attr node*/ -+ sysfs_remove_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -+ -+ aw87xxx_fw_cfg_free(aw87xxx); -+ -+ mutex_lock(&g_aw87xxx_mutex_lock); -+ g_aw87xxx_dev_cnt--; -+ list_del(&aw87xxx->list); -+ mutex_unlock(&g_aw87xxx_mutex_lock); -+ -+ devm_kfree(&client->dev, aw87xxx); -+ aw87xxx = NULL; -+ -+// return 0; -+} -+ -+static void aw87xxx_i2c_shutdown(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -+ -+ AW_DEV_LOGI(&client->dev, "enter"); -+ -+ /*soft and hw power off*/ -+ aw87xxx_update_profile(aw87xxx, aw87xxx->prof_off_name); -+} -+ -+static const struct acpi_device_id aw87xxx_acpi_match[] = { -+ { "AWDZ8830", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(acpi, aw87xxx_acpi_match); -+ -+// This is not necessary if the acpi match probes correctly. This is needed for userspace `new_device() functionality -+static const struct i2c_device_id aw87xxx_i2c_id[] = { -+ {AW87XXX_I2C_NAME, 0}, -+ {}, -+}; -+ -+static struct i2c_driver aw87xxx_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = AW87XXX_I2C_NAME, -+ .acpi_match_table = aw87xxx_acpi_match, -+ }, -+ .probe = aw87xxx_i2c_probe, -+ .remove = aw87xxx_i2c_remove, -+ .shutdown = aw87xxx_i2c_shutdown, -+ .id_table = aw87xxx_i2c_id, -+}; -+ -+module_i2c_driver(aw87xxx_i2c_driver) -+ -+MODULE_AUTHOR("<zhaozhongbo@awinic.com>"); -+MODULE_DESCRIPTION("awinic aw87xxx pa driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx.h b/sound/soc/codecs/aw87xxx/aw87xxx.h -new file mode 100644 -index 000000000..45d3cea77 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx.h -@@ -0,0 +1,121 @@ -+#ifndef __AW87XXX_H__ -+#define __AW87XXX_H__ -+#include <linux/version.h> -+#include <linux/kernel.h> -+#include <sound/control.h> -+#include <sound/soc.h> -+ -+#include "aw87xxx_device.h" -+#include "aw87xxx_monitor.h" -+#include "aw87xxx_acf_bin.h" -+ -+#define AW_CFG_UPDATE_DELAY -+#define AW_CFG_UPDATE_DELAY_TIMER (3000) -+ -+#define AW87XXX_NO_OFF_BIN (0) -+#define AW87XXX_OFF_BIN_OK (1) -+ -+#define AW87XXX_PRIVATE_KCONTROL_NUM (3) -+#define AW87XXX_PUBLIC_KCONTROL_NUM (1) -+ -+#define AW_I2C_RETRIES (5) -+#define AW_I2C_RETRY_DELAY (2) -+#define AW_I2C_READ_MSG_NUM (2) -+ -+#define AW87XXX_FW_NAME_MAX (64) -+#define AW_NAME_BUF_MAX (64) -+#define AW_LOAD_FW_RETRIES (3) -+ -+#define AW_DEV_REG_RD_ACCESS (1 << 0) -+#define AW_DEV_REG_WR_ACCESS (1 << 1) -+ -+#define AWRW_ADDR_BYTES (1) -+#define AWRW_DATA_BYTES (1) -+#define AWRW_HDR_LEN (24) -+ -+/*********************************************************** -+ * -+ * aw87xxx codec control compatible with kernel 4.19 -+ * -+ ***********************************************************/ -+#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 1) -+#define AW_KERNEL_VER_OVER_4_19_1 -+#endif -+ -+#ifdef AW_KERNEL_VER_OVER_4_19_1 -+typedef struct snd_soc_component aw_snd_soc_codec_t; -+#else -+typedef struct snd_soc_codec aw_snd_soc_codec_t; -+#endif -+ -+struct aw_componet_codec_ops { -+ int (*add_codec_controls)(aw_snd_soc_codec_t *codec, -+ const struct snd_kcontrol_new *controls, unsigned int num_controls); -+ void (*unregister_codec)(struct device *dev); -+}; -+ -+ -+/******************************************** -+ * -+ * aw87xxx devices attributes -+ * -+ *******************************************/ -+enum { -+ AWRW_FLAG_WRITE = 0, -+ AWRW_FLAG_READ, -+}; -+ -+enum { -+ AWRW_I2C_ST_NONE = 0, -+ AWRW_I2C_ST_READ, -+ AWRW_I2C_ST_WRITE, -+}; -+ -+enum { -+ AWRW_HDR_WR_FLAG = 0, -+ AWRW_HDR_ADDR_BYTES, -+ AWRW_HDR_DATA_BYTES, -+ AWRW_HDR_REG_NUM, -+ AWRW_HDR_REG_ADDR, -+ AWRW_HDR_MAX, -+}; -+ -+struct aw_i2c_packet { -+ char status; -+ unsigned int reg_num; -+ unsigned int reg_addr; -+ char *reg_data; -+}; -+ -+ -+/******************************************** -+ * -+ * aw87xxx device struct -+ * -+ *******************************************/ -+struct aw87xxx { -+ char fw_name[AW87XXX_FW_NAME_MAX]; -+ int32_t dev_index; -+ char *current_profile; -+ char prof_off_name[AW_PROFILE_STR_MAX]; -+ uint32_t off_bin_status; -+ struct device *dev; -+ -+ struct mutex reg_lock; -+ struct aw_device aw_dev; -+ struct aw_i2c_packet i2c_packet; -+ -+ struct delayed_work fw_load_work; -+ struct acf_bin_info acf_info; -+ -+ aw_snd_soc_codec_t *codec; -+ -+ struct list_head list; -+ -+ struct aw_monitor monitor; -+}; -+ -+int aw87xxx_update_profile(struct aw87xxx *aw87xxx, char *profile); -+int aw87xxx_update_profile_esd(struct aw87xxx *aw87xxx, char *profile); -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.c b/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.c -new file mode 100644 -index 000000000..00c7aedb7 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.c -@@ -0,0 +1,1558 @@ -+/* -+ * aw87xxx_acf_bin.c -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include <linux/module.h> -+#include <asm/uaccess.h> -+#include <linux/delay.h> -+#include <linux/slab.h> -+#include <linux/kernel.h> -+#include <linux/fs.h> -+#include <linux/device.h> -+#include <linux/kernel.h> -+#include <linux/vmalloc.h> -+#include "aw87xxx.h" -+#include "aw87xxx_acf_bin.h" -+#include "aw87xxx_monitor.h" -+#include "aw87xxx_log.h" -+#include "aw87xxx_bin_parse.h" -+ -+/************************************************************************* -+ * -+ *Table corresponding to customized profile ids to profile names -+ * -+ *************************************************************************/ -+enum aw_customers_profile_id { -+ AW_CTOS_PROFILE_OFF = 0, -+ AW_CTOS_PROFILE_MUSIC, -+ AW_CTOS_PROFILE_VOICE, -+ AW_CTOS_PROFILE_VOIP, -+ AW_CTOS_PROFILE_RINGTONE, -+ AW_CTOS_PROFILE_RINGTONE_HS, -+ AW_CTOS_PROFILE_LOWPOWER, -+ AW_CTOS_PROFILE_BYPASS, -+ AW_CTOS_PROFILE_MMI, -+ AW_CTOS_PROFILE_FM, -+ AW_CTOS_PROFILE_NOTIFICATION, -+ AW_CTOS_PROFILE_RECEIVER, -+ AW_CTOS_PROFILE_MAX, -+}; -+ -+static char *g_ctos_profile_name[AW_PROFILE_MAX] = { -+ [AW_CTOS_PROFILE_OFF] = "Off", -+ [AW_CTOS_PROFILE_MUSIC] = "Music", -+ [AW_CTOS_PROFILE_VOICE] = "Voice", -+ [AW_CTOS_PROFILE_VOIP] = "Voip", -+ [AW_CTOS_PROFILE_RINGTONE] = "Ringtone", -+ [AW_CTOS_PROFILE_RINGTONE_HS] = "Ringtone_hs", -+ [AW_CTOS_PROFILE_LOWPOWER] = "Lowpower", -+ [AW_CTOS_PROFILE_BYPASS] = "Bypass", -+ [AW_CTOS_PROFILE_MMI] = "Mmi", -+ [AW_CTOS_PROFILE_FM] = "Fm", -+ [AW_CTOS_PROFILE_NOTIFICATION] = "Notification", -+ [AW_CTOS_PROFILE_RECEIVER] = "Receiver", -+}; -+ -+ -+char *aw87xxx_ctos_get_prof_name(int profile_id) -+{ -+ if (profile_id < 0 || profile_id >= AW_CTOS_PROFILE_MAX) -+ return NULL; -+ else -+ return g_ctos_profile_name[profile_id]; -+} -+ -+ -+static char *g_profile_name[] = {"Music", "Voice", "Voip", -+ "Ringtone", "Ringtone_hs", "Lowpower", "Bypass", "Mmi", -+ "Fm", "Notification", "Receiver", "Off"}; -+ -+static char *g_power_off_name[] = {"Off", "OFF", "off", "oFF", "power_down"}; -+ -+static char *aw_get_prof_name(int profile) -+{ -+ if (profile < 0 || profile >= AW_PROFILE_MAX) -+ return "NULL"; -+ else -+ return g_profile_name[profile]; -+} -+ -+/************************************************************************* -+ * -+ *acf check -+ * -+ *************************************************************************/ -+static int aw_crc8_check(const unsigned char *data, unsigned int data_size) -+ -+{ -+ unsigned char crc_value = 0x00; -+ unsigned char *pdata; -+ int i; -+ unsigned char pdatabuf = 0; -+ -+ pdata = (unsigned char *)data; -+ -+ while (data_size--) { -+ pdatabuf = *pdata++; -+ for (i = 0; i < 8; i++) { -+ if ((crc_value ^ (pdatabuf)) & 0x01) { -+ crc_value ^= 0x18; -+ crc_value >>= 1; -+ crc_value |= 0x80; -+ } else { -+ crc_value >>= 1; -+ } -+ pdatabuf >>= 1; -+ } -+ } -+ -+ return (int)crc_value; -+} -+ -+static int aw_check_file_id(struct device *dev, -+ char *fw_data, int32_t file_id) -+{ -+ int32_t *acf_file_id = NULL; -+ -+ acf_file_id = (int32_t *)fw_data; -+ if (*acf_file_id != file_id) { -+ AW_DEV_LOGE(dev, "file id [%x] check failed", *acf_file_id); -+ return -ENFILE; -+ } -+ -+ return 0; -+} -+ -+static int aw_check_header_size(struct device *dev, -+ char *fw_data, size_t fw_size) -+{ -+ if (fw_size < sizeof(struct aw_acf_hdr)) { -+ AW_DEV_LOGE(dev, "acf size check failed,size less-than aw_acf_hdr"); -+ return -ENOEXEC; -+ } -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * V0.0.0.1 version acf check -+ **************************************************************************/ -+static int aw_check_ddt_size_v_0_0_0_1(struct device *dev, char *fw_data) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)fw_data; -+ struct aw_acf_dde *acf_dde = NULL; -+ -+ acf_dde = (struct aw_acf_dde *)(fw_data + acf_hdr->ddt_offset); -+ -+ /* check ddt_size in acf_header is aqual to ddt_num multiply by dde_size */ -+ if (acf_hdr->ddt_size != acf_hdr->dde_num * sizeof(struct aw_acf_dde)) { -+ AW_DEV_LOGE(dev, "acf ddt size check failed"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_check_data_size_v_0_0_0_1(struct device *dev, -+ char *fw_data, size_t fw_size) -+{ -+ int i = 0; -+ size_t data_size = 0; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ struct aw_acf_dde *acf_dde = NULL; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ acf_dde = (struct aw_acf_dde *)(fw_data + acf_hdr->ddt_offset); -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (acf_dde[i].data_size % 2) { -+ AW_DEV_LOGE(dev, "acf dde[%d].data_size[%d],dev_name[%s],data_type[%d], data_size check failed", -+ i, acf_dde[i].data_size, acf_dde[i].dev_name, -+ acf_dde[i].data_type); -+ return -EINVAL; -+ } -+ data_size += acf_dde[i].data_size; -+ } -+ -+ /* Verify that the file size is equal to the header size plus */ -+ /* the table size and data size */ -+ if (fw_size != data_size + sizeof(struct aw_acf_hdr) + acf_hdr->ddt_size) { -+ AW_DEV_LOGE(dev, "acf size check failed"); -+ AW_DEV_LOGE(dev, "fw_size=%ld,hdr_size and ddt size and data size =%ld", -+ (u_long)fw_size, (u_long)(data_size + sizeof(struct aw_acf_hdr) + -+ acf_hdr->ddt_size)); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_check_data_crc_v_0_0_0_1(struct device *dev, char *fw_data) -+{ -+ int i = 0; -+ size_t crc_val = 0; -+ char *data = NULL; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ struct aw_acf_dde *acf_dde = NULL; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ acf_dde = (struct aw_acf_dde *)(fw_data + acf_hdr->ddt_offset); -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ data = fw_data + acf_dde[i].data_offset; -+ crc_val = aw_crc8_check(data, acf_dde[i].data_size); -+ if (crc_val != acf_dde[i].data_crc) { -+ AW_DEV_LOGE(dev, "acf dde_crc check failed"); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static int aw_check_profile_id_v_0_0_0_1(struct device *dev, char *fw_data) -+{ -+ int i = 0; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ struct aw_acf_dde *acf_dde = NULL; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ acf_dde = (struct aw_acf_dde *)(fw_data + acf_hdr->ddt_offset); -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (acf_dde[i].data_type == AW_MONITOR) -+ continue; -+ if (acf_dde[i].dev_profile > AW_PROFILE_MAX) { -+ AW_DEV_LOGE(dev, "parse profile_id[%d] failed", acf_dde[i].dev_profile); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+static int aw_check_data_v_0_0_0_1(struct device *dev, -+ char *fw_data, size_t size) -+{ -+ int ret = -1; -+ -+ /* check file type id is awinic acf file */ -+ ret = aw_check_file_id(dev, fw_data, AW_ACF_FILE_ID); -+ if (ret < 0) -+ return ret; -+ -+ /* check ddt_size in header is equal to all ddt aize */ -+ ret = aw_check_ddt_size_v_0_0_0_1(dev, fw_data); -+ if (ret < 0) -+ return ret; -+ -+ /* Verify that the file size is equal to the header size plus */ -+ /* the table size and data size */ -+ ret = aw_check_data_size_v_0_0_0_1(dev, fw_data, size); -+ if (ret < 0) -+ return ret; -+ -+ /* check crc in is equal to dde data crc */ -+ ret = aw_check_data_crc_v_0_0_0_1(dev, fw_data); -+ if (ret < 0) -+ return ret; -+ -+ /* check profile id is in profile_id_max */ -+ ret = aw_check_profile_id_v_0_0_0_1(dev, fw_data); -+ if (ret < 0) -+ return ret; -+ -+ AW_DEV_LOGI(dev, "acf fimware check succeed"); -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * V1.0.0.0 version acf chack -+ **************************************************************************/ -+static int aw_check_ddt_size_v_1_0_0_0(struct device *dev, char *fw_data) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)fw_data; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = NULL; -+ -+ acf_dde = (struct aw_acf_dde_v_1_0_0_0 *)(fw_data + acf_hdr->ddt_offset); -+ -+ /* check ddt_size in acf_header is aqual to ddt_num multiply by dde_size */ -+ if (acf_hdr->ddt_size != acf_hdr->dde_num * sizeof(struct aw_acf_dde_v_1_0_0_0)) { -+ AW_DEV_LOGE(dev, "acf ddt size check failed"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_check_data_size_v_1_0_0_0(struct device *dev, -+ char *fw_data, size_t fw_size) -+{ -+ int i = 0; -+ size_t data_size = 0; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = NULL; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ acf_dde = (struct aw_acf_dde_v_1_0_0_0 *)(fw_data + acf_hdr->ddt_offset); -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (acf_dde[i].data_size % 2) { -+ AW_DEV_LOGE(dev, "acf dde[%d].data_size[%d],dev_name[%s],data_type[%d], data_size check failed", -+ i, acf_dde[i].data_size, acf_dde[i].dev_name, -+ acf_dde[i].data_type); -+ return -EINVAL; -+ } -+ data_size += acf_dde[i].data_size; -+ } -+ -+ /* Verify that the file size is equal to the header size plus */ -+ /* the table size and data size */ -+ if (fw_size != data_size + sizeof(struct aw_acf_hdr) + acf_hdr->ddt_size) { -+ AW_DEV_LOGE(dev, "acf size check failed"); -+ AW_DEV_LOGE(dev, "fw_size=%ld,hdr_size and ddt size and data size =%ld", -+ (u_long)fw_size, (u_long)(data_size + sizeof(struct aw_acf_hdr) + -+ acf_hdr->ddt_size)); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_check_data_crc_v_1_0_0_0(struct device *dev, char *fw_data) -+{ -+ int i = 0; -+ size_t crc_val = 0; -+ char *data = NULL; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = NULL; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ acf_dde = (struct aw_acf_dde_v_1_0_0_0 *)(fw_data + acf_hdr->ddt_offset); -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ data = fw_data + acf_dde[i].data_offset; -+ crc_val = aw_crc8_check(data, acf_dde[i].data_size); -+ if (crc_val != acf_dde[i].data_crc) { -+ AW_DEV_LOGE(dev, "acf dde_crc check failed"); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+static int aw_check_data_v_1_0_0_0(struct device *dev, -+ char *fw_data, size_t size) -+{ -+ int ret = -1; -+ -+ /* check file type id is awinic acf file */ -+ ret = aw_check_file_id(dev, fw_data, AW_ACF_FILE_ID); -+ if (ret < 0) -+ return ret; -+ -+ /* check ddt_size in header is equal to all ddt aize */ -+ ret = aw_check_ddt_size_v_1_0_0_0(dev, fw_data); -+ if (ret < 0) -+ return ret; -+ -+ /* Verify that the file size is equal to the header size plus */ -+ /* the table size and data size */ -+ ret = aw_check_data_size_v_1_0_0_0(dev, fw_data, size); -+ if (ret < 0) -+ return ret; -+ -+ /* check crc in is equal to dde data crc */ -+ ret = aw_check_data_crc_v_1_0_0_0(dev, fw_data); -+ if (ret < 0) -+ return ret; -+ -+ AW_DEV_LOGI(dev, "acf fimware check succeed"); -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * acf chack API -+ **************************************************************************/ -+static int aw_check_acf_firmware(struct device *dev, -+ char *fw_data, size_t size) -+{ -+ int ret = -1; -+ struct aw_acf_hdr *acf_hdr = NULL; -+ -+ if (fw_data == NULL) { -+ AW_DEV_LOGE(dev, "fw_data is NULL,fw_data check failed"); -+ return -ENODATA; -+ } -+ -+ /* check file size is less-than header size */ -+ ret = aw_check_header_size(dev, fw_data, size); -+ if (ret < 0) -+ return ret; -+ -+ acf_hdr = (struct aw_acf_hdr *)fw_data; -+ AW_DEV_LOGI(dev, "project name: [%s]", acf_hdr->project); -+ AW_DEV_LOGI(dev, "custom name: [%s]", acf_hdr->custom); -+ AW_DEV_LOGI(dev, "version name: [%s]", acf_hdr->version); -+ AW_DEV_LOGI(dev, "author_id: [%d]", acf_hdr->author_id); -+ -+ switch (acf_hdr->hdr_version) { -+ case AW_ACF_HDR_VER_0_0_0_1: -+ return aw_check_data_v_0_0_0_1(dev, fw_data, size); -+ case AW_ACF_HDR_VER_1_0_0_0: -+ return aw_check_data_v_1_0_0_0(dev, fw_data, size); -+ default: -+ AW_DEV_LOGE(dev, "unsupported hdr_version [0x%x]", -+ acf_hdr->hdr_version); -+ return -EINVAL; -+ } -+ -+ return ret; -+} -+ -+ -+ -+/************************************************************************* -+ * -+ *acf parse -+ * -+ *************************************************************************/ -+static int aw_parse_raw_reg(struct device *dev, uint8_t *data, -+ uint32_t data_len, struct aw_prof_desc *prof_desc) -+{ -+ AW_DEV_LOGD(dev, "data_size:%d enter", data_len); -+ -+ prof_desc->data_container.data = data; -+ prof_desc->data_container.len = data_len; -+ -+ prof_desc->prof_st = AW_PROFILE_OK; -+ -+ return 0; -+} -+ -+static int aw_parse_reg_with_hdr(struct device *dev, uint8_t *data, -+ uint32_t data_len, struct aw_prof_desc *prof_desc) -+{ -+ struct aw_bin *aw_bin = NULL; -+ int ret = -1; -+ -+ AW_DEV_LOGD(dev, "data_size:%d enter", data_len); -+ -+ aw_bin = kzalloc(data_len + sizeof(struct aw_bin), GFP_KERNEL); -+ if (aw_bin == NULL) { -+ AW_DEV_LOGE(dev, "devm_kzalloc aw_bin failed"); -+ return -ENOMEM; -+ } -+ -+ aw_bin->info.len = data_len; -+ memcpy(aw_bin->info.data, data, data_len); -+ -+ ret = aw87xxx_parsing_bin_file(aw_bin); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse bin failed"); -+ goto parse_bin_failed; -+ } -+ -+ if ((aw_bin->all_bin_parse_num != 1) || -+ (aw_bin->header_info[0].bin_data_type != DATA_TYPE_REGISTER)) { -+ AW_DEV_LOGE(dev, "bin num or type error"); -+ goto parse_bin_failed; -+ } -+ -+ prof_desc->data_container.data = -+ data + aw_bin->header_info[0].valid_data_addr; -+ prof_desc->data_container.len = aw_bin->header_info[0].valid_data_len; -+ prof_desc->prof_st = AW_PROFILE_OK; -+ -+ kfree(aw_bin); -+ aw_bin = NULL; -+ -+ return 0; -+ -+parse_bin_failed: -+ kfree(aw_bin); -+ aw_bin = NULL; -+ return ret; -+} -+ -+static int aw_parse_monitor_config(struct device *dev, -+ char *monitor_data, uint32_t data_len) -+{ -+ int ret = -1; -+ -+ if (monitor_data == NULL || data_len == 0) { -+ AW_DEV_LOGE(dev, "no data to parse"); -+ return -EBFONT; -+ } -+ -+ ret = aw87xxx_monitor_bin_parse(dev, monitor_data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "monitor_config parse failed"); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(dev, "monitor_bin parse succeed"); -+ -+ return 0; -+} -+ -+static int aw_check_prof_str_is_off(char *profile_name) -+{ -+ int i = 0; -+ -+ for (i = 0; i < AW_POWER_OFF_NAME_SUPPORT_COUNT; i++) { -+ if (strnstr(profile_name, g_power_off_name[i], -+ strlen(profile_name) + 1)) -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+/*************************************************************************** -+ * V0.0.0.1 version acf paese -+ **************************************************************************/ -+static int aw_check_product_name_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_acf_dde *prof_hdr) -+{ -+ int i = 0; -+ -+ for (i = 0; i < acf_info->product_cnt; i++) { -+ if (0 == strcmp(acf_info->product_tab[i], prof_hdr->dev_name)) { -+ AW_DEV_LOGD(dev, "bin_dev_name:%s", -+ prof_hdr->dev_name); -+ return 0; -+ } -+ } -+ -+ return -ENXIO; -+} -+ -+static int aw_check_data_type_is_monitor_v_0_0_0_1(struct device *dev, -+ struct aw_acf_dde *prof_hdr) -+{ -+ if (prof_hdr->data_type == AW_MONITOR) { -+ AW_DEV_LOGD(dev, "bin data is monitor"); -+ return 0; -+ } -+ -+ return -ENXIO; -+} -+ -+static int aw_parse_data_by_sec_type_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_acf_dde *prof_hdr, -+ struct aw_prof_desc *profile_prof_desc) -+{ -+ int ret = -1; -+ char *cfg_data = acf_info->fw_data + prof_hdr->data_offset; -+ -+ switch (prof_hdr->data_type) { -+ case AW_BIN_TYPE_REG: -+ snprintf(profile_prof_desc->dev_name, sizeof(prof_hdr->dev_name), -+ "%s", prof_hdr->dev_name); -+ profile_prof_desc->prof_name = aw_get_prof_name(prof_hdr->dev_profile); -+ AW_DEV_LOGD(dev, "parse reg type data enter,profile=%s", -+ aw_get_prof_name(prof_hdr->dev_profile)); -+ ret = aw_parse_raw_reg(dev, cfg_data, prof_hdr->data_size, -+ profile_prof_desc); -+ break; -+ case AW_BIN_TYPE_HDR_REG: -+ snprintf(profile_prof_desc->dev_name, sizeof(prof_hdr->dev_name), -+ "%s", prof_hdr->dev_name); -+ profile_prof_desc->prof_name = aw_get_prof_name(prof_hdr->dev_profile); -+ AW_DEV_LOGD(dev, "parse hdr_reg type data enter,profile=%s", -+ aw_get_prof_name(prof_hdr->dev_profile)); -+ ret = aw_parse_reg_with_hdr(dev, cfg_data, -+ prof_hdr->data_size, -+ profile_prof_desc); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int aw_parse_dev_type_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, struct aw_all_prof_info *all_prof_info) -+{ -+ int i = 0; -+ int ret = -1; -+ int sec_num = 0; -+ char *cfg_data = NULL; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_acf_dde *acf_dde = -+ (struct aw_acf_dde *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset); -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ for (i = 0; i < acf_info->acf_hdr.dde_num; i++) { -+ if ((acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) && -+ (acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr) && -+ (acf_dde[i].type == AW_DDE_DEV_TYPE_ID)) { -+ -+ ret = aw_check_product_name_v_0_0_0_1(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ ret = aw_check_data_type_is_monitor_v_0_0_0_1(dev, &acf_dde[i]); -+ if (ret == 0) { -+ cfg_data = acf_info->fw_data + acf_dde[i].data_offset; -+ ret = aw_parse_monitor_config(dev, cfg_data, acf_dde[i].data_size); -+ if (ret < 0) -+ return ret; -+ continue; -+ } -+ -+ prof_desc = &all_prof_info->prof_desc[acf_dde[i].dev_profile]; -+ ret = aw_parse_data_by_sec_type_v_0_0_0_1(dev, acf_info, &acf_dde[i], -+ prof_desc); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse dev type data failed"); -+ return ret; -+ } -+ sec_num++; -+ } -+ } -+ -+ if (sec_num == 0) { -+ AW_DEV_LOGD(dev, "get dev type num is %d, please use default", -+ sec_num); -+ return AW_DEV_TYPE_NONE; -+ } -+ -+ return AW_DEV_TYPE_OK; -+} -+ -+static int aw_parse_default_type_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, struct aw_all_prof_info *all_prof_info) -+{ -+ int i = 0; -+ int ret = -1; -+ int sec_num = 0; -+ char *cfg_data = NULL; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_acf_dde *acf_dde = -+ (struct aw_acf_dde *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset); -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ for (i = 0; i < acf_info->acf_hdr.dde_num; i++) { -+ if ((acf_info->dev_index == acf_dde[i].dev_index) && -+ (acf_dde[i].type == AW_DDE_DEV_DEFAULT_TYPE_ID)) { -+ -+ ret = aw_check_product_name_v_0_0_0_1(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ ret = aw_check_data_type_is_monitor_v_0_0_0_1(dev, &acf_dde[i]); -+ if (ret == 0) { -+ cfg_data = acf_info->fw_data + acf_dde[i].data_offset; -+ ret = aw_parse_monitor_config(dev, cfg_data, acf_dde[i].data_size); -+ if (ret < 0) -+ return ret; -+ continue; -+ } -+ -+ prof_desc = &all_prof_info->prof_desc[acf_dde[i].dev_profile]; -+ ret = aw_parse_data_by_sec_type_v_0_0_0_1(dev, acf_info, &acf_dde[i], -+ prof_desc); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse default type data failed"); -+ return ret; -+ } -+ sec_num++; -+ } -+ } -+ -+ if (sec_num == 0) { -+ AW_DEV_LOGE(dev, "get dev default type failed, get num[%d]", -+ sec_num); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_get_prof_count_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_all_prof_info *all_prof_info) -+{ -+ int i = 0; -+ int prof_count = 0; -+ struct aw_prof_desc *prof_desc = all_prof_info->prof_desc; -+ -+ for (i = 0; i < AW_PROFILE_MAX; i++) { -+ if (prof_desc[i].prof_st == AW_PROFILE_OK) { -+ prof_count++; -+ } else if (i == AW_PROFILE_OFF) { -+ prof_count++; -+ AW_DEV_LOGI(dev, "not found profile [Off], set default"); -+ } -+ } -+ -+ AW_DEV_LOGI(dev, "get profile count=[%d]", prof_count); -+ return prof_count; -+} -+ -+static int aw_set_prof_off_info_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_all_prof_info *all_prof_info, -+ int index) -+{ -+ struct aw_prof_desc *prof_desc = all_prof_info->prof_desc; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ if (index >= prof_info->count) { -+ AW_DEV_LOGE(dev, "index[%d] is out of table,profile count[%d]", -+ index, prof_info->count); -+ return -EINVAL; -+ } -+ -+ if (prof_desc[AW_PROFILE_OFF].prof_st == AW_PROFILE_OK) { -+ prof_info->prof_desc[index] = prof_desc[AW_PROFILE_OFF]; -+ AW_DEV_LOGI(dev, "product=[%s]----profile=[%s]", -+ prof_info->prof_desc[index].dev_name, -+ aw_get_prof_name(AW_PROFILE_OFF)); -+ } else { -+ memset(&prof_info->prof_desc[index].data_container, 0, -+ sizeof(struct aw_data_container)); -+ prof_info->prof_desc[index].prof_st = AW_PROFILE_WAIT; -+ prof_info->prof_desc[index].prof_name = aw_get_prof_name(AW_PROFILE_OFF); -+ AW_DEV_LOGI(dev, "set default power_off with no data to profile"); -+ } -+ -+ return 0; -+} -+ -+ -+static int aw_get_vaild_prof_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_all_prof_info *all_prof_info) -+{ -+ int i = 0; -+ int ret = 0; -+ int index = 0; -+ struct aw_prof_desc *prof_desc = all_prof_info->prof_desc; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ prof_info->count = 0; -+ ret = aw_get_prof_count_v_0_0_0_1(dev, acf_info, all_prof_info); -+ if (ret < 0) -+ return ret; -+ prof_info->count = ret; -+ prof_info->prof_desc = devm_kzalloc(dev, -+ prof_info->count * sizeof(struct aw_prof_desc), -+ GFP_KERNEL); -+ if (prof_info->prof_desc == NULL) { -+ AW_DEV_LOGE(dev, "prof_desc kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < AW_PROFILE_MAX; i++) { -+ if (i != AW_PROFILE_OFF && prof_desc[i].prof_st == AW_PROFILE_OK) { -+ if (index >= prof_info->count) { -+ AW_DEV_LOGE(dev, "get profile index[%d] overflow count[%d]", -+ index, prof_info->count); -+ return -ENOMEM; -+ } -+ prof_info->prof_desc[index] = prof_desc[i]; -+ AW_DEV_LOGI(dev, "product=[%s]----profile=[%s]", -+ prof_info->prof_desc[index].dev_name, -+ aw_get_prof_name(i)); -+ index++; -+ } -+ } -+ -+ ret = aw_set_prof_off_info_v_0_0_0_1(dev, acf_info, all_prof_info, index); -+ if (ret < 0) -+ return ret; -+ -+ AW_DEV_LOGD(dev, "get vaild profile succeed"); -+ return 0; -+} -+ -+static int aw_set_prof_name_list_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int i = 0; -+ int count = acf_info->prof_info.count; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ prof_info->prof_name_list = (char (*)[AW_PROFILE_STR_MAX])devm_kzalloc(dev, -+ count * (AW_PROFILE_STR_MAX), GFP_KERNEL); -+ if (prof_info->prof_name_list == NULL) { -+ AW_DEV_LOGE(dev, "prof_name_list devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ for (i = 0; i < count; ++i) { -+ snprintf(prof_info->prof_name_list[i], AW_PROFILE_STR_MAX, "%s", -+ prof_info->prof_desc[i].prof_name); -+ AW_DEV_LOGI(dev, "index=[%d], profile_name=[%s]", -+ i, prof_info->prof_name_list[i]); -+ } -+ -+ return 0; -+} -+ -+static int aw_parse_acf_v_0_0_0_1(struct device *dev, -+ struct acf_bin_info *acf_info) -+ -+{ -+ int ret = 0; -+ struct aw_all_prof_info all_prof_info; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ acf_info->prof_info.status = AW_ACF_WAIT; -+ -+ memset(&all_prof_info, 0, sizeof(struct aw_all_prof_info)); -+ -+ ret = aw_parse_dev_type_v_0_0_0_1(dev, acf_info, &all_prof_info); -+ if (ret < 0) { -+ return ret; -+ } else if (ret == AW_DEV_TYPE_NONE) { -+ AW_DEV_LOGD(dev, "get dev type num is 0, parse default dev type"); -+ ret = aw_parse_default_type_v_0_0_0_1(dev, acf_info, &all_prof_info); -+ if (ret < 0) -+ return ret; -+ } -+ -+ ret = aw_get_vaild_prof_v_0_0_0_1(dev, acf_info, &all_prof_info); -+ if (ret < 0) { -+ aw87xxx_acf_profile_free(dev, acf_info); -+ AW_DEV_LOGE(dev, "hdr_cersion[0x%x] parse failed", -+ acf_info->acf_hdr.hdr_version); -+ return ret; -+ } -+ -+ ret = aw_set_prof_name_list_v_0_0_0_1(dev, acf_info); -+ if (ret < 0) { -+ aw87xxx_acf_profile_free(dev, acf_info); -+ AW_DEV_LOGE(dev, "creat prof_id_and_name_list failed"); -+ return ret; -+ } -+ -+ acf_info->prof_info.status = AW_ACF_UPDATE; -+ AW_DEV_LOGI(dev, "acf parse success"); -+ return 0; -+} -+ -+/*************************************************************************** -+ * V1.0.0.0 version acf paese -+ **************************************************************************/ -+static int aw_check_product_name_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_acf_dde_v_1_0_0_0 *prof_hdr) -+{ -+ int i = 0; -+ -+ for (i = 0; i < acf_info->product_cnt; i++) { -+ if (0 == strcmp(acf_info->product_tab[i], prof_hdr->dev_name)) { -+ AW_DEV_LOGI(dev, "bin_dev_name:%s", prof_hdr->dev_name); -+ return 0; -+ } -+ } -+ -+ return -ENXIO; -+} -+ -+static int aw_get_dde_type_info_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int i; -+ int dev_num = 0; -+ int default_num = 0; -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset); -+ -+ prof_info->prof_type = AW_DEV_NONE_TYPE_ID; -+ for (i = 0; i < acf_hdr->dde_num; i++) { -+ if (acf_dde[i].type == AW_DDE_DEV_TYPE_ID) -+ dev_num++; -+ if (acf_dde[i].type == AW_DDE_DEV_DEFAULT_TYPE_ID) -+ default_num++; -+ } -+ -+ if (!(dev_num || default_num)) { -+ AW_DEV_LOGE(dev, "can't find scene"); -+ return -EINVAL; -+ } -+ -+ if (dev_num != 0) -+ prof_info->prof_type = AW_DDE_DEV_TYPE_ID; -+ else if (default_num != 0) -+ prof_info->prof_type = AW_DDE_DEV_DEFAULT_TYPE_ID; -+ -+ return 0; -+} -+ -+ -+static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset); -+ int i = 0; -+ int ret = 0; -+ int found_off_prof_flag = 0; -+ int count = acf_info->prof_info.count; -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) || -+ (acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) && -+ ((acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) && -+ (acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr)) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ ret = aw_check_prof_str_is_off(acf_dde[i].dev_profile_str); -+ if (ret == 0) { -+ found_off_prof_flag = AW_PROFILE_OK; -+ } -+ count++; -+ } -+ } -+ -+ if (count == 0) { -+ AW_DEV_LOGE(dev, "can't find profile"); -+ return -EINVAL; -+ } -+ -+ if (!found_off_prof_flag) { -+ count++; -+ AW_DEV_LOGD(dev, "set no config power off profile in count"); -+ } -+ -+ acf_info->prof_info.count = count; -+ AW_DEV_LOGI(dev, "profile dev_type profile count is %d", acf_info->prof_info.count); -+ return 0; -+} -+ -+static int aw_parse_get_default_type_prof_count_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset); -+ int i = 0; -+ int ret = 0; -+ int found_off_prof_flag = 0; -+ int count = acf_info->prof_info.count; -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) || -+ (acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) && -+ (acf_info->dev_index == acf_dde[i].dev_index) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ ret = aw_check_prof_str_is_off(acf_dde[i].dev_profile_str); -+ if (ret == 0) { -+ found_off_prof_flag = AW_PROFILE_OK; -+ } -+ count++; -+ } -+ } -+ -+ if (count == 0) { -+ AW_DEV_LOGE(dev, "can't find profile"); -+ return -EINVAL; -+ } -+ -+ if (!found_off_prof_flag) { -+ count++; -+ AW_DEV_LOGD(dev, "set no config power off profile in count"); -+ } -+ -+ acf_info->prof_info.count = count; -+ AW_DEV_LOGI(dev, "profile default_type profile count is %d", acf_info->prof_info.count); -+ return 0; -+} -+ -+static int aw_parse_get_profile_count_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int ret = 0; -+ -+ ret = aw_get_dde_type_info_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) -+ return ret; -+ -+ if (acf_info->prof_info.prof_type == AW_DDE_DEV_TYPE_ID) { -+ ret = aw_parse_get_dev_type_prof_count_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse dev_type profile count failed"); -+ return ret; -+ } -+ } else if (acf_info->prof_info.prof_type == AW_DDE_DEV_DEFAULT_TYPE_ID) { -+ ret = aw_parse_get_default_type_prof_count_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse default_type profile count failed"); -+ return ret; -+ } -+ } else { -+ AW_DEV_LOGE(dev, "unsupport prof_type[0x%x]", -+ acf_info->prof_info.prof_type); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(dev, "profile count is %d", acf_info->prof_info.count); -+ return 0; -+} -+ -+static int aw_parse_dev_type_prof_name_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset); -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ int i, ret, list_index = 0; -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) || -+ (acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) && -+ (acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) && -+ (acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ if (list_index > prof_info->count) { -+ AW_DEV_LOGE(dev, "%s:Alrealdy set list_index [%d], redundant profile [%s]exist\n", -+ __func__, list_index, -+ acf_dde[i].dev_profile_str); -+ return -EINVAL; -+ } -+ -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ snprintf(prof_info->prof_name_list[list_index], AW_PROFILE_STR_MAX, "%s", -+ acf_dde[i].dev_profile_str); -+ AW_DEV_LOGI(dev, "profile_name=[%s]", -+ prof_info->prof_name_list[list_index]); -+ list_index++; -+ } -+ } -+ -+ return 0; -+} -+ -+static int aw_parse_default_type_prof_name_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset); -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ int i, ret, list_index = 0; -+ -+ for (i = 0; i < acf_hdr->dde_num; ++i) { -+ if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) || -+ (acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) && -+ (acf_info->dev_index == acf_dde[i].dev_index) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ if (list_index > prof_info->count) { -+ AW_DEV_LOGE(dev, "%s:Alrealdy set list_index [%d], redundant profile [%s]exist\n", -+ __func__, list_index, -+ acf_dde[i].dev_profile_str); -+ return -EINVAL; -+ } -+ -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ snprintf(prof_info->prof_name_list[list_index], AW_PROFILE_STR_MAX, "%s", -+ acf_dde[i].dev_profile_str); -+ AW_DEV_LOGI(dev, "profile_name=[%s]", -+ prof_info->prof_name_list[list_index]); -+ list_index++; -+ } -+ } -+ -+ return 0; -+} -+ -+static int aw_parse_prof_name_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int ret = 0; -+ int count = acf_info->prof_info.count; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ prof_info->prof_name_list = (char (*)[AW_PROFILE_STR_MAX])devm_kzalloc(dev, -+ count * (AW_PROFILE_STR_MAX), GFP_KERNEL); -+ if (prof_info->prof_name_list == NULL) { -+ AW_DEV_LOGE(dev, "prof_name_list devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ if (acf_info->prof_info.prof_type == AW_DDE_DEV_TYPE_ID) { -+ ret = aw_parse_dev_type_prof_name_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse dev_type profile count failed"); -+ return ret; -+ } -+ } else if (acf_info->prof_info.prof_type == AW_DDE_DEV_DEFAULT_TYPE_ID) { -+ ret = aw_parse_default_type_prof_name_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse default_type profile count failed"); -+ return ret; -+ } -+ } else { -+ AW_DEV_LOGE(dev, "unsupport prof_type[0x%x]", -+ acf_info->prof_info.prof_type); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(dev, "profile name parse succeed"); -+ return 0; -+} -+ -+ -+static int aw_search_prof_index_from_list_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_prof_desc **prof_desc, -+ struct aw_acf_dde_v_1_0_0_0 *prof_hdr) -+{ -+ int i = 0; -+ int count = acf_info->prof_info.count; -+ char (*prof_name_list)[AW_PROFILE_STR_MAX] = acf_info->prof_info.prof_name_list; -+ -+ for (i = 0; i < count; i++) { -+ if (!strncmp(prof_name_list[i], prof_hdr->dev_profile_str, AW_PROFILE_STR_MAX)) { -+ *prof_desc = &(acf_info->prof_info.prof_desc[i]); -+ return 0; -+ } -+ } -+ -+ if (i == count) -+ AW_DEV_LOGE(dev, "not find prof_id and prof_name in list"); -+ -+ return -EINVAL; -+} -+ -+static int aw_parse_data_by_sec_type_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info, -+ struct aw_acf_dde_v_1_0_0_0 *prof_hdr) -+{ -+ int ret = -1; -+ char *cfg_data = acf_info->fw_data + prof_hdr->data_offset; -+ struct aw_prof_desc *prof_desc = NULL; -+ -+ ret = aw_search_prof_index_from_list_v_1_0_0_0(dev, acf_info, &prof_desc, prof_hdr); -+ if (ret < 0) -+ return ret; -+ -+ switch (prof_hdr->data_type) { -+ case AW_BIN_TYPE_REG: -+ snprintf(prof_desc->dev_name, sizeof(prof_hdr->dev_name), -+ "%s", prof_hdr->dev_name); -+ AW_DEV_LOGI(dev, "parse reg type data enter,product=[%s],prof_id=[%d],prof_name=[%s]", -+ prof_hdr->dev_name, prof_hdr->dev_profile, -+ prof_hdr->dev_profile_str); -+ prof_desc->prof_name = prof_hdr->dev_profile_str; -+ ret = aw_parse_raw_reg(dev, cfg_data, prof_hdr->data_size, -+ prof_desc); -+ break; -+ case AW_BIN_TYPE_HDR_REG: -+ snprintf(prof_desc->dev_name, sizeof(prof_hdr->dev_name), -+ "%s", prof_hdr->dev_name); -+ AW_DEV_LOGI(dev, "parse hdr_reg type data enter,product=[%s],prof_id=[%d],prof_name=[%s]", -+ prof_hdr->dev_name, prof_hdr->dev_profile, -+ prof_hdr->dev_profile_str); -+ prof_desc->prof_name = prof_hdr->dev_profile_str; -+ ret = aw_parse_reg_with_hdr(dev, cfg_data, -+ prof_hdr->data_size, prof_desc); -+ break; -+ } -+ -+ return ret; -+} -+ -+static int aw_parse_dev_type_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int i = 0; -+ int ret; -+ int parse_prof_count = 0; -+ char *cfg_data = NULL; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset); -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ for (i = 0; i < acf_info->acf_hdr.dde_num; i++) { -+ if ((acf_dde[i].type == AW_DDE_DEV_TYPE_ID) && -+ (acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) && -+ (acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ if (acf_dde[i].data_type == AW_MONITOR) { -+ cfg_data = acf_info->fw_data + acf_dde[i].data_offset; -+ AW_DEV_LOGD(dev, "parse monitor type data enter"); -+ ret = aw_parse_monitor_config(dev, cfg_data, -+ acf_dde[i].data_size); -+ } else { -+ ret = aw_parse_data_by_sec_type_v_1_0_0_0(dev, acf_info, -+ &acf_dde[i]); -+ if (ret < 0) -+ AW_DEV_LOGE(dev, "parse dev type data failed"); -+ else -+ parse_prof_count++; -+ } -+ } -+ } -+ -+ if (parse_prof_count == 0) { -+ AW_DEV_LOGE(dev, "get dev type num is %d, parse failed", parse_prof_count); -+ return -EINVAL; -+ } -+ -+ return AW_DEV_TYPE_OK; -+} -+ -+static int aw_parse_default_type_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int i = 0; -+ int ret; -+ int parse_prof_count = 0; -+ char *cfg_data = NULL; -+ struct aw_acf_dde_v_1_0_0_0 *acf_dde = -+ (struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset); -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ for (i = 0; i < acf_info->acf_hdr.dde_num; i++) { -+ if ((acf_dde[i].type == AW_DDE_DEV_DEFAULT_TYPE_ID) && -+ (acf_info->dev_index == acf_dde[i].dev_index) && -+ (acf_info->aw_dev->chipid == acf_dde[i].chip_id)) { -+ ret = aw_check_product_name_v_1_0_0_0(dev, acf_info, &acf_dde[i]); -+ if (ret < 0) -+ continue; -+ -+ if (acf_dde[i].data_type == AW_MONITOR) { -+ cfg_data = acf_info->fw_data + acf_dde[i].data_offset; -+ AW_DEV_LOGD(dev, "parse monitor type data enter"); -+ ret = aw_parse_monitor_config(dev, cfg_data, -+ acf_dde[i].data_size); -+ } else { -+ ret = aw_parse_data_by_sec_type_v_1_0_0_0(dev, acf_info, -+ &acf_dde[i]); -+ if (ret < 0) -+ AW_DEV_LOGE(dev, "parse default type data failed"); -+ else -+ parse_prof_count++; -+ } -+ } -+ } -+ -+ if (parse_prof_count == 0) { -+ AW_DEV_LOGE(dev, "get default type num is %d,parse failed", parse_prof_count); -+ return -EINVAL; -+ } -+ -+ return AW_DEV_TYPE_OK; -+} -+ -+static int aw_parse_by_hdr_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int ret; -+ -+ if (acf_info->prof_info.prof_type == AW_DDE_DEV_TYPE_ID) { -+ ret = aw_parse_dev_type_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) -+ return ret; -+ } else if (acf_info->prof_info.prof_type == AW_DDE_DEV_DEFAULT_TYPE_ID) { -+ ret = aw_parse_default_type_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int aw_set_prof_off_info_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ int i = 0; -+ int ret = 0; -+ -+ for (i = 0; i < prof_info->count; ++i) { -+ if (!(prof_info->prof_desc[i].prof_st)) { -+ snprintf(prof_info->prof_name_list[i], AW_PROFILE_STR_MAX, "%s", -+ g_power_off_name[0]); -+ prof_info->prof_desc[i].prof_name = prof_info->prof_name_list[i]; -+ prof_info->prof_desc[i].prof_st = AW_PROFILE_WAIT; -+ memset(&prof_info->prof_desc[i].data_container, 0, -+ sizeof(struct aw_data_container)); -+ return 0; -+ } -+ -+ ret = aw_check_prof_str_is_off(prof_info->prof_name_list[i]); -+ if (ret == 0) { -+ AW_DEV_LOGD(dev, "found profile off,data_len=[%d]", -+ prof_info->prof_desc[i].data_container.len); -+ return 0; -+ } -+ } -+ -+ AW_DEV_LOGE(dev, "index[%d] is out of table,profile count[%d]", -+ i, prof_info->count); -+ return -EINVAL; -+} -+ -+static int aw_parse_acf_v_1_0_0_0(struct device *dev, -+ struct acf_bin_info *acf_info) -+ -+{ -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ int ret; -+ -+ ret = aw_parse_get_profile_count_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "get profile count failed"); -+ return ret; -+ } -+ -+ ret = aw_parse_prof_name_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "get profile count failed"); -+ return ret; -+ } -+ -+ acf_info->prof_info.prof_desc = devm_kzalloc(dev, -+ prof_info->count * sizeof(struct aw_prof_desc), GFP_KERNEL); -+ if (acf_info->prof_info.prof_desc == NULL) { -+ AW_DEV_LOGE(dev, "prof_desc devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ ret = aw_parse_by_hdr_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "parse data failed"); -+ return ret; -+ } -+ -+ ret = aw_set_prof_off_info_v_1_0_0_0(dev, acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "set profile off info failed"); -+ return ret; -+ } -+ -+ prof_info->status = AW_ACF_UPDATE; -+ AW_DEV_LOGI(dev, "acf paese succeed"); -+ return 0; -+} -+ -+ -+/************************************************************************* -+ * -+ *acf parse API -+ * -+ *************************************************************************/ -+void aw87xxx_acf_profile_free(struct device *dev, struct acf_bin_info *acf_info) -+{ -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ prof_info->count = 0; -+ prof_info->status = AW_ACF_WAIT; -+ memset(&acf_info->acf_hdr, 0, sizeof(struct aw_acf_hdr)); -+ -+ if (prof_info->prof_desc) { -+ devm_kfree(dev, prof_info->prof_desc); -+ prof_info->prof_desc = NULL; -+ } -+ -+ if (prof_info->prof_name_list) { -+ devm_kfree(dev, prof_info->prof_name_list); -+ prof_info->prof_name_list = NULL; -+ } -+ -+ if (acf_info->fw_data) { -+ vfree(acf_info->fw_data); -+ acf_info->fw_data = NULL; -+ } -+} -+ -+int aw87xxx_acf_parse(struct device *dev, struct acf_bin_info *acf_info) -+{ -+ int ret = 0; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ acf_info->prof_info.status = AW_ACF_WAIT; -+ ret = aw_check_acf_firmware(dev, acf_info->fw_data, -+ acf_info->fw_size); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "load firmware check failed"); -+ return -EINVAL; -+ } -+ -+ memcpy(&acf_info->acf_hdr, acf_info->fw_data, -+ sizeof(struct aw_acf_hdr)); -+ -+ switch (acf_info->acf_hdr.hdr_version) { -+ case AW_ACF_HDR_VER_0_0_0_1: -+ return aw_parse_acf_v_0_0_0_1(dev, acf_info); -+ case AW_ACF_HDR_VER_1_0_0_0: -+ return aw_parse_acf_v_1_0_0_0(dev, acf_info); -+ default: -+ AW_DEV_LOGE(dev, "unsupported hdr_version [0x%x]", -+ acf_info->acf_hdr.hdr_version); -+ return -EINVAL; -+ } -+ -+ return ret; -+} -+ -+struct aw_prof_desc *aw87xxx_acf_get_prof_desc_form_name(struct device *dev, -+ struct acf_bin_info *acf_info, char *profile_name) -+{ -+ int i = 0; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ if (!acf_info->prof_info.status) { -+ AW_DEV_LOGE(dev, "profile_cfg not load"); -+ return NULL; -+ } -+ -+ for (i = 0; i < prof_info->count; i++) { -+ if (!strncmp(profile_name, prof_info->prof_desc[i].prof_name, -+ AW_PROFILE_STR_MAX)) { -+ prof_desc = &prof_info->prof_desc[i]; -+ break; -+ } -+ } -+ -+ if (i == prof_info->count) { -+ AW_DEV_LOGE(dev, "profile not found"); -+ return NULL; -+ } -+ -+ AW_DEV_LOGI(dev, "get prof desc down"); -+ return prof_desc; -+} -+ -+int aw87xxx_acf_get_prof_index_form_name(struct device *dev, -+ struct acf_bin_info *acf_info, char *profile_name) -+{ -+ int i = 0; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ if (!acf_info->prof_info.status) { -+ AW_DEV_LOGE(dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < prof_info->count; i++) { -+ if (!strncmp(profile_name, prof_info->prof_name_list[i], -+ AW_PROFILE_STR_MAX)) { -+ return i; -+ } -+ } -+ -+ AW_DEV_LOGE(dev, "profile_index not found"); -+ return -EINVAL; -+} -+ -+char *aw87xxx_acf_get_prof_name_form_index(struct device *dev, -+ struct acf_bin_info *acf_info, int index) -+{ -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ if (!acf_info->prof_info.status) { -+ AW_DEV_LOGE(dev, "profile_cfg not load"); -+ return NULL; -+ } -+ -+ if (index >= prof_info->count || index < 0) { -+ AW_DEV_LOGE(dev, "profile_index out of table"); -+ return NULL; -+ } -+ -+ return prof_info->prof_desc[index].prof_name; -+} -+ -+ -+int aw87xxx_acf_get_profile_count(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ if (!acf_info->prof_info.status) { -+ AW_DEV_LOGE(dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ if (prof_info->count > 0) { -+ return prof_info->count; -+ } -+ -+ return -EINVAL; -+} -+ -+char *aw87xxx_acf_get_prof_off_name(struct device *dev, -+ struct acf_bin_info *acf_info) -+{ -+ int i = 0; -+ int ret = 0; -+ struct aw_prof_info *prof_info = &acf_info->prof_info; -+ -+ if (!acf_info->prof_info.status) { -+ AW_DEV_LOGE(dev, "profile_cfg not load"); -+ return NULL; -+ } -+ -+ for (i = 0; i < prof_info->count; i++) { -+ ret = aw_check_prof_str_is_off(prof_info->prof_name_list[i]); -+ if (ret == 0) -+ return prof_info->prof_name_list[i]; -+ } -+ -+ return NULL; -+} -+ -+void aw87xxx_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index) -+{ -+ -+ acf_info->load_count = 0; -+ acf_info->prof_info.status = AW_ACF_WAIT; -+ acf_info->dev_index = index; -+ acf_info->aw_dev = aw_dev; -+ acf_info->product_cnt = aw_dev->product_cnt; -+ acf_info->product_tab = aw_dev->product_tab; -+ acf_info->prof_info.prof_desc = NULL; -+ acf_info->fw_data = NULL; -+ acf_info->fw_size = 0; -+} -+ -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.h b/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.h -new file mode 100644 -index 000000000..ebe0c77f5 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_acf_bin.h -@@ -0,0 +1,191 @@ -+#ifndef __AW87XXX_ACF_BIN_H__ -+#define __AW87XXX_ACF_BIN_H__ -+ -+#include "aw87xxx_device.h" -+ -+#define AW_PROJECT_NAME_MAX (24) -+#define AW_CUSTOMER_NAME_MAX (16) -+#define AW_CFG_VERSION_MAX (4) -+#define AW_TBL_VERSION_MAX (4) -+#define AW_DDE_DEVICE_TYPE (0) -+#define AW_DDE_SKT_TYPE (1) -+#define AW_DDE_DEFAULT_TYPE (2) -+ -+#define AW_REG_ADDR_BYTE (1) -+#define AW_REG_DATA_BYTE (1) -+ -+#define AW_ACF_FILE_ID (0xa15f908) -+#define AW_PROFILE_STR_MAX (32) -+#define AW_POWER_OFF_NAME_SUPPORT_COUNT (5) -+ -+enum aw_cfg_hdr_version { -+ AW_ACF_HDR_VER_0_0_0_1 = 0x00000001, -+ AW_ACF_HDR_VER_1_0_0_0 = 0x01000000, -+}; -+ -+enum aw_acf_dde_type_id { -+ AW_DEV_NONE_TYPE_ID = 0xFFFFFFFF, -+ AW_DDE_DEV_TYPE_ID = 0x00000000, -+ AW_DDE_SKT_TYPE_ID = 0x00000001, -+ AW_DDE_DEV_DEFAULT_TYPE_ID = 0x00000002, -+ AW_DDE_TYPE_MAX, -+}; -+ -+enum aw_raw_data_type_id { -+ AW_BIN_TYPE_REG = 0x00000000, -+ AW_BIN_TYPE_DSP, -+ AW_BIN_TYPE_DSP_CFG, -+ AW_BIN_TYPE_DSP_FW, -+ AW_BIN_TYPE_HDR_REG, -+ AW_BIN_TYPE_HDR_DSP_CFG, -+ AW_BIN_TYPE_HDR_DSP_FW, -+ AW_BIN_TYPE_MUTLBIN, -+ AW_SKT_UI_PROJECT, -+ AW_DSP_CFG, -+ AW_MONITOR, -+ AW_BIN_TYPE_MAX, -+}; -+ -+enum { -+ AW_DEV_TYPE_OK = 0, -+ AW_DEV_TYPE_NONE = 1, -+}; -+ -+enum aw_profile_status { -+ AW_PROFILE_WAIT = 0, -+ AW_PROFILE_OK, -+}; -+ -+enum aw_acf_load_status { -+ AW_ACF_WAIT = 0, -+ AW_ACF_UPDATE, -+}; -+ -+enum aw_bin_dev_profile_id { -+ AW_PROFILE_MUSIC = 0x0000, -+ AW_PROFILE_VOICE, -+ AW_PROFILE_VOIP, -+ AW_PROFILE_RINGTONE, -+ AW_PROFILE_RINGTONE_HS, -+ AW_PROFILE_LOWPOWER, -+ AW_PROFILE_BYPASS, -+ AW_PROFILE_MMI, -+ AW_PROFILE_FM, -+ AW_PROFILE_NOTIFICATION, -+ AW_PROFILE_RECEIVER, -+ AW_PROFILE_OFF, -+ AW_PROFILE_MAX, -+}; -+ -+struct aw_acf_hdr { -+ int32_t a_id; /* acf file ID 0xa15f908 */ -+ char project[AW_PROJECT_NAME_MAX]; /* project name */ -+ char custom[AW_CUSTOMER_NAME_MAX]; /* custom name :huawei xiaomi vivo oppo */ -+ uint8_t version[AW_CFG_VERSION_MAX]; /* author update version */ -+ int32_t author_id; /* author id */ -+ int32_t ddt_size; /* sub section table entry size */ -+ int32_t dde_num; /* sub section table entry num */ -+ int32_t ddt_offset; /* sub section table offset in file */ -+ int32_t hdr_version; /* sub section table version */ -+ int32_t reserve[3]; /* Reserved Bits */ -+}; -+ -+struct aw_acf_dde { -+ int32_t type; /* dde type id */ -+ char dev_name[AW_CUSTOMER_NAME_MAX]; /* customer dev name */ -+ int16_t dev_index; /* dev id */ -+ int16_t dev_bus; /* dev bus id */ -+ int16_t dev_addr; /* dev addr id */ -+ int16_t dev_profile; /* dev profile id */ -+ int32_t data_type; /* data type id */ -+ int32_t data_size; /* dde data size in block */ -+ int32_t data_offset; /* dde data offset in block */ -+ int32_t data_crc; /* dde data crc checkout */ -+ int32_t reserve[5]; /* Reserved Bits */ -+}; -+ -+struct aw_acf_dde_v_1_0_0_0 { -+ uint32_t type; /* DDE type id */ -+ char dev_name[AW_CUSTOMER_NAME_MAX]; /* customer dev name */ -+ uint16_t dev_index; /* dev id */ -+ uint16_t dev_bus; /* dev bus id */ -+ uint16_t dev_addr; /* dev addr id */ -+ uint16_t dev_profile; /* dev profile id*/ -+ uint32_t data_type; /* data type id */ -+ uint32_t data_size; /* dde data size in block */ -+ uint32_t data_offset; /* dde data offset in block */ -+ uint32_t data_crc; /* dde data crc checkout */ -+ char dev_profile_str[AW_PROFILE_STR_MAX]; /* dde custom profile name */ -+ uint32_t chip_id; /* dde custom product chip id */ -+ uint32_t reserve[4]; -+}; -+ -+struct aw_data_with_header { -+ uint32_t check_sum; -+ uint32_t header_ver; -+ uint32_t bin_data_type; -+ uint32_t bin_data_ver; -+ uint32_t bin_data_size; -+ uint32_t ui_ver; -+ char product[8]; -+ uint32_t addr_byte_len; -+ uint32_t data_byte_len; -+ uint32_t device_addr; -+ uint32_t reserve[4]; -+}; -+ -+struct aw_data_container { -+ uint32_t len; -+ uint8_t *data; -+}; -+ -+struct aw_prof_desc { -+ uint32_t prof_st; -+ char *prof_name; -+ char dev_name[AW_CUSTOMER_NAME_MAX]; -+ struct aw_data_container data_container; -+}; -+ -+struct aw_all_prof_info { -+ struct aw_prof_desc prof_desc[AW_PROFILE_MAX]; -+}; -+ -+struct aw_prof_info { -+ int count; -+ int status; -+ int prof_type; -+ char (*prof_name_list)[AW_PROFILE_STR_MAX]; -+ struct aw_prof_desc *prof_desc; -+}; -+ -+struct acf_bin_info { -+ int load_count; -+ int fw_size; -+ int16_t dev_index; -+ char *fw_data; -+ int product_cnt; -+ const char **product_tab; -+ struct aw_device *aw_dev; -+ -+ struct aw_acf_hdr acf_hdr; -+ struct aw_prof_info prof_info; -+}; -+ -+char *aw87xxx_ctos_get_prof_name(int profile_id); -+void aw87xxx_acf_profile_free(struct device *dev, -+ struct acf_bin_info *acf_info); -+int aw87xxx_acf_parse(struct device *dev, struct acf_bin_info *acf_info); -+struct aw_prof_desc *aw87xxx_acf_get_prof_desc_form_name(struct device *dev, -+ struct acf_bin_info *acf_info, char *profile_name); -+int aw87xxx_acf_get_prof_index_form_name(struct device *dev, -+ struct acf_bin_info *acf_info, char *profile_name); -+char *aw87xxx_acf_get_prof_name_form_index(struct device *dev, -+ struct acf_bin_info *acf_info, int index); -+int aw87xxx_acf_get_profile_count(struct device *dev, -+ struct acf_bin_info *acf_info); -+char *aw87xxx_acf_get_prof_off_name(struct device *dev, -+ struct acf_bin_info *acf_info); -+void aw87xxx_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index); -+ -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.c b/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.c -new file mode 100644 -index 000000000..7eab9efde ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.c -@@ -0,0 +1,515 @@ -+/* -+* aw87xxx_bin_parse.c -+* -+* Copyright (c) 2020 AWINIC Technology CO., LTD -+* -+* This program is free software; you can redistribute it and/or modify it -+* under the terms of the GNU General Public License as published by the -+* Free Software Foundation; either version 2 of the License, or (at your -+* option) any later version. -+*/ -+ -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/i2c.h> -+#include <linux/of_gpio.h> -+#include <linux/delay.h> -+#include <linux/device.h> -+#include <linux/firmware.h> -+#include <linux/slab.h> -+#include <linux/version.h> -+#include <linux/input.h> -+#include <linux/interrupt.h> -+#include <linux/debugfs.h> -+#include <linux/miscdevice.h> -+#include <asm/uaccess.h> -+#include <linux/regmap.h> -+#include <linux/timer.h> -+#include <linux/workqueue.h> -+#include <linux/hrtimer.h> -+#include <linux/mutex.h> -+#include <linux/cdev.h> -+#include <linux/list.h> -+#include <linux/string.h> -+#include "aw87xxx_bin_parse.h" -+ -+#define AWINIC_CODE_VERSION "V0.0.7-V1.0.4" /* "code version"-"excel version" */ -+ -+#define DEBUG_LOG_LEVEL -+#ifdef DEBUG_LOG_LEVEL -+#define DBG(fmt, arg...) do {\ -+printk("AWINIC_BIN %s,line= %d,"fmt, __func__, __LINE__, ##arg);\ -+} while (0) -+#define DBG_ERR(fmt, arg...) do {\ -+printk("AWINIC_BIN_ERR %s,line= %d,"fmt, __func__, __LINE__, ##arg);\ -+} while (0) -+#else -+#define DBG(fmt, arg...) do {} while (0) -+#define DBG_ERR(fmt, arg...) do {} while (0) -+#endif -+ -+#define printing_data_code -+ -+typedef unsigned short int aw_uint16; -+typedef unsigned long int aw_uint32; -+ -+#define BigLittleSwap16(A) ((((aw_uint16)(A) & 0xff00) >> 8) | \ -+ (((aw_uint16)(A) & 0x00ff) << 8)) -+ -+#define BigLittleSwap32(A) ((((aw_uint32)(A) & 0xff000000) >> 24) | \ -+ (((aw_uint32)(A) & 0x00ff0000) >> 8) | \ -+ (((aw_uint32)(A) & 0x0000ff00) << 8) | \ -+ (((aw_uint32)(A) & 0x000000ff) << 24)) -+ -+ -+static int aw_parse_bin_header_1_0_0(struct aw_bin *bin); -+ -+/** -+* -+* Interface function -+* -+* return value: -+* value = 0 :success; -+* value = -1 :check bin header version -+* value = -2 :check bin data type -+* value = -3 :check sum or check bin data len error -+* value = -4 :check data version -+* value = -5 :check register num -+* value = -6 :check dsp reg num -+* value = -7 :check soc app num -+* value = -8 :bin is NULL point -+* -+**/ -+ -+/******************************************************** -+* -+* check sum data -+* -+********************************************************/ -+static int aw_check_sum(struct aw_bin *bin, int bin_num) -+{ -+ unsigned int i = 0; -+ unsigned int sum_data = 0; -+ unsigned int check_sum = 0; -+ unsigned char *p_check_sum = NULL; -+ -+ DBG("enter\n"); -+ -+ p_check_sum = -+ &(bin->info.data[(bin->header_info[bin_num].valid_data_addr - -+ bin->header_info[bin_num].header_len)]); -+ DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum); -+ check_sum = GET_32_DATA(*(p_check_sum + 3), -+ *(p_check_sum + 2), -+ *(p_check_sum + 1), *(p_check_sum)); -+ -+ for (i = 4; -+ i < -+ bin->header_info[bin_num].bin_data_len + -+ bin->header_info[bin_num].header_len; i++) { -+ sum_data += *(p_check_sum + i); -+ } -+ DBG("aw_bin_parse bin_num=%d, check_sum = 0x%x, sum_data = 0x%x\n", -+ bin_num, check_sum, sum_data); -+ if (sum_data != check_sum) { -+ p_check_sum = NULL; -+ DBG_ERR("aw_bin_parse check sum or check bin data len error\n"); -+ DBG_ERR("aw_bin_parse bin_num=%d, check_sum = 0x%x, sum_data = 0x%x\n", bin_num, check_sum, sum_data); -+ return -3; -+ } -+ p_check_sum = NULL; -+ -+ return 0; -+} -+ -+static int aw_check_data_version(struct aw_bin *bin, int bin_num) -+{ -+ int i = 0; -+ DBG("enter\n"); -+ -+ for (i = DATA_VERSION_V1; i < DATA_VERSION_MAX; i++) { -+ if (bin->header_info[bin_num].bin_data_ver == i) { -+ return 0; -+ } -+ } -+ DBG_ERR("aw_bin_parse Unrecognized this bin data version\n"); -+ return -4; -+} -+ -+static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num) -+{ -+ unsigned int check_register_num = 0; -+ unsigned int parse_register_num = 0; -+ unsigned char *p_check_sum = NULL; -+ -+ DBG("enter\n"); -+ -+ p_check_sum = -+ &(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]); -+ DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum); -+ parse_register_num = GET_32_DATA(*(p_check_sum + 3), -+ *(p_check_sum + 2), -+ *(p_check_sum + 1), *(p_check_sum)); -+ check_register_num = (bin->header_info[bin_num].bin_data_len - 4) / -+ (bin->header_info[bin_num].reg_byte_len + -+ bin->header_info[bin_num].data_byte_len); -+ DBG -+ ("aw_bin_parse bin_num=%d, parse_register_num = 0x%x, check_register_num = 0x%x\n", -+ bin_num, parse_register_num, check_register_num); -+ if (parse_register_num != check_register_num) { -+ p_check_sum = NULL; -+ DBG_ERR("aw_bin_parse register num is error\n"); -+ DBG_ERR("aw_bin_parse bin_num=%d, parse_register_num = 0x%x, check_register_num = 0x%x\n", bin_num, parse_register_num, check_register_num); -+ return -5; -+ } -+ bin->header_info[bin_num].reg_num = parse_register_num; -+ bin->header_info[bin_num].valid_data_len = -+ bin->header_info[bin_num].bin_data_len - 4; -+ p_check_sum = NULL; -+ bin->header_info[bin_num].valid_data_addr = -+ bin->header_info[bin_num].valid_data_addr + 4; -+ return 0; -+} -+ -+static int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num) -+{ -+ unsigned int check_dsp_reg_num = 0; -+ unsigned int parse_dsp_reg_num = 0; -+ unsigned char *p_check_sum = NULL; -+ -+ DBG("enter\n"); -+ -+ p_check_sum = -+ &(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]); -+ DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum); -+ parse_dsp_reg_num = GET_32_DATA(*(p_check_sum + 7), -+ *(p_check_sum + 6), -+ *(p_check_sum + 5), *(p_check_sum + 4)); -+ bin->header_info[bin_num].reg_data_byte_len = -+ GET_32_DATA(*(p_check_sum + 11), *(p_check_sum + 10), -+ *(p_check_sum + 9), *(p_check_sum + 8)); -+ check_dsp_reg_num = -+ (bin->header_info[bin_num].bin_data_len - -+ 12) / bin->header_info[bin_num].reg_data_byte_len; -+ DBG -+ ("aw_bin_parse bin_num=%d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x\n", -+ bin_num, parse_dsp_reg_num, check_dsp_reg_num); -+ if (parse_dsp_reg_num != check_dsp_reg_num) { -+ p_check_sum = NULL; -+ DBG_ERR("aw_bin_parse dsp reg num is error\n"); -+ DBG_ERR("aw_bin_parse bin_num=%d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x\n", bin_num, parse_dsp_reg_num, check_dsp_reg_num); -+ return -6; -+ } -+ bin->header_info[bin_num].download_addr = -+ GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2), -+ *(p_check_sum + 1), *(p_check_sum)); -+ bin->header_info[bin_num].reg_num = parse_dsp_reg_num; -+ bin->header_info[bin_num].valid_data_len = -+ bin->header_info[bin_num].bin_data_len - 12; -+ p_check_sum = NULL; -+ bin->header_info[bin_num].valid_data_addr = -+ bin->header_info[bin_num].valid_data_addr + 12; -+ return 0; -+} -+ -+static int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num) -+{ -+ unsigned int check_soc_app_num = 0; -+ unsigned int parse_soc_app_num = 0; -+ unsigned char *p_check_sum = NULL; -+ -+ DBG("enter\n"); -+ -+ p_check_sum = -+ &(bin->info.data[(bin->header_info[bin_num].valid_data_addr)]); -+ DBG("aw_bin_parse p_check_sum = %p\n", p_check_sum); -+ bin->header_info[bin_num].app_version = GET_32_DATA(*(p_check_sum + 3), -+ *(p_check_sum + 2), -+ *(p_check_sum + 1), -+ *(p_check_sum)); -+ parse_soc_app_num = GET_32_DATA(*(p_check_sum + 11), -+ *(p_check_sum + 10), -+ *(p_check_sum + 9), *(p_check_sum + 8)); -+ check_soc_app_num = bin->header_info[bin_num].bin_data_len - 12; -+ DBG -+ ("aw_bin_parse bin_num=%d, parse_soc_app_num = 0x%x, check_soc_app_num = 0x%x\n", -+ bin_num, parse_soc_app_num, check_soc_app_num); -+ if (parse_soc_app_num != check_soc_app_num) { -+ p_check_sum = NULL; -+ DBG_ERR("aw_bin_parse soc app num is error\n"); -+ DBG_ERR("aw_bin_parse bin_num=%d, parse_soc_app_num = 0x%x, check_soc_app_num = 0x%x\n", bin_num, parse_soc_app_num, check_soc_app_num); -+ return -7; -+ } -+ bin->header_info[bin_num].reg_num = parse_soc_app_num; -+ bin->header_info[bin_num].download_addr = -+ GET_32_DATA(*(p_check_sum + 7), *(p_check_sum + 6), -+ *(p_check_sum + 5), *(p_check_sum + 4)); -+ bin->header_info[bin_num].valid_data_len = -+ bin->header_info[bin_num].bin_data_len - 12; -+ p_check_sum = NULL; -+ bin->header_info[bin_num].valid_data_addr = -+ bin->header_info[bin_num].valid_data_addr + 12; -+ return 0; -+} -+ -+/************************ -+*** -+***bin header 1_0_0 -+*** -+************************/ -+static void aw_get_single_bin_header_1_0_0(struct aw_bin *bin) -+{ -+ int i; -+ DBG("enter %s\n", __func__); -+ bin->header_info[bin->all_bin_parse_num].header_len = 60; -+ bin->header_info[bin->all_bin_parse_num].check_sum = -+ GET_32_DATA(*(bin->p_addr + 3), *(bin->p_addr + 2), -+ *(bin->p_addr + 1), *(bin->p_addr)); -+ bin->header_info[bin->all_bin_parse_num].header_ver = -+ GET_32_DATA(*(bin->p_addr + 7), *(bin->p_addr + 6), -+ *(bin->p_addr + 5), *(bin->p_addr + 4)); -+ bin->header_info[bin->all_bin_parse_num].bin_data_type = -+ GET_32_DATA(*(bin->p_addr + 11), *(bin->p_addr + 10), -+ *(bin->p_addr + 9), *(bin->p_addr + 8)); -+ bin->header_info[bin->all_bin_parse_num].bin_data_ver = -+ GET_32_DATA(*(bin->p_addr + 15), *(bin->p_addr + 14), -+ *(bin->p_addr + 13), *(bin->p_addr + 12)); -+ bin->header_info[bin->all_bin_parse_num].bin_data_len = -+ GET_32_DATA(*(bin->p_addr + 19), *(bin->p_addr + 18), -+ *(bin->p_addr + 17), *(bin->p_addr + 16)); -+ bin->header_info[bin->all_bin_parse_num].ui_ver = -+ GET_32_DATA(*(bin->p_addr + 23), *(bin->p_addr + 22), -+ *(bin->p_addr + 21), *(bin->p_addr + 20)); -+ bin->header_info[bin->all_bin_parse_num].reg_byte_len = -+ GET_32_DATA(*(bin->p_addr + 35), *(bin->p_addr + 34), -+ *(bin->p_addr + 33), *(bin->p_addr + 32)); -+ bin->header_info[bin->all_bin_parse_num].data_byte_len = -+ GET_32_DATA(*(bin->p_addr + 39), *(bin->p_addr + 38), -+ *(bin->p_addr + 37), *(bin->p_addr + 36)); -+ bin->header_info[bin->all_bin_parse_num].device_addr = -+ GET_32_DATA(*(bin->p_addr + 43), *(bin->p_addr + 42), -+ *(bin->p_addr + 41), *(bin->p_addr + 40)); -+ for (i = 0; i < 8; i++) { -+ bin->header_info[bin->all_bin_parse_num].chip_type[i] = -+ *(bin->p_addr + 24 + i); -+ } -+ bin->header_info[bin->all_bin_parse_num].reg_num = 0x00000000; -+ bin->header_info[bin->all_bin_parse_num].reg_data_byte_len = 0x00000000; -+ bin->header_info[bin->all_bin_parse_num].download_addr = 0x00000000; -+ bin->header_info[bin->all_bin_parse_num].app_version = 0x00000000; -+ bin->header_info[bin->all_bin_parse_num].valid_data_len = 0x00000000; -+ bin->all_bin_parse_num += 1; -+} -+ -+static int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num, -+ struct aw_bin *bin) -+{ -+ int ret = 0; -+ unsigned int bin_start_addr = 0; -+ unsigned int valid_data_len = 0; -+ DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__); -+ if (!bin_serial_num) { -+ bin_start_addr = GET_32_DATA(*(bin->p_addr + 67), -+ *(bin->p_addr + 66), -+ *(bin->p_addr + 65), -+ *(bin->p_addr + 64)); -+ bin->p_addr += (60 + bin_start_addr); -+ bin->header_info[bin->all_bin_parse_num].valid_data_addr = -+ bin->header_info[bin->all_bin_parse_num - -+ 1].valid_data_addr + 4 + 8 * bin_num + 60; -+ } else { -+ valid_data_len = -+ bin->header_info[bin->all_bin_parse_num - 1].bin_data_len; -+ bin->p_addr += (60 + valid_data_len); -+ bin->header_info[bin->all_bin_parse_num].valid_data_addr = -+ bin->header_info[bin->all_bin_parse_num - -+ 1].valid_data_addr + -+ bin->header_info[bin->all_bin_parse_num - 1].bin_data_len + -+ 60; -+ } -+ -+ ret = aw_parse_bin_header_1_0_0(bin); -+ return ret; -+} -+ -+/* Get the number of bins in multi bins, and set a for loop, loop processing each bin data */ -+static int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin) -+{ -+ int i = 0; -+ int ret = 0; -+ unsigned int bin_num = 0; -+ DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__); -+ bin_num = GET_32_DATA(*(bin->p_addr + 63), -+ *(bin->p_addr + 62), -+ *(bin->p_addr + 61), *(bin->p_addr + 60)); -+ if (bin->multi_bin_parse_num == 1) { -+ bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60; -+ } -+ aw_get_single_bin_header_1_0_0(bin); -+ -+ for (i = 0; i < bin_num; i++) { -+ DBG("aw_bin_parse enter multi bin for is %d\n", i); -+ ret = aw_parse_each_of_multi_bins_1_0_0(bin_num, i, bin); -+ if (ret < 0) { -+ return ret; -+ } -+ } -+ return 0; -+} -+ -+/******************************************************** -+* -+* If the bin framework header version is 1.0.0, -+ determine the data type of bin, and then perform different processing -+ according to the data type -+ If it is a single bin data type, write the data directly into the structure array -+ If it is a multi-bin data type, first obtain the number of bins, -+ and then recursively call the bin frame header processing function -+ according to the bin number to process the frame header information of each bin separately -+* -+********************************************************/ -+static int aw_parse_bin_header_1_0_0(struct aw_bin *bin) -+{ -+ int ret = 0; -+ unsigned int bin_data_type; -+ DBG("enter %s\n", __func__); -+ bin_data_type = GET_32_DATA(*(bin->p_addr + 11), -+ *(bin->p_addr + 10), -+ *(bin->p_addr + 9), *(bin->p_addr + 8)); -+ DBG("aw_bin_parse bin_data_type 0x%x\n", bin_data_type); -+ switch (bin_data_type) { -+ case DATA_TYPE_REGISTER: -+ case DATA_TYPE_DSP_REG: -+ case DATA_TYPE_SOC_APP: -+ /* Divided into two processing methods, -+ one is single bin processing, -+ and the other is single bin processing in multi bin */ -+ DBG("aw_bin_parse enter single bin branch\n"); -+ bin->single_bin_parse_num += 1; -+ DBG("%s bin->single_bin_parse_num is %d\n", __func__, -+ bin->single_bin_parse_num); -+ if (!bin->multi_bin_parse_num) { -+ bin->header_info[bin-> -+ all_bin_parse_num].valid_data_addr = -+ 60; -+ } -+ aw_get_single_bin_header_1_0_0(bin); -+ break; -+ case DATA_TYPE_MULTI_BINS: -+ /* Get the number of times to enter multi bins */ -+ DBG("aw_bin_parse enter multi bin branch\n"); -+ bin->multi_bin_parse_num += 1; -+ DBG("%s bin->multi_bin_parse_num is %d\n", __func__, -+ bin->multi_bin_parse_num); -+ ret = aw_get_multi_bin_header_1_0_0(bin); -+ if (ret < 0) { -+ return ret; -+ } -+ break; -+ default: -+ DBG_ERR("aw_bin_parse Unrecognized this bin data type\n"); -+ return -2; -+ } -+ return 0; -+} -+ -+/* get the bin's header version */ -+static int aw_check_bin_header_version(struct aw_bin *bin) -+{ -+ int ret = 0; -+ unsigned int header_version = 0; -+ -+ header_version = GET_32_DATA(*(bin->p_addr + 7), -+ *(bin->p_addr + 6), -+ *(bin->p_addr + 5), *(bin->p_addr + 4)); -+ -+ DBG("aw_bin_parse header_version 0x%x\n", header_version); -+ -+ /* Write data to the corresponding structure array -+ according to different formats of the bin frame header version */ -+ switch (header_version) { -+ case HEADER_VERSION_1_0_0: -+ ret = aw_parse_bin_header_1_0_0(bin); -+ return ret; -+ default: -+ DBG_ERR("aw_bin_parse Unrecognized this bin header version \n"); -+ return -1; -+ } -+} -+ -+int aw87xxx_parsing_bin_file(struct aw_bin *bin) -+{ -+ int i = 0; -+ int ret = 0; -+ -+ DBG("aw_bin_parse code version:%s\n", AWINIC_CODE_VERSION); -+ if (!bin) { -+ DBG_ERR("aw_bin_parse bin is NULL\n"); -+ return -8; -+ } -+ bin->p_addr = bin->info.data; -+ bin->all_bin_parse_num = 0; -+ bin->multi_bin_parse_num = 0; -+ bin->single_bin_parse_num = 0; -+ -+ /* filling bins header info */ -+ ret = aw_check_bin_header_version(bin); -+ if (ret < 0) { -+ DBG_ERR("aw_bin_parse check bin header version error\n"); -+ return ret; -+ } -+ bin->p_addr = NULL; -+ -+ /* check bin header info */ -+ for (i = 0; i < bin->all_bin_parse_num; i++) { -+ /* check sum */ -+ ret = aw_check_sum(bin, i); -+ if (ret < 0) { -+ DBG_ERR("aw_bin_parse check sum data error\n"); -+ return ret; -+ } -+ /* check bin data version */ -+ ret = aw_check_data_version(bin, i); -+ if (ret < 0) { -+ DBG_ERR("aw_bin_parse check data version error\n"); -+ return ret; -+ } -+ /* check valid data */ -+ if (bin->header_info[i].bin_data_ver == DATA_VERSION_V1) { -+ /* check register num */ -+ if (bin->header_info[i].bin_data_type == -+ DATA_TYPE_REGISTER) { -+ ret = aw_check_register_num_v1(bin, i); -+ if (ret < 0) { -+ DBG_ERR -+ ("aw_bin_parse check register num error\n"); -+ return ret; -+ } -+ /* check dsp reg num */ -+ } else if (bin->header_info[i].bin_data_type == -+ DATA_TYPE_DSP_REG) { -+ ret = aw_check_dsp_reg_num_v1(bin, i); -+ if (ret < 0) { -+ DBG_ERR -+ ("aw_bin_parse check dsp reg num error\n"); -+ return ret; -+ } -+ /* check soc app num */ -+ } else if (bin->header_info[i].bin_data_type == -+ DATA_TYPE_SOC_APP) { -+ ret = aw_check_soc_app_num_v1(bin, i); -+ if (ret < 0) { -+ DBG_ERR -+ ("aw_bin_parse check soc app num error\n"); -+ return ret; -+ } -+ } else { -+ bin->header_info[i].valid_data_len = -+ bin->header_info[i].bin_data_len; -+ } -+ } -+ } -+ DBG("aw_bin_parse parsing success\n"); -+ -+ return 0; -+} -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.h b/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.h -new file mode 100644 -index 000000000..c6e6eaa8a ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_bin_parse.h -@@ -0,0 +1,73 @@ -+#ifndef __AW87XXX_BIN_PARSE_H__ -+#define __AW87XXX_BIN_PARSE_H__ -+ -+#define NULL ((void *)0) -+#define GET_32_DATA(w, x, y, z) ((unsigned int)(((w) << 24) | ((x) << 16) | ((y) << 8) | (z))) -+#define BIN_NUM_MAX 100 -+#define HEADER_LEN 60 -+/********************************************************* -+ * -+ * header information -+ * -+ ********************************************************/ -+enum bin_header_version_enum { -+ HEADER_VERSION_1_0_0 = 0x01000000, -+}; -+ -+enum data_type_enum { -+ DATA_TYPE_REGISTER = 0x00000000, -+ DATA_TYPE_DSP_REG = 0x00000010, -+ DATA_TYPE_DSP_CFG = 0x00000011, -+ DATA_TYPE_SOC_REG = 0x00000020, -+ DATA_TYPE_SOC_APP = 0x00000021, -+ DATA_TYPE_MULTI_BINS = 0x00002000, -+ DATA_TYPE_MONITOR_ANALOG = 0x00020000, -+}; -+ -+enum data_version_enum { -+ DATA_VERSION_V1 = 0X00000001, /*default little edian */ -+ DATA_VERSION_MAX, -+}; -+ -+struct bin_header_info { -+ unsigned int header_len; /* Frame header length */ -+ unsigned int check_sum; /* Frame header information-Checksum */ -+ unsigned int header_ver; /* Frame header information-Frame header version */ -+ unsigned int bin_data_type; /* Frame header information-Data type */ -+ unsigned int bin_data_ver; /* Frame header information-Data version */ -+ unsigned int bin_data_len; /* Frame header information-Data length */ -+ unsigned int ui_ver; /* Frame header information-ui version */ -+ unsigned char chip_type[8]; /* Frame header information-chip type */ -+ unsigned int reg_byte_len; /* Frame header information-reg byte len */ -+ unsigned int data_byte_len; /* Frame header information-data byte len */ -+ unsigned int device_addr; /* Frame header information-device addr */ -+ unsigned int valid_data_len; /* Length of valid data obtained after parsing */ -+ unsigned int valid_data_addr; /* The offset address of the valid data obtained after parsing relative to info */ -+ -+ unsigned int reg_num; /* The number of registers obtained after parsing */ -+ unsigned int reg_data_byte_len; /* The byte length of the register obtained after parsing */ -+ unsigned int download_addr; /* The starting address or download address obtained after parsing */ -+ unsigned int app_version; /* The software version number obtained after parsing */ -+}; -+ -+/************************************************************ -+* -+* function define -+* -+************************************************************/ -+struct bin_container { -+ unsigned int len; /* The size of the bin file obtained from the firmware */ -+ unsigned char data[]; /* Store the bin file obtained from the firmware */ -+}; -+ -+struct aw_bin { -+ unsigned char *p_addr; /* Offset pointer (backward offset pointer to obtain frame header information and important information) */ -+ unsigned int all_bin_parse_num; /* The number of all bin files */ -+ unsigned int multi_bin_parse_num; /* The number of single bin files */ -+ unsigned int single_bin_parse_num; /* The number of multiple bin files */ -+ struct bin_header_info header_info[BIN_NUM_MAX]; /* Frame header information and other important data obtained after parsing */ -+ struct bin_container info; /* Obtained bin file data that needs to be parsed */ -+}; -+ -+extern int aw87xxx_parsing_bin_file(struct aw_bin *bin); -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_device.c b/sound/soc/codecs/aw87xxx/aw87xxx_device.c -new file mode 100644 -index 000000000..087770857 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_device.c -@@ -0,0 +1,977 @@ -+/* -+ * aw87xxx_device.c aw87xxx pa module -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#include <linux/i2c.h> -+#include <linux/gpio.h> -+#include <linux/of_gpio.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+#include <linux/kernel.h> -+#include <linux/device.h> -+#include <linux/irq.h> -+#include <linux/io.h> -+#include <linux/init.h> -+#include <linux/timer.h> -+#include "aw87xxx.h" -+#include "aw87xxx_device.h" -+#include "aw87xxx_log.h" -+#include "aw87xxx_pid_9b_reg.h" -+#include "aw87xxx_pid_18_reg.h" -+#include "aw87xxx_pid_39_reg.h" -+#include "aw87xxx_pid_59_3x9_reg.h" -+#include "aw87xxx_pid_59_5x9_reg.h" -+#include "aw87xxx_pid_5a_reg.h" -+#include "aw87xxx_pid_76_reg.h" -+#include "aw87xxx_pid_60_reg.h" -+ -+/************************************************************************* -+ * aw87xxx variable -+ ************************************************************************/ -+const char *g_aw_pid_9b_product[] = { -+ "aw87319", -+}; -+const char *g_aw_pid_18_product[] = { -+ "aw87418", -+}; -+ -+const char *g_aw_pid_39_product[] = { -+ "aw87329", -+ "aw87339", -+ "aw87349", -+}; -+ -+const char *g_aw_pid_59_3x9_product[] = { -+ "aw87359", -+ "aw87389", -+}; -+ -+const char *g_aw_pid_59_5x9_product[] = { -+ "aw87509", -+ "aw87519", -+ "aw87529", -+ "aw87539", -+}; -+ -+const char *g_aw_pid_5a_product[] = { -+ "aw87549", -+ "aw87559", -+ "aw87569", -+ "aw87579", -+ "aw81509", -+}; -+ -+const char *g_aw_pid_76_product[] = { -+ "aw87390", -+ "aw87320", -+ "aw87401", -+ "aw87360", -+}; -+ -+const char *g_aw_pid_60_product[] = { -+ "aw87560", -+ "aw87561", -+ "aw87562", -+ "aw87501", -+ "aw87550", -+}; -+ -+static int aw87xxx_dev_get_chipid(struct aw_device *aw_dev); -+ -+/*************************************************************************** -+ * -+ * reading and writing of I2C bus -+ * -+ ***************************************************************************/ -+int aw87xxx_dev_i2c_write_byte(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t reg_data) -+{ -+ int ret = -1; -+ unsigned char cnt = 0; -+ -+ while (cnt < AW_I2C_RETRIES) { -+ ret = i2c_smbus_write_byte_data(aw_dev->i2c, reg_addr, reg_data); -+ if (ret < 0) -+ AW_DEV_LOGE(aw_dev->dev, "i2c_write cnt=%d error=%d", -+ cnt, ret); -+ else -+ break; -+ -+ cnt++; -+ msleep(AW_I2C_RETRY_DELAY); -+ } -+ -+ return ret; -+} -+ -+int aw87xxx_dev_i2c_read_byte(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t *reg_data) -+{ -+ int ret = -1; -+ unsigned char cnt = 0; -+ -+ while (cnt < AW_I2C_RETRIES) { -+ ret = i2c_smbus_read_byte_data(aw_dev->i2c, reg_addr); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "i2c_read cnt=%d error=%d", -+ cnt, ret); -+ } else { -+ *reg_data = ret; -+ break; -+ } -+ cnt++; -+ msleep(AW_I2C_RETRY_DELAY); -+ } -+ -+ return ret; -+} -+ -+int aw87xxx_dev_i2c_read_msg(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len) -+{ -+ int ret = -1; -+ -+ struct i2c_msg msg[] = { -+ [0] = { -+ .addr = aw_dev->i2c_addr, -+ .flags = 0, -+ .len = sizeof(uint8_t), -+ .buf = ®_addr, -+ }, -+ [1] = { -+ .addr = aw_dev->i2c_addr, -+ .flags = I2C_M_RD, -+ .len = data_len, -+ .buf = data_buf, -+ }, -+ }; -+ -+ ret = i2c_transfer(aw_dev->i2c->adapter, msg, ARRAY_SIZE(msg)); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "transfer failed"); -+ return ret; -+ } else if (ret != AW_I2C_READ_MSG_NUM) { -+ AW_DEV_LOGE(aw_dev->dev, "transfer failed(size error)"); -+ return -ENXIO; -+ } -+ -+ return 0; -+} -+ -+int aw87xxx_dev_i2c_write_bits(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t mask, uint8_t reg_data) -+{ -+ int ret = -1; -+ unsigned char reg_val = 0; -+ -+ ret = aw87xxx_dev_i2c_read_byte(aw_dev, reg_addr, ®_val); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "i2c read error, ret=%d", ret); -+ return ret; -+ } -+ reg_val &= mask; -+ reg_val |= (reg_data & (~mask)); -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, reg_addr, reg_val); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "i2c write error, ret=%d", ret); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/************************************************************************ -+ * -+ * aw87xxx device update profile data to registers -+ * -+ ************************************************************************/ -+static int aw87xxx_dev_reg_update(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data) -+{ -+ int i = 0; -+ int ret = -1; -+ -+ if (profile_data == NULL) -+ return -EINVAL; -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGE(aw_dev->dev, "dev is pwr_off,can not update reg"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < profile_data->len; i = i + 2) { -+ AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x", -+ profile_data->data[i], profile_data->data[i + 1]); -+ -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, profile_data->data[i], -+ profile_data->data[i + 1]); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static void aw87xxx_dev_reg_mute_bits_set(struct aw_device *aw_dev, -+ uint8_t *reg_val, bool enable) -+{ -+ if (enable) { -+ *reg_val &= aw_dev->mute_desc.mask; -+ *reg_val |= aw_dev->mute_desc.enable; -+ } else { -+ *reg_val &= aw_dev->mute_desc.mask; -+ *reg_val |= aw_dev->mute_desc.disable; -+ } -+} -+ -+static int aw87xxx_dev_reg_update_mute(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data) -+{ -+ int i = 0; -+ int ret = -1; -+ uint8_t reg_val = 0; -+ -+ if (profile_data == NULL) -+ return -EINVAL; -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGE(aw_dev->dev, "hwen is off,can not update reg"); -+ return -EINVAL; -+ } -+ -+ if (aw_dev->mute_desc.mask == AW_DEV_REG_INVALID_MASK) { -+ AW_DEV_LOGE(aw_dev->dev, "mute ctrl mask invalid"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < profile_data->len; i = i + 2) { -+ AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x", -+ profile_data->data[i], profile_data->data[i + 1]); -+ -+ reg_val = profile_data->data[i + 1]; -+ if (profile_data->data[i] == aw_dev->mute_desc.addr) { -+ aw87xxx_dev_reg_mute_bits_set(aw_dev, ®_val, true); -+ AW_DEV_LOGD(aw_dev->dev, "change mute_mask, val = 0x%02x", -+ reg_val); -+ } -+ -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, profile_data->data[i], reg_val); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/************************************************************************ -+ * -+ * aw87xxx device hadware and soft contols -+ * -+ ************************************************************************/ -+static bool aw87xxx_dev_gpio_is_valid(struct aw_device *aw_dev) -+{ -+ if (gpio_is_valid(aw_dev->rst_gpio)) -+ return true; -+ else -+ return false; -+} -+ -+void aw87xxx_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable) -+{ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_INVALID) { -+ AW_DEV_LOGD(aw_dev->dev, "product not have reset-pin,hardware pwd control invalid"); -+ return; -+ } -+ if (enable) { -+ if (aw87xxx_dev_gpio_is_valid(aw_dev)) { -+ gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL); -+ mdelay(2); -+ gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_HIGHT_LEVEL); -+ mdelay(2); -+ aw_dev->hwen_status = AW_DEV_HWEN_ON; -+ AW_DEV_LOGI(aw_dev->dev, "hw power on"); -+ } else { -+ AW_DEV_LOGI(aw_dev->dev, "hw already power on"); -+ } -+ } else { -+ if (aw87xxx_dev_gpio_is_valid(aw_dev)) { -+ gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL); -+ mdelay(2); -+ aw_dev->hwen_status = AW_DEV_HWEN_OFF; -+ AW_DEV_LOGI(aw_dev->dev, "hw power off"); -+ } else { -+ AW_DEV_LOGI(aw_dev->dev, "hw already power off"); -+ } -+ } -+} -+ -+static int aw87xxx_dev_mute_ctrl(struct aw_device *aw_dev, bool enable) -+{ -+ int ret = 0; -+ -+ if (enable) { -+ ret = aw87xxx_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr, -+ aw_dev->mute_desc.mask, aw_dev->mute_desc.enable); -+ if (ret < 0) -+ return ret; -+ AW_DEV_LOGI(aw_dev->dev, "set mute down"); -+ } else { -+ ret = aw87xxx_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr, -+ aw_dev->mute_desc.mask, aw_dev->mute_desc.disable); -+ if (ret < 0) -+ return ret; -+ AW_DEV_LOGI(aw_dev->dev, "close mute down"); -+ } -+ -+ return 0; -+} -+ -+void aw87xxx_dev_soft_reset(struct aw_device *aw_dev) -+{ -+ int i = 0; -+ int ret = -1; -+ struct aw_soft_rst_desc *soft_rst = &aw_dev->soft_rst_desc; -+ -+ AW_DEV_LOGD(aw_dev->dev, "enter"); -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGE(aw_dev->dev, "hw is off,can not softrst"); -+ return; -+ } -+ -+ if (aw_dev->soft_rst_enable == AW_DEV_SOFT_RST_DISENABLE) { -+ AW_DEV_LOGD(aw_dev->dev, "softrst is disenable"); -+ return; -+ } -+ -+ if (soft_rst->access == NULL || soft_rst->len == 0) { -+ AW_DEV_LOGE(aw_dev->dev, "softrst_info not init"); -+ return; -+ } -+ -+ if (soft_rst->len % 2) { -+ AW_DEV_LOGE(aw_dev->dev, "softrst data_len[%d] is odd number,data not available", -+ aw_dev->soft_rst_desc.len); -+ return; -+ } -+ -+ for (i = 0; i < soft_rst->len; i += 2) { -+ AW_DEV_LOGD(aw_dev->dev, "softrst_reg=0x%02x, val = 0x%02x", -+ soft_rst->access[i], soft_rst->access[i + 1]); -+ -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, soft_rst->access[i], -+ soft_rst->access[i + 1]); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "write failed,ret = %d,cnt=%d", -+ ret, i); -+ return; -+ } -+ } -+ AW_DEV_LOGD(aw_dev->dev, "down"); -+} -+ -+ -+int aw87xxx_dev_default_pwr_off(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data) -+{ -+ int ret = 0; -+ -+ AW_DEV_LOGD(aw_dev->dev, "enter"); -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGE(aw_dev->dev, "hwen is already off"); -+ return 0; -+ } -+ -+ if (aw_dev->soft_off_enable && profile_data) { -+ ret = aw87xxx_dev_reg_update(aw_dev, profile_data); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "update profile[Off] fw config failed"); -+ goto reg_off_update_failed; -+ } -+ } -+ -+ aw87xxx_dev_hw_pwr_ctrl(aw_dev, false); -+ AW_DEV_LOGD(aw_dev->dev, "down"); -+ return 0; -+ -+reg_off_update_failed: -+ aw87xxx_dev_hw_pwr_ctrl(aw_dev, false); -+ return ret; -+} -+ -+ -+/************************************************************************ -+ * -+ * aw87xxx device power on process function -+ * -+ ************************************************************************/ -+ -+int aw87xxx_dev_default_pwr_on(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data) -+{ -+ int ret = 0; -+ -+ /*hw power on*/ -+ aw87xxx_dev_hw_pwr_ctrl(aw_dev, true); -+ -+ ret = aw87xxx_dev_reg_update(aw_dev, profile_data); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+/**************************************************************************** -+ * -+ * aw87xxx chip esd status check -+ * -+ ****************************************************************************/ -+int aw87xxx_dev_esd_reg_status_check(struct aw_device *aw_dev) -+{ -+ int ret; -+ unsigned char reg_val = 0; -+ struct aw_esd_check_desc *esd_desc = &aw_dev->esd_desc; -+ -+ AW_DEV_LOGD(aw_dev->dev, "enter"); -+ -+ if (!esd_desc->first_update_reg_addr) { -+ AW_DEV_LOGE(aw_dev->dev, "esd check info if not init,please check"); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_dev_i2c_read_byte(aw_dev, esd_desc->first_update_reg_addr, -+ ®_val); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed", -+ esd_desc->first_update_reg_addr); -+ return ret; -+ } -+ -+ AW_DEV_LOGD(aw_dev->dev, "0x%02x:default val=0x%02x real val=0x%02x", -+ esd_desc->first_update_reg_addr, -+ esd_desc->first_update_reg_val, reg_val); -+ -+ if (reg_val == esd_desc->first_update_reg_val) { -+ AW_DEV_LOGE(aw_dev->dev, "reg status check failed"); -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+int aw87xxx_dev_check_reg_is_rec_mode(struct aw_device *aw_dev) -+{ -+ int ret; -+ unsigned char reg_val = 0; -+ struct aw_rec_mode_desc *rec_desc = &aw_dev->rec_desc; -+ -+ if (!rec_desc->addr) { -+ AW_DEV_LOGE(aw_dev->dev, "rec check info if not init,please check"); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_dev_i2c_read_byte(aw_dev, rec_desc->addr, ®_val); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed", -+ rec_desc->addr); -+ return ret; -+ } -+ -+ if (rec_desc->enable) { -+ if (reg_val & ~(rec_desc->mask)) { -+ AW_DEV_LOGI(aw_dev->dev, "reg status is receiver mode"); -+ aw_dev->is_rec_mode = AW_IS_REC_MODE; -+ } else { -+ aw_dev->is_rec_mode = AW_NOT_REC_MODE; -+ } -+ } else { -+ if (!(reg_val & ~(rec_desc->mask))) { -+ AW_DEV_LOGI(aw_dev->dev, "reg status is receiver mode"); -+ aw_dev->is_rec_mode = AW_IS_REC_MODE; -+ } else { -+ aw_dev->is_rec_mode = AW_NOT_REC_MODE; -+ } -+ } -+ return 0; -+} -+ -+ -+/**************************************************************************** -+ * -+ * aw87xxx product attributes init info -+ * -+ ****************************************************************************/ -+ -+/********************** aw87xxx_pid_9A attributes ***************************/ -+ -+static int aw_dev_pid_9b_reg_update(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data) -+{ -+ int i = 0; -+ int ret = -1; -+ uint8_t reg_val = 0; -+ -+ if (profile_data == NULL) -+ return -EINVAL; -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGE(aw_dev->dev, "dev is pwr_off,can not update reg"); -+ return -EINVAL; -+ } -+ -+ if (profile_data->len != AW_PID_9B_BIN_REG_CFG_COUNT) { -+ AW_DEV_LOGE(aw_dev->dev, "reg_config count of bin is error,can not update reg"); -+ return -EINVAL; -+ } -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG, -+ AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET); -+ if (ret < 0) -+ return ret; -+ -+ for (i = 1; i < AW_PID_9B_BIN_REG_CFG_COUNT; i++) { -+ AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x", -+ i, profile_data->data[i]); -+ reg_val = profile_data->data[i]; -+ if (i == AW87XXX_PID_9B_SYSCTRL_REG) { -+ aw87xxx_dev_reg_mute_bits_set(aw_dev, ®_val, true); -+ AW_DEV_LOGD(aw_dev->dev, "change mute_mask, val = 0x%02x", -+ reg_val); -+ } -+ -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, i, reg_val); -+ if (ret < 0) -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int aw_dev_pid_9b_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data) -+{ -+ int ret = 0; -+ -+ /*hw power on*/ -+ aw87xxx_dev_hw_pwr_ctrl(aw_dev, true); -+ -+ /* open the mute */ -+ ret = aw87xxx_dev_mute_ctrl(aw_dev, true); -+ if (ret < 0) -+ return ret; -+ -+ /* Update scene parameters in mute mode */ -+ ret = aw_dev_pid_9b_reg_update(aw_dev, data); -+ if (ret < 0) -+ return ret; -+ -+ /* close the mute */ -+ ret = aw87xxx_dev_mute_ctrl(aw_dev, false); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+static void aw_dev_pid_9b_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_9B_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_9b_reg_access; -+ -+ aw_dev->mute_desc.addr = AW87XXX_PID_9B_SYSCTRL_REG; -+ aw_dev->mute_desc.mask = AW87XXX_PID_9B_REG_EN_SW_MASK; -+ aw_dev->mute_desc.enable = AW87XXX_PID_9B_REG_EN_SW_DISABLE_VALUE; -+ aw_dev->mute_desc.disable = AW87XXX_PID_9B_REG_EN_SW_ENABLE_VALUE; -+ aw_dev->ops.pwr_on_func = aw_dev_pid_9b_pwr_on; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_9b_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_9b_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_DISENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_9b_product; -+ aw_dev->product_cnt = AW87XXX_PID_9B_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_9B_SYSCTRL_REG; -+ aw_dev->rec_desc.disable = AW87XXX_PID_9B_SPK_MODE_ENABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_9B_SPK_MODE_DISABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_9B_SPK_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_9B_SYSCTRL_REG; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_9B_SYSCTRL_DEFAULT; -+} -+ -+static int aw_dev_pid_9a_init(struct aw_device *aw_dev) -+{ -+ int ret = 0; -+ -+ ret = aw87xxx_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG, -+ AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "write 0x64=0x2C error"); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_dev_get_chipid(aw_dev); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret); -+ return ret; -+ } -+ -+ if (aw_dev->chipid == AW_DEV_CHIPID_9B) { -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class"); -+ aw_dev_pid_9b_init(aw_dev); -+ } else { -+ AW_DEV_LOGE(aw_dev->dev, "product is not pid_9B class，not support"); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+/********************** aw87xxx_pid_9b attributes end ***********************/ -+ -+/********************** aw87xxx_pid_18 attributes ***************************/ -+static int aw_dev_pid_18_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data) -+{ -+ int ret = 0; -+ -+ /*hw power on*/ -+ aw87xxx_dev_hw_pwr_ctrl(aw_dev, true); -+ -+ /* open the mute */ -+ ret = aw87xxx_dev_mute_ctrl(aw_dev, true); -+ if (ret < 0) -+ return ret; -+ -+ /* Update scene parameters in mute mode */ -+ ret = aw87xxx_dev_reg_update_mute(aw_dev, data); -+ if (ret < 0) -+ return ret; -+ -+ /* close the mute */ -+ ret = aw87xxx_dev_mute_ctrl(aw_dev, false); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+} -+ -+static void aw_dev_chipid_18_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_18_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_18_reg_access; -+ -+ aw_dev->mute_desc.addr = AW87XXX_PID_18_SYSCTRL_REG; -+ aw_dev->mute_desc.mask = AW87XXX_PID_18_REG_EN_SW_MASK; -+ aw_dev->mute_desc.enable = AW87XXX_PID_18_REG_EN_SW_DISABLE_VALUE; -+ aw_dev->mute_desc.disable = AW87XXX_PID_18_REG_EN_SW_ENABLE_VALUE; -+ aw_dev->ops.pwr_on_func = aw_dev_pid_18_pwr_on; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_18_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_18_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_18_product; -+ aw_dev->product_cnt = AW87XXX_PID_18_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_18_SYSCTRL_REG; -+ aw_dev->rec_desc.disable = AW87XXX_PID_18_REG_REC_MODE_DISABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_18_REG_REC_MODE_ENABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_18_REG_REC_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_18_CLASSD_REG; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_18_CLASSD_DEFAULT; -+} -+/********************** aw87xxx_pid_18 attributes end ***********************/ -+ -+/********************** aw87xxx_pid_39 attributes ***************************/ -+static void aw_dev_chipid_39_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_39_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_39_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_39_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_39_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_39_product; -+ aw_dev->product_cnt = AW87XXX_PID_39_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_39_REG_MODECTRL; -+ aw_dev->rec_desc.disable = AW87XXX_PID_39_REC_MODE_DISABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_39_REC_MODE_ENABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_39_REC_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_39_REG_MODECTRL; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_39_MODECTRL_DEFAULT; -+} -+/********************* aw87xxx_pid_39 attributes end *************************/ -+ -+ -+/********************* aw87xxx_pid_59_5x9 attributes *************************/ -+static void aw_dev_chipid_59_5x9_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_59_5X9_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_59_5x9_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_59_5x9_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_59_5x9_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_59_5x9_product; -+ aw_dev->product_cnt = AW87XXX_PID_59_5X9_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_59_5X9_REG_SYSCTRL; -+ aw_dev->rec_desc.disable = AW87XXX_PID_59_5X9_REC_MODE_DISABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_59_5X9_REC_MODE_ENABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_59_5X9_REC_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_5X9_REG_ENCR; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_5X9_ENCRY_DEFAULT; -+} -+/******************* aw87xxx_pid_59_5x9 attributes end ***********************/ -+ -+/********************* aw87xxx_pid_59_3x9 attributes *************************/ -+static void aw_dev_chipid_59_3x9_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_59_3X9_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_59_3x9_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_59_3x9_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_59_3x9_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_59_3x9_product; -+ aw_dev->product_cnt = AW87XXX_PID_59_3X9_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_59_3X9_REG_MDCRTL; -+ aw_dev->rec_desc.disable = AW87XXX_PID_59_3X9_SPK_MODE_ENABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_59_3X9_SPK_MODE_DISABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_59_3X9_SPK_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_3X9_REG_ENCR; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_3X9_ENCR_DEFAULT; -+} -+/******************* aw87xxx_pid_59_3x9 attributes end ***********************/ -+ -+/********************** aw87xxx_pid_5a attributes ****************************/ -+static void aw_dev_chipid_5a_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_5A_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_5a_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_5a_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_5a_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* Whether to allow register operation to power off */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_5a_product; -+ aw_dev->product_cnt = AW87XXX_PID_5A_PRODUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_5A_REG_SYSCTRL_REG; -+ aw_dev->rec_desc.disable = AW87XXX_PID_5A_REG_RCV_MODE_DISABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_5A_REG_RCV_MODE_ENABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_5A_REG_RCV_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_5A_REG_DFT3R_REG; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_5A_DFT3R_DEFAULT; -+} -+/********************** aw87xxx_pid_5a attributes end ************************/ -+ -+/********************** aw87xxx_pid_76 attributes ****************************/ -+static void aw_dev_chipid_76_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_76_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_76_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_76_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_76_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* software power off control info */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_76_product; -+ aw_dev->product_cnt = AW87XXX_PID_76_PROFUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_76_MDCTRL_REG; -+ aw_dev->rec_desc.disable = AW87XXX_PID_76_EN_SPK_ENABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_76_EN_SPK_DISABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_76_EN_SPK_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_76_DFT_ADP1_REG; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_76_DFT_ADP1_CHECK; -+} -+/********************** aw87xxx_pid_76 attributes end ************************/ -+ -+/********************** aw87xxx_pid_60 attributes ****************************/ -+static void aw_dev_chipid_60_init(struct aw_device *aw_dev) -+{ -+ /* Product register permission info */ -+ aw_dev->reg_max_addr = AW87XXX_PID_60_REG_MAX; -+ aw_dev->reg_access = aw87xxx_pid_60_reg_access; -+ -+ /* software reset control info */ -+ aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_60_softrst_access); -+ aw_dev->soft_rst_desc.access = aw87xxx_pid_60_softrst_access; -+ aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE; -+ -+ /* software power off control info */ -+ aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE; -+ -+ aw_dev->product_tab = g_aw_pid_60_product; -+ aw_dev->product_cnt = AW87XXX_PID_60_PROFUCT_MAX; -+ -+ aw_dev->rec_desc.addr = AW87XXX_PID_60_SYSCTRL_REG; -+ aw_dev->rec_desc.disable = AW87XXX_PID_60_RCV_MODE_DISABLE; -+ aw_dev->rec_desc.enable = AW87XXX_PID_60_RCV_MODE_ENABLE; -+ aw_dev->rec_desc.mask = AW87XXX_PID_60_RCV_MODE_MASK; -+ -+ /* esd reg info */ -+ aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_60_NG3_REG; -+ aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_60_ESD_REG_VAL; -+} -+/********************** aw87xxx_pid_60 attributes end ************************/ -+ -+static int aw_dev_chip_init(struct aw_device *aw_dev) -+{ -+ int ret = 0; -+ -+ /*get info by chipid*/ -+ switch (aw_dev->chipid) { -+ case AW_DEV_CHIPID_9A: -+ ret = aw_dev_pid_9a_init(aw_dev); -+ if (ret < 0) -+ AW_DEV_LOGE(aw_dev->dev, "product is pid_9B init failed"); -+ break; -+ case AW_DEV_CHIPID_9B: -+ aw_dev_pid_9b_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class"); -+ break; -+ case AW_DEV_CHIPID_18: -+ aw_dev_chipid_18_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_18 class"); -+ break; -+ case AW_DEV_CHIPID_39: -+ aw_dev_chipid_39_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_39 class"); -+ break; -+ case AW_DEV_CHIPID_59: -+ if (aw87xxx_dev_gpio_is_valid(aw_dev)) { -+ aw_dev_chipid_59_5x9_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_59_5x9 class"); -+ } else { -+ aw_dev_chipid_59_3x9_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_59_3x9 class"); -+ } -+ break; -+ case AW_DEV_CHIPID_5A: -+ aw_dev_chipid_5a_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_5A class"); -+ break; -+ case AW_DEV_CHIPID_76: -+ aw_dev_chipid_76_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_76 class"); -+ break; -+ case AW_DEV_CHIPID_60: -+ aw_dev_chipid_60_init(aw_dev); -+ AW_DEV_LOGI(aw_dev->dev, "product is pid_60 class"); -+ break; -+ default: -+ AW_DEV_LOGE(aw_dev->dev, "unsupported device revision [0x%x]", -+ aw_dev->chipid); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw87xxx_dev_get_chipid(struct aw_device *aw_dev) -+{ -+ int ret = -1; -+ unsigned int cnt = 0; -+ unsigned char reg_val = 0; -+ -+ for (cnt = 0; cnt < AW_READ_CHIPID_RETRIES; cnt++) { -+ ret = aw87xxx_dev_i2c_read_byte(aw_dev, AW_DEV_REG_CHIPID, ®_val); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "[%d] read chip is failed, ret=%d", -+ cnt, ret); -+ continue; -+ } -+ break; -+ } -+ -+ -+ if (cnt == AW_READ_CHIPID_RETRIES) { -+ AW_DEV_LOGE(aw_dev->dev, "read chip is failed,cnt=%d", cnt); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(aw_dev->dev, "read chipid[0x%x] succeed", reg_val); -+ aw_dev->chipid = reg_val; -+ -+ return 0; -+} -+ -+int aw87xxx_dev_init(struct aw_device *aw_dev) -+{ -+ int ret = -1; -+ -+ ret = aw87xxx_dev_get_chipid(aw_dev); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret); -+ return ret; -+ } -+ -+ ret = aw_dev_chip_init(aw_dev); -+ -+ return ret; -+} -+ -+ -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_device.h b/sound/soc/codecs/aw87xxx/aw87xxx_device.h -new file mode 100644 -index 000000000..b063218e3 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_device.h -@@ -0,0 +1,149 @@ -+#ifndef __AW87XXX_DEVICE_H__ -+#define __AW87XXX_DEVICE_H__ -+#include <linux/version.h> -+#include <linux/kernel.h> -+#include <sound/control.h> -+#include <sound/soc.h> -+#include "aw87xxx_acf_bin.h" -+ -+#define AW87XXX_PID_9B_PRODUCT_MAX (1) -+#define AW87XXX_PID_18_PRODUCT_MAX (1) -+#define AW87XXX_PID_39_PRODUCT_MAX (3) -+#define AW87XXX_PID_59_3X9_PRODUCT_MAX (2) -+#define AW87XXX_PID_59_5X9_PRODUCT_MAX (4) -+#define AW87XXX_PID_5A_PRODUCT_MAX (5) -+#define AW87XXX_PID_76_PROFUCT_MAX (4) -+#define AW87XXX_PID_60_PROFUCT_MAX (5) -+#define AW_PRODUCT_NAME_LEN (8) -+ -+#define AW_GPIO_HIGHT_LEVEL (1) -+#define AW_GPIO_LOW_LEVEL (0) -+ -+#define AW_I2C_RETRIES (5) -+#define AW_I2C_RETRY_DELAY (2) -+#define AW_I2C_READ_MSG_NUM (2) -+ -+#define AW_READ_CHIPID_RETRIES (5) -+#define AW_READ_CHIPID_RETRY_DELAY (2) -+#define AW_DEV_REG_CHIPID (0x00) -+ -+#define AW_DEV_REG_INVALID_MASK (0xff) -+ -+#define AW_NO_RESET_GPIO (-1) -+ -+#define AW_PID_9B_BIN_REG_CFG_COUNT (10) -+ -+/******************************************** -+ * -+ * aw87xxx devices attributes -+ * -+ *******************************************/ -+struct aw_device; -+ -+struct aw_device_ops { -+ int (*pwr_on_func)(struct aw_device *aw_dev, struct aw_data_container *data); -+ int (*pwr_off_func)(struct aw_device *aw_dev, struct aw_data_container *data); -+}; -+ -+enum aw_dev_chipid { -+ AW_DEV_CHIPID_18 = 0x18, -+ AW_DEV_CHIPID_39 = 0x39, -+ AW_DEV_CHIPID_59 = 0x59, -+ AW_DEV_CHIPID_69 = 0x69, -+ AW_DEV_CHIPID_5A = 0x5A, -+ AW_DEV_CHIPID_9A = 0x9A, -+ AW_DEV_CHIPID_9B = 0x9B, -+ AW_DEV_CHIPID_76 = 0x76, -+ AW_DEV_CHIPID_60 = 0x60, -+}; -+ -+enum aw_dev_hw_status { -+ AW_DEV_HWEN_OFF = 0, -+ AW_DEV_HWEN_ON, -+ AW_DEV_HWEN_INVALID, -+ AW_DEV_HWEN_STATUS_MAX, -+}; -+ -+enum aw_dev_soft_off_enable { -+ AW_DEV_SOFT_OFF_DISENABLE = 0, -+ AW_DEV_SOFT_OFF_ENABLE = 1, -+}; -+ -+enum aw_dev_soft_rst_enable { -+ AW_DEV_SOFT_RST_DISENABLE = 0, -+ AW_DEV_SOFT_RST_ENABLE = 1, -+}; -+ -+enum aw_reg_receiver_mode { -+ AW_NOT_REC_MODE = 0, -+ AW_IS_REC_MODE = 1, -+}; -+ -+struct aw_mute_desc { -+ uint8_t addr; -+ uint8_t enable; -+ uint8_t disable; -+ uint16_t mask; -+}; -+ -+struct aw_soft_rst_desc { -+ int len; -+ unsigned char *access; -+}; -+ -+struct aw_esd_check_desc { -+ uint8_t first_update_reg_addr; -+ uint8_t first_update_reg_val; -+}; -+ -+struct aw_rec_mode_desc { -+ uint8_t addr; -+ uint8_t enable; -+ uint8_t disable; -+ uint8_t mask; -+}; -+ -+struct aw_device { -+ uint8_t i2c_addr; -+ uint8_t chipid; -+ uint8_t soft_rst_enable; -+ uint8_t soft_off_enable; -+ uint8_t is_rec_mode; -+ int hwen_status; -+ int i2c_bus; -+ int rst_gpio; -+ int reg_max_addr; -+ int product_cnt; -+ const char **product_tab; -+ const unsigned char *reg_access; -+ -+ struct device *dev; -+ struct i2c_client *i2c; -+ struct aw_mute_desc mute_desc; -+ struct aw_soft_rst_desc soft_rst_desc; -+ struct aw_esd_check_desc esd_desc; -+ struct aw_rec_mode_desc rec_desc; -+ -+ struct aw_device_ops ops; -+}; -+ -+ -+int aw87xxx_dev_i2c_write_byte(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t reg_data); -+int aw87xxx_dev_i2c_read_byte(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t *reg_data); -+int aw87xxx_dev_i2c_read_msg(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len); -+int aw87xxx_dev_i2c_write_bits(struct aw_device *aw_dev, -+ uint8_t reg_addr, uint8_t mask, uint8_t reg_data); -+void aw87xxx_dev_soft_reset(struct aw_device *aw_dev); -+void aw87xxx_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable); -+int aw87xxx_dev_default_pwr_on(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data); -+int aw87xxx_dev_default_pwr_off(struct aw_device *aw_dev, -+ struct aw_data_container *profile_data); -+int aw87xxx_dev_esd_reg_status_check(struct aw_device *aw_dev); -+int aw87xxx_dev_check_reg_is_rec_mode(struct aw_device *aw_dev); -+int aw87xxx_dev_init(struct aw_device *aw_dev); -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_dsp.c b/sound/soc/codecs/aw87xxx/aw87xxx_dsp.c -new file mode 100644 -index 000000000..bd9896cd1 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_dsp.c -@@ -0,0 +1,355 @@ -+/* -+ * aw87xxx_dsp.c -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+ -+#include <linux/uaccess.h> -+#include <linux/delay.h> -+#include <linux/device.h> -+#include <linux/kernel.h> -+#include <linux/of.h> -+#include <linux/slab.h> -+#include <linux/hrtimer.h> -+#include <linux/proc_fs.h> -+#include <linux/init.h> -+#include "aw87xxx_log.h" -+#include "aw87xxx_dsp.h" -+ -+static DEFINE_MUTEX(g_dsp_lock); -+static unsigned int g_spin_value = 0; -+ -+static int g_rx_topo_id = AW_RX_DEFAULT_TOPO_ID; -+static int g_rx_port_id = AW_RX_DEFAULT_PORT_ID; -+ -+#ifdef AW_MTK_OPEN_DSP_PLATFORM -+extern int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer, -+ uint32_t data_size); -+extern int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer, -+ int16_t size, uint32_t *buf_len); -+/* -+static int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer, -+ uint32_t data_size) -+{ -+ AW_LOGI("enter"); -+ return 0; -+} -+ -+static int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer, -+ int16_t size, uint32_t *buf_len) -+{ -+ AW_LOGI("enter"); -+ return 0; -+} -+*/ -+#elif defined AW_QCOM_OPEN_DSP_PLATFORM -+extern int afe_get_topology(int port_id); -+extern int aw_send_afe_cal_apr(uint32_t param_id, -+ void *buf, int cmd_size, bool write); -+/* -+static int afe_get_topology(int port_id) -+{ -+ return -EPERM; -+} -+ -+static int aw_send_afe_cal_apr(uint32_t param_id, -+ void *buf, int cmd_size, bool write) -+{ -+ AW_LOGI("enter, no define AWINIC_ADSP_ENABLE", __func__); -+ return 0; -+} -+*/ -+#endif -+ -+#ifdef AW_QCOM_OPEN_DSP_PLATFORM -+extern void aw_set_port_id(int rx_port_id); -+#else -+static void aw_set_port_id(int rx_port_id) -+{ -+ return; -+} -+#endif -+ -+uint8_t aw87xxx_dsp_isEnable(void) -+{ -+#if (defined AW_QCOM_OPEN_DSP_PLATFORM) || (defined AW_MTK_OPEN_DSP_PLATFORM) -+ return true; -+#else -+ return false; -+#endif -+} -+ -+/*****************mtk dsp communication function start**********************/ -+#ifdef AW_MTK_OPEN_DSP_PLATFORM -+static int aw_mtk_write_data_to_dsp(int32_t param_id, -+ void *data, int size) -+{ -+ int32_t *dsp_data = NULL; -+ mtk_dsp_hdr_t *hdr = NULL; -+ int ret; -+ -+ dsp_data = kzalloc(sizeof(mtk_dsp_hdr_t) + size, GFP_KERNEL); -+ if (!dsp_data) { -+ AW_LOGE("kzalloc dsp_msg error"); -+ return -ENOMEM; -+ } -+ -+ hdr = (mtk_dsp_hdr_t *)dsp_data; -+ hdr->type = DSP_MSG_TYPE_DATA; -+ hdr->opcode_id = param_id; -+ hdr->version = AW_DSP_MSG_HDR_VER; -+ -+ memcpy(((char *)dsp_data) + sizeof(mtk_dsp_hdr_t), -+ data, size); -+ -+ ret = mtk_spk_send_ipi_buf_to_dsp(dsp_data, -+ sizeof(mtk_dsp_hdr_t) + size); -+ if (ret < 0) { -+ AW_LOGE("write data failed"); -+ kfree(dsp_data); -+ dsp_data = NULL; -+ return ret; -+ } -+ -+ kfree(dsp_data); -+ dsp_data = NULL; -+ return 0; -+} -+ -+static int aw_mtk_read_data_from_dsp(int32_t param_id, void *data, -+ int data_size) -+{ -+ int ret; -+ mtk_dsp_hdr_t hdr; -+ -+ mutex_lock(&g_dsp_lock); -+ hdr.type = DSP_MSG_TYPE_CMD; -+ hdr.opcode_id = param_id; -+ hdr.version = AW_DSP_MSG_HDR_VER; -+ -+ ret = mtk_spk_send_ipi_buf_to_dsp(&hdr, sizeof(mtk_dsp_hdr_t)); -+ if (ret < 0) -+ goto failed; -+ -+ ret = mtk_spk_recv_ipi_buf_from_dsp(data, data_size, &data_size); -+ if (ret < 0) -+ goto failed; -+ -+ mutex_unlock(&g_dsp_lock); -+ return 0; -+ -+failed: -+ mutex_unlock(&g_dsp_lock); -+ return ret; -+} -+ -+#endif -+/********************mtk dsp communication function end***********************/ -+ -+/******************qcom dsp communication function start**********************/ -+#ifdef AW_QCOM_OPEN_DSP_PLATFORM -+static void aw_check_dsp_ready(void) -+{ -+ int ret; -+ -+ ret = afe_get_topology(g_rx_port_id); -+ AW_LOGD("topo_id 0x%x", ret); -+ -+ if (ret != g_rx_topo_id) -+ AW_LOGE("topo id 0x%x", ret); -+ -+} -+ -+static int aw_qcom_write_data_to_dsp(int32_t param_id, -+ void *data, int data_size) -+{ -+ int ret = 0; -+ -+ AW_LOGI("enter"); -+ mutex_lock(&g_dsp_lock); -+ aw_check_dsp_ready(); -+ ret = aw_send_afe_cal_apr(param_id, data, -+ data_size, true); -+ mutex_unlock(&g_dsp_lock); -+ return ret; -+} -+ -+static int aw_qcom_read_data_from_dsp(int32_t param_id, -+ void *data, int data_size) -+{ -+ int ret = 0; -+ -+ AW_LOGI("enter"); -+ mutex_lock(&g_dsp_lock); -+ aw_check_dsp_ready(); -+ ret = aw_send_afe_cal_apr(param_id, data, -+ data_size, false); -+ mutex_unlock(&g_dsp_lock); -+ return ret; -+} -+ -+#endif -+/*****************qcom dsp communication function end*********************/ -+ -+/*****************read/write msg communication function*********************/ -+static int aw_write_data_to_dsp(int32_t param_id, void *data, int data_size) -+{ -+#if defined AW_QCOM_OPEN_DSP_PLATFORM -+ return aw_qcom_write_data_to_dsp(param_id, data, data_size); -+#elif defined AW_MTK_OPEN_DSP_PLATFORM -+ return aw_mtk_write_data_to_dsp(param_id, data, data_size); -+#else -+ return -EINVAL; -+#endif -+} -+ -+static int aw_read_data_from_dsp(int32_t param_id, void *data, int data_size) -+{ -+#if defined AW_QCOM_OPEN_DSP_PLATFORM -+ return aw_qcom_read_data_from_dsp(param_id, data, data_size); -+#elif defined AW_MTK_OPEN_DSP_PLATFORM -+ return aw_mtk_read_data_from_dsp(param_id, data, data_size); -+#else -+ return -EINVAL; -+#endif -+} -+ -+/***************read/write msg communication function end*******************/ -+ -+int aw87xxx_dsp_get_rx_module_enable(int *enable) -+{ -+ if (!enable) { -+ AW_LOGE("enable is NULL"); -+ return -EINVAL; -+ } -+ -+ return aw_read_data_from_dsp(AWDSP_RX_SET_ENABLE, -+ (void *)enable, sizeof(uint32_t)); -+} -+ -+int aw87xxx_dsp_set_rx_module_enable(int enable) -+{ -+ switch (enable) { -+ case AW_RX_MODULE_DISENABLE: -+ AW_LOGD("set enable=%d", enable); -+ break; -+ case AW_RX_MODULE_ENABLE: -+ AW_LOGD("set enable=%d", enable); -+ break; -+ default: -+ AW_LOGE("unsupport enable=%d", enable); -+ return -EINVAL; -+ } -+ -+ return aw_write_data_to_dsp(AWDSP_RX_SET_ENABLE, -+ &enable, sizeof(uint32_t)); -+} -+ -+ -+int aw87xxx_dsp_get_vmax(uint32_t *vmax, int dev_index) -+{ -+ int32_t param_id = 0; -+ -+ switch (dev_index % AW_DSP_CHANNEL_MAX) { -+ case AW_DSP_CHANNEL_0: -+ param_id = AWDSP_RX_VMAX_0; -+ break; -+ case AW_DSP_CHANNEL_1: -+ param_id = AWDSP_RX_VMAX_1; -+ break; -+ default: -+ AW_LOGE("algo only support double PA channel:%d unsupport", -+ dev_index); -+ return -EINVAL; -+ } -+ -+ return aw_read_data_from_dsp(param_id, -+ (void *)vmax, sizeof(uint32_t)); -+} -+ -+int aw87xxx_dsp_set_vmax(uint32_t vmax, int dev_index) -+{ -+ int32_t param_id = 0; -+ -+ switch (dev_index % AW_DSP_CHANNEL_MAX) { -+ case AW_DSP_CHANNEL_0: -+ param_id = AWDSP_RX_VMAX_0; -+ break; -+ case AW_DSP_CHANNEL_1: -+ param_id = AWDSP_RX_VMAX_1; -+ break; -+ default: -+ AW_LOGE("algo only support double PA channel:%d unsupport", -+ dev_index); -+ return -EINVAL; -+ } -+ -+ return aw_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t)); -+} -+ -+int aw87xxx_dsp_set_spin(uint32_t ctrl_value) -+{ -+ int ret = 0; -+ -+ if (ctrl_value >= AW_SPIN_MAX) { -+ AW_LOGE("spin [%d] unsupported ", ctrl_value); -+ return -EINVAL; -+ } -+ ret = aw_write_data_to_dsp(AW_MSG_ID_SPIN, &ctrl_value, -+ sizeof(uint32_t)); -+ if (ret) { -+ AW_LOGE("spin [%d] set failed ", ctrl_value); -+ return ret; -+ } -+ -+ g_spin_value = ctrl_value; -+ return 0; -+} -+ -+int aw87xxx_dsp_get_spin(void) -+{ -+ return g_spin_value; -+} -+ -+int aw87xxx_spin_set_record_val(void) -+{ -+ AW_LOGD("record write spin enter"); -+ -+ return aw87xxx_dsp_set_spin(g_spin_value); -+} -+EXPORT_SYMBOL(aw87xxx_spin_set_record_val); -+ -+void aw87xxx_device_parse_topo_id_dt(struct aw_device *aw_dev) -+{ -+ int ret; -+ -+ ret = of_property_read_u32(aw_dev->dev->of_node, "aw-rx-topo-id", &g_rx_topo_id); -+ if (ret < 0) { -+ g_rx_topo_id = AW_RX_DEFAULT_TOPO_ID; -+ AW_DEV_LOGI(aw_dev->dev, "read aw-rx-topo-id failed,use default"); -+ } -+ -+ AW_DEV_LOGI(aw_dev->dev, "rx-topo-id: 0x%x", g_rx_topo_id); -+} -+ -+void aw87xxx_device_parse_port_id_dt(struct aw_device *aw_dev) -+{ -+ int ret; -+ -+ ret = of_property_read_u32(aw_dev->dev->of_node, "aw-rx-port-id", &g_rx_port_id); -+ if (ret < 0) { -+ g_rx_port_id = AW_RX_DEFAULT_PORT_ID; -+ AW_DEV_LOGI(aw_dev->dev, "read aw-rx-port-id failed,use default"); -+ } -+ -+ aw_set_port_id(g_rx_port_id); -+ AW_DEV_LOGI(aw_dev->dev, "rx-port-id: 0x%x", g_rx_port_id); -+} -+ -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_dsp.h b/sound/soc/codecs/aw87xxx/aw87xxx_dsp.h -new file mode 100644 -index 000000000..2668170f1 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_dsp.h -@@ -0,0 +1,65 @@ -+#ifndef __AW87XXX_DSP_H__ -+#define __AW87XXX_DSP_H__ -+ -+#include "aw87xxx_device.h" -+ -+/*#define AW_MTK_OPEN_DSP_PLATFORM*/ -+/*#define AW_QCOM_OPEN_DSP_PLATFORM*/ -+ -+/*Note: The pord_ID is configured according to different platforms*/ -+#define AW_DSP_SLEEP_TIME (10) -+ -+#define AW_DSP_MSG_HDR_VER (1) -+ -+#define AW_RX_DEFAULT_TOPO_ID (0x1000FF01) -+#define AW_RX_DEFAULT_PORT_ID (0x4000) -+ -+#define AWDSP_RX_SET_ENABLE (0x10013D11) -+#define AWDSP_RX_PARAMS (0x10013D12) -+#define AWDSP_RX_VMAX_0 (0X10013D17) -+#define AWDSP_RX_VMAX_1 (0X10013D18) -+#define AW_MSG_ID_SPIN (0x10013D2E) -+ -+enum { -+ AW_SPIN_0 = 0, -+ AW_SPIN_90, -+ AW_SPIN_180, -+ AW_SPIN_270, -+ AW_SPIN_MAX, -+}; -+ -+typedef struct mtk_dsp_msg_header { -+ int32_t type; -+ int32_t opcode_id; -+ int32_t version; -+ int32_t reserver[3]; -+} mtk_dsp_hdr_t; -+ -+enum aw_rx_module_enable { -+ AW_RX_MODULE_DISENABLE = 0, -+ AW_RX_MODULE_ENABLE, -+}; -+ -+enum aw_dsp_msg_type { -+ DSP_MSG_TYPE_DATA = 0, -+ DSP_MSG_TYPE_CMD = 1, -+}; -+ -+enum aw_dsp_channel { -+ AW_DSP_CHANNEL_0 = 0, -+ AW_DSP_CHANNEL_1, -+ AW_DSP_CHANNEL_MAX, -+}; -+ -+uint8_t aw87xxx_dsp_isEnable(void); -+int aw87xxx_dsp_get_rx_module_enable(int *enable); -+int aw87xxx_dsp_set_rx_module_enable(int enable); -+int aw87xxx_dsp_get_vmax(uint32_t *vmax, int channel); -+int aw87xxx_dsp_set_vmax(uint32_t vmax, int channel); -+int aw87xxx_dsp_set_spin(uint32_t ctrl_value); -+int aw87xxx_dsp_get_spin(void); -+int aw87xxx_spin_set_record_val(void); -+void aw87xxx_device_parse_port_id_dt(struct aw_device *aw_dev); -+void aw87xxx_device_parse_topo_id_dt(struct aw_device *aw_dev); -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_log.h b/sound/soc/codecs/aw87xxx/aw87xxx_log.h -new file mode 100644 -index 000000000..67263484d ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_log.h -@@ -0,0 +1,33 @@ -+#ifndef __AW87XXX_LOG_H__ -+#define __AW87XXX_LOG_H__ -+ -+#include <linux/kernel.h> -+ -+ -+/******************************************** -+ * -+ * print information control -+ * -+ *******************************************/ -+#define AW_LOGI(fmt, ...)\ -+ pr_info("[Awinic] %s:" fmt "\n", __func__, ##__VA_ARGS__) -+ -+#define AW_LOGD(fmt, ...)\ -+ pr_debug("[Awinic] %s:" fmt "\n", __func__, ##__VA_ARGS__) -+ -+#define AW_LOGE(fmt, ...)\ -+ pr_err("[Awinic] %s:" fmt "\n", __func__, ##__VA_ARGS__) -+ -+ -+#define AW_DEV_LOGI(dev, fmt, ...)\ -+ pr_info("[Awinic] [%s]%s: " fmt "\n", dev_name(dev), __func__, ##__VA_ARGS__) -+ -+#define AW_DEV_LOGD(dev, fmt, ...)\ -+ pr_debug("[Awinic] [%s]%s: " fmt "\n", dev_name(dev), __func__, ##__VA_ARGS__) -+ -+#define AW_DEV_LOGE(dev, fmt, ...)\ -+ pr_err("[Awinic] [%s]%s: " fmt "\n", dev_name(dev), __func__, ##__VA_ARGS__) -+ -+ -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_monitor.c b/sound/soc/codecs/aw87xxx/aw87xxx_monitor.c -new file mode 100644 -index 000000000..92305f9c4 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_monitor.c -@@ -0,0 +1,1208 @@ -+/* -+ * aw87xxx_monitor.c -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+#include <linux/module.h> -+#include <linux/uaccess.h> -+#include <linux/delay.h> -+#include <linux/slab.h> -+#include <linux/fs.h> -+#include <linux/device.h> -+#include <linux/kernel.h> -+#include <linux/power_supply.h> -+#include <linux/of.h> -+#include <linux/power_supply.h> -+#include <linux/hrtimer.h> -+#include <linux/i2c.h> -+#include <linux/gpio.h> -+#include <linux/of_gpio.h> -+#include <linux/interrupt.h> -+#include <linux/irq.h> -+#include <linux/firmware.h> -+#include <linux/platform_device.h> -+#include <linux/proc_fs.h> -+#include <linux/io.h> -+#include <linux/init.h> -+#include <linux/pci.h> -+#include <linux/dma-mapping.h> -+#include <linux/gameport.h> -+#include <linux/moduleparam.h> -+#include <linux/mutex.h> -+#include <linux/workqueue.h> -+#include "aw87xxx.h" -+#include "aw87xxx_log.h" -+#include "aw87xxx_monitor.h" -+#include "aw87xxx_dsp.h" -+#include "aw87xxx_bin_parse.h" -+#include "aw87xxx_device.h" -+ -+#define AW_MONITOT_BIN_PARSE_VERSION "V0.1.0" -+ -+#define AW_GET_32_DATA(w, x, y, z) \ -+ ((uint32_t)((((uint8_t)w) << 24) | (((uint8_t)x) << 16) | \ -+ (((uint8_t)y) << 8) | ((uint8_t)z))) -+ -+/**************************************************************************** -+ * -+ * aw87xxx monitor bin check -+ * -+ ****************************************************************************/ -+static int aw_monitor_check_header_v_1_0_0(struct device *dev, -+ char *data, uint32_t data_len) -+{ -+ int i = 0; -+ struct aw_bin_header *header = (struct aw_bin_header *)data; -+ -+ if (header->bin_data_type != DATA_TYPE_MONITOR_ANALOG) { -+ AW_DEV_LOGE(dev, "monitor data_type check error!"); -+ return -EINVAL; -+ } -+ -+ if (header->bin_data_size != AW_MONITOR_HDR_DATA_SIZE) { -+ AW_DEV_LOGE(dev, "monitor data_size error!"); -+ return -EINVAL; -+ } -+ -+ if (header->data_byte_len != AW_MONITOR_HDR_DATA_BYTE_LEN) { -+ AW_DEV_LOGE(dev, "monitor data_byte_len error!"); -+ return -EINVAL; -+ } -+ -+ for (i = 0; i < AW_MONITOR_DATA_VER_MAX; i++) { -+ if (header->bin_data_ver == i) { -+ AW_LOGD("monitor bin_data_ver[0x%x]", i); -+ break; -+ } -+ } -+ if (i == AW_MONITOR_DATA_VER_MAX) -+ return -EINVAL; -+ -+ return 0; -+} -+ -+static int aw_monitor_check_data_v1_size(struct device *dev, -+ char *data, int32_t data_len) -+{ -+ int32_t bin_header_len = sizeof(struct aw_bin_header); -+ int32_t monitor_header_len = sizeof(struct aw_monitor_header); -+ int32_t monitor_data_len = sizeof(struct vmax_step_config); -+ int32_t len = 0; -+ struct aw_monitor_header *monitor_header = NULL; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ if (data_len < bin_header_len + monitor_header_len) { -+ AW_DEV_LOGE(dev, "bin len is less than aw_bin_header and monitoor_header,check failed"); -+ return -EINVAL; -+ } -+ -+ monitor_header = (struct aw_monitor_header *)(data + bin_header_len); -+ len = data_len - bin_header_len - monitor_header_len; -+ if (len < monitor_header->step_count * monitor_data_len) { -+ AW_DEV_LOGE(dev, "bin data len is not enough,check failed"); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGD(dev, "succeed"); -+ -+ return 0; -+} -+ -+static int aw_monitor_check_data_size(struct device *dev, -+ char *data, int32_t data_len) -+{ -+ int ret = -1; -+ struct aw_bin_header *header = (struct aw_bin_header *)data; -+ -+ switch (header->bin_data_ver) { -+ case AW_MONITOR_DATA_VER: -+ ret = aw_monitor_check_data_v1_size(dev, data, data_len); -+ if (ret < 0) -+ return ret; -+ break; -+ default: -+ AW_DEV_LOGE(dev, "bin data_ver[0x%x] non support", -+ header->bin_data_ver); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+ -+static int aw_monitor_check_bin_header(struct device *dev, -+ char *data, int32_t data_len) -+{ -+ int ret = -1; -+ struct aw_bin_header *header = NULL; -+ -+ if (data_len < sizeof(struct aw_bin_header)) { -+ AW_DEV_LOGE(dev, "bin len is less than aw_bin_header,check failed"); -+ return -EINVAL; -+ } -+ header = (struct aw_bin_header *)data; -+ -+ switch (header->header_ver) { -+ case HEADER_VERSION_1_0_0: -+ ret = aw_monitor_check_header_v_1_0_0(dev, data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "monitor bin haeder info check error!"); -+ return ret; -+ } -+ break; -+ default: -+ AW_DEV_LOGE(dev, "bin version[0x%x] non support", -+ header->header_ver); -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+static int aw_monitor_bin_check_sum(struct device *dev, -+ char *data, int32_t data_len) -+{ -+ int i, data_sum = 0; -+ uint32_t *check_sum = (uint32_t *)data; -+ -+ for (i = 4; i < data_len; i++) -+ data_sum += data[i]; -+ -+ if (*check_sum != data_sum) { -+ AW_DEV_LOGE(dev, "check_sum[%d] is not equal to data_sum[%d]", -+ *check_sum, data_sum); -+ return -ENOMEM; -+ } -+ -+ AW_DEV_LOGD(dev, "succeed"); -+ -+ return 0; -+} -+ -+static int aw_monitor_bin_check(struct device *dev, -+ char *monitor_data, uint32_t data_len) -+{ -+ int ret = -1; -+ -+ if (monitor_data == NULL || data_len == 0) { -+ AW_DEV_LOGE(dev, "none data to parse"); -+ return -EINVAL; -+ } -+ -+ ret = aw_monitor_bin_check_sum(dev, monitor_data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "bin data check sum failed"); -+ return ret; -+ } -+ -+ ret = aw_monitor_check_bin_header(dev, monitor_data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "bin data len check failed"); -+ return ret; -+ } -+ -+ ret = aw_monitor_check_data_size(dev, monitor_data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "bin header info check failed"); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+/***************************************************************************** -+ * -+ * aw87xxx monitor header bin parse -+ * -+ *****************************************************************************/ -+static void aw_monitor_write_to_table_v1(struct device *dev, -+ struct vmax_step_config *vmax_step, -+ char *vmax_data, uint32_t step_count) -+{ -+ int i = 0; -+ int index = 0; -+ int vmax_step_size = (int)sizeof(struct vmax_step_config); -+ -+ for (i = 0; i < step_count; i++) { -+ index = vmax_step_size * i; -+ vmax_step[i].vbat_min = -+ AW_GET_32_DATA(vmax_data[index + 3], -+ vmax_data[index + 2], -+ vmax_data[index + 1], -+ vmax_data[index + 0]); -+ vmax_step[i].vbat_max = -+ AW_GET_32_DATA(vmax_data[index + 7], -+ vmax_data[index + 6], -+ vmax_data[index + 5], -+ vmax_data[index + 4]); -+ vmax_step[i].vmax_vol = -+ AW_GET_32_DATA(vmax_data[index + 11], -+ vmax_data[index + 10], -+ vmax_data[index + 9], -+ vmax_data[index + 8]); -+ } -+ -+ for (i = 0; i < step_count; i++) -+ AW_DEV_LOGI(dev, "vbat_min:%d, vbat_max%d, vmax_vol:0x%x", -+ vmax_step[i].vbat_min, -+ vmax_step[i].vbat_max, -+ vmax_step[i].vmax_vol); -+} -+ -+static int aw_monitor_parse_vol_data_v1(struct device *dev, -+ struct aw_monitor *monitor, char *monitor_data) -+{ -+ uint32_t step_count = 0; -+ char *vmax_data = NULL; -+ struct vmax_step_config *vmax_step = NULL; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ step_count = monitor->monitor_hdr.step_count; -+ if (step_count) { -+ vmax_step = devm_kzalloc(dev, sizeof(struct vmax_step_config) * step_count, -+ GFP_KERNEL); -+ if (vmax_step == NULL) { -+ AW_DEV_LOGE(dev, "vmax_cfg vmalloc failed"); -+ return -ENOMEM; -+ } -+ memset(vmax_step, 0, -+ sizeof(struct vmax_step_config) * step_count); -+ } -+ -+ vmax_data = monitor_data + sizeof(struct aw_bin_header) + -+ sizeof(struct aw_monitor_header); -+ aw_monitor_write_to_table_v1(dev, vmax_step, vmax_data, step_count); -+ monitor->vmax_cfg = vmax_step; -+ -+ AW_DEV_LOGI(dev, "vmax_data parse succeed"); -+ -+ return 0; -+} -+ -+static int aw_monitor_parse_data_v1(struct device *dev, -+ struct aw_monitor *monitor, char *monitor_data) -+{ -+ int ret = -1; -+ int header_len = 0; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ header_len = sizeof(struct aw_bin_header); -+ memcpy(monitor_hdr, monitor_data + header_len, -+ sizeof(struct aw_monitor_header)); -+ -+ AW_DEV_LOGI(dev, "monitor_switch:%d, monitor_time:%d (ms), monitor_count:%d, step_count:%d", -+ monitor_hdr->monitor_switch, monitor_hdr->monitor_time, -+ monitor_hdr->monitor_count, monitor_hdr->step_count); -+ -+ ret = aw_monitor_parse_vol_data_v1(dev, monitor, monitor_data); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "vmax_data parse failed"); -+ return ret; -+ } -+ -+ monitor->bin_status = AW_MONITOR_CFG_OK; -+ -+ return 0; -+} -+ -+ -+static int aw_monitor_parse_v_1_0_0(struct device *dev, -+ struct aw_monitor *monitor, char *monitor_data) -+{ -+ int ret = -1; -+ struct aw_bin_header *header = (struct aw_bin_header *)monitor_data; -+ -+ switch (header->bin_data_ver) { -+ case AW_MONITOR_DATA_VER: -+ ret = aw_monitor_parse_data_v1(dev, monitor, monitor_data); -+ if (ret < 0) -+ return ret; -+ break; -+ default: -+ return -EINVAL; -+ } -+ -+ return 0; -+} -+ -+void aw87xxx_monitor_cfg_free(struct aw_monitor *monitor) -+{ -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ -+ monitor->bin_status = AW_MONITOR_CFG_WAIT; -+ memset(&monitor->monitor_hdr, 0, -+ sizeof(struct aw_monitor_header)); -+ if (monitor->vmax_cfg) { -+ devm_kfree(aw87xxx->dev, monitor->vmax_cfg); -+ monitor->vmax_cfg = NULL; -+ } -+} -+ -+int aw87xxx_monitor_bin_parse(struct device *dev, -+ char *monitor_data, uint32_t data_len) -+{ -+ int ret = -1; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = NULL; -+ struct aw_bin_header *bin_header = NULL; -+ -+ if (aw87xxx == NULL) { -+ AW_DEV_LOGE(dev, "get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ monitor = &aw87xxx->monitor; -+ monitor->bin_status = AW_MONITOR_CFG_WAIT; -+ -+ AW_DEV_LOGI(dev, "monitor bin parse version: %s", -+ AW_MONITOT_BIN_PARSE_VERSION); -+ -+ ret = aw_monitor_bin_check(dev, monitor_data, data_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "monitor bin check failed"); -+ return ret; -+ } -+ -+ bin_header = (struct aw_bin_header *)monitor_data; -+ switch (bin_header->bin_data_ver) { -+ case DATA_VERSION_V1: -+ ret = aw_monitor_parse_v_1_0_0(dev, monitor, -+ monitor_data); -+ if (ret < 0) { -+ aw87xxx_monitor_cfg_free(monitor); -+ return ret; -+ } -+ break; -+ default: -+ AW_DEV_LOGE(dev, "Unrecognized this bin data version[0x%x]", -+ bin_header->bin_data_ver); -+ } -+ -+ return 0; -+} -+ -+/*************************************************************************** -+ * -+ * aw87xxx monitor get adjustment vmax of power -+ * -+ ***************************************************************************/ -+static int aw_monitor_get_battery_capacity(struct device *dev, -+ struct aw_monitor *monitor, int *vbat_capacity) -+{ -+ char name[] = "battery"; -+ int ret = -1; -+ union power_supply_propval prop = { 0 }; -+ struct power_supply *psy = NULL; -+ -+ psy = power_supply_get_by_name(name); -+ if (psy == NULL) { -+ AW_DEV_LOGE(dev, "no struct power supply name:%s", name); -+ return -EINVAL; -+ } -+ -+ ret = power_supply_get_property(psy, POWER_SUPPLY_PROP_CAPACITY, &prop); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "get vbat capacity failed"); -+ return -EINVAL; -+ } -+ *vbat_capacity = prop.intval; -+ AW_DEV_LOGI(dev, "The percentage is %d", -+ *vbat_capacity); -+ -+ return 0; -+} -+ -+static int aw_search_vmax_from_table(struct device *dev, -+ struct aw_monitor *monitor, -+ const int vbat_vol, int *vmax_vol) -+{ -+ int i = 0; -+ int vmax_set = 0; -+ uint32_t vmax_flag = 0; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ struct vmax_step_config *vmax_cfg = monitor->vmax_cfg; -+ -+ if (monitor->bin_status == AW_MONITOR_CFG_WAIT) { -+ AW_DEV_LOGE(dev, "vmax_cfg not loaded or parse failed"); -+ return -ENODATA; -+ } -+ -+ for (i = 0; i < monitor_hdr->step_count; i++) { -+ if (vbat_vol == AW_VBAT_MAX) { -+ vmax_set = AW_VMAX_MAX; -+ vmax_flag = 1; -+ AW_DEV_LOGD(dev, "vbat=%d, setting vmax=0x%x", -+ vbat_vol, vmax_set); -+ break; -+ } -+ -+ if (vbat_vol >= vmax_cfg[i].vbat_min && -+ vbat_vol < vmax_cfg[i].vbat_max) { -+ vmax_set = vmax_cfg[i].vmax_vol; -+ vmax_flag = 1; -+ AW_DEV_LOGD(dev, "read setting vmax=0x%x, step[%d]: vbat_min=%d,vbat_max=%d", -+ vmax_set, i, -+ vmax_cfg[i].vbat_min, -+ vmax_cfg[i].vbat_max); -+ break; -+ } -+ } -+ -+ if (!vmax_flag) { -+ AW_DEV_LOGE(dev, "vmax_cfg not found"); -+ return -ENODATA; -+ } -+ -+ *vmax_vol = vmax_set; -+ return 0; -+} -+ -+ -+/*************************************************************************** -+ * -+ *monitor_esd_func -+ * -+ ***************************************************************************/ -+static int aw_chip_status_recover(struct aw87xxx *aw87xxx) -+{ -+ int ret = -1; -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ char *profile = aw87xxx->current_profile; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ ret = aw87xxx_update_profile_esd(aw87xxx, profile); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -+ profile); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "current prof[%s], dev_index[%d] ", -+ profile, aw87xxx->dev_index); -+ -+ monitor->pre_vmax = AW_VMAX_INIT_VAL; -+ monitor->first_entry = AW_FIRST_ENTRY; -+ monitor->timer_cnt = 0; -+ monitor->vbat_sum = 0; -+ -+ return 0; -+} -+ -+static int aw_monitor_chip_esd_check_work(struct aw87xxx *aw87xxx) -+{ -+ int ret = 0; -+ int i = 0; -+ -+ for (i = 0; i < REG_STATUS_CHECK_MAX; i++) { -+ AW_DEV_LOGD(aw87xxx->dev, "reg_status_check[%d]", i); -+ -+ ret = aw87xxx_dev_esd_reg_status_check(&aw87xxx->aw_dev); -+ if (ret < 0) { -+ aw_chip_status_recover(aw87xxx); -+ } else { -+ AW_DEV_LOGD(aw87xxx->dev, "chip status check succeed"); -+ break; -+ } -+ msleep(AW_ESD_CHECK_DELAY); -+ } -+ -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "chip status recover failed,chip off"); -+ aw87xxx_update_profile_esd(aw87xxx, aw87xxx->prof_off_name); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+ -+/*************************************************************************** -+ * -+ * aw87xxx monitor work with dsp -+ * -+ ***************************************************************************/ -+static int aw_monitor_update_vmax_to_dsp(struct device *dev, -+ struct aw_monitor *monitor, int vmax_set) -+{ -+ int ret = -1; -+ uint32_t enable = 0; -+ -+ if (monitor->pre_vmax != vmax_set) { -+ ret = aw87xxx_dsp_get_rx_module_enable(&enable); -+ if (!enable || ret < 0) { -+ AW_DEV_LOGE(dev, "get rx failed or rx disable, ret=%d, enable=%d", -+ ret, enable); -+ return -EPERM; -+ } -+ -+ ret = aw87xxx_dsp_set_vmax(vmax_set, monitor->dev_index); -+ if (ret) { -+ AW_DEV_LOGE(dev, "set dsp msg fail, ret=%d", ret); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(dev, "set dsp vmax=0x%x sucess", vmax_set); -+ monitor->pre_vmax = vmax_set; -+ } else { -+ AW_DEV_LOGI(dev, "vmax=0x%x no change", vmax_set); -+ } -+ -+ return 0; -+} -+ -+static void aw_monitor_with_dsp_vmax_work(struct device *dev, -+ struct aw_monitor *monitor) -+{ -+ int ret = -1; -+ int vmax_set = 0; -+ int vbat_capacity = 0; -+ int ave_capacity = 0; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ AW_DEV_LOGD(dev, "enter with dsp monitor"); -+ -+ ret = aw_monitor_get_battery_capacity(dev, monitor, &vbat_capacity); -+ if (ret < 0) -+ return; -+ -+ if (monitor->timer_cnt < monitor_hdr->monitor_count) { -+ monitor->timer_cnt++; -+ monitor->vbat_sum += vbat_capacity; -+ AW_DEV_LOGI(dev, "timer_cnt = %d", -+ monitor->timer_cnt); -+ } -+ if ((monitor->timer_cnt >= monitor_hdr->monitor_count) || -+ (monitor->first_entry == AW_FIRST_ENTRY)) { -+ if (monitor->first_entry == AW_FIRST_ENTRY) -+ monitor->first_entry = AW_NOT_FIRST_ENTRY; -+ ave_capacity = monitor->vbat_sum / monitor->timer_cnt; -+ -+ if (monitor->custom_capacity) -+ ave_capacity = monitor->custom_capacity; -+ -+ AW_DEV_LOGI(dev, "get average capacity = %d", ave_capacity); -+ -+ ret = aw_search_vmax_from_table(dev, monitor, -+ ave_capacity, &vmax_set); -+ if (ret < 0) -+ AW_DEV_LOGE(dev, "not find vmax_vol"); -+ else -+ aw_monitor_update_vmax_to_dsp(dev, monitor, vmax_set); -+ -+ monitor->timer_cnt = 0; -+ monitor->vbat_sum = 0; -+ } -+} -+ -+static void aw_monitor_work_func(struct work_struct *work) -+{ -+ int ret = 0; -+ struct aw87xxx *aw87xxx = container_of(work, -+ struct aw87xxx, monitor.with_dsp_work.work); -+ struct device *dev = aw87xxx->dev; -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ AW_DEV_LOGD(dev, "enter"); -+ -+ if (monitor->esd_enable) { -+ ret = aw_monitor_chip_esd_check_work(aw87xxx); -+ if (ret < 0) -+ return; -+ } -+ -+ if (monitor_hdr->monitor_switch && !(aw87xxx->aw_dev.is_rec_mode) && -+ monitor->open_dsp_en && monitor->bin_status == AW_ACF_UPDATE) { -+ AW_DEV_LOGD(dev, "start low power protection"); -+ aw_monitor_with_dsp_vmax_work(dev, monitor); -+ } -+ -+ if (monitor->esd_enable || (monitor_hdr->monitor_switch && -+ !(aw87xxx->aw_dev.is_rec_mode) && monitor->open_dsp_en && -+ monitor->bin_status == AW_ACF_UPDATE)) { -+ schedule_delayed_work(&monitor->with_dsp_work, -+ msecs_to_jiffies(monitor_hdr->monitor_time)); -+ } -+} -+ -+void aw87xxx_monitor_stop(struct aw_monitor *monitor) -+{ -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ cancel_delayed_work_sync(&monitor->with_dsp_work); -+} -+ -+void aw87xxx_monitor_start(struct aw_monitor *monitor) -+{ -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ int ret = 0; -+ -+ ret = aw87xxx_dev_check_reg_is_rec_mode(&aw87xxx->aw_dev); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "get reg current mode failed"); -+ return; -+ } -+ -+ if (monitor->esd_enable || (monitor->monitor_hdr.monitor_switch && -+ !(aw87xxx->aw_dev.is_rec_mode) && monitor->open_dsp_en -+ && monitor->bin_status == AW_ACF_UPDATE)) { -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ monitor->pre_vmax = AW_VMAX_INIT_VAL; -+ monitor->first_entry = AW_FIRST_ENTRY; -+ monitor->timer_cnt = 0; -+ monitor->vbat_sum = 0; -+ -+ schedule_delayed_work(&monitor->with_dsp_work, -+ msecs_to_jiffies(monitor->monitor_hdr.monitor_time)); -+ } -+} -+/*************************************************************************** -+ * -+ * aw87xxx no dsp monitor func -+ * -+ ***************************************************************************/ -+int aw87xxx_monitor_no_dsp_get_vmax(struct aw_monitor *monitor, int32_t *vmax) -+{ -+ int vbat_capacity = 0; -+ int ret = -1; -+ int vmax_vol = 0; -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ struct device *dev = aw87xxx->dev; -+ -+ ret = aw_monitor_get_battery_capacity(dev, monitor, &vbat_capacity); -+ if (ret < 0) -+ return ret; -+ -+ if (monitor->custom_capacity) -+ vbat_capacity = monitor->custom_capacity; -+ AW_DEV_LOGI(dev, "get_battery_capacity is[%d]", vbat_capacity); -+ -+ ret = aw_search_vmax_from_table(dev, monitor, -+ vbat_capacity, &vmax_vol); -+ if (ret < 0) { -+ AW_DEV_LOGE(dev, "not find vmax_vol"); -+ return ret; -+ } -+ -+ *vmax = vmax_vol; -+ return 0; -+} -+ -+ -+/*************************************************************************** -+ * -+ * aw87xxx monitor sysfs nodes -+ * -+ ***************************************************************************/ -+static ssize_t aw_attr_get_esd_enable(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ if (monitor->esd_enable) { -+ AW_DEV_LOGI(aw87xxx->dev, "esd-enable=true"); -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "esd-enable=true\n"); -+ } else { -+ AW_DEV_LOGI(aw87xxx->dev, "esd-enable=false"); -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "esd-enable=false\n"); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_set_esd_enable(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t len) -+{ -+ char esd_enable[AW_ESD_ENABLE_STRLEN] = {0}; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ if (strlen(buf) > AW_ESD_ENABLE_STRLEN) { -+ AW_DEV_LOGE(aw87xxx->dev, "input esd_enable_str_len is out of max[%d]", -+ AW_ESD_ENABLE_STRLEN); -+ return -EINVAL; -+ } -+ -+ if (sscanf(buf, "%s", esd_enable) == 1) { -+ AW_DEV_LOGD(aw87xxx->dev, "input esd-enable=[%s]", esd_enable); -+ if (!strcmp(esd_enable, "true")) -+ monitor->esd_enable = AW_ESD_ENABLE; -+ else -+ monitor->esd_enable = AW_ESD_DISABLE; -+ AW_DEV_LOGI(dev, "set esd-enable=[%s]", -+ monitor->esd_enable ? "true" : "false"); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "input esd-enable error"); -+ return -EINVAL; -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_get_vbat(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int ret = -1; -+ int vbat_capacity = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ if (monitor->custom_capacity == 0) { -+ ret = aw_monitor_get_battery_capacity(dev, monitor, -+ &vbat_capacity); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "get battery_capacity failed"); -+ return ret; -+ } -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "vbat capacity=%d\n", vbat_capacity); -+ } else { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "vbat capacity=%d\n", -+ monitor->custom_capacity); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_set_vbat(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t len) -+{ -+ int ret = -1; -+ int capacity = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ ret = kstrtouint(buf, 0, &capacity); -+ if (ret < 0) -+ return ret; -+ AW_DEV_LOGI(aw87xxx->dev, "set capacity = %d", capacity); -+ if (capacity >= AW_VBAT_CAPACITY_MIN && -+ capacity <= AW_VBAT_CAPACITY_MAX){ -+ monitor->custom_capacity = capacity; -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "vbat_set=invalid,please input value [%d-%d]", -+ AW_VBAT_CAPACITY_MIN, AW_VBAT_CAPACITY_MAX); -+ return -EINVAL; -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_get_vmax(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int ret = -1; -+ int vbat_capacity = 0; -+ int vmax_get = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ if (monitor->open_dsp_en) { -+ ret = aw87xxx_dsp_get_vmax(&vmax_get, aw87xxx->dev_index); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, -+ "get dsp vmax fail, ret=%d", ret); -+ return ret; -+ } -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "get_vmax=%d\n", vmax_get); -+ } else { -+ ret = aw_monitor_get_battery_capacity(dev, monitor, -+ &vbat_capacity); -+ if (ret < 0) -+ return ret; -+ AW_DEV_LOGI(aw87xxx->dev, "get_battery_capacity is [%d]", -+ vbat_capacity); -+ -+ if (monitor->custom_capacity) { -+ vbat_capacity = monitor->custom_capacity; -+ AW_DEV_LOGI(aw87xxx->dev, "get custom_capacity is [%d]", -+ vbat_capacity); -+ } -+ -+ ret = aw_search_vmax_from_table(aw87xxx->dev, monitor, -+ vbat_capacity, &vmax_get); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "not find vmax_vol"); -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "not_find_vmax_vol\n"); -+ return len; -+ } -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "0x%x\n", vmax_get); -+ AW_DEV_LOGI(aw87xxx->dev, "0x%x", vmax_get); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_set_vmax(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ uint32_t vmax_set = 0; -+ int ret = -1; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ ret = kstrtouint(buf, 0, &vmax_set); -+ if (ret < 0) -+ return ret; -+ -+ AW_DEV_LOGI(aw87xxx->dev, "vmax_set=0x%x", vmax_set); -+ -+ if (monitor->open_dsp_en) { -+ ret = aw87xxx_dsp_set_vmax(vmax_set, aw87xxx->dev_index); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "send dsp_msg error, ret = %d", -+ ret); -+ return ret; -+ } -+ msleep(2); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "no_dsp system,vmax_set invalid"); -+ return -EINVAL; -+ } -+ -+ return count; -+} -+ -+static ssize_t aw_attr_get_monitor_switch(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "aw87xxx monitor switch: %u\n", -+ monitor_hdr->monitor_switch); -+ return len; -+} -+ -+ -+int aw87xxx_dev_monitor_switch_set(struct aw_monitor *monitor, uint32_t enable) -+{ -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ AW_DEV_LOGI(aw87xxx->dev, "monitor switch set =%d", enable); -+ -+ if (!monitor->bin_status) { -+ AW_DEV_LOGE(aw87xxx->dev, "bin parse faile or not loaded,set invalid"); -+ return -EINVAL; -+ } -+ -+ if (monitor_hdr->monitor_switch == enable) -+ return 0; -+ -+ if (enable > 0) { -+ monitor_hdr->monitor_switch = 1; -+ if (monitor->open_dsp_en) { -+ monitor->pre_vmax = AW_VMAX_INIT_VAL; -+ monitor->first_entry = AW_FIRST_ENTRY; -+ monitor->timer_cnt = 0; -+ monitor->vbat_sum = 0; -+ } -+ } else { -+ monitor_hdr->monitor_switch = 0; -+ } -+ -+ return 0; -+} -+ -+static ssize_t aw_attr_set_monitor_switch(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ uint32_t enable = 0; -+ int ret = -1; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ -+ ret = kstrtouint(buf, 0, &enable); -+ if (ret < 0) -+ return ret; -+ -+ ret = aw87xxx_dev_monitor_switch_set(monitor, enable); -+ if (ret) -+ return ret; -+ -+ return count; -+} -+ -+static ssize_t aw_attr_get_monitor_time(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "aw_monitor_timer = %u(ms)\n", -+ monitor_hdr->monitor_time); -+ return len; -+} -+ -+static ssize_t aw_attr_set_monitor_time(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned int timer_val = 0; -+ int ret = -1; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ ret = kstrtouint(buf, 0, &timer_val); -+ if (ret < 0) -+ return ret; -+ -+ AW_DEV_LOGI(aw87xxx->dev, "input monitor timer=%d(ms)", timer_val); -+ -+ if (!monitor->bin_status) { -+ AW_DEV_LOGE(aw87xxx->dev, "bin parse faile or not loaded,set invalid"); -+ return -EINVAL; -+ } -+ -+ if (timer_val != monitor_hdr->monitor_time) -+ monitor_hdr->monitor_time = timer_val; -+ else -+ AW_DEV_LOGI(aw87xxx->dev, "no_change monitor_time"); -+ -+ return count; -+} -+ -+static ssize_t aw_attr_get_monitor_count(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "aw_monitor_count = %u\n", -+ monitor_hdr->monitor_count); -+ return len; -+} -+ -+static ssize_t aw_attr_set_monitor_count(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ unsigned int monitor_count = 0; -+ int ret = -1; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ struct aw_monitor_header *monitor_hdr = &monitor->monitor_hdr; -+ -+ ret = kstrtouint(buf, 0, &monitor_count); -+ if (ret < 0) -+ return ret; -+ AW_DEV_LOGI(aw87xxx->dev, "input monitor count=%d", monitor_count); -+ -+ if (!monitor->bin_status) { -+ AW_DEV_LOGE(aw87xxx->dev, "bin parse faile or not loaded,set invalid"); -+ return -EINVAL; -+ } -+ -+ if (monitor_count != monitor_hdr->monitor_count) -+ monitor_hdr->monitor_count = monitor_count; -+ else -+ AW_DEV_LOGI(aw87xxx->dev, "no_change monitor_count"); -+ -+ return count; -+} -+ -+ -+static ssize_t aw_attr_get_rx(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ ssize_t len = 0; -+ int ret = -1; -+ uint32_t enable = 0; -+ -+ if (monitor->open_dsp_en) { -+ ret = aw87xxx_dsp_get_rx_module_enable(&enable); -+ if (ret) { -+ AW_DEV_LOGE(aw87xxx->dev, "dsp_msg error, ret=%d", ret); -+ return ret; -+ } -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "aw87xxx rx: %u\n", enable); -+ } else { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "command is invalid\n"); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw_attr_set_rx(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_monitor *monitor = &aw87xxx->monitor; -+ int ret = -1; -+ uint32_t enable; -+ -+ ret = kstrtouint(buf, 0, &enable); -+ if (ret < 0) -+ return ret; -+ -+ if (monitor->open_dsp_en) { -+ AW_DEV_LOGI(aw87xxx->dev, "set rx enable=%d", enable); -+ -+ ret = aw87xxx_dsp_set_rx_module_enable(enable); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "dsp_msg error, ret=%d", -+ ret); -+ return ret; -+ } -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "command is invalid"); -+ return -EINVAL; -+ } -+ -+ return count; -+} -+ -+ -+static DEVICE_ATTR(esd_enable, S_IWUSR | S_IRUGO, -+ aw_attr_get_esd_enable, aw_attr_set_esd_enable); -+static DEVICE_ATTR(vbat, S_IWUSR | S_IRUGO, -+ aw_attr_get_vbat, aw_attr_set_vbat); -+static DEVICE_ATTR(vmax, S_IWUSR | S_IRUGO, -+ aw_attr_get_vmax, aw_attr_set_vmax); -+ -+static DEVICE_ATTR(monitor_switch, S_IWUSR | S_IRUGO, -+ aw_attr_get_monitor_switch, aw_attr_set_monitor_switch); -+static DEVICE_ATTR(monitor_time, S_IWUSR | S_IRUGO, -+ aw_attr_get_monitor_time, aw_attr_set_monitor_time); -+static DEVICE_ATTR(monitor_count, S_IWUSR | S_IRUGO, -+ aw_attr_get_monitor_count, aw_attr_set_monitor_count); -+static DEVICE_ATTR(rx, S_IWUSR | S_IRUGO, -+ aw_attr_get_rx, aw_attr_set_rx); -+ -+static struct attribute *aw_monitor_vol_adjust[] = { -+ &dev_attr_esd_enable.attr, -+ &dev_attr_vbat.attr, -+ &dev_attr_vmax.attr, -+ NULL -+}; -+ -+static struct attribute_group aw_monitor_vol_adjust_group = { -+ .attrs = aw_monitor_vol_adjust, -+}; -+ -+static struct attribute *aw_monitor_control[] = { -+ &dev_attr_monitor_switch.attr, -+ &dev_attr_monitor_time.attr, -+ &dev_attr_monitor_count.attr, -+ &dev_attr_rx.attr, -+ NULL -+}; -+ -+static struct attribute_group aw_monitor_control_group = { -+ .attrs = aw_monitor_control, -+}; -+ -+/*************************************************************************** -+ * -+ * aw87xxx monitor init -+ * -+ ***************************************************************************/ -+static void aw_monitor_dtsi_parse(struct device *dev, -+ struct aw_monitor *monitor, -+ struct device_node *dev_node) -+{ -+ int ret = -1; -+ const char *esd_enable; -+ -+ ret = of_property_read_string(dev_node, "esd-enable", &esd_enable); -+ if (ret < 0) { -+ AW_DEV_LOGI(dev, "esd_enable parse failed, user default[disable]"); -+ monitor->esd_enable = AW_ESD_DISABLE; -+ } else { -+ if (!strcmp(esd_enable, "true")) -+ monitor->esd_enable = AW_ESD_ENABLE; -+ else -+ monitor->esd_enable = AW_ESD_DISABLE; -+ -+ AW_DEV_LOGI(dev, "parse esd-enable=[%s]", -+ monitor->esd_enable ? "true" : "false"); -+ } -+} -+ -+void aw87xxx_monitor_init(struct device *dev, struct aw_monitor *monitor, -+ struct device_node *dev_node) -+{ -+ int ret = -1; -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ -+ monitor->dev_index = aw87xxx->dev_index; -+ monitor->monitor_hdr.monitor_time = AW_DEFAULT_MONITOR_TIME; -+ -+ aw_monitor_dtsi_parse(dev, monitor, dev_node); -+ -+ /* get platform open dsp type */ -+ monitor->open_dsp_en = aw87xxx_dsp_isEnable(); -+ -+ ret = sysfs_create_group(&dev->kobj, &aw_monitor_vol_adjust_group); -+ if (ret < 0) -+ AW_DEV_LOGE(dev, "failed to create monitor vol_adjust sysfs nodes"); -+ -+ INIT_DELAYED_WORK(&monitor->with_dsp_work, aw_monitor_work_func); -+ -+ if (monitor->open_dsp_en) { -+ ret = sysfs_create_group(&dev->kobj, &aw_monitor_control_group); -+ if (ret < 0) -+ AW_DEV_LOGE(dev, "failed to create monitor dsp control sysfs nodes"); -+ } -+ -+ if (!ret) -+ AW_DEV_LOGI(dev, "monitor init succeed"); -+} -+ -+void aw87xxx_monitor_exit(struct aw_monitor *monitor) -+{ -+ struct aw87xxx *aw87xxx = -+ container_of(monitor, struct aw87xxx, monitor); -+ /*rm attr node*/ -+ sysfs_remove_group(&aw87xxx->dev->kobj, -+ &aw_monitor_vol_adjust_group); -+ -+ aw87xxx_monitor_stop(monitor); -+ -+ if (monitor->open_dsp_en) { -+ sysfs_remove_group(&aw87xxx->dev->kobj, -+ &aw_monitor_control_group); -+ } -+} -+ -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_monitor.h b/sound/soc/codecs/aw87xxx/aw87xxx_monitor.h -new file mode 100644 -index 000000000..4b0282b41 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_monitor.h -@@ -0,0 +1,96 @@ -+#ifndef __AW87XXX_MONITOR_H__ -+#define __AW87XXX_MONITOR_H__ -+ -+#define AW_WAIT_DSP_OPEN_TIME (3000) -+#define AW_VBAT_CAPACITY_MIN (0) -+#define AW_VBAT_CAPACITY_MAX (100) -+#define AW_VMAX_INIT_VAL (0xFFFFFFFF) -+#define AW_VBAT_MAX (100) -+#define AW_VMAX_MAX (0) -+#define AW_DEFAULT_MONITOR_TIME (3000) -+#define AW_WAIT_TIME (3000) -+#define REG_STATUS_CHECK_MAX (10) -+#define AW_ESD_CHECK_DELAY (1) -+ -+#define AW_ESD_ENABLE (true) -+#define AW_ESD_DISABLE (false) -+#define AW_ESD_ENABLE_STRLEN (16) -+ -+enum aw_monitor_init { -+ AW_MONITOR_CFG_WAIT = 0, -+ AW_MONITOR_CFG_OK = 1, -+}; -+ -+enum aw_monitor_hdr_info { -+ AW_MONITOR_HDR_DATA_SIZE = 0x00000004, -+ AW_MONITOR_HDR_DATA_BYTE_LEN = 0x00000004, -+}; -+ -+enum aw_monitor_data_ver { -+ AW_MONITOR_DATA_VER = 0x00000001, -+ AW_MONITOR_DATA_VER_MAX, -+}; -+ -+enum aw_monitor_first_enter { -+ AW_FIRST_ENTRY = 0, -+ AW_NOT_FIRST_ENTRY = 1, -+}; -+ -+struct aw_bin_header { -+ uint32_t check_sum; -+ uint32_t header_ver; -+ uint32_t bin_data_type; -+ uint32_t bin_data_ver; -+ uint32_t bin_data_size; -+ uint32_t ui_ver; -+ char product[8]; -+ uint32_t addr_byte_len; -+ uint32_t data_byte_len; -+ uint32_t device_addr; -+ uint32_t reserve[4]; -+}; -+ -+struct aw_monitor_header { -+ uint32_t monitor_switch; -+ uint32_t monitor_time; -+ uint32_t monitor_count; -+ uint32_t step_count; -+ uint32_t reserve[4]; -+}; -+ -+struct vmax_step_config { -+ uint32_t vbat_min; -+ uint32_t vbat_max; -+ int vmax_vol; -+}; -+ -+struct aw_monitor { -+ bool open_dsp_en; -+ bool esd_enable; -+ int32_t dev_index; -+ uint8_t first_entry; -+ uint8_t timer_cnt; -+ uint32_t vbat_sum; -+ int32_t custom_capacity; -+ uint32_t pre_vmax; -+ -+ int bin_status; -+ struct aw_monitor_header monitor_hdr; -+ struct vmax_step_config *vmax_cfg; -+ -+ struct delayed_work with_dsp_work; -+}; -+ -+void aw87xxx_monitor_cfg_free(struct aw_monitor *monitor); -+int aw87xxx_monitor_bin_parse(struct device *dev, -+ char *monitor_data, uint32_t data_len); -+void aw87xxx_monitor_stop(struct aw_monitor *monitor); -+void aw87xxx_monitor_start(struct aw_monitor *monitor); -+int aw87xxx_monitor_no_dsp_get_vmax(struct aw_monitor *monitor, -+ int32_t *vmax); -+void aw87xxx_monitor_init(struct device *dev, struct aw_monitor *monitor, -+ struct device_node *dev_node); -+void aw87xxx_monitor_exit(struct aw_monitor *monitor); -+int aw87xxx_dev_monitor_switch_set(struct aw_monitor *monitor, uint32_t enable); -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h -new file mode 100644 -index 000000000..7b95d2252 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h -@@ -0,0 +1,2315 @@ -+#ifndef __AW87XXX_PID_18_REG_H__ -+#define __AW87XXX_PID_18_REG_H__ -+ -+/* registers list */ -+#define AW87XXX_PID_18_CHIPID_REG (0x00) -+#define AW87XXX_PID_18_SYSST_REG (0x01) -+#define AW87XXX_PID_18_SYSINT_REG (0x02) -+#define AW87XXX_PID_18_SYSCTRL_REG (0x03) -+#define AW87XXX_PID_18_CPOC_REG (0x04) -+#define AW87XXX_PID_18_CLASSD_REG (0x05) -+#define AW87XXX_PID_18_MADPVTH_REG (0x06) -+#define AW87XXX_PID_18_A3PARAM_REG (0x07) -+#define AW87XXX_PID_18_A3A2PO_REG (0x08) -+#define AW87XXX_PID_18_A2PARAM_REG (0x09) -+#define AW87XXX_PID_18_A1PARAM_REG (0x0A) -+#define AW87XXX_PID_18_POPCLK_REG (0x0B) -+#define AW87XXX_PID_18_GTDRCPSS_REG (0x0C) -+#define AW87XXX_PID_18_MULTI_REG (0x0D) -+#define AW87XXX_PID_18_DFT1_REG (0x61) -+#define AW87XXX_PID_18_DFT2_REG (0x62) -+#define AW87XXX_PID_18_DFT3_REG (0x63) -+#define AW87XXX_PID_18_DFT4_REG (0x64) -+#define AW87XXX_PID_18_DFT5_REG (0x65) -+#define AW87XXX_PID_18_DFT6_REG (0x66) -+ -+#define AW87XXX_PID_18_CLASSD_DEFAULT (0x10) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_18_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_18_REG_MAX (0x67) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_18_reg_access[AW87XXX_PID_18_REG_MAX] = { -+ [AW87XXX_PID_18_CHIPID_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_18_SYSST_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_18_SYSINT_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_18_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_CPOC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_CLASSD_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_MADPVTH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_A3PARAM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_A3A2PO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_A2PARAM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_A1PARAM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_POPCLK_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_GTDRCPSS_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_MULTI_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT5_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_18_DFT6_REG] = (REG_RD_ACCESS), -+}; -+ -+/* detail information of registers begin */ -+/* CHIPID (0x00) detail */ -+/* IDCODE bit 7:0 (CHIPID 0x00) */ -+#define AW87XXX_PID_18_IDCODE_START_BIT (0) -+#define AW87XXX_PID_18_IDCODE_BITS_LEN (8) -+#define AW87XXX_PID_18_IDCODE_MASK \ -+ (~(((1<<AW87XXX_PID_18_IDCODE_BITS_LEN)-1) << AW87XXX_PID_18_IDCODE_START_BIT)) -+ -+#define AW87XXX_PID_18_IDCODE_DEFAULT_VALUE (0x18) -+#define AW87XXX_PID_18_IDCODE_DEFAULT \ -+ (AW87XXX_PID_18_IDCODE_DEFAULT_VALUE << AW87XXX_PID_18_IDCODE_START_BIT) -+ -+/* default value of CHIPID (0x00) */ -+/* #define AW87XXX_PID_18_CHIPID_DEFAULT (0x18) */ -+ -+/* SYSST (0x01) detail */ -+/* UVLOS bit 7 (SYSST 0x01) */ -+#define AW87XXX_PID_18_UVLOS_START_BIT (7) -+#define AW87XXX_PID_18_UVLOS_BITS_LEN (1) -+#define AW87XXX_PID_18_UVLOS_MASK \ -+ (~(((1<<AW87XXX_PID_18_UVLOS_BITS_LEN)-1) << AW87XXX_PID_18_UVLOS_START_BIT)) -+ -+#define AW87XXX_PID_18_UVLOS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_18_UVLOS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_UVLOS_NORMAL_OPERATION << AW87XXX_PID_18_UVLOS_START_BIT) -+ -+#define AW87XXX_PID_18_UVLOS_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_18_UVLOS_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_18_UVLOS_VBAT_UNDER_VOLTAGE << AW87XXX_PID_18_UVLOS_START_BIT) -+ -+#define AW87XXX_PID_18_UVLOS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_UVLOS_DEFAULT \ -+ (AW87XXX_PID_18_UVLOS_DEFAULT_VALUE << AW87XXX_PID_18_UVLOS_START_BIT) -+ -+/* OTNS bit 6 (SYSST 0x01) */ -+#define AW87XXX_PID_18_OTNS_START_BIT (6) -+#define AW87XXX_PID_18_OTNS_BITS_LEN (1) -+#define AW87XXX_PID_18_OTNS_MASK \ -+ (~(((1<<AW87XXX_PID_18_OTNS_BITS_LEN)-1) << AW87XXX_PID_18_OTNS_START_BIT)) -+ -+#define AW87XXX_PID_18_OTNS_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (0) -+#define AW87XXX_PID_18_OTNS_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OTNS_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_18_OTNS_START_BIT) -+ -+#define AW87XXX_PID_18_OTNS_NORMAL_OPERATION (1) -+#define AW87XXX_PID_18_OTNS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_OTNS_NORMAL_OPERATION << AW87XXX_PID_18_OTNS_START_BIT) -+ -+#define AW87XXX_PID_18_OTNS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OTNS_DEFAULT \ -+ (AW87XXX_PID_18_OTNS_DEFAULT_VALUE << AW87XXX_PID_18_OTNS_START_BIT) -+ -+/* OC_FLAGS bit 5 (SYSST 0x01) */ -+#define AW87XXX_PID_18_OC_FLAGS_START_BIT (5) -+#define AW87XXX_PID_18_OC_FLAGS_BITS_LEN (1) -+#define AW87XXX_PID_18_OC_FLAGS_MASK \ -+ (~(((1<<AW87XXX_PID_18_OC_FLAGS_BITS_LEN)-1) << AW87XXX_PID_18_OC_FLAGS_START_BIT)) -+ -+#define AW87XXX_PID_18_OC_FLAGS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_18_OC_FLAGS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_OC_FLAGS_NORMAL_OPERATION << AW87XXX_PID_18_OC_FLAGS_START_BIT) -+ -+#define AW87XXX_PID_18_OC_FLAGS_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_18_OC_FLAGS_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OC_FLAGS_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_18_OC_FLAGS_START_BIT) -+ -+#define AW87XXX_PID_18_OC_FLAGS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OC_FLAGS_DEFAULT \ -+ (AW87XXX_PID_18_OC_FLAGS_DEFAULT_VALUE << AW87XXX_PID_18_OC_FLAGS_START_BIT) -+ -+/* VOUTDECTS bit 4 (SYSST 0x01) */ -+#define AW87XXX_PID_18_VOUTDECTS_START_BIT (4) -+#define AW87XXX_PID_18_VOUTDECTS_BITS_LEN (1) -+#define AW87XXX_PID_18_VOUTDECTS_MASK \ -+ (~(((1<<AW87XXX_PID_18_VOUTDECTS_BITS_LEN)-1) << AW87XXX_PID_18_VOUTDECTS_START_BIT)) -+ -+#define AW87XXX_PID_18_VOUTDECTS_PVDDBELOWVDD (0) -+#define AW87XXX_PID_18_VOUTDECTS_PVDDBELOWVDD_VALUE \ -+ (AW87XXX_PID_18_VOUTDECTS_PVDDBELOWVDD << AW87XXX_PID_18_VOUTDECTS_START_BIT) -+ -+#define AW87XXX_PID_18_VOUTDECTS_PVDDABOVEVDD (1) -+#define AW87XXX_PID_18_VOUTDECTS_PVDDABOVEVDD_VALUE \ -+ (AW87XXX_PID_18_VOUTDECTS_PVDDABOVEVDD << AW87XXX_PID_18_VOUTDECTS_START_BIT) -+ -+#define AW87XXX_PID_18_VOUTDECTS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_VOUTDECTS_DEFAULT \ -+ (AW87XXX_PID_18_VOUTDECTS_DEFAULT_VALUE << AW87XXX_PID_18_VOUTDECTS_START_BIT) -+ -+/* STARTOKS bit 3 (SYSST 0x01) */ -+#define AW87XXX_PID_18_STARTOKS_START_BIT (3) -+#define AW87XXX_PID_18_STARTOKS_BITS_LEN (1) -+#define AW87XXX_PID_18_STARTOKS_MASK \ -+ (~(((1<<AW87XXX_PID_18_STARTOKS_BITS_LEN)-1) << AW87XXX_PID_18_STARTOKS_START_BIT)) -+ -+#define AW87XXX_PID_18_STARTOKS_CP_START_FAIL_DECTECTED (0) -+#define AW87XXX_PID_18_STARTOKS_CP_START_FAIL_DECTECTED_VALUE \ -+ (AW87XXX_PID_18_STARTOKS_CP_START_FAIL_DECTECTED << AW87XXX_PID_18_STARTOKS_START_BIT) -+ -+#define AW87XXX_PID_18_STARTOKS_NORMAL_OPERATION (1) -+#define AW87XXX_PID_18_STARTOKS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_STARTOKS_NORMAL_OPERATION << AW87XXX_PID_18_STARTOKS_START_BIT) -+ -+#define AW87XXX_PID_18_STARTOKS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_STARTOKS_DEFAULT \ -+ (AW87XXX_PID_18_STARTOKS_DEFAULT_VALUE << AW87XXX_PID_18_STARTOKS_START_BIT) -+ -+/* VBGOKN1S bit 2 (SYSST 0x01) */ -+#define AW87XXX_PID_18_VBGOKN1S_START_BIT (2) -+#define AW87XXX_PID_18_VBGOKN1S_BITS_LEN (1) -+#define AW87XXX_PID_18_VBGOKN1S_MASK \ -+ (~(((1<<AW87XXX_PID_18_VBGOKN1S_BITS_LEN)-1) << AW87XXX_PID_18_VBGOKN1S_START_BIT)) -+ -+#define AW87XXX_PID_18_VBGOKN1S_NORMAL_WORKS (0) -+#define AW87XXX_PID_18_VBGOKN1S_NORMAL_WORKS_VALUE \ -+ (AW87XXX_PID_18_VBGOKN1S_NORMAL_WORKS << AW87XXX_PID_18_VBGOKN1S_START_BIT) -+ -+#define AW87XXX_PID_18_VBGOKN1S_ABNORMAL_WORKS (1) -+#define AW87XXX_PID_18_VBGOKN1S_ABNORMAL_WORKS_VALUE \ -+ (AW87XXX_PID_18_VBGOKN1S_ABNORMAL_WORKS << AW87XXX_PID_18_VBGOKN1S_START_BIT) -+ -+#define AW87XXX_PID_18_VBGOKN1S_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_VBGOKN1S_DEFAULT \ -+ (AW87XXX_PID_18_VBGOKN1S_DEFAULT_VALUE << AW87XXX_PID_18_VBGOKN1S_START_BIT) -+ -+/* OVPS bit 1 (SYSST 0x01) */ -+#define AW87XXX_PID_18_OVPS_START_BIT (1) -+#define AW87XXX_PID_18_OVPS_BITS_LEN (1) -+#define AW87XXX_PID_18_OVPS_MASK \ -+ (~(((1<<AW87XXX_PID_18_OVPS_BITS_LEN)-1) << AW87XXX_PID_18_OVPS_START_BIT)) -+ -+#define AW87XXX_PID_18_OVPS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_18_OVPS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_OVPS_NORMAL_OPERATION << AW87XXX_PID_18_OVPS_START_BIT) -+ -+#define AW87XXX_PID_18_OVPS_CP_OVP_DETECTED (1) -+#define AW87XXX_PID_18_OVPS_CP_OVP_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OVPS_CP_OVP_DETECTED << AW87XXX_PID_18_OVPS_START_BIT) -+ -+#define AW87XXX_PID_18_OVPS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OVPS_DEFAULT \ -+ (AW87XXX_PID_18_OVPS_DEFAULT_VALUE << AW87XXX_PID_18_OVPS_START_BIT) -+ -+/* CP_2PS bit 0 (SYSST 0x01) */ -+#define AW87XXX_PID_18_CP_2PS_START_BIT (0) -+#define AW87XXX_PID_18_CP_2PS_BITS_LEN (1) -+#define AW87XXX_PID_18_CP_2PS_MASK \ -+ (~(((1<<AW87XXX_PID_18_CP_2PS_BITS_LEN)-1) << AW87XXX_PID_18_CP_2PS_START_BIT)) -+ -+#define AW87XXX_PID_18_CP_2PS_WEAK_SIGNAL (0) -+#define AW87XXX_PID_18_CP_2PS_WEAK_SIGNAL_VALUE \ -+ (AW87XXX_PID_18_CP_2PS_WEAK_SIGNAL << AW87XXX_PID_18_CP_2PS_START_BIT) -+ -+#define AW87XXX_PID_18_CP_2PS_STRONG_SIGNAL (1) -+#define AW87XXX_PID_18_CP_2PS_STRONG_SIGNAL_VALUE \ -+ (AW87XXX_PID_18_CP_2PS_STRONG_SIGNAL << AW87XXX_PID_18_CP_2PS_START_BIT) -+ -+#define AW87XXX_PID_18_CP_2PS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_CP_2PS_DEFAULT \ -+ (AW87XXX_PID_18_CP_2PS_DEFAULT_VALUE << AW87XXX_PID_18_CP_2PS_START_BIT) -+ -+/* default value of SYSST (0x01) */ -+/* #define AW87XXX_PID_18_SYSST_DEFAULT (0x00) */ -+ -+/* SYSINT (0x02) detail */ -+/* UVLOI bit 7 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_UVLOI_START_BIT (7) -+#define AW87XXX_PID_18_UVLOI_BITS_LEN (1) -+#define AW87XXX_PID_18_UVLOI_MASK \ -+ (~(((1<<AW87XXX_PID_18_UVLOI_BITS_LEN)-1) << AW87XXX_PID_18_UVLOI_START_BIT)) -+ -+#define AW87XXX_PID_18_UVLOI_SIGNAL_STATUS_DO_NOT_CHANGE (0) -+#define AW87XXX_PID_18_UVLOI_SIGNAL_STATUS_DO_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_18_UVLOI_SIGNAL_STATUS_DO_NOT_CHANGE << AW87XXX_PID_18_UVLOI_START_BIT) -+ -+#define AW87XXX_PID_18_UVLOI_UNDER_VOLTAGE_LOCK_OUT_DETECTED (1) -+#define AW87XXX_PID_18_UVLOI_UNDER_VOLTAGE_LOCK_OUT_DETECTED_VALUE \ -+ (AW87XXX_PID_18_UVLOI_UNDER_VOLTAGE_LOCK_OUT_DETECTED << AW87XXX_PID_18_UVLOI_START_BIT) -+ -+#define AW87XXX_PID_18_UVLOI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_UVLOI_DEFAULT \ -+ (AW87XXX_PID_18_UVLOI_DEFAULT_VALUE << AW87XXX_PID_18_UVLOI_START_BIT) -+ -+/* OTNI bit 6 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_OTNI_START_BIT (6) -+#define AW87XXX_PID_18_OTNI_BITS_LEN (1) -+#define AW87XXX_PID_18_OTNI_MASK \ -+ (~(((1<<AW87XXX_PID_18_OTNI_BITS_LEN)-1) << AW87XXX_PID_18_OTNI_START_BIT)) -+ -+#define AW87XXX_PID_18_OTNI_SIGNAL_STATUS_DO_NOT_CHANGE (0) -+#define AW87XXX_PID_18_OTNI_SIGNAL_STATUS_DO_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_18_OTNI_SIGNAL_STATUS_DO_NOT_CHANGE << AW87XXX_PID_18_OTNI_START_BIT) -+ -+#define AW87XXX_PID_18_OTNI_OVER_TEMPRETURE_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_18_OTNI_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OTNI_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_18_OTNI_START_BIT) -+ -+#define AW87XXX_PID_18_OTNI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OTNI_DEFAULT \ -+ (AW87XXX_PID_18_OTNI_DEFAULT_VALUE << AW87XXX_PID_18_OTNI_START_BIT) -+ -+/* OC_FLAGI bit 5 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_OC_FLAGI_START_BIT (5) -+#define AW87XXX_PID_18_OC_FLAGI_BITS_LEN (1) -+#define AW87XXX_PID_18_OC_FLAGI_MASK \ -+ (~(((1<<AW87XXX_PID_18_OC_FLAGI_BITS_LEN)-1) << AW87XXX_PID_18_OC_FLAGI_START_BIT)) -+ -+#define AW87XXX_PID_18_OC_FLAGI_SIGNAL_STATUS_DO_NOT_CHANGE (0) -+#define AW87XXX_PID_18_OC_FLAGI_SIGNAL_STATUS_DO_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_18_OC_FLAGI_SIGNAL_STATUS_DO_NOT_CHANGE << AW87XXX_PID_18_OC_FLAGI_START_BIT) -+ -+#define AW87XXX_PID_18_OC_FLAGI_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_18_OC_FLAGI_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OC_FLAGI_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_18_OC_FLAGI_START_BIT) -+ -+#define AW87XXX_PID_18_OC_FLAGI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OC_FLAGI_DEFAULT \ -+ (AW87XXX_PID_18_OC_FLAGI_DEFAULT_VALUE << AW87XXX_PID_18_OC_FLAGI_START_BIT) -+ -+/* VOUTDECTI bit 4 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_VOUTDECTI_START_BIT (4) -+#define AW87XXX_PID_18_VOUTDECTI_BITS_LEN (1) -+#define AW87XXX_PID_18_VOUTDECTI_MASK \ -+ (~(((1<<AW87XXX_PID_18_VOUTDECTI_BITS_LEN)-1) << AW87XXX_PID_18_VOUTDECTI_START_BIT)) -+ -+#define AW87XXX_PID_18_VOUTDECTI_PVDDBELOWVDD (0) -+#define AW87XXX_PID_18_VOUTDECTI_PVDDBELOWVDD_VALUE \ -+ (AW87XXX_PID_18_VOUTDECTI_PVDDBELOWVDD << AW87XXX_PID_18_VOUTDECTI_START_BIT) -+ -+#define AW87XXX_PID_18_VOUTDECTI_PVDDABOVEVDD (1) -+#define AW87XXX_PID_18_VOUTDECTI_PVDDABOVEVDD_VALUE \ -+ (AW87XXX_PID_18_VOUTDECTI_PVDDABOVEVDD << AW87XXX_PID_18_VOUTDECTI_START_BIT) -+ -+#define AW87XXX_PID_18_VOUTDECTI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_VOUTDECTI_DEFAULT \ -+ (AW87XXX_PID_18_VOUTDECTI_DEFAULT_VALUE << AW87XXX_PID_18_VOUTDECTI_START_BIT) -+ -+/* STARTOKI bit 3 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_STARTOKI_START_BIT (3) -+#define AW87XXX_PID_18_STARTOKI_BITS_LEN (1) -+#define AW87XXX_PID_18_STARTOKI_MASK \ -+ (~(((1<<AW87XXX_PID_18_STARTOKI_BITS_LEN)-1) << AW87XXX_PID_18_STARTOKI_START_BIT)) -+ -+#define AW87XXX_PID_18_STARTOKI_SIGNAL_STATUS_DO_NOT_CHANGE (0) -+#define AW87XXX_PID_18_STARTOKI_SIGNAL_STATUS_DO_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_18_STARTOKI_SIGNAL_STATUS_DO_NOT_CHANGE << AW87XXX_PID_18_STARTOKI_START_BIT) -+ -+#define AW87XXX_PID_18_STARTOKI_CHARGEPUMB_START_UP_OK_DECTECTED (1) -+#define AW87XXX_PID_18_STARTOKI_CHARGEPUMB_START_UP_OK_DECTECTED_VALUE \ -+ (AW87XXX_PID_18_STARTOKI_CHARGEPUMB_START_UP_OK_DECTECTED << AW87XXX_PID_18_STARTOKI_START_BIT) -+ -+#define AW87XXX_PID_18_STARTOKI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_STARTOKI_DEFAULT \ -+ (AW87XXX_PID_18_STARTOKI_DEFAULT_VALUE << AW87XXX_PID_18_STARTOKI_START_BIT) -+ -+/* VBGOKN1I bit 2 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_VBGOKN1I_START_BIT (2) -+#define AW87XXX_PID_18_VBGOKN1I_BITS_LEN (1) -+#define AW87XXX_PID_18_VBGOKN1I_MASK \ -+ (~(((1<<AW87XXX_PID_18_VBGOKN1I_BITS_LEN)-1) << AW87XXX_PID_18_VBGOKN1I_START_BIT)) -+ -+#define AW87XXX_PID_18_VBGOKN1I_NORMAL_WORKS (0) -+#define AW87XXX_PID_18_VBGOKN1I_NORMAL_WORKS_VALUE \ -+ (AW87XXX_PID_18_VBGOKN1I_NORMAL_WORKS << AW87XXX_PID_18_VBGOKN1I_START_BIT) -+ -+#define AW87XXX_PID_18_VBGOKN1I_ABNORMAL_WORKS (1) -+#define AW87XXX_PID_18_VBGOKN1I_ABNORMAL_WORKS_VALUE \ -+ (AW87XXX_PID_18_VBGOKN1I_ABNORMAL_WORKS << AW87XXX_PID_18_VBGOKN1I_START_BIT) -+ -+#define AW87XXX_PID_18_VBGOKN1I_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_VBGOKN1I_DEFAULT \ -+ (AW87XXX_PID_18_VBGOKN1I_DEFAULT_VALUE << AW87XXX_PID_18_VBGOKN1I_START_BIT) -+ -+/* OVPI bit 1 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_OVPI_START_BIT (1) -+#define AW87XXX_PID_18_OVPI_BITS_LEN (1) -+#define AW87XXX_PID_18_OVPI_MASK \ -+ (~(((1<<AW87XXX_PID_18_OVPI_BITS_LEN)-1) << AW87XXX_PID_18_OVPI_START_BIT)) -+ -+#define AW87XXX_PID_18_OVPI_NORMAL_OPERATION (0) -+#define AW87XXX_PID_18_OVPI_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_18_OVPI_NORMAL_OPERATION << AW87XXX_PID_18_OVPI_START_BIT) -+ -+#define AW87XXX_PID_18_OVPI_CP_OVP_DETECTED (1) -+#define AW87XXX_PID_18_OVPI_CP_OVP_DETECTED_VALUE \ -+ (AW87XXX_PID_18_OVPI_CP_OVP_DETECTED << AW87XXX_PID_18_OVPI_START_BIT) -+ -+#define AW87XXX_PID_18_OVPI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_OVPI_DEFAULT \ -+ (AW87XXX_PID_18_OVPI_DEFAULT_VALUE << AW87XXX_PID_18_OVPI_START_BIT) -+ -+/* CP_2PI bit 0 (SYSINT 0x02) */ -+#define AW87XXX_PID_18_CP_2PI_START_BIT (0) -+#define AW87XXX_PID_18_CP_2PI_BITS_LEN (1) -+#define AW87XXX_PID_18_CP_2PI_MASK \ -+ (~(((1<<AW87XXX_PID_18_CP_2PI_BITS_LEN)-1) << AW87XXX_PID_18_CP_2PI_START_BIT)) -+ -+#define AW87XXX_PID_18_CP_2PI_WEAK_SIGNAL (0) -+#define AW87XXX_PID_18_CP_2PI_WEAK_SIGNAL_VALUE \ -+ (AW87XXX_PID_18_CP_2PI_WEAK_SIGNAL << AW87XXX_PID_18_CP_2PI_START_BIT) -+ -+#define AW87XXX_PID_18_CP_2PI_STRONG_SIGNAL (1) -+#define AW87XXX_PID_18_CP_2PI_STRONG_SIGNAL_VALUE \ -+ (AW87XXX_PID_18_CP_2PI_STRONG_SIGNAL << AW87XXX_PID_18_CP_2PI_START_BIT) -+ -+#define AW87XXX_PID_18_CP_2PI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_CP_2PI_DEFAULT \ -+ (AW87XXX_PID_18_CP_2PI_DEFAULT_VALUE << AW87XXX_PID_18_CP_2PI_START_BIT) -+ -+/* default value of SYSINT (0x02) */ -+/* #define AW87XXX_PID_18_SYSINT_DEFAULT (0x00) */ -+ -+/* SYSCTRL (0x03) detail */ -+/* EN_SS bit 7 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_EN_SS_START_BIT (7) -+#define AW87XXX_PID_18_EN_SS_BITS_LEN (1) -+#define AW87XXX_PID_18_EN_SS_MASK \ -+ (~(((1<<AW87XXX_PID_18_EN_SS_BITS_LEN)-1) << AW87XXX_PID_18_EN_SS_START_BIT)) -+ -+#define AW87XXX_PID_18_EN_SS_DISABLE_REG_FSS11001P6MHZ (0) -+#define AW87XXX_PID_18_EN_SS_DISABLE_REG_FSS11001P6MHZ_VALUE \ -+ (AW87XXX_PID_18_EN_SS_DISABLE_REG_FSS11001P6MHZ << AW87XXX_PID_18_EN_SS_START_BIT) -+ -+#define AW87XXX_PID_18_EN_SS_ENABLE (1) -+#define AW87XXX_PID_18_EN_SS_ENABLE_VALUE \ -+ (AW87XXX_PID_18_EN_SS_ENABLE << AW87XXX_PID_18_EN_SS_START_BIT) -+ -+#define AW87XXX_PID_18_EN_SS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_EN_SS_DEFAULT \ -+ (AW87XXX_PID_18_EN_SS_DEFAULT_VALUE << AW87XXX_PID_18_EN_SS_START_BIT) -+ -+/* REG_EN_SW bit 6 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_EN_SW_START_BIT (6) -+#define AW87XXX_PID_18_REG_EN_SW_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_SW_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_SW_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_SW_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_SW_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_SW_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_SW_DISABLE << AW87XXX_PID_18_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_SW_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_SW_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_SW_ENABLE << AW87XXX_PID_18_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_SW_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_SW_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_SW_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_SW_START_BIT) -+ -+/* REG_EN_PA bit 5 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_EN_PA_START_BIT (5) -+#define AW87XXX_PID_18_REG_EN_PA_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_PA_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_PA_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_PA_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_PA_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_PA_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_PA_DISABLE << AW87XXX_PID_18_REG_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_PA_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_PA_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_PA_ENABLE << AW87XXX_PID_18_REG_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_PA_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_PA_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_PA_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_PA_START_BIT) -+ -+/* REG_EN_ADAP bit 4 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_EN_ADAP_START_BIT (4) -+#define AW87XXX_PID_18_REG_EN_ADAP_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_ADAP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_ADAP_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_ADAP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_ADAP_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_ADAP_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_ADAP_DISABLE << AW87XXX_PID_18_REG_EN_ADAP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_ADAP_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_ADAP_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_ADAP_ENABLE << AW87XXX_PID_18_REG_EN_ADAP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_ADAP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_ADAP_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_ADAP_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_ADAP_START_BIT) -+ -+/* REG_EN_MPD bit 3 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_EN_MPD_START_BIT (3) -+#define AW87XXX_PID_18_REG_EN_MPD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_MPD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_MPD_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_MPD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_MPD_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_MPD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_MPD_DISABLE << AW87XXX_PID_18_REG_EN_MPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_MPD_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_MPD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_MPD_ENABLE << AW87XXX_PID_18_REG_EN_MPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_MPD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_MPD_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_MPD_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_MPD_START_BIT) -+ -+/* REG_EN_CP bit 2 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_EN_CP_START_BIT (2) -+#define AW87XXX_PID_18_REG_EN_CP_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_CP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_CP_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_CP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_CP_DISABLE_PVDDVBAT_DIRECT_TROUGH_MODE (0) -+#define AW87XXX_PID_18_REG_EN_CP_DISABLE_PVDDVBAT_DIRECT_TROUGH_MODE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_CP_DISABLE_PVDDVBAT_DIRECT_TROUGH_MODE << AW87XXX_PID_18_REG_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_CP_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_CP_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_CP_ENABLE << AW87XXX_PID_18_REG_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_CP_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_CP_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_CP_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_CP_START_BIT) -+ -+/* REG_REC_MODE bit 1 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_REC_MODE_START_BIT (1) -+#define AW87XXX_PID_18_REG_REC_MODE_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_REC_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_18_REG_REC_MODE_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_REC_MODE_DISABLE (0) -+#define AW87XXX_PID_18_REG_REC_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_REC_MODE_DISABLE << AW87XXX_PID_18_REG_REC_MODE_START_BIT) -+ -+#define AW87XXX_PID_18_REG_REC_MODE_ENABLE (1) -+#define AW87XXX_PID_18_REG_REC_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_REC_MODE_ENABLE << AW87XXX_PID_18_REG_REC_MODE_START_BIT) -+ -+#define AW87XXX_PID_18_REG_REC_MODE_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_REC_MODE_DEFAULT \ -+ (AW87XXX_PID_18_REG_REC_MODE_DEFAULT_VALUE << AW87XXX_PID_18_REG_REC_MODE_START_BIT) -+ -+/* REG_FORCE_2X bit 0 (SYSCTRL 0x03) */ -+#define AW87XXX_PID_18_REG_FORCE_2X_START_BIT (0) -+#define AW87XXX_PID_18_REG_FORCE_2X_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_FORCE_2X_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_FORCE_2X_BITS_LEN)-1) << AW87XXX_PID_18_REG_FORCE_2X_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_FORCE_2X_DISABLE_CPS_WORKING_STATUS_DEPENDS_ON_THE_SYSTEM (0) -+#define AW87XXX_PID_18_REG_FORCE_2X_DISABLE_CPS_WORKING_STATUS_DEPENDS_ON_THE_SYSTEM_VALUE \ -+ (AW87XXX_PID_18_REG_FORCE_2X_DISABLE_CPS_WORKING_STATUS_DEPENDS_ON_THE_SYSTEM << AW87XXX_PID_18_REG_FORCE_2X_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FORCE_2X_ENABLE_FORCE_THE_CP_WORKS_IN_X2_MODE (1) -+#define AW87XXX_PID_18_REG_FORCE_2X_ENABLE_FORCE_THE_CP_WORKS_IN_X2_MODE_VALUE \ -+ (AW87XXX_PID_18_REG_FORCE_2X_ENABLE_FORCE_THE_CP_WORKS_IN_X2_MODE << AW87XXX_PID_18_REG_FORCE_2X_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FORCE_2X_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_FORCE_2X_DEFAULT \ -+ (AW87XXX_PID_18_REG_FORCE_2X_DEFAULT_VALUE << AW87XXX_PID_18_REG_FORCE_2X_START_BIT) -+ -+/* default value of SYSCTRL (0x03) */ -+/* #define AW87XXX_PID_18_SYSCTRL_DEFAULT (0xE5) */ -+ -+/* CPOC (0x04) detail */ -+/* REG_CP_OVP bit 5:2 (CPOC 0x04) */ -+#define AW87XXX_PID_18_REG_CP_OVP_START_BIT (2) -+#define AW87XXX_PID_18_REG_CP_OVP_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_CP_OVP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_OVP_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_OVP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_8P5V (8) -+#define AW87XXX_PID_18_REG_CP_OVP_8P5V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_8P5V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_8P25V (7) -+#define AW87XXX_PID_18_REG_CP_OVP_8P25V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_8P25V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_8V (6) -+#define AW87XXX_PID_18_REG_CP_OVP_8V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_8V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_7P75V (5) -+#define AW87XXX_PID_18_REG_CP_OVP_7P75V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_7P75V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_7P5V (4) -+#define AW87XXX_PID_18_REG_CP_OVP_7P5V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_7P5V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_7P25V (3) -+#define AW87XXX_PID_18_REG_CP_OVP_7P25V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_7P25V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_7V (2) -+#define AW87XXX_PID_18_REG_CP_OVP_7V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_7V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_6P75V (1) -+#define AW87XXX_PID_18_REG_CP_OVP_6P75V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_6P75V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_6P5V (0) -+#define AW87XXX_PID_18_REG_CP_OVP_6P5V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_6P5V << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_DEFAULT_VALUE (0x6) -+#define AW87XXX_PID_18_REG_CP_OVP_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_OVP_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_OVP_START_BIT) -+ -+/* REG_OC_DELAY bit 1:0 (CPOC 0x04) */ -+#define AW87XXX_PID_18_REG_OC_DELAY_START_BIT (0) -+#define AW87XXX_PID_18_REG_OC_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_OC_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_OC_DELAY_BITS_LEN)-1) << AW87XXX_PID_18_REG_OC_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_OC_DELAY_60NS (0) -+#define AW87XXX_PID_18_REG_OC_DELAY_60NS_VALUE \ -+ (AW87XXX_PID_18_REG_OC_DELAY_60NS << AW87XXX_PID_18_REG_OC_DELAY_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OC_DELAY_80NS (1) -+#define AW87XXX_PID_18_REG_OC_DELAY_80NS_VALUE \ -+ (AW87XXX_PID_18_REG_OC_DELAY_80NS << AW87XXX_PID_18_REG_OC_DELAY_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OC_DELAY_90NS (2) -+#define AW87XXX_PID_18_REG_OC_DELAY_90NS_VALUE \ -+ (AW87XXX_PID_18_REG_OC_DELAY_90NS << AW87XXX_PID_18_REG_OC_DELAY_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OC_DELAY_110NS (3) -+#define AW87XXX_PID_18_REG_OC_DELAY_110NS_VALUE \ -+ (AW87XXX_PID_18_REG_OC_DELAY_110NS << AW87XXX_PID_18_REG_OC_DELAY_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OC_DELAY_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_OC_DELAY_DEFAULT \ -+ (AW87XXX_PID_18_REG_OC_DELAY_DEFAULT_VALUE << AW87XXX_PID_18_REG_OC_DELAY_START_BIT) -+ -+/* default value of CPOC (0x04) */ -+/* #define AW87XXX_PID_18_CPOC_DEFAULT (0x18) */ -+ -+/* CLASSD (0x05) detail */ -+/* REG_BK1 bit 7 (CLASSD 0x05) */ -+#define AW87XXX_PID_18_REG_BK1_START_BIT (7) -+#define AW87XXX_PID_18_REG_BK1_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_BK1_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_BK1_BITS_LEN)-1) << AW87XXX_PID_18_REG_BK1_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_BK1_22MV (0) -+#define AW87XXX_PID_18_REG_BK1_22MV_VALUE \ -+ (AW87XXX_PID_18_REG_BK1_22MV << AW87XXX_PID_18_REG_BK1_START_BIT) -+ -+#define AW87XXX_PID_18_REG_BK1_15MV (1) -+#define AW87XXX_PID_18_REG_BK1_15MV_VALUE \ -+ (AW87XXX_PID_18_REG_BK1_15MV << AW87XXX_PID_18_REG_BK1_START_BIT) -+ -+#define AW87XXX_PID_18_REG_BK1_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_BK1_DEFAULT \ -+ (AW87XXX_PID_18_REG_BK1_DEFAULT_VALUE << AW87XXX_PID_18_REG_BK1_START_BIT) -+ -+/* REG_BK2 bit 6 (CLASSD 0x05) */ -+#define AW87XXX_PID_18_REG_BK2_START_BIT (6) -+#define AW87XXX_PID_18_REG_BK2_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_BK2_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_BK2_BITS_LEN)-1) << AW87XXX_PID_18_REG_BK2_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_BK2_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_BK2_DEFAULT \ -+ (AW87XXX_PID_18_REG_BK2_DEFAULT_VALUE << AW87XXX_PID_18_REG_BK2_START_BIT) -+ -+/* REG_BK3 bit 5 (CLASSD 0x05) */ -+#define AW87XXX_PID_18_REG_BK3_START_BIT (5) -+#define AW87XXX_PID_18_REG_BK3_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_BK3_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_BK3_BITS_LEN)-1) << AW87XXX_PID_18_REG_BK3_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_BK3_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_BK3_DEFAULT \ -+ (AW87XXX_PID_18_REG_BK3_DEFAULT_VALUE << AW87XXX_PID_18_REG_BK3_START_BIT) -+ -+/* REG_D_GAIN bit 4:0 (CLASSD 0x05) */ -+#define AW87XXX_PID_18_REG_D_GAIN_START_BIT (0) -+#define AW87XXX_PID_18_REG_D_GAIN_BITS_LEN (5) -+#define AW87XXX_PID_18_REG_D_GAIN_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_D_GAIN_BITS_LEN)-1) << AW87XXX_PID_18_REG_D_GAIN_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_0DB (0) -+#define AW87XXX_PID_18_REG_D_GAIN_0DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_0DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_1P5DB (1) -+#define AW87XXX_PID_18_REG_D_GAIN_1P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_1P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_3DB (2) -+#define AW87XXX_PID_18_REG_D_GAIN_3DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_3DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_4P5DB (3) -+#define AW87XXX_PID_18_REG_D_GAIN_4P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_4P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_6DB (4) -+#define AW87XXX_PID_18_REG_D_GAIN_6DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_6DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_7P5DB (5) -+#define AW87XXX_PID_18_REG_D_GAIN_7P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_7P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_9DB (6) -+#define AW87XXX_PID_18_REG_D_GAIN_9DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_9DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_10P5DB (7) -+#define AW87XXX_PID_18_REG_D_GAIN_10P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_10P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_12DB (8) -+#define AW87XXX_PID_18_REG_D_GAIN_12DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_12DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_13P5DB (9) -+#define AW87XXX_PID_18_REG_D_GAIN_13P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_13P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_15DB (10) -+#define AW87XXX_PID_18_REG_D_GAIN_15DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_15DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_16P5DB (11) -+#define AW87XXX_PID_18_REG_D_GAIN_16P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_16P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_18DB (12) -+#define AW87XXX_PID_18_REG_D_GAIN_18DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_18DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_19P5DB (13) -+#define AW87XXX_PID_18_REG_D_GAIN_19P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_19P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_21DB (14) -+#define AW87XXX_PID_18_REG_D_GAIN_21DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_21DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_22P5DB (15) -+#define AW87XXX_PID_18_REG_D_GAIN_22P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_22P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_24DB (16) -+#define AW87XXX_PID_18_REG_D_GAIN_24DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_24DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_25P5DB (17) -+#define AW87XXX_PID_18_REG_D_GAIN_25P5DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_25P5DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_27DB (18) -+#define AW87XXX_PID_18_REG_D_GAIN_27DB_VALUE \ -+ (AW87XXX_PID_18_REG_D_GAIN_27DB << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+#define AW87XXX_PID_18_REG_D_GAIN_DEFAULT_VALUE (0x10) -+#define AW87XXX_PID_18_REG_D_GAIN_DEFAULT \ -+ (AW87XXX_PID_18_REG_D_GAIN_DEFAULT_VALUE << AW87XXX_PID_18_REG_D_GAIN_START_BIT) -+ -+/* default value of CLASSD (0x05) */ -+/* #define AW87XXX_PID_18_CLASSD_DEFAULT (0x10) */ -+ -+/* MADPVTH (0x06) detail */ -+/* REG_ADAP_VTH bit 3:2 (MADPVTH 0x06) */ -+#define AW87XXX_PID_18_REG_ADAP_VTH_START_BIT (2) -+#define AW87XXX_PID_18_REG_ADAP_VTH_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_ADAP_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_ADAP_VTH_BITS_LEN)-1) << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P1W0P05W (0) -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P1W0P05W_VALUE \ -+ (AW87XXX_PID_18_REG_ADAP_VTH_0P1W0P05W << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P2W0P15W (1) -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P2W0P15W_VALUE \ -+ (AW87XXX_PID_18_REG_ADAP_VTH_0P2W0P15W << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P3W0P25W (2) -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P3W0P25W_VALUE \ -+ (AW87XXX_PID_18_REG_ADAP_VTH_0P3W0P25W << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P4W0P35W (3) -+#define AW87XXX_PID_18_REG_ADAP_VTH_0P4W0P35W_VALUE \ -+ (AW87XXX_PID_18_REG_ADAP_VTH_0P4W0P35W << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ADAP_VTH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_ADAP_VTH_DEFAULT \ -+ (AW87XXX_PID_18_REG_ADAP_VTH_DEFAULT_VALUE << AW87XXX_PID_18_REG_ADAP_VTH_START_BIT) -+ -+/* REG_MPD_VTH bit 1:0 (MADPVTH 0x06) */ -+#define AW87XXX_PID_18_REG_MPD_VTH_START_BIT (0) -+#define AW87XXX_PID_18_REG_MPD_VTH_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_MPD_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_MPD_VTH_BITS_LEN)-1) << AW87XXX_PID_18_REG_MPD_VTH_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_MPD_VTH_8P1MW3P6MW (0) -+#define AW87XXX_PID_18_REG_MPD_VTH_8P1MW3P6MW_VALUE \ -+ (AW87XXX_PID_18_REG_MPD_VTH_8P1MW3P6MW << AW87XXX_PID_18_REG_MPD_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_MPD_VTH_11MW5P6MW (1) -+#define AW87XXX_PID_18_REG_MPD_VTH_11MW5P6MW_VALUE \ -+ (AW87XXX_PID_18_REG_MPD_VTH_11MW5P6MW << AW87XXX_PID_18_REG_MPD_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_MPD_VTH_14P4MW8P1MW (2) -+#define AW87XXX_PID_18_REG_MPD_VTH_14P4MW8P1MW_VALUE \ -+ (AW87XXX_PID_18_REG_MPD_VTH_14P4MW8P1MW << AW87XXX_PID_18_REG_MPD_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_MPD_VTH_18P2MW11W (3) -+#define AW87XXX_PID_18_REG_MPD_VTH_18P2MW11W_VALUE \ -+ (AW87XXX_PID_18_REG_MPD_VTH_18P2MW11W << AW87XXX_PID_18_REG_MPD_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_MPD_VTH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_MPD_VTH_DEFAULT \ -+ (AW87XXX_PID_18_REG_MPD_VTH_DEFAULT_VALUE << AW87XXX_PID_18_REG_MPD_VTH_START_BIT) -+ -+/* default value of MADPVTH (0x06) */ -+/* #define AW87XXX_PID_18_MADPVTH_DEFAULT (0x05) */ -+ -+/* A3PARAM (0x07) detail */ -+/* REG_AGC3_RT bit 7:5 (A3PARAM 0x07) */ -+#define AW87XXX_PID_18_REG_AGC3_RT_START_BIT (5) -+#define AW87XXX_PID_18_REG_AGC3_RT_BITS_LEN (3) -+#define AW87XXX_PID_18_REG_AGC3_RT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC3_RT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC3_RT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_69P12MS (0) -+#define AW87XXX_PID_18_REG_AGC3_RT_69P12MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_69P12MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_138P24MS (1) -+#define AW87XXX_PID_18_REG_AGC3_RT_138P24MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_138P24MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_276P48MS (2) -+#define AW87XXX_PID_18_REG_AGC3_RT_276P48MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_276P48MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_552P96MS (3) -+#define AW87XXX_PID_18_REG_AGC3_RT_552P96MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_552P96MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_1107MS (4) -+#define AW87XXX_PID_18_REG_AGC3_RT_1107MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_1107MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_2160MS (5) -+#define AW87XXX_PID_18_REG_AGC3_RT_2160MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_2160MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_4320MS (6) -+#define AW87XXX_PID_18_REG_AGC3_RT_4320MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_RT_4320MS << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_RT_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_18_REG_AGC3_RT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC3_RT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC3_RT_START_BIT) -+ -+/* REG_AGC3_AT bit 4:2 (A3PARAM 0x07) */ -+#define AW87XXX_PID_18_REG_AGC3_AT_START_BIT (2) -+#define AW87XXX_PID_18_REG_AGC3_AT_BITS_LEN (3) -+#define AW87XXX_PID_18_REG_AGC3_AT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC3_AT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC3_AT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_5P76MS_0P32MSSTEP (0) -+#define AW87XXX_PID_18_REG_AGC3_AT_5P76MS_0P32MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_5P76MS_0P32MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_11P52MS_0P64MSSTEP (1) -+#define AW87XXX_PID_18_REG_AGC3_AT_11P52MS_0P64MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_11P52MS_0P64MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_23P04MS_1P28MSSTEP (2) -+#define AW87XXX_PID_18_REG_AGC3_AT_23P04MS_1P28MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_23P04MS_1P28MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_92P16MS_5P12MSSTEP (3) -+#define AW87XXX_PID_18_REG_AGC3_AT_92P16MS_5P12MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_92P16MS_5P12MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_368P64MS_20P48MSSTEP (4) -+#define AW87XXX_PID_18_REG_AGC3_AT_368P64MS_20P48MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_368P64MS_20P48MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_738MS_41MSSTEP (5) -+#define AW87XXX_PID_18_REG_AGC3_AT_738MS_41MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_738MS_41MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_1476MS_82MSSTEP (6) -+#define AW87XXX_PID_18_REG_AGC3_AT_1476MS_82MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_1476MS_82MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_2952MS_164MSSTEP (7) -+#define AW87XXX_PID_18_REG_AGC3_AT_2952MS_164MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_AT_2952MS_164MSSTEP << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_AT_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_18_REG_AGC3_AT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC3_AT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC3_AT_START_BIT) -+ -+/* REG_AGC3_1ST_AT bit 1:0 (A3PARAM 0x07) */ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT (0) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC3_1ST_AT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_5P12MS (0) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_5P12MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_1ST_AT_5P12MS << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_10P24MS (1) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_10P24MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_1ST_AT_10P24MS << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_20P48MS (2) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_20P48MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_1ST_AT_20P48MS << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_41MS (3) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_41MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_1ST_AT_41MS << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_18_REG_AGC3_1ST_AT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC3_1ST_AT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC3_1ST_AT_START_BIT) -+ -+/* default value of A3PARAM (0x07) */ -+/* #define AW87XXX_PID_18_A3PARAM_DEFAULT (0x52) */ -+ -+/* A3A2PO (0x08) detail */ -+/* REG_AGC3_PO bit 7:4 (A3A2PO 0x08) */ -+#define AW87XXX_PID_18_REG_AGC3_PO_START_BIT (4) -+#define AW87XXX_PID_18_REG_AGC3_PO_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_AGC3_PO_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC3_PO_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC3_PO_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P2W8_OHM_0P27W6_OHM_0P05W32_OHM (0) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P2W8_OHM_0P27W6_OHM_0P05W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P2W8_OHM_0P27W6_OHM_0P05W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P3W8_OHM_0P4W6_OHM_0P075W32_OHM (1) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P3W8_OHM_0P4W6_OHM_0P075W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P3W8_OHM_0P4W6_OHM_0P075W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM (2) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P5W8_OHM_0P67W6_OHM_0P125W32_OHM (3) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P5W8_OHM_0P67W6_OHM_0P125W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P5W8_OHM_0P67W6_OHM_0P125W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM (4) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P7W8_OHM_0P93W6_OHM_0P175W32_OHM (5) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P7W8_OHM_0P93W6_OHM_0P175W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P7W8_OHM_0P93W6_OHM_0P175W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM (6) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_0P9W8_OHM_1P2W6_OHM_0P225W32_OHM (7) -+#define AW87XXX_PID_18_REG_AGC3_PO_0P9W8_OHM_1P2W6_OHM_0P225W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_0P9W8_OHM_1P2W6_OHM_0P225W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM (8) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P1W8_OHM_1P46W6_OHM_0P275W32_OHM (9) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P1W8_OHM_1P46W6_OHM_0P275W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P1W8_OHM_1P46W6_OHM_0P275W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P2W8_OHM_1P6W6_OHM_0P30W32_OHM (10) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P2W8_OHM_1P6W6_OHM_0P30W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P2W8_OHM_1P6W6_OHM_0P30W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P3W8_OHM_1P73W6_OHM_0P325W32_OHM (11) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P3W8_OHM_1P73W6_OHM_0P325W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P3W8_OHM_1P73W6_OHM_0P325W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM (12) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P5W8_OHM_2W6_OHM_0P375W32_OHM (13) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P5W8_OHM_2W6_OHM_0P375W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P5W8_OHM_2W6_OHM_0P375W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM (14) -+#define AW87XXX_PID_18_REG_AGC3_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_AGC3_OFF (15) -+#define AW87XXX_PID_18_REG_AGC3_PO_AGC3_OFF_VALUE \ -+ (AW87XXX_PID_18_REG_AGC3_PO_AGC3_OFF << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC3_PO_DEFAULT_VALUE (0xA) -+#define AW87XXX_PID_18_REG_AGC3_PO_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC3_PO_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC3_PO_START_BIT) -+ -+/* REG_AGC2_PO bit 3:0 (A3A2PO 0x08) */ -+#define AW87XXX_PID_18_REG_AGC2_PO_START_BIT (0) -+#define AW87XXX_PID_18_REG_AGC2_PO_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_AGC2_PO_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC2_PO_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC2_PO_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM (0) -+#define AW87XXX_PID_18_REG_AGC2_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_0P4W8_OHM_0P53W6_OHM_0P1W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM (1) -+#define AW87XXX_PID_18_REG_AGC2_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_0P6W8_OHM_0P8W6_OHM_0P15W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM (2) -+#define AW87XXX_PID_18_REG_AGC2_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_0P8W8_OHM_1P06W6_OHM_0P2W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM (3) -+#define AW87XXX_PID_18_REG_AGC2_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_1P0W8_OHM_1P33W6_OHM_0P25W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_1P2W8_OHM_1P6W6_OHM_0P3W32_OHM (4) -+#define AW87XXX_PID_18_REG_AGC2_PO_1P2W8_OHM_1P6W6_OHM_0P3W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_1P2W8_OHM_1P6W6_OHM_0P3W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM (5) -+#define AW87XXX_PID_18_REG_AGC2_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_1P4W8_OHM_1P86W6_OHM_0P35W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM (6) -+#define AW87XXX_PID_18_REG_AGC2_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_1P6W8_OHM_2P13W6_OHM_0P4W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_1P8W8_OHM_2P4W6_OHM_0P45W32_OHM (7) -+#define AW87XXX_PID_18_REG_AGC2_PO_1P8W8_OHM_2P4W6_OHM_0P45W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_1P8W8_OHM_2P4W6_OHM_0P45W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_2P0W8_OHM_2P66W6_OHM_0P5W32_OHM (8) -+#define AW87XXX_PID_18_REG_AGC2_PO_2P0W8_OHM_2P66W6_OHM_0P5W32_OHM_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_2P0W8_OHM_2P66W6_OHM_0P5W32_OHM << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_AGC2_OFF (9) -+#define AW87XXX_PID_18_REG_AGC2_PO_AGC2_OFF_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_PO_AGC2_OFF << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_PO_DEFAULT_VALUE (0x6) -+#define AW87XXX_PID_18_REG_AGC2_PO_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC2_PO_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC2_PO_START_BIT) -+ -+/* default value of A3A2PO (0x08) */ -+/* #define AW87XXX_PID_18_A3A2PO_DEFAULT (0xA6) */ -+ -+/* A2PARAM (0x09) detail */ -+/* REG_TEDGE bit 5 (A2PARAM 0x09) */ -+#define AW87XXX_PID_18_REG_TEDGE_START_BIT (5) -+#define AW87XXX_PID_18_REG_TEDGE_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_TEDGE_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_TEDGE_BITS_LEN)-1) << AW87XXX_PID_18_REG_TEDGE_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_TEDGE_4NS (0) -+#define AW87XXX_PID_18_REG_TEDGE_4NS_VALUE \ -+ (AW87XXX_PID_18_REG_TEDGE_4NS << AW87XXX_PID_18_REG_TEDGE_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TEDGE_12NS (1) -+#define AW87XXX_PID_18_REG_TEDGE_12NS_VALUE \ -+ (AW87XXX_PID_18_REG_TEDGE_12NS << AW87XXX_PID_18_REG_TEDGE_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TEDGE_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_TEDGE_DEFAULT \ -+ (AW87XXX_PID_18_REG_TEDGE_DEFAULT_VALUE << AW87XXX_PID_18_REG_TEDGE_START_BIT) -+ -+/* REG_AGC2_AT bit 4:2 (A2PARAM 0x09) */ -+#define AW87XXX_PID_18_REG_AGC2_AT_START_BIT (2) -+#define AW87XXX_PID_18_REG_AGC2_AT_BITS_LEN (3) -+#define AW87XXX_PID_18_REG_AGC2_AT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC2_AT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC2_AT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_1P44MS_0P08MSSTEP (0) -+#define AW87XXX_PID_18_REG_AGC2_AT_1P44MS_0P08MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_1P44MS_0P08MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_2P88MS_0P16MSSTEP (1) -+#define AW87XXX_PID_18_REG_AGC2_AT_2P88MS_0P16MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_2P88MS_0P16MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_5P76MS_0P32MSSTEP (2) -+#define AW87XXX_PID_18_REG_AGC2_AT_5P76MS_0P32MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_5P76MS_0P32MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_23P04MS_1P28MSSTEP (3) -+#define AW87XXX_PID_18_REG_AGC2_AT_23P04MS_1P28MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_23P04MS_1P28MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_92P16MS_5P12MSSTEP (4) -+#define AW87XXX_PID_18_REG_AGC2_AT_92P16MS_5P12MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_92P16MS_5P12MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_368P64MS_20P48MSSTEP (5) -+#define AW87XXX_PID_18_REG_AGC2_AT_368P64MS_20P48MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_368P64MS_20P48MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_737P28MS_41MSSTEP (6) -+#define AW87XXX_PID_18_REG_AGC2_AT_737P28MS_41MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_737P28MS_41MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_1474P56MS_82MSSTEP (7) -+#define AW87XXX_PID_18_REG_AGC2_AT_1474P56MS_82MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_AT_1474P56MS_82MSSTEP << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_AT_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_18_REG_AGC2_AT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC2_AT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC2_AT_START_BIT) -+ -+/* REG_AGC2_1ST_AT bit 1:0 (A2PARAM 0x09) */ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT (0) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC2_1ST_AT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_0P08MS (0) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_0P08MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_1ST_AT_0P08MS << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_0P32MS (1) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_0P32MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_1ST_AT_0P32MS << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_1P28MS (2) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_1P28MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_1ST_AT_1P28MS << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_5P12MS (3) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_5P12MS_VALUE \ -+ (AW87XXX_PID_18_REG_AGC2_1ST_AT_5P12MS << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_AGC2_1ST_AT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC2_1ST_AT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC2_1ST_AT_START_BIT) -+ -+/* default value of A2PARAM (0x09) */ -+/* #define AW87XXX_PID_18_A2PARAM_DEFAULT (0x08) */ -+ -+/* A1PARAM (0x0A) detail */ -+/* REG_AGC1_PO bit 6:3 (A1PARAM 0x0A) */ -+#define AW87XXX_PID_18_REG_AGC1_PO_START_BIT (3) -+#define AW87XXX_PID_18_REG_AGC1_PO_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_AGC1_PO_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC1_PO_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC1_PO_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_5V (0) -+#define AW87XXX_PID_18_REG_AGC1_PO_5V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_5V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_5P2V (1) -+#define AW87XXX_PID_18_REG_AGC1_PO_5P2V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_5P2V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_5P4V (2) -+#define AW87XXX_PID_18_REG_AGC1_PO_5P4V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_5P4V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_5P6V (3) -+#define AW87XXX_PID_18_REG_AGC1_PO_5P6V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_5P6V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_5P8V (4) -+#define AW87XXX_PID_18_REG_AGC1_PO_5P8V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_5P8V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_6P0V (5) -+#define AW87XXX_PID_18_REG_AGC1_PO_6P0V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_6P0V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_6P2V (6) -+#define AW87XXX_PID_18_REG_AGC1_PO_6P2V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_6P2V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_6P4V (7) -+#define AW87XXX_PID_18_REG_AGC1_PO_6P4V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_6P4V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_6P6V (8) -+#define AW87XXX_PID_18_REG_AGC1_PO_6P6V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_6P6V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_6P8V (9) -+#define AW87XXX_PID_18_REG_AGC1_PO_6P8V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_6P8V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_7V (10) -+#define AW87XXX_PID_18_REG_AGC1_PO_7V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_7V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_7P2V (11) -+#define AW87XXX_PID_18_REG_AGC1_PO_7P2V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_7P2V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_7P4V (12) -+#define AW87XXX_PID_18_REG_AGC1_PO_7P4V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_7P4V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_7P6V (13) -+#define AW87XXX_PID_18_REG_AGC1_PO_7P6V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_7P6V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_7P8V (14) -+#define AW87XXX_PID_18_REG_AGC1_PO_7P8V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_7P8V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_8V (15) -+#define AW87XXX_PID_18_REG_AGC1_PO_8V_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_PO_8V << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_PO_DEFAULT_VALUE (0x9) -+#define AW87XXX_PID_18_REG_AGC1_PO_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC1_PO_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC1_PO_START_BIT) -+ -+/* REG_AGC1_AT bit 2:1 (A1PARAM 0x0A) */ -+#define AW87XXX_PID_18_REG_AGC1_AT_START_BIT (1) -+#define AW87XXX_PID_18_REG_AGC1_AT_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_AGC1_AT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC1_AT_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC1_AT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC1_AT_0P48MS_0P02MSSTEP (0) -+#define AW87XXX_PID_18_REG_AGC1_AT_0P48MS_0P02MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_AT_0P48MS_0P02MSSTEP << AW87XXX_PID_18_REG_AGC1_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_AT_0P96MS_0P04MSSTEP (1) -+#define AW87XXX_PID_18_REG_AGC1_AT_0P96MS_0P04MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_AT_0P96MS_0P04MSSTEP << AW87XXX_PID_18_REG_AGC1_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_AT_1P92MS_0P08MSSTEP (2) -+#define AW87XXX_PID_18_REG_AGC1_AT_1P92MS_0P08MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_AT_1P92MS_0P08MSSTEP << AW87XXX_PID_18_REG_AGC1_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_AT_3P84MS_0P16MSSTEP (3) -+#define AW87XXX_PID_18_REG_AGC1_AT_3P84MS_0P16MSSTEP_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_AT_3P84MS_0P16MSSTEP << AW87XXX_PID_18_REG_AGC1_AT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_AT_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_AGC1_AT_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC1_AT_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC1_AT_START_BIT) -+ -+/* REG_PD_AGC1 bit 0 (A1PARAM 0x0A) */ -+#define AW87XXX_PID_18_REG_PD_AGC1_START_BIT (0) -+#define AW87XXX_PID_18_REG_PD_AGC1_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_PD_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_18_REG_PD_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_PD_AGC1_ENABLE_FASTEST_LEVEL_AGC (0) -+#define AW87XXX_PID_18_REG_PD_AGC1_ENABLE_FASTEST_LEVEL_AGC_VALUE \ -+ (AW87XXX_PID_18_REG_PD_AGC1_ENABLE_FASTEST_LEVEL_AGC << AW87XXX_PID_18_REG_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_AGC1_DISABLE_FASTEST_LEVEL_AGC (1) -+#define AW87XXX_PID_18_REG_PD_AGC1_DISABLE_FASTEST_LEVEL_AGC_VALUE \ -+ (AW87XXX_PID_18_REG_PD_AGC1_DISABLE_FASTEST_LEVEL_AGC << AW87XXX_PID_18_REG_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_AGC1_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_PD_AGC1_DEFAULT \ -+ (AW87XXX_PID_18_REG_PD_AGC1_DEFAULT_VALUE << AW87XXX_PID_18_REG_PD_AGC1_START_BIT) -+ -+/* default value of A1PARAM (0x0A) */ -+/* #define AW87XXX_PID_18_A1PARAM_DEFAULT (0x4A) */ -+ -+/* POPCLK (0x0B) detail */ -+/* REG_DCLK_L bit 7 (POPCLK 0x0B) */ -+#define AW87XXX_PID_18_REG_DCLK_L_START_BIT (7) -+#define AW87XXX_PID_18_REG_DCLK_L_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_DCLK_L_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_DCLK_L_BITS_LEN)-1) << AW87XXX_PID_18_REG_DCLK_L_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_DCLK_L_30NS (0) -+#define AW87XXX_PID_18_REG_DCLK_L_30NS_VALUE \ -+ (AW87XXX_PID_18_REG_DCLK_L_30NS << AW87XXX_PID_18_REG_DCLK_L_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DCLK_L_45NS (1) -+#define AW87XXX_PID_18_REG_DCLK_L_45NS_VALUE \ -+ (AW87XXX_PID_18_REG_DCLK_L_45NS << AW87XXX_PID_18_REG_DCLK_L_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DCLK_L_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_DCLK_L_DEFAULT \ -+ (AW87XXX_PID_18_REG_DCLK_L_DEFAULT_VALUE << AW87XXX_PID_18_REG_DCLK_L_START_BIT) -+ -+/* REG_CLK_MAPD bit 6:5 (POPCLK 0x0B) */ -+#define AW87XXX_PID_18_REG_CLK_MAPD_START_BIT (5) -+#define AW87XXX_PID_18_REG_CLK_MAPD_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CLK_MAPD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CLK_MAPD_BITS_LEN)-1) << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CLK_MAPD_40MS (0) -+#define AW87XXX_PID_18_REG_CLK_MAPD_40MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_MAPD_40MS << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_MAPD_80MS (1) -+#define AW87XXX_PID_18_REG_CLK_MAPD_80MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_MAPD_80MS << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_MAPD_160MS (2) -+#define AW87XXX_PID_18_REG_CLK_MAPD_160MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_MAPD_160MS << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_MAPD_320MS (3) -+#define AW87XXX_PID_18_REG_CLK_MAPD_320MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_MAPD_320MS << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_MAPD_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_CLK_MAPD_DEFAULT \ -+ (AW87XXX_PID_18_REG_CLK_MAPD_DEFAULT_VALUE << AW87XXX_PID_18_REG_CLK_MAPD_START_BIT) -+ -+/* REG_CLK_POP bit 4:3 (POPCLK 0x0B) */ -+#define AW87XXX_PID_18_REG_CLK_POP_START_BIT (3) -+#define AW87XXX_PID_18_REG_CLK_POP_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CLK_POP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CLK_POP_BITS_LEN)-1) << AW87XXX_PID_18_REG_CLK_POP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CLK_POP_40MS (0) -+#define AW87XXX_PID_18_REG_CLK_POP_40MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_POP_40MS << AW87XXX_PID_18_REG_CLK_POP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_POP_10MS (1) -+#define AW87XXX_PID_18_REG_CLK_POP_10MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_POP_10MS << AW87XXX_PID_18_REG_CLK_POP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_POP_5MS (2) -+#define AW87XXX_PID_18_REG_CLK_POP_5MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_POP_5MS << AW87XXX_PID_18_REG_CLK_POP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_POP_2P5MS (3) -+#define AW87XXX_PID_18_REG_CLK_POP_2P5MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_POP_2P5MS << AW87XXX_PID_18_REG_CLK_POP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_POP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_CLK_POP_DEFAULT \ -+ (AW87XXX_PID_18_REG_CLK_POP_DEFAULT_VALUE << AW87XXX_PID_18_REG_CLK_POP_START_BIT) -+ -+/* REG_CLK_OC bit 2:1 (POPCLK 0x0B) */ -+#define AW87XXX_PID_18_REG_CLK_OC_START_BIT (1) -+#define AW87XXX_PID_18_REG_CLK_OC_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CLK_OC_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CLK_OC_BITS_LEN)-1) << AW87XXX_PID_18_REG_CLK_OC_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CLK_OC_160MS (0) -+#define AW87XXX_PID_18_REG_CLK_OC_160MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_OC_160MS << AW87XXX_PID_18_REG_CLK_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_OC_640MS (1) -+#define AW87XXX_PID_18_REG_CLK_OC_640MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_OC_640MS << AW87XXX_PID_18_REG_CLK_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_OC_1280MS (2) -+#define AW87XXX_PID_18_REG_CLK_OC_1280MS_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_OC_1280MS << AW87XXX_PID_18_REG_CLK_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_OC_SHUTDOWN_OUTPUT (3) -+#define AW87XXX_PID_18_REG_CLK_OC_SHUTDOWN_OUTPUT_VALUE \ -+ (AW87XXX_PID_18_REG_CLK_OC_SHUTDOWN_OUTPUT << AW87XXX_PID_18_REG_CLK_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CLK_OC_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_CLK_OC_DEFAULT \ -+ (AW87XXX_PID_18_REG_CLK_OC_DEFAULT_VALUE << AW87XXX_PID_18_REG_CLK_OC_START_BIT) -+ -+/* REG_AGC1_VTH bit 0 (POPCLK 0x0B) */ -+#define AW87XXX_PID_18_REG_AGC1_VTH_START_BIT (0) -+#define AW87XXX_PID_18_REG_AGC1_VTH_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_AGC1_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_AGC1_VTH_BITS_LEN)-1) << AW87XXX_PID_18_REG_AGC1_VTH_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_SELECT_ONLY_FROM_RAMP_GEN (0) -+#define AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_SELECT_ONLY_FROM_RAMP_GEN_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_SELECT_ONLY_FROM_RAMP_GEN << AW87XXX_PID_18_REG_AGC1_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_ADAPTIVELY_SELECT_FROM_RAMP_GEN_AND_THGEN (1) -+#define AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_ADAPTIVELY_SELECT_FROM_RAMP_GEN_AND_THGEN_VALUE \ -+ (AW87XXX_PID_18_REG_AGC1_VTH_AGC1_VTH_ADAPTIVELY_SELECT_FROM_RAMP_GEN_AND_THGEN << AW87XXX_PID_18_REG_AGC1_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_AGC1_VTH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_AGC1_VTH_DEFAULT \ -+ (AW87XXX_PID_18_REG_AGC1_VTH_DEFAULT_VALUE << AW87XXX_PID_18_REG_AGC1_VTH_START_BIT) -+ -+/* default value of POPCLK (0x0B) */ -+/* #define AW87XXX_PID_18_POPCLK_DEFAULT (0x21) */ -+ -+/* GTDRCPSS (0x0C) detail */ -+/* REG_TDEAD bit 5 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_REG_TDEAD_START_BIT (5) -+#define AW87XXX_PID_18_REG_TDEAD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_TDEAD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_TDEAD_BITS_LEN)-1) << AW87XXX_PID_18_REG_TDEAD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_TDEAD_17NS (0) -+#define AW87XXX_PID_18_REG_TDEAD_17NS_VALUE \ -+ (AW87XXX_PID_18_REG_TDEAD_17NS << AW87XXX_PID_18_REG_TDEAD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TDEAD_25NS (1) -+#define AW87XXX_PID_18_REG_TDEAD_25NS_VALUE \ -+ (AW87XXX_PID_18_REG_TDEAD_25NS << AW87XXX_PID_18_REG_TDEAD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TDEAD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_TDEAD_DEFAULT \ -+ (AW87XXX_PID_18_REG_TDEAD_DEFAULT_VALUE << AW87XXX_PID_18_REG_TDEAD_START_BIT) -+ -+/* REG_CZ_35MV bit 4 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_REG_CZ_35MV_START_BIT (4) -+#define AW87XXX_PID_18_REG_CZ_35MV_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_CZ_35MV_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CZ_35MV_BITS_LEN)-1) << AW87XXX_PID_18_REG_CZ_35MV_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CZ_35MV_25MV (0) -+#define AW87XXX_PID_18_REG_CZ_35MV_25MV_VALUE \ -+ (AW87XXX_PID_18_REG_CZ_35MV_25MV << AW87XXX_PID_18_REG_CZ_35MV_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CZ_35MV_35MV (1) -+#define AW87XXX_PID_18_REG_CZ_35MV_35MV_VALUE \ -+ (AW87XXX_PID_18_REG_CZ_35MV_35MV << AW87XXX_PID_18_REG_CZ_35MV_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CZ_35MV_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_CZ_35MV_DEFAULT \ -+ (AW87XXX_PID_18_REG_CZ_35MV_DEFAULT_VALUE << AW87XXX_PID_18_REG_CZ_35MV_START_BIT) -+ -+/* BIT_CTRL bit 3 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_BIT_CTRL_START_BIT (3) -+#define AW87XXX_PID_18_BIT_CTRL_BITS_LEN (1) -+#define AW87XXX_PID_18_BIT_CTRL_MASK \ -+ (~(((1<<AW87XXX_PID_18_BIT_CTRL_BITS_LEN)-1) << AW87XXX_PID_18_BIT_CTRL_START_BIT)) -+ -+#define AW87XXX_PID_18_BIT_CTRL_32_STEP_SPREAD_SPECTRUM (0) -+#define AW87XXX_PID_18_BIT_CTRL_32_STEP_SPREAD_SPECTRUM_VALUE \ -+ (AW87XXX_PID_18_BIT_CTRL_32_STEP_SPREAD_SPECTRUM << AW87XXX_PID_18_BIT_CTRL_START_BIT) -+ -+#define AW87XXX_PID_18_BIT_CTRL_14_STEP_SPREAD_SPECTRUM (1) -+#define AW87XXX_PID_18_BIT_CTRL_14_STEP_SPREAD_SPECTRUM_VALUE \ -+ (AW87XXX_PID_18_BIT_CTRL_14_STEP_SPREAD_SPECTRUM << AW87XXX_PID_18_BIT_CTRL_START_BIT) -+ -+#define AW87XXX_PID_18_BIT_CTRL_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_BIT_CTRL_DEFAULT \ -+ (AW87XXX_PID_18_BIT_CTRL_DEFAULT_VALUE << AW87XXX_PID_18_BIT_CTRL_START_BIT) -+ -+/* SS_EXCH bit 2 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_SS_EXCH_START_BIT (2) -+#define AW87XXX_PID_18_SS_EXCH_BITS_LEN (1) -+#define AW87XXX_PID_18_SS_EXCH_MASK \ -+ (~(((1<<AW87XXX_PID_18_SS_EXCH_BITS_LEN)-1) << AW87XXX_PID_18_SS_EXCH_START_BIT)) -+ -+#define AW87XXX_PID_18_SS_EXCH_12_RANGE (0) -+#define AW87XXX_PID_18_SS_EXCH_12_RANGE_VALUE \ -+ (AW87XXX_PID_18_SS_EXCH_12_RANGE << AW87XXX_PID_18_SS_EXCH_START_BIT) -+ -+#define AW87XXX_PID_18_SS_EXCH_6_RANGE (1) -+#define AW87XXX_PID_18_SS_EXCH_6_RANGE_VALUE \ -+ (AW87XXX_PID_18_SS_EXCH_6_RANGE << AW87XXX_PID_18_SS_EXCH_START_BIT) -+ -+#define AW87XXX_PID_18_SS_EXCH_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_SS_EXCH_DEFAULT \ -+ (AW87XXX_PID_18_SS_EXCH_DEFAULT_VALUE << AW87XXX_PID_18_SS_EXCH_START_BIT) -+ -+/* REG_ISTART bit 1 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_REG_ISTART_START_BIT (1) -+#define AW87XXX_PID_18_REG_ISTART_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_ISTART_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_ISTART_BITS_LEN)-1) << AW87XXX_PID_18_REG_ISTART_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_ISTART_IBIAS_WI_46P8NA (0) -+#define AW87XXX_PID_18_REG_ISTART_IBIAS_WI_46P8NA_VALUE \ -+ (AW87XXX_PID_18_REG_ISTART_IBIAS_WI_46P8NA << AW87XXX_PID_18_REG_ISTART_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ISTART_IBIAS_WI_62P5NA (1) -+#define AW87XXX_PID_18_REG_ISTART_IBIAS_WI_62P5NA_VALUE \ -+ (AW87XXX_PID_18_REG_ISTART_IBIAS_WI_62P5NA << AW87XXX_PID_18_REG_ISTART_START_BIT) -+ -+#define AW87XXX_PID_18_REG_ISTART_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_ISTART_DEFAULT \ -+ (AW87XXX_PID_18_REG_ISTART_DEFAULT_VALUE << AW87XXX_PID_18_REG_ISTART_START_BIT) -+ -+/* REG_PD_OVPICTRL bit 0 (GTDRCPSS 0x0C) */ -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_START_BIT (0) -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_PD_OVPICTRL_BITS_LEN)-1) << AW87XXX_PID_18_REG_PD_OVPICTRL_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_DISABLE (0) -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_OVPICTRL_DISABLE << AW87XXX_PID_18_REG_PD_OVPICTRL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_ENABLE (1) -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_OVPICTRL_ENABLE << AW87XXX_PID_18_REG_PD_OVPICTRL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_PD_OVPICTRL_DEFAULT \ -+ (AW87XXX_PID_18_REG_PD_OVPICTRL_DEFAULT_VALUE << AW87XXX_PID_18_REG_PD_OVPICTRL_START_BIT) -+ -+/* default value of GTDRCPSS (0x0C) */ -+/* #define AW87XXX_PID_18_GTDRCPSS_DEFAULT (0x08) */ -+ -+/* MULTI (0x0D) detail */ -+/* REG_CP_FREQ bit 7:6 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_CP_FREQ_START_BIT (6) -+#define AW87XXX_PID_18_REG_CP_FREQ_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CP_FREQ_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_FREQ_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_FREQ_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_FREQ_1P8MHZ (0) -+#define AW87XXX_PID_18_REG_CP_FREQ_1P8MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_CP_FREQ_1P8MHZ << AW87XXX_PID_18_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_FREQ_1P6MHZ (1) -+#define AW87XXX_PID_18_REG_CP_FREQ_1P6MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_CP_FREQ_1P6MHZ << AW87XXX_PID_18_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_FREQ_1P4MHZ (2) -+#define AW87XXX_PID_18_REG_CP_FREQ_1P4MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_CP_FREQ_1P4MHZ << AW87XXX_PID_18_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_FREQ_2P1MHZ (3) -+#define AW87XXX_PID_18_REG_CP_FREQ_2P1MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_CP_FREQ_2P1MHZ << AW87XXX_PID_18_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_FREQ_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_CP_FREQ_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_FREQ_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_FREQ_START_BIT) -+ -+/* REG_EN_OT150 bit 5 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_OT150_START_BIT (5) -+#define AW87XXX_PID_18_REG_EN_OT150_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_OT150_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_OT150_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_OT150_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_OT150_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_OT150_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_OT150_DISABLE << AW87XXX_PID_18_REG_EN_OT150_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_OT150_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_OT150_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_OT150_ENABLE << AW87XXX_PID_18_REG_EN_OT150_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_OT150_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_OT150_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_OT150_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_OT150_START_BIT) -+ -+/* REG_EN_TEST bit 4 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_TEST_START_BIT (4) -+#define AW87XXX_PID_18_REG_EN_TEST_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_TEST_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_TEST_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_TEST_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_TEST_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_TEST_DISABLE << AW87XXX_PID_18_REG_EN_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_TEST_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_TEST_ENABLE << AW87XXX_PID_18_REG_EN_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_TEST_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_TEST_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_TEST_START_BIT) -+ -+/* REG_EN_CLASSD bit 3 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_CLASSD_START_BIT (3) -+#define AW87XXX_PID_18_REG_EN_CLASSD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_CLASSD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_CLASSD_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_CLASSD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_CLASSD_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_CLASSD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_CLASSD_DISABLE << AW87XXX_PID_18_REG_EN_CLASSD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_CLASSD_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_CLASSD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_CLASSD_ENABLE << AW87XXX_PID_18_REG_EN_CLASSD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_CLASSD_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_CLASSD_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_CLASSD_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_CLASSD_START_BIT) -+ -+/* REG_EN_DEFAULT bit 2 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_DEFAULT_START_BIT (2) -+#define AW87XXX_PID_18_REG_EN_DEFAULT_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_DEFAULT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_DEFAULT_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_DEFAULT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_DEFAULT_SELF_DEFINE_THE_SETTINGS (0) -+#define AW87XXX_PID_18_REG_EN_DEFAULT_SELF_DEFINE_THE_SETTINGS_VALUE \ -+ (AW87XXX_PID_18_REG_EN_DEFAULT_SELF_DEFINE_THE_SETTINGS << AW87XXX_PID_18_REG_EN_DEFAULT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_DEFAULT_USE_THE_DEFAULT_SETTING_IN_THE_SYSCTRL_BLOCK (1) -+#define AW87XXX_PID_18_REG_EN_DEFAULT_USE_THE_DEFAULT_SETTING_IN_THE_SYSCTRL_BLOCK_VALUE \ -+ (AW87XXX_PID_18_REG_EN_DEFAULT_USE_THE_DEFAULT_SETTING_IN_THE_SYSCTRL_BLOCK << AW87XXX_PID_18_REG_EN_DEFAULT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_DEFAULT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_DEFAULT_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_DEFAULT_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_DEFAULT_START_BIT) -+ -+/* REG_EN_ESD bit 1 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_ESD_START_BIT (1) -+#define AW87XXX_PID_18_REG_EN_ESD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_ESD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_ESD_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_ESD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_ESD_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_ESD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_ESD_DISABLE << AW87XXX_PID_18_REG_EN_ESD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_ESD_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_ESD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_ESD_ENABLE << AW87XXX_PID_18_REG_EN_ESD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_ESD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_ESD_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_ESD_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_ESD_START_BIT) -+ -+/* REG_EN_MT bit 0 (MULTI 0x0D) */ -+#define AW87XXX_PID_18_REG_EN_MT_START_BIT (0) -+#define AW87XXX_PID_18_REG_EN_MT_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_MT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_MT_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_MT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_MT_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_MT_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_MT_DISABLE << AW87XXX_PID_18_REG_EN_MT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_MT_ENBLAE (1) -+#define AW87XXX_PID_18_REG_EN_MT_ENBLAE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_MT_ENBLAE << AW87XXX_PID_18_REG_EN_MT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_MT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_MT_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_MT_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_MT_START_BIT) -+ -+/* default value of MULTI (0x0D) */ -+/* #define AW87XXX_PID_18_MULTI_DEFAULT (0x68) */ -+ -+/* DFT1 (0x61) detail */ -+/* REG_SET_R2 bit 7 (DFT1 0x61) */ -+#define AW87XXX_PID_18_REG_SET_R2_START_BIT (7) -+#define AW87XXX_PID_18_REG_SET_R2_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_SET_R2_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_SET_R2_BITS_LEN)-1) << AW87XXX_PID_18_REG_SET_R2_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_SET_R2_NOT_LIMIT_THE_HIGH_LEVEL_VTH (0) -+#define AW87XXX_PID_18_REG_SET_R2_NOT_LIMIT_THE_HIGH_LEVEL_VTH_VALUE \ -+ (AW87XXX_PID_18_REG_SET_R2_NOT_LIMIT_THE_HIGH_LEVEL_VTH << AW87XXX_PID_18_REG_SET_R2_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_R2_LIMIT_THE_HIGH_LEVEL_VTH (1) -+#define AW87XXX_PID_18_REG_SET_R2_LIMIT_THE_HIGH_LEVEL_VTH_VALUE \ -+ (AW87XXX_PID_18_REG_SET_R2_LIMIT_THE_HIGH_LEVEL_VTH << AW87XXX_PID_18_REG_SET_R2_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_R2_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_SET_R2_DEFAULT \ -+ (AW87XXX_PID_18_REG_SET_R2_DEFAULT_VALUE << AW87XXX_PID_18_REG_SET_R2_START_BIT) -+ -+/* REG_CP_ISOFT bit 6:5 (DFT1 0x61) */ -+#define AW87XXX_PID_18_REG_CP_ISOFT_START_BIT (5) -+#define AW87XXX_PID_18_REG_CP_ISOFT_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CP_ISOFT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_ISOFT_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P2A (0) -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P2A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_ISOFT_0P2A << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P3A (1) -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P3A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_ISOFT_0P3A << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P4A (2) -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P4A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_ISOFT_0P4A << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P5A (3) -+#define AW87XXX_PID_18_REG_CP_ISOFT_0P5A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_ISOFT_0P5A << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_ISOFT_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_CP_ISOFT_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_ISOFT_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_ISOFT_START_BIT) -+ -+/* REG_CP_IPEAK bit 4:2 (DFT1 0x61) */ -+#define AW87XXX_PID_18_REG_CP_IPEAK_START_BIT (2) -+#define AW87XXX_PID_18_REG_CP_IPEAK_BITS_LEN (3) -+#define AW87XXX_PID_18_REG_CP_IPEAK_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_IPEAK_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_2A (0) -+#define AW87XXX_PID_18_REG_CP_IPEAK_2A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_2A << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_2P5A (1) -+#define AW87XXX_PID_18_REG_CP_IPEAK_2P5A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_2P5A << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_3A (2) -+#define AW87XXX_PID_18_REG_CP_IPEAK_3A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_3A << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_3P5A (3) -+#define AW87XXX_PID_18_REG_CP_IPEAK_3P5A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_3P5A << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_4A (4) -+#define AW87XXX_PID_18_REG_CP_IPEAK_4A_VALUE \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_4A << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_IPEAK_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_CP_IPEAK_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_IPEAK_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_IPEAK_START_BIT) -+ -+/* REG_SET_OCDT bit 1:0 (DFT1 0x61) */ -+#define AW87XXX_PID_18_REG_SET_OCDT_START_BIT (0) -+#define AW87XXX_PID_18_REG_SET_OCDT_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_SET_OCDT_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_SET_OCDT_BITS_LEN)-1) << AW87XXX_PID_18_REG_SET_OCDT_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_SET_OCDT_4P1A (0) -+#define AW87XXX_PID_18_REG_SET_OCDT_4P1A_VALUE \ -+ (AW87XXX_PID_18_REG_SET_OCDT_4P1A << AW87XXX_PID_18_REG_SET_OCDT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_OCDT_4P5A (1) -+#define AW87XXX_PID_18_REG_SET_OCDT_4P5A_VALUE \ -+ (AW87XXX_PID_18_REG_SET_OCDT_4P5A << AW87XXX_PID_18_REG_SET_OCDT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_OCDT_4P9A (2) -+#define AW87XXX_PID_18_REG_SET_OCDT_4P9A_VALUE \ -+ (AW87XXX_PID_18_REG_SET_OCDT_4P9A << AW87XXX_PID_18_REG_SET_OCDT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_OCDT_5P3A (3) -+#define AW87XXX_PID_18_REG_SET_OCDT_5P3A_VALUE \ -+ (AW87XXX_PID_18_REG_SET_OCDT_5P3A << AW87XXX_PID_18_REG_SET_OCDT_START_BIT) -+ -+#define AW87XXX_PID_18_REG_SET_OCDT_DEFAULT_VALUE (0X2) -+#define AW87XXX_PID_18_REG_SET_OCDT_DEFAULT \ -+ (AW87XXX_PID_18_REG_SET_OCDT_DEFAULT_VALUE << AW87XXX_PID_18_REG_SET_OCDT_START_BIT) -+ -+/* default value of DFT1 (0x61) */ -+/* #define AW87XXX_PID_18_DFT1_DEFAULT (0xA6) */ -+ -+/* DFT2 (0x62) detail */ -+/* REG_CP_TEST bit 7 (DFT2 0x62) */ -+#define AW87XXX_PID_18_REG_CP_TEST_START_BIT (7) -+#define AW87XXX_PID_18_REG_CP_TEST_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_CP_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_TEST_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_TEST_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_TEST_DISABLE (0) -+#define AW87XXX_PID_18_REG_CP_TEST_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_CP_TEST_DISABLE << AW87XXX_PID_18_REG_CP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_TEST_ENABLE (1) -+#define AW87XXX_PID_18_REG_CP_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_CP_TEST_ENABLE << AW87XXX_PID_18_REG_CP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_CP_TEST_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_TEST_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_TEST_START_BIT) -+ -+/* REG_VFAGC bit 6:4 (DFT2 0x62) */ -+#define AW87XXX_PID_18_REG_VFAGC_START_BIT (4) -+#define AW87XXX_PID_18_REG_VFAGC_BITS_LEN (3) -+#define AW87XXX_PID_18_REG_VFAGC_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_VFAGC_BITS_LEN)-1) << AW87XXX_PID_18_REG_VFAGC_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P775VDDVREF_FAGC_VHYS0P7VDD (0) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P775VDDVREF_FAGC_VHYS0P7VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P775VDDVREF_FAGC_VHYS0P7VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P8VDDVREF_FAGC_VHYS0P725VDD (1) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P8VDDVREF_FAGC_VHYS0P725VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P8VDDVREF_FAGC_VHYS0P725VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P825VDDVREF_FAGC_VHYS0P75VDD (2) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P825VDDVREF_FAGC_VHYS0P75VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P825VDDVREF_FAGC_VHYS0P75VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P85VDDVREF_FAGC_VHYS0P775VDD (3) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P85VDDVREF_FAGC_VHYS0P775VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P85VDDVREF_FAGC_VHYS0P775VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P875VDDVREF_FAGC_VHYS0P8VDD (4) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P875VDDVREF_FAGC_VHYS0P8VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P875VDDVREF_FAGC_VHYS0P8VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P9VDDVREF_FAGC_VHYS0P825VDD (5) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P9VDDVREF_FAGC_VHYS0P825VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P9VDDVREF_FAGC_VHYS0P825VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P925VDDVREF_FAGC_VHYS0P85VDD (6) -+#define AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P925VDDVREF_FAGC_VHYS0P85VDD_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_VREF_FAGC0P925VDDVREF_FAGC_VHYS0P85VDD << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_001 (7) -+#define AW87XXX_PID_18_REG_VFAGC_001_VALUE \ -+ (AW87XXX_PID_18_REG_VFAGC_001 << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_VFAGC_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_VFAGC_DEFAULT \ -+ (AW87XXX_PID_18_REG_VFAGC_DEFAULT_VALUE << AW87XXX_PID_18_REG_VFAGC_START_BIT) -+ -+/* REG_CP_OVP_TEST bit 3:2 (DFT2 0x62) */ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT (2) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_CP_OVP_TEST_BITS_LEN)-1) << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_8P7V (0) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_8P7V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_TEST_8P7V << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P0V (1) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P0V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_TEST_9P0V << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P20V (2) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P20V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_TEST_9P20V << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P5V (3) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_9P5V_VALUE \ -+ (AW87XXX_PID_18_REG_CP_OVP_TEST_9P5V << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_CP_OVP_TEST_DEFAULT \ -+ (AW87XXX_PID_18_REG_CP_OVP_TEST_DEFAULT_VALUE << AW87XXX_PID_18_REG_CP_OVP_TEST_START_BIT) -+ -+/* REG_PAVG bit 1:0 (DFT2 0x62) */ -+#define AW87XXX_PID_18_REG_PAVG_START_BIT (0) -+#define AW87XXX_PID_18_REG_PAVG_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_PAVG_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_PAVG_BITS_LEN)-1) << AW87XXX_PID_18_REG_PAVG_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_PAVG_PO0P94 (0) -+#define AW87XXX_PID_18_REG_PAVG_PO0P94_VALUE \ -+ (AW87XXX_PID_18_REG_PAVG_PO0P94 << AW87XXX_PID_18_REG_PAVG_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PAVG_PO1 (1) -+#define AW87XXX_PID_18_REG_PAVG_PO1_VALUE \ -+ (AW87XXX_PID_18_REG_PAVG_PO1 << AW87XXX_PID_18_REG_PAVG_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PAVG_PO1P06 (2) -+#define AW87XXX_PID_18_REG_PAVG_PO1P06_VALUE \ -+ (AW87XXX_PID_18_REG_PAVG_PO1P06 << AW87XXX_PID_18_REG_PAVG_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PAVG_TURN_TO_10 (3) -+#define AW87XXX_PID_18_REG_PAVG_TURN_TO_10_VALUE \ -+ (AW87XXX_PID_18_REG_PAVG_TURN_TO_10 << AW87XXX_PID_18_REG_PAVG_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PAVG_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_PAVG_DEFAULT \ -+ (AW87XXX_PID_18_REG_PAVG_DEFAULT_VALUE << AW87XXX_PID_18_REG_PAVG_START_BIT) -+ -+/* default value of DFT2 (0x62) */ -+/* #define AW87XXX_PID_18_DFT2_DEFAULT (0x11) */ -+ -+/* DFT3 (0x63) detail */ -+/* REG_TDEAD_CP bit 7 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_TDEAD_CP_START_BIT (7) -+#define AW87XXX_PID_18_REG_TDEAD_CP_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_TDEAD_CP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_TDEAD_CP_BITS_LEN)-1) << AW87XXX_PID_18_REG_TDEAD_CP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT_SETTIG (0) -+#define AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT_SETTIG_VALUE \ -+ (AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT_SETTIG << AW87XXX_PID_18_REG_TDEAD_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TDEAD_CP_ENLARGE_THE_DEAD_TIME (1) -+#define AW87XXX_PID_18_REG_TDEAD_CP_ENLARGE_THE_DEAD_TIME_VALUE \ -+ (AW87XXX_PID_18_REG_TDEAD_CP_ENLARGE_THE_DEAD_TIME << AW87XXX_PID_18_REG_TDEAD_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT \ -+ (AW87XXX_PID_18_REG_TDEAD_CP_DEFAULT_VALUE << AW87XXX_PID_18_REG_TDEAD_CP_START_BIT) -+ -+/* REG_EN_EXPVDD bit 6 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_EN_EXPVDD_START_BIT (6) -+#define AW87XXX_PID_18_REG_EN_EXPVDD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_EXPVDD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_EXPVDD_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_EXPVDD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_EXPVDD_DISABLE (0) -+#define AW87XXX_PID_18_REG_EN_EXPVDD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_EXPVDD_DISABLE << AW87XXX_PID_18_REG_EN_EXPVDD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_EXPVDD_ENABLE (1) -+#define AW87XXX_PID_18_REG_EN_EXPVDD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_EN_EXPVDD_ENABLE << AW87XXX_PID_18_REG_EN_EXPVDD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_EXPVDD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EN_EXPVDD_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_EXPVDD_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_EXPVDD_START_BIT) -+ -+/* REG_TM_MADP bit 5 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_TM_MADP_START_BIT (5) -+#define AW87XXX_PID_18_REG_TM_MADP_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_TM_MADP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_TM_MADP_BITS_LEN)-1) << AW87XXX_PID_18_REG_TM_MADP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_TM_MADP_DISABLE (0) -+#define AW87XXX_PID_18_REG_TM_MADP_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_TM_MADP_DISABLE << AW87XXX_PID_18_REG_TM_MADP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TM_MADP_ENABLE (1) -+#define AW87XXX_PID_18_REG_TM_MADP_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_TM_MADP_ENABLE << AW87XXX_PID_18_REG_TM_MADP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TM_MADP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_TM_MADP_DEFAULT \ -+ (AW87XXX_PID_18_REG_TM_MADP_DEFAULT_VALUE << AW87XXX_PID_18_REG_TM_MADP_START_BIT) -+ -+/* REG_PD_UVLO bit 4 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_PD_UVLO_START_BIT (4) -+#define AW87XXX_PID_18_REG_PD_UVLO_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_PD_UVLO_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_PD_UVLO_BITS_LEN)-1) << AW87XXX_PID_18_REG_PD_UVLO_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_PD_UVLO_ENABLE (0) -+#define AW87XXX_PID_18_REG_PD_UVLO_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_UVLO_ENABLE << AW87XXX_PID_18_REG_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_UVLO_DISABLE (1) -+#define AW87XXX_PID_18_REG_PD_UVLO_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_UVLO_DISABLE << AW87XXX_PID_18_REG_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_UVLO_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_PD_UVLO_DEFAULT \ -+ (AW87XXX_PID_18_REG_PD_UVLO_DEFAULT_VALUE << AW87XXX_PID_18_REG_PD_UVLO_START_BIT) -+ -+/* REG_UVLO_VTH bit 3:2 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_UVLO_VTH_START_BIT (2) -+#define AW87XXX_PID_18_REG_UVLO_VTH_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_UVLO_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_UVLO_VTH_BITS_LEN)-1) << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P6V2P5V (0) -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P6V2P5V_VALUE \ -+ (AW87XXX_PID_18_REG_UVLO_VTH_2P6V2P5V << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P7V2P6V (1) -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P7V2P6V_VALUE \ -+ (AW87XXX_PID_18_REG_UVLO_VTH_2P7V2P6V << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P5V2P4V (2) -+#define AW87XXX_PID_18_REG_UVLO_VTH_2P5V2P4V_VALUE \ -+ (AW87XXX_PID_18_REG_UVLO_VTH_2P5V2P4V << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_UVLO_VTH_TURN_TO_00 (3) -+#define AW87XXX_PID_18_REG_UVLO_VTH_TURN_TO_00_VALUE \ -+ (AW87XXX_PID_18_REG_UVLO_VTH_TURN_TO_00 << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_18_REG_UVLO_VTH_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_UVLO_VTH_DEFAULT \ -+ (AW87XXX_PID_18_REG_UVLO_VTH_DEFAULT_VALUE << AW87XXX_PID_18_REG_UVLO_VTH_START_BIT) -+ -+/* REG_PD_CRS0 bit 1:0 (DFT3 0x63) */ -+#define AW87XXX_PID_18_REG_PD_CRS0_START_BIT (0) -+#define AW87XXX_PID_18_REG_PD_CRS0_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_PD_CRS0_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_PD_CRS0_BITS_LEN)-1) << AW87XXX_PID_18_REG_PD_CRS0_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_ENABLE (0) -+#define AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_ENABLE << AW87XXX_PID_18_REG_PD_CRS0_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_CRS0_BOTH_AGC2_AND_AGC3_CROSS_ZERO_ENABLE_AGC1_CROSS_ZERO_DISABLE (1) -+#define AW87XXX_PID_18_REG_PD_CRS0_BOTH_AGC2_AND_AGC3_CROSS_ZERO_ENABLE_AGC1_CROSS_ZERO_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_CRS0_BOTH_AGC2_AND_AGC3_CROSS_ZERO_ENABLE_AGC1_CROSS_ZERO_DISABLE << AW87XXX_PID_18_REG_PD_CRS0_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_CRS0_ONLY_AGC3_CROSS_ZERO_ENABLE_AGC1_AND_AGC2_CROSS_ZERO_DISABLE (2) -+#define AW87XXX_PID_18_REG_PD_CRS0_ONLY_AGC3_CROSS_ZERO_ENABLE_AGC1_AND_AGC2_CROSS_ZERO_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_CRS0_ONLY_AGC3_CROSS_ZERO_ENABLE_AGC1_AND_AGC2_CROSS_ZERO_DISABLE << AW87XXX_PID_18_REG_PD_CRS0_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_DISABLE (3) -+#define AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_PD_CRS0_ALL_OF_AGC1_AGC2_AND_AGC3_CROSS_ZERO_DISABLE << AW87XXX_PID_18_REG_PD_CRS0_START_BIT) -+ -+#define AW87XXX_PID_18_REG_PD_CRS0_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_PD_CRS0_DEFAULT \ -+ (AW87XXX_PID_18_REG_PD_CRS0_DEFAULT_VALUE << AW87XXX_PID_18_REG_PD_CRS0_START_BIT) -+ -+/* default value of DFT3 (0x63) */ -+/* #define AW87XXX_PID_18_DFT3_DEFAULT (0x00) */ -+ -+/* DFT4 (0x64) detail */ -+/* REG_DEGLITCH_CP bit 7:6 (DFT4 0x64) */ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT (6) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_DEGLITCH_CP_BITS_LEN)-1) << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_3NS (0) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_3NS_VALUE \ -+ (AW87XXX_PID_18_REG_DEGLITCH_CP_3NS << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_5NS (1) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_5NS_VALUE \ -+ (AW87XXX_PID_18_REG_DEGLITCH_CP_5NS << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_1NS (2) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_1NS_VALUE \ -+ (AW87XXX_PID_18_REG_DEGLITCH_CP_1NS << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_0NS (3) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_0NS_VALUE \ -+ (AW87XXX_PID_18_REG_DEGLITCH_CP_0NS << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_DEGLITCH_CP_DEFAULT \ -+ (AW87XXX_PID_18_REG_DEGLITCH_CP_DEFAULT_VALUE << AW87XXX_PID_18_REG_DEGLITCH_CP_START_BIT) -+ -+/* REG_EDGE_CP bit 5:4 (DFT4 0x64) */ -+#define AW87XXX_PID_18_REG_EDGE_CP_START_BIT (4) -+#define AW87XXX_PID_18_REG_EDGE_CP_BITS_LEN (2) -+#define AW87XXX_PID_18_REG_EDGE_CP_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EDGE_CP_BITS_LEN)-1) << AW87XXX_PID_18_REG_EDGE_CP_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EDGE_CP_DEFAULT_14P8NS (0) -+#define AW87XXX_PID_18_REG_EDGE_CP_DEFAULT_14P8NS_VALUE \ -+ (AW87XXX_PID_18_REG_EDGE_CP_DEFAULT_14P8NS << AW87XXX_PID_18_REG_EDGE_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EDGE_CP_MODERATE_13P5NS (1) -+#define AW87XXX_PID_18_REG_EDGE_CP_MODERATE_13P5NS_VALUE \ -+ (AW87XXX_PID_18_REG_EDGE_CP_MODERATE_13P5NS << AW87XXX_PID_18_REG_EDGE_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EDGE_CP_SLOWEST_19P3NS (2) -+#define AW87XXX_PID_18_REG_EDGE_CP_SLOWEST_19P3NS_VALUE \ -+ (AW87XXX_PID_18_REG_EDGE_CP_SLOWEST_19P3NS << AW87XXX_PID_18_REG_EDGE_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EDGE_CP_FASTEST_4P6NS00 (3) -+#define AW87XXX_PID_18_REG_EDGE_CP_FASTEST_4P6NS00_VALUE \ -+ (AW87XXX_PID_18_REG_EDGE_CP_FASTEST_4P6NS00 << AW87XXX_PID_18_REG_EDGE_CP_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EDGE_CP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_EDGE_CP_DEFAULT \ -+ (AW87XXX_PID_18_REG_EDGE_CP_DEFAULT_VALUE << AW87XXX_PID_18_REG_EDGE_CP_START_BIT) -+ -+/* REG_TESTSEL bit 3:0 (DFT4 0x64) */ -+#define AW87XXX_PID_18_REG_TESTSEL_START_BIT (0) -+#define AW87XXX_PID_18_REG_TESTSEL_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_TESTSEL_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_TESTSEL_BITS_LEN)-1) << AW87XXX_PID_18_REG_TESTSEL_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_VBG_FROM_BIAS (0) -+#define AW87XXX_PID_18_REG_TESTSEL_VBG_FROM_BIAS_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_VBG_FROM_BIAS << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_VCOM1_FROM_PREAMP (1) -+#define AW87XXX_PID_18_REG_TESTSEL_VCOM1_FROM_PREAMP_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_VCOM1_FROM_PREAMP << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_VREF_AGC_FROM_RAMP (2) -+#define AW87XXX_PID_18_REG_TESTSEL_VREF_AGC_FROM_RAMP_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_VREF_AGC_FROM_RAMP << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_VREF_ADP_FROM_THGEN (3) -+#define AW87XXX_PID_18_REG_TESTSEL_VREF_ADP_FROM_THGEN_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_VREF_ADP_FROM_THGEN << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_OC (4) -+#define AW87XXX_PID_18_REG_TESTSEL_OC_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_OC << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_OT160 (5) -+#define AW87XXX_PID_18_REG_TESTSEL_OT160_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_OT160 << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_UVLO (6) -+#define AW87XXX_PID_18_REG_TESTSEL_UVLO_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_UVLO << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_GT_P_TEST_FROM_GATEDRIVER (7) -+#define AW87XXX_PID_18_REG_TESTSEL_GT_P_TEST_FROM_GATEDRIVER_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_GT_P_TEST_FROM_GATEDRIVER << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_GT_N_TEST_FROM_GATEDRIVER (8) -+#define AW87XXX_PID_18_REG_TESTSEL_GT_N_TEST_FROM_GATEDRIVER_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_GT_N_TEST_FROM_GATEDRIVER << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_GT1_P_TEST_FROM_GATEDRIVER (9) -+#define AW87XXX_PID_18_REG_TESTSEL_GT1_P_TEST_FROM_GATEDRIVER_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_GT1_P_TEST_FROM_GATEDRIVER << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_GT1_N_TEST_FROM_GATEDRIVER (10) -+#define AW87XXX_PID_18_REG_TESTSEL_GT1_N_TEST_FROM_GATEDRIVER_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_GT1_N_TEST_FROM_GATEDRIVER << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_OVP0_TEST_FROM_OVP (11) -+#define AW87XXX_PID_18_REG_TESTSEL_OVP0_TEST_FROM_OVP_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_OVP0_TEST_FROM_OVP << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_OVP1_TEST_FROM_OVP (12) -+#define AW87XXX_PID_18_REG_TESTSEL_OVP1_TEST_FROM_OVP_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_OVP1_TEST_FROM_OVP << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_PORN_TEST_FROM_PORN (13) -+#define AW87XXX_PID_18_REG_TESTSEL_PORN_TEST_FROM_PORN_VALUE \ -+ (AW87XXX_PID_18_REG_TESTSEL_PORN_TEST_FROM_PORN << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+#define AW87XXX_PID_18_REG_TESTSEL_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_TESTSEL_DEFAULT \ -+ (AW87XXX_PID_18_REG_TESTSEL_DEFAULT_VALUE << AW87XXX_PID_18_REG_TESTSEL_START_BIT) -+ -+/* default value of DFT4 (0x64) */ -+/* #define AW87XXX_PID_18_DFT4_DEFAULT (0x00) */ -+ -+/* DFT5 (0x65) detail */ -+/* FCLK_CS bit 5 (DFT5 0x65) */ -+#define AW87XXX_PID_18_FCLK_CS_START_BIT (5) -+#define AW87XXX_PID_18_FCLK_CS_BITS_LEN (1) -+#define AW87XXX_PID_18_FCLK_CS_MASK \ -+ (~(((1<<AW87XXX_PID_18_FCLK_CS_BITS_LEN)-1) << AW87XXX_PID_18_FCLK_CS_START_BIT)) -+ -+#define AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNALCLK_PA_FROM_THE_ANALOG_PART (0) -+#define AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNALCLK_PA_FROM_THE_ANALOG_PART_VALUE \ -+ (AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNALCLK_PA_FROM_THE_ANALOG_PART << AW87XXX_PID_18_FCLK_CS_START_BIT) -+ -+#define AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNAL_GENERATED_BY_DIGITAL_PART_THEN_WRITE_0XA5_TO_THE_0X66_REGISTORGENERATE_A_PULSE_AFTER_EACH_WRITING (1) -+#define AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNAL_GENERATED_BY_DIGITAL_PART_THEN_WRITE_0XA5_TO_THE_0X66_REGISTORGENERATE_A_PULSE_AFTER_EACH_WRITING_VALUE \ -+ (AW87XXX_PID_18_FCLK_CS_CHOOSE_THE_CLOCK_SIGNAL_GENERATED_BY_DIGITAL_PART_THEN_WRITE_0XA5_TO_THE_0X66_REGISTORGENERATE_A_PULSE_AFTER_EACH_WRITING << AW87XXX_PID_18_FCLK_CS_START_BIT) -+ -+#define AW87XXX_PID_18_FCLK_CS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_FCLK_CS_DEFAULT \ -+ (AW87XXX_PID_18_FCLK_CS_DEFAULT_VALUE << AW87XXX_PID_18_FCLK_CS_START_BIT) -+ -+/* REG_OT_TEST bit 4 (DFT5 0x65) */ -+#define AW87XXX_PID_18_REG_OT_TEST_START_BIT (4) -+#define AW87XXX_PID_18_REG_OT_TEST_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_OT_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_OT_TEST_BITS_LEN)-1) << AW87XXX_PID_18_REG_OT_TEST_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_OT_TEST_DISABLE_NOT_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK (0) -+#define AW87XXX_PID_18_REG_OT_TEST_DISABLE_NOT_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK_VALUE \ -+ (AW87XXX_PID_18_REG_OT_TEST_DISABLE_NOT_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK << AW87XXX_PID_18_REG_OT_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OT_TEST_ENABLE_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK (1) -+#define AW87XXX_PID_18_REG_OT_TEST_ENABLE_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK_VALUE \ -+ (AW87XXX_PID_18_REG_OT_TEST_ENABLE_TO_TRANSFER_THE_OTN_TO_THE_TEST_BLOCK << AW87XXX_PID_18_REG_OT_TEST_START_BIT) -+ -+#define AW87XXX_PID_18_REG_OT_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_OT_TEST_DEFAULT \ -+ (AW87XXX_PID_18_REG_OT_TEST_DEFAULT_VALUE << AW87XXX_PID_18_REG_OT_TEST_START_BIT) -+ -+/* REG_EN_OC bit 3 (DFT5 0x65) */ -+#define AW87XXX_PID_18_REG_EN_OC_START_BIT (3) -+#define AW87XXX_PID_18_REG_EN_OC_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_EN_OC_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_EN_OC_BITS_LEN)-1) << AW87XXX_PID_18_REG_EN_OC_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_EN_OC_TURN_OFF_THE_OC_BLOCK_FORCE_0C0 (0) -+#define AW87XXX_PID_18_REG_EN_OC_TURN_OFF_THE_OC_BLOCK_FORCE_0C0_VALUE \ -+ (AW87XXX_PID_18_REG_EN_OC_TURN_OFF_THE_OC_BLOCK_FORCE_0C0 << AW87XXX_PID_18_REG_EN_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_OC_TURN_ON_THE_OC_BLOCK_FUNCTION (1) -+#define AW87XXX_PID_18_REG_EN_OC_TURN_ON_THE_OC_BLOCK_FUNCTION_VALUE \ -+ (AW87XXX_PID_18_REG_EN_OC_TURN_ON_THE_OC_BLOCK_FUNCTION << AW87XXX_PID_18_REG_EN_OC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_EN_OC_DEFAULT_VALUE (1) -+#define AW87XXX_PID_18_REG_EN_OC_DEFAULT \ -+ (AW87XXX_PID_18_REG_EN_OC_DEFAULT_VALUE << AW87XXX_PID_18_REG_EN_OC_START_BIT) -+ -+/* EN_RD bit 2 (DFT5 0x65) */ -+#define AW87XXX_PID_18_EN_RD_START_BIT (2) -+#define AW87XXX_PID_18_EN_RD_BITS_LEN (1) -+#define AW87XXX_PID_18_EN_RD_MASK \ -+ (~(((1<<AW87XXX_PID_18_EN_RD_BITS_LEN)-1) << AW87XXX_PID_18_EN_RD_START_BIT)) -+ -+#define AW87XXX_PID_18_EN_RD_DISABLE (0) -+#define AW87XXX_PID_18_EN_RD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_EN_RD_DISABLE << AW87XXX_PID_18_EN_RD_START_BIT) -+ -+#define AW87XXX_PID_18_EN_RD_ENABLE (1) -+#define AW87XXX_PID_18_EN_RD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_EN_RD_ENABLE << AW87XXX_PID_18_EN_RD_START_BIT) -+ -+#define AW87XXX_PID_18_EN_RD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_EN_RD_DEFAULT \ -+ (AW87XXX_PID_18_EN_RD_DEFAULT_VALUE << AW87XXX_PID_18_EN_RD_START_BIT) -+ -+/* REG_FAST_VFAGC bit 1 (DFT5 0x65) */ -+#define AW87XXX_PID_18_REG_FAST_VFAGC_START_BIT (1) -+#define AW87XXX_PID_18_REG_FAST_VFAGC_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_FAST_VFAGC_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_FAST_VFAGC_BITS_LEN)-1) << AW87XXX_PID_18_REG_FAST_VFAGC_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_FAST_VFAGC_DISABLE (0) -+#define AW87XXX_PID_18_REG_FAST_VFAGC_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_FAST_VFAGC_DISABLE << AW87XXX_PID_18_REG_FAST_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FAST_VFAGC_ENABLE (1) -+#define AW87XXX_PID_18_REG_FAST_VFAGC_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_FAST_VFAGC_ENABLE << AW87XXX_PID_18_REG_FAST_VFAGC_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FAST_VFAGC_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_FAST_VFAGC_DEFAULT \ -+ (AW87XXX_PID_18_REG_FAST_VFAGC_DEFAULT_VALUE << AW87XXX_PID_18_REG_FAST_VFAGC_START_BIT) -+ -+/* REG_FAST_HVDD bit 0 (DFT5 0x65) */ -+#define AW87XXX_PID_18_REG_FAST_HVDD_START_BIT (0) -+#define AW87XXX_PID_18_REG_FAST_HVDD_BITS_LEN (1) -+#define AW87XXX_PID_18_REG_FAST_HVDD_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_FAST_HVDD_BITS_LEN)-1) << AW87XXX_PID_18_REG_FAST_HVDD_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_FAST_HVDD_DISABLE (0) -+#define AW87XXX_PID_18_REG_FAST_HVDD_DISABLE_VALUE \ -+ (AW87XXX_PID_18_REG_FAST_HVDD_DISABLE << AW87XXX_PID_18_REG_FAST_HVDD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FAST_HVDD_ENABLE (1) -+#define AW87XXX_PID_18_REG_FAST_HVDD_ENABLE_VALUE \ -+ (AW87XXX_PID_18_REG_FAST_HVDD_ENABLE << AW87XXX_PID_18_REG_FAST_HVDD_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FAST_HVDD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_REG_FAST_HVDD_DEFAULT \ -+ (AW87XXX_PID_18_REG_FAST_HVDD_DEFAULT_VALUE << AW87XXX_PID_18_REG_FAST_HVDD_START_BIT) -+ -+/* default value of DFT5 (0x65) */ -+/* #define AW87XXX_PID_18_DFT5_DEFAULT (0x08) */ -+ -+/* DFT6 (0x66) detail */ -+/* Q_SHDN bit 7:4 (DFT6 0x66) */ -+#define AW87XXX_PID_18_Q_SHDN_START_BIT (4) -+#define AW87XXX_PID_18_Q_SHDN_BITS_LEN (4) -+#define AW87XXX_PID_18_Q_SHDN_MASK \ -+ (~(((1<<AW87XXX_PID_18_Q_SHDN_BITS_LEN)-1) << AW87XXX_PID_18_Q_SHDN_START_BIT)) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE1 (0) -+#define AW87XXX_PID_18_Q_SHDN_MODE1_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE1 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE2 (1) -+#define AW87XXX_PID_18_Q_SHDN_MODE2_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE2 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE3 (2) -+#define AW87XXX_PID_18_Q_SHDN_MODE3_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE3 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE4 (3) -+#define AW87XXX_PID_18_Q_SHDN_MODE4_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE4 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE5 (4) -+#define AW87XXX_PID_18_Q_SHDN_MODE5_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE5 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE6 (5) -+#define AW87XXX_PID_18_Q_SHDN_MODE6_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE6 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE7 (6) -+#define AW87XXX_PID_18_Q_SHDN_MODE7_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE7 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE8 (7) -+#define AW87XXX_PID_18_Q_SHDN_MODE8_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE8 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE9 (8) -+#define AW87XXX_PID_18_Q_SHDN_MODE9_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE9 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_MODE10 (9) -+#define AW87XXX_PID_18_Q_SHDN_MODE10_VALUE \ -+ (AW87XXX_PID_18_Q_SHDN_MODE10 << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+#define AW87XXX_PID_18_Q_SHDN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_18_Q_SHDN_DEFAULT \ -+ (AW87XXX_PID_18_Q_SHDN_DEFAULT_VALUE << AW87XXX_PID_18_Q_SHDN_START_BIT) -+ -+/* REG_FSS bit 3:0 (DFT6 0x66) */ -+#define AW87XXX_PID_18_REG_FSS_START_BIT (0) -+#define AW87XXX_PID_18_REG_FSS_BITS_LEN (4) -+#define AW87XXX_PID_18_REG_FSS_MASK \ -+ (~(((1<<AW87XXX_PID_18_REG_FSS_BITS_LEN)-1) << AW87XXX_PID_18_REG_FSS_START_BIT)) -+ -+#define AW87XXX_PID_18_REG_FSS_1P408MHZ (0) -+#define AW87XXX_PID_18_REG_FSS_1P408MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P408MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P432MHZ (1) -+#define AW87XXX_PID_18_REG_FSS_1P432MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P432MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P456MHZ (3) -+#define AW87XXX_PID_18_REG_FSS_1P456MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P456MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P48MHZ (2) -+#define AW87XXX_PID_18_REG_FSS_1P48MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P48MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P504MHZ (6) -+#define AW87XXX_PID_18_REG_FSS_1P504MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P504MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P528MHZ (7) -+#define AW87XXX_PID_18_REG_FSS_1P528MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P528MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P552MHZ (5) -+#define AW87XXX_PID_18_REG_FSS_1P552MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P552MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P576MHZ (4) -+#define AW87XXX_PID_18_REG_FSS_1P576MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P576MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P6MHZ (12) -+#define AW87XXX_PID_18_REG_FSS_1P6MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P6MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P627MHZ (13) -+#define AW87XXX_PID_18_REG_FSS_1P627MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P627MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P655MHZ (15) -+#define AW87XXX_PID_18_REG_FSS_1P655MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P655MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P682MHZ (14) -+#define AW87XXX_PID_18_REG_FSS_1P682MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P682MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P71MHZ (10) -+#define AW87XXX_PID_18_REG_FSS_1P71MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P71MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P737MHZ (11) -+#define AW87XXX_PID_18_REG_FSS_1P737MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P737MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P765MHZ (9) -+#define AW87XXX_PID_18_REG_FSS_1P765MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P765MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_1P792MHZ (8) -+#define AW87XXX_PID_18_REG_FSS_1P792MHZ_VALUE \ -+ (AW87XXX_PID_18_REG_FSS_1P792MHZ << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+#define AW87XXX_PID_18_REG_FSS_DEFAULT_VALUE (0x0C) -+#define AW87XXX_PID_18_REG_FSS_DEFAULT \ -+ (AW87XXX_PID_18_REG_FSS_DEFAULT_VALUE << AW87XXX_PID_18_REG_FSS_START_BIT) -+ -+/* default value of DFT6 (0x66) */ -+/* #define AW87XXX_PID_18_DFT6_DEFAULT (0x0C) */ -+ -+/* detail information of registers end */ -+ -+#endif /* #ifndef __AW87XXX_PID_18_REG_H__ */ -\ No newline at end of file -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h -new file mode 100644 -index 000000000..3391673f9 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h -@@ -0,0 +1,67 @@ -+#ifndef __AW87XXX_PID_39_REG_H__ -+#define __AW87XXX_PID_39_REG_H__ -+ -+#define AW87XXX_PID_39_REG_CHIPID (0x00) -+#define AW87XXX_PID_39_REG_SYSCTRL (0x01) -+#define AW87XXX_PID_39_REG_MODECTRL (0x02) -+#define AW87XXX_PID_39_REG_CPOVP (0x03) -+#define AW87XXX_PID_39_REG_CPP (0x04) -+#define AW87XXX_PID_39_REG_GAIN (0x05) -+#define AW87XXX_PID_39_REG_AGC3_PO (0x06) -+#define AW87XXX_PID_39_REG_AGC3 (0x07) -+#define AW87XXX_PID_39_REG_AGC2_PO (0x08) -+#define AW87XXX_PID_39_REG_AGC2 (0x09) -+#define AW87XXX_PID_39_REG_AGC1 (0x0A) -+#define AW87XXX_PID_39_REG_DFT1 (0x62) -+#define AW87XXX_PID_39_REG_DFT2 (0x63) -+#define AW87XXX_PID_39_REG_ENCRY (0x64) -+ -+#define AW87XXX_PID_39_MODECTRL_DEFAULT (0xa0) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_39_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_39_REG_MAX (0x65) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_39_reg_access[AW87XXX_PID_39_REG_MAX] = { -+ [AW87XXX_PID_39_REG_CHIPID] = (REG_RD_ACCESS), -+ [AW87XXX_PID_39_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_MODECTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_CPOVP] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_CPP] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_GAIN] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_AGC3_PO] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_AGC3] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_AGC2_PO] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_AGC2] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_AGC1] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_39_REG_DFT1] = (REG_RD_ACCESS), -+ [AW87XXX_PID_39_REG_DFT2] = (REG_RD_ACCESS), -+ [AW87XXX_PID_39_REG_ENCRY] = (REG_RD_ACCESS), -+}; -+ -+/* RCV_MODE bit 3 (MODECTRL 0x02) */ -+#define AW87XXX_PID_39_REC_MODE_START_BIT (3) -+#define AW87XXX_PID_39_REC_MODE_BITS_LEN (1) -+#define AW87XXX_PID_39_REC_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_39_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_39_REC_MODE_START_BIT)) -+ -+#define AW87XXX_PID_39_REC_MODE_DISABLE (0) -+#define AW87XXX_PID_39_REC_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_39_REC_MODE_DISABLE << AW87XXX_PID_39_REC_MODE_START_BIT) -+ -+#define AW87XXX_PID_39_REC_MODE_ENABLE (1) -+#define AW87XXX_PID_39_REC_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_39_REC_MODE_ENABLE << AW87XXX_PID_39_REC_MODE_START_BIT) -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h -new file mode 100644 -index 000000000..46a88aea5 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h -@@ -0,0 +1,93 @@ -+/* -+ * @Descripttion: Header file of AW87XXX_PID_59_3X9_REG -+ * @version: V1.33 -+ * @Author: zhaozhongbo -+ * @Date: 2021-03-10 -+ * @LastEditors: Please set LastEditors -+ * @LastEditTime: 2021-03-10 -+ */ -+#ifndef __AW87XXX_PID_59_3X9_REG_H__ -+#define __AW87XXX_PID_59_3X9_REG_H__ -+ -+#define AW87XXX_PID_59_3X9_REG_CHIPID (0x00) -+#define AW87XXX_PID_59_3X9_REG_SYSCTRL (0x01) -+#define AW87XXX_PID_59_3X9_REG_MDCRTL (0x02) -+#define AW87XXX_PID_59_3X9_REG_CPOVP (0x03) -+#define AW87XXX_PID_59_3X9_REG_CPP (0x04) -+#define AW87XXX_PID_59_3X9_REG_PAG (0x05) -+#define AW87XXX_PID_59_3X9_REG_AGC3PO (0x06) -+#define AW87XXX_PID_59_3X9_REG_AGC3PA (0x07) -+#define AW87XXX_PID_59_3X9_REG_AGC2PO (0x08) -+#define AW87XXX_PID_59_3X9_REG_AGC2PA (0x09) -+#define AW87XXX_PID_59_3X9_REG_AGC1PA (0x0A) -+#define AW87XXX_PID_59_3X9_REG_SYSST (0x59) -+#define AW87XXX_PID_59_3X9_REG_SYSINT (0x60) -+#define AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL (0x61) -+#define AW87XXX_PID_59_3X9_REG_DFT_MDCTRL (0x62) -+#define AW87XXX_PID_59_3X9_REG_DFT_CPOVP2 (0x63) -+#define AW87XXX_PID_59_3X9_REG_DFT_AGCPA (0x64) -+#define AW87XXX_PID_59_3X9_REG_DFT_POFR (0x65) -+#define AW87XXX_PID_59_3X9_REG_DFT_OC (0x66) -+#define AW87XXX_PID_59_3X9_REG_DFT_OTA (0x67) -+#define AW87XXX_PID_59_3X9_REG_DFT_REF (0x68) -+#define AW87XXX_PID_59_3X9_REG_DFT_LDO (0x69) -+#define AW87XXX_PID_59_3X9_REG_ENCR (0x70) -+ -+#define AW87XXX_PID_59_3X9_ENCR_DEFAULT (0x00) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_59_3x9_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_59_3X9_REG_MAX (0x71) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_59_3x9_reg_access[AW87XXX_PID_59_3X9_REG_MAX] = { -+ [AW87XXX_PID_59_3X9_REG_CHIPID] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_MDCRTL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_CPOVP] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_CPP] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_PAG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_AGC3PO] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_AGC3PA] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_AGC2PO] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_AGC2PA] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_AGC1PA] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_SYSST] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_SYSINT] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_MDCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_CPOVP2] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_AGCPA] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_POFR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_OC] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_OTA] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_REF] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_DFT_LDO] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_3X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+/* SPK_MODE bit 2 (MDCRTL 0x02) */ -+#define AW87XXX_PID_59_3X9_SPK_MODE_START_BIT (2) -+#define AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN (1) -+#define AW87XXX_PID_59_3X9_SPK_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_59_3X9_SPK_MODE_BITS_LEN)-1) << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT)) -+ -+#define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE (0) -+#define AW87XXX_PID_59_3X9_SPK_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_59_3X9_SPK_MODE_DISABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT) -+ -+#define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE (1) -+#define AW87XXX_PID_59_3X9_SPK_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_59_3X9_SPK_MODE_ENABLE << AW87XXX_PID_59_3X9_SPK_MODE_START_BIT) -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h -new file mode 100644 -index 000000000..819761b5c ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h -@@ -0,0 +1,94 @@ -+/* -+ * @Descripttion: Header file of AW87XXX_PID_59_5X9_REG -+ * @version: V1.33 -+ * @Author: zhaozhongbo -+ * @Date: 2021-03-10 -+ * @LastEditors: Please set LastEditors -+ * @LastEditTime: 2021-03-10 -+ */ -+#ifndef __AW87XXX_PID_59_5X9_REG_H__ -+#define __AW87XXX_PID_59_5X9_REG_H__ -+ -+ -+#define AW87XXX_PID_59_5X9_REG_CHIPID (0x00) -+#define AW87XXX_PID_59_5X9_REG_SYSCTRL (0x01) -+#define AW87XXX_PID_59_5X9_REG_BATSAFE (0x02) -+#define AW87XXX_PID_59_5X9_REG_BSTOVR (0x03) -+#define AW87XXX_PID_59_5X9_REG_BSTVPR (0x04) -+#define AW87XXX_PID_59_5X9_REG_PAGR (0x05) -+#define AW87XXX_PID_59_5X9_REG_PAGC3OPR (0x06) -+#define AW87XXX_PID_59_5X9_REG_PAGC3PR (0x07) -+#define AW87XXX_PID_59_5X9_REG_PAGC2OPR (0x08) -+#define AW87XXX_PID_59_5X9_REG_PAGC2PR (0x09) -+#define AW87XXX_PID_59_5X9_REG_PAGC1PR (0x0A) -+#define AW87XXX_PID_59_5X9_REG_SYSST (0x58) -+#define AW87XXX_PID_59_5X9_REG_SYSINT (0x59) -+#define AW87XXX_PID_59_5X9_REG_CPCR (0x60) -+#define AW87XXX_PID_59_5X9_REG_DFT1R (0x61) -+#define AW87XXX_PID_59_5X9_REG_DFT2R (0x62) -+#define AW87XXX_PID_59_5X9_REG_DFT3R (0x63) -+#define AW87XXX_PID_59_5X9_REG_DFT4R (0x64) -+#define AW87XXX_PID_59_5X9_REG_DFT5R (0x65) -+#define AW87XXX_PID_59_5X9_REG_DFT6R (0x66) -+#define AW87XXX_PID_59_5X9_REG_DFT7R (0x67) -+#define AW87XXX_PID_59_5X9_REG_DFT8R (0x68) -+#define AW87XXX_PID_59_5X9_REG_ENCR (0x69) -+ -+#define AW87XXX_PID_59_5X9_ENCRY_DEFAULT (0x00) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_59_5x9_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_59_5X9_REG_MAX (0x70) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_59_5x9_reg_access[AW87XXX_PID_59_5X9_REG_MAX] = { -+ [AW87XXX_PID_59_5X9_REG_CHIPID] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_SYSCTRL] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_BATSAFE] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_BSTOVR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_BSTVPR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGC3OPR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGC3PR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGC2OPR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGC2PR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_PAGC1PR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_SYSST] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_SYSINT] = (REG_RD_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_CPCR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT1R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT2R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT3R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT4R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT5R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT6R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT7R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_DFT8R] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_59_5X9_REG_ENCR] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+/* RCV_MODE bit 3 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_59_5X9_REC_MODE_START_BIT (3) -+#define AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN (1) -+#define AW87XXX_PID_59_5X9_REC_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_59_5X9_REC_MODE_BITS_LEN)-1) << AW87XXX_PID_59_5X9_REC_MODE_START_BIT)) -+ -+#define AW87XXX_PID_59_5X9_REC_MODE_DISABLE (0) -+#define AW87XXX_PID_59_5X9_REC_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_59_5X9_REC_MODE_DISABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT) -+ -+#define AW87XXX_PID_59_5X9_REC_MODE_ENABLE (1) -+#define AW87XXX_PID_59_5X9_REC_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_59_5X9_REC_MODE_ENABLE << AW87XXX_PID_59_5X9_REC_MODE_START_BIT) -+ -+#endif -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h -new file mode 100644 -index 000000000..e56922a3c ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h -@@ -0,0 +1,4124 @@ -+/* -+ * @Descripttion: Header file of AW87XXX_PID_5A_REG -+ * @version: V1.4 -+ * @Author: zhaozhongbo -+ * @Date: 2021-03-10 -+ * @LastEditors: Please set LastEditors -+ * @LastEditTime: 2021-03-10 -+ */ -+#ifndef __AW87XXX_PID_5A_REG_H__ -+#define __AW87XXX_PID_5A_REG_H__ -+ -+/* registers list */ -+#define AW87XXX_PID_5A_REG_ID_REG (0x00) -+#define AW87XXX_PID_5A_REG_SYSCTRL_REG (0x01) -+#define AW87XXX_PID_5A_REG_BATSAFE_REG (0x02) -+#define AW87XXX_PID_5A_REG_BSTOVR_REG (0x03) -+#define AW87XXX_PID_5A_REG_BSTCPR1_REG (0x04) -+#define AW87XXX_PID_5A_REG_BSTCPR2_REG (0x05) -+#define AW87XXX_PID_5A_REG_PAGR_REG (0x06) -+#define AW87XXX_PID_5A_REG_PAGC3OPR_REG (0x07) -+#define AW87XXX_PID_5A_REG_PAGC3PR_REG (0x08) -+#define AW87XXX_PID_5A_REG_PAGC2OPR_REG (0x09) -+#define AW87XXX_PID_5A_REG_PAGC2PR_REG (0x0A) -+#define AW87XXX_PID_5A_REG_PAGC1PR_REG (0x0B) -+#define AW87XXX_PID_5A_REG_ADP_MODE_REG (0x0C) -+#define AW87XXX_PID_5A_REG_ADPBST_TIME1_REG (0x0D) -+#define AW87XXX_PID_5A_REG_ADPBST_TIME2_REG (0x0E) -+#define AW87XXX_PID_5A_REG_ADPBST_VTH_REG (0x0F) -+#define AW87XXX_PID_5A_REG_BOOST_PAR_REG (0x10) -+#define AW87XXX_PID_5A_REG_BOOST_VOUT_DET_REG (0x57) -+#define AW87XXX_PID_5A_REG_SYSST_REG (0x58) -+#define AW87XXX_PID_5A_REG_SYSINT_REG (0x59) -+#define AW87XXX_PID_5A_REG_DFT1R_REG (0x60) -+#define AW87XXX_PID_5A_REG_DFT2R_REG (0x61) -+#define AW87XXX_PID_5A_REG_DFT3R_REG (0x62) -+#define AW87XXX_PID_5A_REG_DFT4R_REG (0x63) -+#define AW87XXX_PID_5A_REG_DFT5R_REG (0x64) -+#define AW87XXX_PID_5A_REG_DFT6R_REG (0x65) -+#define AW87XXX_PID_5A_REG_DFT7R_REG (0x66) -+#define AW87XXX_PID_5A_REG_DFT8R_REG (0x67) -+#define AW87XXX_PID_5A_REG_DFT9R_REG (0x68) -+#define AW87XXX_PID_5A_REG_DFTAR_REG (0x69) -+#define AW87XXX_PID_5A_REG_DFTBR_REG (0x70) -+#define AW87XXX_PID_5A_REG_DFTCR_REG (0x71) -+#define AW87XXX_PID_5A_REG_DFTDR_REG (0x72) -+#define AW87XXX_PID_5A_REG_DFTER_REG (0x73) -+#define AW87XXX_PID_5A_REG_DFTFR_REG (0x74) -+#define AW87XXX_PID_5A_REG_test1_REG (0x75) -+#define AW87XXX_PID_5A_REG_test2_REG (0x76) -+#define AW87XXX_PID_5A_REG_ENCR_REG (0x77) -+ -+#define AW87XXX_PID_5A_DFT3R_DEFAULT (0x02) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_5a_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_5A_REG_MAX (0x78) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = { -+ [AW87XXX_PID_5A_REG_ID_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_5A_REG_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BATSAFE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BSTOVR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BSTCPR1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BSTCPR2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGC3OPR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGC3PR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGC2OPR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGC2PR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_PAGC1PR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_ADP_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_ADPBST_TIME1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_ADPBST_TIME2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_ADPBST_VTH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BOOST_PAR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_BOOST_VOUT_DET_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_5A_REG_SYSST_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_5A_REG_SYSINT_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT1R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT2R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT3R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT4R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT5R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT6R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT7R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT8R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFT9R_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTAR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTBR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTCR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTDR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTER_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_DFTFR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_test1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_test2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_5A_REG_ENCR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+/* detail information of registers begin */ -+/* ID (0x00) detail */ -+/* IDCODE bit 7:0 (ID 0x00) */ -+#define AW87XXX_PID_5A_REG_IDCODE_START_BIT (0) -+#define AW87XXX_PID_5A_REG_IDCODE_BITS_LEN (8) -+#define AW87XXX_PID_5A_REG_IDCODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_IDCODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_IDCODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_IDCODE_DEFAULT_VALUE (0x5A) -+#define AW87XXX_PID_5A_REG_IDCODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_IDCODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_IDCODE_START_BIT) -+ -+/* default value of ID (0x00) */ -+/* #define AW87XXX_PID_5A_REG_ID_DEFAULT (0x5A) */ -+ -+/* SYSCTRL (0x01) detail */ -+/* EN_SW bit 6 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_SW_START_BIT (6) -+#define AW87XXX_PID_5A_REG_EN_SW_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_SW_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_SW_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_SW_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_SW_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_SW_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_SW_DISABLE << AW87XXX_PID_5A_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_SW_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_SW_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_SW_ENABLE << AW87XXX_PID_5A_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_SW_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_SW_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_SW_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_SW_START_BIT) -+ -+/* EN_CP bit 5 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_CP_START_BIT (5) -+#define AW87XXX_PID_5A_REG_EN_CP_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_CP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_CP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_CP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_CP_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_CP_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_CP_DISABLE << AW87XXX_PID_5A_REG_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_CP_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_CP_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_CP_ENABLE << AW87XXX_PID_5A_REG_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_CP_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_EN_CP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_CP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_CP_START_BIT) -+ -+/* EN_BOOST bit 4 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_BOOST_START_BIT (4) -+#define AW87XXX_PID_5A_REG_EN_BOOST_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_BOOST_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_BOOST_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_BOOST_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_DISABLE << AW87XXX_PID_5A_REG_EN_BOOST_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_ENABLE << AW87XXX_PID_5A_REG_EN_BOOST_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_BOOST_START_BIT) -+ -+/* EN_PA bit 3 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_PA_START_BIT (3) -+#define AW87XXX_PID_5A_REG_EN_PA_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_PA_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_PA_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_PA_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_PA_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_PA_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_PA_DISABLE << AW87XXX_PID_5A_REG_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_PA_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_PA_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_PA_ENABLE << AW87XXX_PID_5A_REG_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_PA_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_EN_PA_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_PA_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_PA_START_BIT) -+ -+/* RCV_MODE bit 2 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_RCV_MODE_START_BIT (2) -+#define AW87XXX_PID_5A_REG_RCV_MODE_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_RCV_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_RCV_MODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_RCV_MODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_RCV_MODE_DISABLE (0) -+#define AW87XXX_PID_5A_REG_RCV_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_RCV_MODE_DISABLE << AW87XXX_PID_5A_REG_RCV_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RCV_MODE_ENABLE (1) -+#define AW87XXX_PID_5A_REG_RCV_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_RCV_MODE_ENABLE << AW87XXX_PID_5A_REG_RCV_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RCV_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_RCV_MODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_RCV_MODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_RCV_MODE_START_BIT) -+ -+/* EN_OVERLOAD bit 1 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_START_BIT (1) -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_OVERLOAD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_OVERLOAD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_DISABL (0) -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_DISABL_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_OVERLOAD_DISABL << AW87XXX_PID_5A_REG_EN_OVERLOAD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_OVERLOAD_ENABLE << AW87XXX_PID_5A_REG_EN_OVERLOAD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_OVERLOAD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_OVERLOAD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_OVERLOAD_START_BIT) -+ -+/* EN_HVBAT bit 0 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_5A_REG_EN_HVBAT_START_BIT (0) -+#define AW87XXX_PID_5A_REG_EN_HVBAT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_HVBAT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_HVBAT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_HVBAT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_HVBAT_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_HVBAT_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HVBAT_DISABLE << AW87XXX_PID_5A_REG_EN_HVBAT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HVBAT_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_HVBAT_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HVBAT_ENABLE << AW87XXX_PID_5A_REG_EN_HVBAT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HVBAT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_HVBAT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_HVBAT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_HVBAT_START_BIT) -+ -+/* default value of SYSCTRL (0x01) */ -+/* #define AW87XXX_PID_5A_REG_SYSCTRL_DEFAULT (0x38) */ -+ -+/* BATSAFE (0x02) detail */ -+/* BAT_SFGD_DEGLITCH bit 6:5 (BATSAFE 0x02) */ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT (5) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_1MS (0) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_1MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_1MS << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_500US (1) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_500US_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_500US << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_200US (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_200US_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_200US << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DISABLE (3) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DISABLE << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BAT_SFGD_DEGLITCH_START_BIT) -+ -+/* BAT_SFGD_VTH bit 4:3 (BATSAFE 0x02) */ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BAT_SFGD_VTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P3V (0) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P3V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P3V << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P4V (1) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P4V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P4V << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P5V (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P5V << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P6V (3) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_VTH_3P6V << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_VTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_VTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BAT_SFGD_VTH_START_BIT) -+ -+/* EN_BAT_SFGD bit 2 (BATSAFE 0x02) */ -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_START_BIT (2) -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_BAT_SFGD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_BAT_SFGD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BAT_SFGD_DISABLE << AW87XXX_PID_5A_REG_EN_BAT_SFGD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BAT_SFGD_ENABLE << AW87XXX_PID_5A_REG_EN_BAT_SFGD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_BAT_SFGD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_BAT_SFGD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_BAT_SFGD_START_BIT) -+ -+/* BAT_SFGD_LEVEL bit 1:0 (BATSAFE 0x02) */ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5V (0) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5V << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5P5V (1) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_5P5V << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6V (2) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6V << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6P5V (3) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_6P5V << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_DEFAULT_VALUE (0x01) -+#define AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BAT_SFGD_LEVEL_START_BIT) -+ -+/* default value of BATSAFE (0x02) */ -+/* #define AW87XXX_PID_5A_REG_BATSAFE_DEFAULT (0x09) */ -+ -+/* BSTOVR (0x03) detail */ -+/* BST_VOUT bit 4:0 (BSTOVR 0x03) */ -+#define AW87XXX_PID_5A_REG_BST_VOUT_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_VOUT_BITS_LEN (5) -+#define AW87XXX_PID_5A_REG_BST_VOUT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_VOUT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_6P5V (0) -+#define AW87XXX_PID_5A_REG_BST_VOUT_6P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_6P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_6P75V (1) -+#define AW87XXX_PID_5A_REG_BST_VOUT_6P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_6P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P0V (2) -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_7P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P25V (3) -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_7P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P5V (4) -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_7P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P75V (5) -+#define AW87XXX_PID_5A_REG_BST_VOUT_7P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_7P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P0V (6) -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_8P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P25V (7) -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_8P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P5V (8) -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_8P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P75V (9) -+#define AW87XXX_PID_5A_REG_BST_VOUT_8P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_8P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P0V (10) -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_9P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P25V (11) -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_9P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P5V (12) -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_9P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P75V (13) -+#define AW87XXX_PID_5A_REG_BST_VOUT_9P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_9P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P0V (14) -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_10P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P25V (15) -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_10P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P5V (16) -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_10P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P75V (17) -+#define AW87XXX_PID_5A_REG_BST_VOUT_10P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_10P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P0V (18) -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_11P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P25V (19) -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_11P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P5V (20) -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_11P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P75V (21) -+#define AW87XXX_PID_5A_REG_BST_VOUT_11P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_11P75V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P0V (22) -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_12P0V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P25V (23) -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_12P25V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P5V (24) -+#define AW87XXX_PID_5A_REG_BST_VOUT_12P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_12P5V << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_VOUT_DEFAULT_VALUE (0x0C) -+#define AW87XXX_PID_5A_REG_BST_VOUT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_VOUT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_VOUT_START_BIT) -+ -+/* default value of BSTOVR (0x03) */ -+/* #define AW87XXX_PID_5A_REG_BSTOVR_DEFAULT (0x0C) */ -+ -+/* BSTCPR1 (0x04) detail */ -+/* BURST_HYS_SELA bit 7 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT (7) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BURST_HYS_SELA_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_3P3MV (0) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_3P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SELA_3P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_5MV (1) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_5MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SELA_5MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV (2) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV (3) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_DEFAULT_VALUE (0) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SELA_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT) -+ -+/* BST_IPEAK_SS bit 6:5 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT (5) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_IPEAK_SS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_0P8A (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_0P8A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_SS_0P8A << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_1A (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_1A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_SS_1A << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_1P5A (2) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_1P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_SS_1P5A << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_2A (3) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_2A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_SS_2A << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_SS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_SS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_IPEAK_SS_START_BIT) -+ -+/* BST_IPEAK_ADJ bit 4 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK << AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK0P5A (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK0P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_IPEAK0P5A << AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_IPEAK_ADJ_START_BIT) -+ -+/* BST_IPEAK_LOWBAT_EN bit 3 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DISABLE (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DISABLE << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_ENABLE (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_ENABLE << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+/* BST_IPEAK_LOWBAT bit 2 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P5A (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P5A << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P75A (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P75A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_2P75A << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_IPEAK_LOWBAT_START_BIT) -+ -+/* BURST_HYS_SEL bit 1 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT (1) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BURST_HYS_SEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_3P3MV (0) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_3P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SEL_3P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_5MV (1) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_5MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SEL_5MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV (2) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV (3) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BURST_HYS_SEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT) -+ -+/* BURST_MODE bit 0 (BSTCPR1 0x04) */ -+#define AW87XXX_PID_5A_REG_BURST_MODE_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BURST_MODE_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BURST_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BURST_MODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BURST_MODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BURST_MODE_PVDD_DECIDE (0) -+#define AW87XXX_PID_5A_REG_BURST_MODE_PVDD_DECIDE_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_MODE_PVDD_DECIDE << AW87XXX_PID_5A_REG_BURST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_MODE_BUEST_PEAK_DECIDE (1) -+#define AW87XXX_PID_5A_REG_BURST_MODE_BUEST_PEAK_DECIDE_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_MODE_BUEST_PEAK_DECIDE << AW87XXX_PID_5A_REG_BURST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BURST_MODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BURST_MODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BURST_MODE_START_BIT) -+ -+/* default value of BSTCPR1 (0x04) */ -+/* #define AW87XXX_PID_5A_REG_BSTCPR1_DEFAULT (0x00) */ -+ -+/* BSTCPR2 (0x05) detail */ -+/* BURST_PEAK bit 5:4 (BSTCPR2 0x05) */ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BURST_PEAK_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_660MV_HYS_800MV (0) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_660MV_HYS_800MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_660MV_HYS_800MV << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_730MV_HYS_890MV (1) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_730MV_HYS_890MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_730MV_HYS_890MV << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_780MV_HYS_930MV (2) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_780MV_HYS_930MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_780MV_HYS_930MV << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_810MV_HYS_970MV (3) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_810MV_HYS_970MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BURST_PEAK_CLAMP_810MV_HYS_970MV << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BURST_PEAK_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BURST_PEAK_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BURST_PEAK_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BURST_PEAK_START_BIT) -+ -+/* BST_IPEAK bit 3:0 (BSTCPR2 0x05) */ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_IPEAK_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_1P5A (0) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_1P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_1P5A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_1P75A (1) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_1P75A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_1P75A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2A (2) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_2A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P25A (3) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P25A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_2P25A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P5A (4) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_2P5A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P75A (5) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_2P75A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_2P75A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3A (6) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_3A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P25 (7) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P25_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_3P25 << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P5A (8) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_3P5A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P75A (9) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_3P75A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_3P75A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4A (10) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_4A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4P25A (11) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4P25A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_4P25A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4P5A (12) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_4P5A_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_4P5A << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_IPEAK_DEFAULT_VALUE (0x8) -+#define AW87XXX_PID_5A_REG_BST_IPEAK_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_IPEAK_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_IPEAK_START_BIT) -+ -+/* default value of BSTCPR2 (0x05) */ -+/* #define AW87XXX_PID_5A_REG_BSTCPR2_DEFAULT (0x08) */ -+ -+/* PAGR (0x06) detail */ -+/* PA_GAIN bit 4:0 (PAGR 0x06) */ -+#define AW87XXX_PID_5A_REG_PA_GAIN_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PA_GAIN_BITS_LEN (5) -+#define AW87XXX_PID_5A_REG_PA_GAIN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_GAIN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_0DB (0) -+#define AW87XXX_PID_5A_REG_PA_GAIN_0DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_0DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_1P5DB (1) -+#define AW87XXX_PID_5A_REG_PA_GAIN_1P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_1P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_3DB (2) -+#define AW87XXX_PID_5A_REG_PA_GAIN_3DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_3DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_4P5DB (3) -+#define AW87XXX_PID_5A_REG_PA_GAIN_4P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_4P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_6DB (4) -+#define AW87XXX_PID_5A_REG_PA_GAIN_6DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_6DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_7P5DB (5) -+#define AW87XXX_PID_5A_REG_PA_GAIN_7P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_7P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_9DB (6) -+#define AW87XXX_PID_5A_REG_PA_GAIN_9DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_9DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_10P5DB (7) -+#define AW87XXX_PID_5A_REG_PA_GAIN_10P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_10P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_12DB (8) -+#define AW87XXX_PID_5A_REG_PA_GAIN_12DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_12DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_13P5DB (9) -+#define AW87XXX_PID_5A_REG_PA_GAIN_13P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_13P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_15DB (10) -+#define AW87XXX_PID_5A_REG_PA_GAIN_15DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_15DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_16P5DB (11) -+#define AW87XXX_PID_5A_REG_PA_GAIN_16P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_16P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_18DB (12) -+#define AW87XXX_PID_5A_REG_PA_GAIN_18DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_18DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_19P5DB (13) -+#define AW87XXX_PID_5A_REG_PA_GAIN_19P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_19P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_21DB (14) -+#define AW87XXX_PID_5A_REG_PA_GAIN_21DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_21DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_22P5DB (15) -+#define AW87XXX_PID_5A_REG_PA_GAIN_22P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_22P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_24DB (16) -+#define AW87XXX_PID_5A_REG_PA_GAIN_24DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_24DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_25P5DB (17) -+#define AW87XXX_PID_5A_REG_PA_GAIN_25P5DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_25P5DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_27DB (18) -+#define AW87XXX_PID_5A_REG_PA_GAIN_27DB_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_27DB << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GAIN_DEFAULT_VALUE (0x10) -+#define AW87XXX_PID_5A_REG_PA_GAIN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_GAIN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_GAIN_START_BIT) -+ -+/* default value of PAGR (0x06) */ -+/* #define AW87XXX_PID_5A_REG_PAGR_DEFAULT (0x10) */ -+ -+/* PAGC3OPR (0x07) detail */ -+/* PAVG_ADJ bit 7:5 (PAGC3OPR 0x07) */ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT (5) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PAVG_ADJ_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_0P94PO (0) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_0P94PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_0P94PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_0P97PO (1) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_0P97PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_0P97PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P0PO (2) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P0PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_1P0PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P03PO (3) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P03PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_1P03PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P06PO (4) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P06PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_1P06PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P09PO (5) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_1P09PO_VALUE \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_1P09PO << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_PAVG_ADJ_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PAVG_ADJ_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PAVG_ADJ_START_BIT) -+ -+/* PD_AGC3 bit 4 (PAGC3OPR 0x07) */ -+#define AW87XXX_PID_5A_REG_PD_AGC3_START_BIT (4) -+#define AW87XXX_PID_5A_REG_PD_AGC3_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PD_AGC3_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PD_AGC3_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PD_AGC3_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC3_ENABLE (0) -+#define AW87XXX_PID_5A_REG_PD_AGC3_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_AGC3_ENABLE << AW87XXX_PID_5A_REG_PD_AGC3_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC3_DISABLE (1) -+#define AW87XXX_PID_5A_REG_PD_AGC3_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_AGC3_DISABLE << AW87XXX_PID_5A_REG_PD_AGC3_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC3_DEFAULT_VALUE (0) -+#define AW87XXX_PID_5A_REG_PD_AGC3_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PD_AGC3_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PD_AGC3_START_BIT) -+ -+/* AGC3_OUTPUT_POWER bit 3:0 (PAGC3OPR 0x07) */ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT (0) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P5W8_OHM (0) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P5W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P5W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P6W8_OHM (1) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P6W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P6W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P7W8_OHM (2) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P7W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P7W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P8W8_OHM (3) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P8W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P8W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P9W8_OHM (4) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P9W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_0P9W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P0W8_OHM (5) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P0W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P0W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P1W8_OHM (6) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P1W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P1W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P2W8_OHM (7) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P2W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P2W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P3W8_OHM (8) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P3W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P3W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P4W8_OHM (9) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P4W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P4W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P5W8_OHM (10) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P5W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P5W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P6W8_OHM (11) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P6W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P6W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P7W8_OHM (12) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P7W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P7W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P8W8_OHM (13) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P8W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P8W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P9W8_OHM (14) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P9W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_1P9W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_2P0W8_OHM (15) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_2P0W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_2P0W8_OHM << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC3_OUTPUT_POWER_START_BIT) -+ -+/* default value of PAGC3OPR (0x07) */ -+/* #define AW87XXX_PID_5A_REG_PAGC3OPR_DEFAULT (0x43) */ -+ -+/* PAGC3PR (0x08) detail */ -+/* AGC3_REL_TIME bit 7:5 (PAGC3PR 0x08) */ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT (5) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC3_REL_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_5P12MSDB (0) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_5P12MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_5P12MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_10P24MSDB (1) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_10P24MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_20P48MSDB (2) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_20P48MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_20P48MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_40P96MSDB (3) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_40P96MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_81P92MSDB (4) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_81P92MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_81P92MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_163P84MSDB (5) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_163P84MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_163P84MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_327P68MSDB (6) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_327P68MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_327P68MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_655P36MSDB (7) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_655P36MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_655P36MSDB << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_AGC3_REL_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC3_REL_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC3_REL_TIME_START_BIT) -+ -+/* AGC3_ATT_TIME bit 4:2 (PAGC3PR 0x08) */ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT (2) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC3_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_1P28MSDB (0) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_1P28MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_1P28MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_2P56MSDB (1) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_2P56MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_2P56MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_10P24MSDB (2) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_10P24MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_40P96MSDB (3) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_40P96MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_82MSDB (4) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_82MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_82MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_164MSDB (5) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_164MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_164MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_328MSDB (6) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_328MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_328MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_656MSDB (7) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_656MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_656MSDB << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_AGC3_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC3_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC3_ATT_TIME_START_BIT) -+ -+/* AGC3_FIRST_ATT_TIME bit 1:0 (PAGC3PR 0x08) */ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_5P12MS (0) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_5P12MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_5P12MS << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_10P24MS (1) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_10P24MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_10P24MS << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_20P48MS (2) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_20P48MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_20P48MS << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_41MS (3) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_41MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_41MS << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+/* default value of PAGC3PR (0x08) */ -+/* #define AW87XXX_PID_5A_REG_PAGC3PR_DEFAULT (0x4E) */ -+ -+/* PAGC2OPR (0x09) detail */ -+/* AGC2_OUTPUT_POWER bit 3:0 (PAGC2OPR 0x09) */ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT (0) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P0W8_OHM (0) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P0W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P0W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P2W8_OHM (1) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P2W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P2W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P4W8_OHM (2) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P4W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P4W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P6W8_OHM (3) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P6W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P6W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P8W8_OHM (4) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P8W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_1P8W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P0W8_OHM (5) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P0W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P0W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P2W8_OHM (6) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P2W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P2W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P4W8_OHM (7) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P4W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P4W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P6W8_OHM (8) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P6W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P6W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P8W8_OHM (9) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P8W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_2P8W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_3P0W8_OHM (10) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_3P0W8_OHM_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_3P0W8_OHM << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_AGC2_OFF (11) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_AGC2_OFF_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_AGC2_OFF << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC2_OUTPUT_POWER_START_BIT) -+ -+/* default value of PAGC2OPR (0x09) */ -+/* #define AW87XXX_PID_5A_REG_PAGC2OPR_DEFAULT (0x03) */ -+ -+/* PAGC2PR (0x0A) detail */ -+/* AGC2_ATT_TIME bit 4:2 (PAGC2PR 0x0A) */ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT (2) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC2_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P16MSDB (0) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P16MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P16MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P32MSDB (1) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P32MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P32MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P64MSDB (2) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P64MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_0P64MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_2P56MSDB (3) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_2P56MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_2P56MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_10P24MSDB (4) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_10P24MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_40P96MSDB (5) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_40P96MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_82MSDB (6) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_82MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_82MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_164MSDB (7) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_164MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_164MSDB << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_AGC2_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC2_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC2_ATT_TIME_START_BIT) -+ -+/* AGC2_FIRST_ATT_TIME bit 1:0 (PAGC2PR 0x0A) */ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P08MS (0) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P08MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P08MS << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P32MS (1) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P32MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_0P32MS << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_1P28MS (2) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_1P28MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_1P28MS << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_5P12MS (3) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_5P12MS_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_5P12MS << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+/* default value of PAGC2PR (0x0A) */ -+/* #define AW87XXX_PID_5A_REG_PAGC2PR_DEFAULT (0x08) */ -+ -+/* PAGC1PR (0x0B) detail */ -+/* AGC1_OUTPUT_LEVEL bit 6:3 (PAGC1PR 0x0B) */ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT (3) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5V (0) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P2V (1) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P2V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P2V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P4V (2) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P4V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P4V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P6V (3) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P6V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P8V (4) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P8V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_5P8V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P0V (5) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P0V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P2V (6) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P2V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P2V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P4V (7) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P4V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P4V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P6V (8) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P6V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P8V (9) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P8V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_6P8V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7V (10) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P2V (11) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P2V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P2V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P4V (12) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P4V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P4V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P6V (13) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P6V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P8V (14) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P8V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_7P8V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_8V (15) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_8V_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_8V << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_DEFAULT_VALUE (0x9) -+#define AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+/* AGC1_ATT_TIME bit 2:1 (PAGC1PR 0x0B) */ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT (1) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC1_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P04MSDB (0) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P04MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P04MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P08MSDB (1) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P08MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P08MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P16MSDB (2) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P16MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P16MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P32MSDB (3) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P32MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P32MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P02MSDB (4) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P02MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P02MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P01MSDB (5) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P01MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P01MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB (6) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB (7) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT) -+ -+/* PD_AGC1 bit 0 (PAGC1PR 0x0B) */ -+#define AW87XXX_PID_5A_REG_PD_AGC1_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PD_AGC1_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PD_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PD_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC1_ENABLE (0) -+#define AW87XXX_PID_5A_REG_PD_AGC1_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_AGC1_ENABLE << AW87XXX_PID_5A_REG_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC1_DISABLE (1) -+#define AW87XXX_PID_5A_REG_PD_AGC1_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_AGC1_DISABLE << AW87XXX_PID_5A_REG_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_AGC1_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PD_AGC1_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PD_AGC1_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PD_AGC1_START_BIT) -+ -+/* default value of PAGC1PR (0x0B) */ -+/* #define AW87XXX_PID_5A_REG_PAGC1PR_DEFAULT (0x4A) */ -+ -+/* ADP_MODE (0x0C) detail */ -+/* AGC1_ATT_TIMEA bit 3 (ADP_MODE 0x0C) */ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT (3) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P04MSDB (0) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P04MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P04MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P08MSDB (1) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P08MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P08MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P16MSDB (2) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P16MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P16MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P32MSDB (3) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P32MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P32MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P02MSDB (4) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P02MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P02MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P01MSDB (5) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P01MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P01MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB (6) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB (7) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_DEFAULT_VALUE (0) -+#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT) -+ -+/* ADPBOOST_MODE bit 2:0 (ADP_MODE 0x0C) */ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT (0) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADPBOOST_MODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_PASS_THROUGH (0) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_PASS_THROUGH_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_PASS_THROUGH << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_FORCE_BOOST (1) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_FORCE_BOOST_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_FORCE_BOOST << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD1 (2) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD1_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD1 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 (3) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD3 (4) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD3_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD3 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD4 (5) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD4_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD4 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD5 (6) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD5_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD5 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 (7) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2_VALUE \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADPBOOST_MODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT) -+ -+/* default value of ADP_MODE (0x0C) */ -+/* #define AW87XXX_PID_5A_REG_ADP_MODE_DEFAULT (0x03) */ -+ -+/* ADPBST_TIME1 (0x0D) detail */ -+/* ADP_BST_TIME_2W bit 7:4 (ADPBST_TIME1 0x0D) */ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT (4) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_1P25MS (0) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_1P25MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_1P25MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_2P5MS (1) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_2P5MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_2P5MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_5MS (2) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_5MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_5MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_10MS (3) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_10MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_10MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_15MS (4) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_15MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_15MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_20MS (5) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_20MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_20MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_30MS (6) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_30MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_30MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_40MS (7) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_40MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_40MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_65MS (8) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_65MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_65MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_80MS (9) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_80MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_80MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_100MS (10) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_100MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_100MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_120MS (11) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_120MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_120MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_140MS (12) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_140MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_140MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_160MS (13) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_160MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_160MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_320MS (14) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_320MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_320MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_480MS (15) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_480MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_480MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_DEFAULT_VALUE (0xD) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_BST_TIME_2W_START_BIT) -+ -+/* ADP_BST_TIME_0P4W bit 3:0 (ADPBST_TIME1 0x0D) */ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT (0) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_1P25MS (0) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_1P25MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_1P25MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_2P5MS (1) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_2P5MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_2P5MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_5MS (2) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_5MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_5MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_10MS (3) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_10MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_10MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_15MS (4) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_15MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_15MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_20MS (5) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_20MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_20MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_30MS (6) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_30MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_30MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_40MS (7) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_40MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_40MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_65MS (8) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_65MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_65MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_80MS (9) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_80MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_80MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_100MS (10) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_100MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_100MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_120MS (11) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_120MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_120MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_140MS (12) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_140MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_140MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_160MS (13) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_160MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_160MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_320MS (14) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_320MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_320MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_480MS (15) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_480MS_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_480MS << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_DEFAULT_VALUE (0xD) -+#define AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_BST_TIME_0P4W_START_BIT) -+ -+/* default value of ADPBST_TIME1 (0x0D) */ -+/* #define AW87XXX_PID_5A_REG_ADPBST_TIME1_DEFAULT (0xDD) */ -+ -+/* ADPBST_TIME2 (0x0E) detail */ -+/* BST_UP_DT bit 7:4 (ADPBST_TIME2 0x0E) */ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_UP_DT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P005MS (0) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P005MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P005MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P01MS (1) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P01MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P01MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P015MS (2) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P015MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P015MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P02MS (3) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P02MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P02MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P03MS (4) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P03MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P03MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P04MS (5) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P04MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P04MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P05MS (6) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P05MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P05MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P06MS (7) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P06MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P06MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P07MS (8) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P07MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P07MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P08MS (9) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P08MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P08MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P10MS (10) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P10MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P10MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P16MS (11) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P16MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P16MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P20MS (12) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P20MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P20MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P32MS (13) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P32MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P32MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P64MS (14) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_0P64MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_0P64MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_1P28MS (15) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_1P28MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_1P28MS << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_UP_DT_DEFAULT_VALUE (0x7) -+#define AW87XXX_PID_5A_REG_BST_UP_DT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_UP_DT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_UP_DT_START_BIT) -+ -+/* BST_DOWN_TD bit 3:0 (ADPBST_TIME2 0x0E) */ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_BITS_LEN (4) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_DOWN_TD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P01MS (0) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P01MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P01MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P02MS (1) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P02MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P02MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P04MS (2) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P04MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P04MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P08MS (3) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P08MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P08MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P12MS (4) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P12MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P12MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P16MS (5) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P16MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P16MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P24MS (6) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P24MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P24MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P32MS (7) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P32MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P32MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P64MS (8) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P64MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P64MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P96MS (9) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_0P96MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_0P96MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P28MS (10) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P28MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_1P28MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P60MS (11) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P60MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_1P60MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P92MS (12) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_1P92MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_1P92MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_2P56MS (13) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_2P56MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_2P56MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_5P12MS (14) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_5P12MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_5P12MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_10P24MS (15) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_10P24MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_10P24MS << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_DEFAULT_VALUE (0xA) -+#define AW87XXX_PID_5A_REG_BST_DOWN_TD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_DOWN_TD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_DOWN_TD_START_BIT) -+ -+/* default value of ADPBST_TIME2 (0x0E) */ -+/* #define AW87XXX_PID_5A_REG_ADPBST_TIME2_DEFAULT (0x7A) */ -+ -+/* ADPBST_VTH (0x0F) detail */ -+/* ADP_LOW_STEP bit 7:6 (ADPBST_VTH 0x0F) */ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT (6) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_LOW_STEP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00000 (0) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00000_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00000 << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00001 (1) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00001_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00001 << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00010 (2) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00010_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00010 << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00011 (3) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00011_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_LOW_STEP_1ST_BST_OUT00011 << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_ADP_LOW_STEP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_LOW_STEP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_LOW_STEP_START_BIT) -+ -+/* SET_BOOST_VTH2 bit 5:3 (ADPBST_VTH 0x0F) */ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT (3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SET_BOOST_VTH2_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P2W (0) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P2W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P2W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P4W (1) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P4W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P6W (2) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P6W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P8W (3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P8W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_1P8W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P0W (4) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P0W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P0W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P2W (5) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P2W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P2W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W (6) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W (7) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT) -+ -+/* SET_BOOST_VTH1 bit 2:0 (ADPBST_VTH 0x0F) */ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT (0) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SET_BOOST_VTH1_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P1W (0) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P1W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P1W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P2W (1) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P2W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P2W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P3W (2) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P3W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P3W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P4W (3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P4W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P5W (4) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P5W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P5W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (5) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (6) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (7) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT) -+ -+/* default value of ADPBST_VTH (0x0F) */ -+/* #define AW87XXX_PID_5A_REG_ADPBST_VTH_DEFAULT (0x23) */ -+ -+/* BOOST_PAR (0x10) detail */ -+/* CLKDLY_SELECT bit 7 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_START_BIT (7) -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CLKDLY_SELECT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CLKDLY_SELECT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_CLK_DLY (0) -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_CLK_DLY_VALUE \ -+ (AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_CLK_DLY << AW87XXX_PID_5A_REG_CLKDLY_SELECT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_MAXIM_DUTY (1) -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_MAXIM_DUTY_VALUE \ -+ (AW87XXX_PID_5A_REG_CLKDLY_SELECT_DELAY_CLK_CHOOSE_MAXIM_DUTY << AW87XXX_PID_5A_REG_CLKDLY_SELECT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_CLKDLY_SELECT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CLKDLY_SELECT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CLKDLY_SELECT_START_BIT) -+ -+/* CPOK_VBGOK bit 6 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_START_BIT (6) -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CPOK_VBGOK_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CPOK_VBGOK_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_CPOK (0) -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_CPOK_VALUE \ -+ (AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_CPOK << AW87XXX_PID_5A_REG_CPOK_VBGOK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_VBGOK (1) -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_VBGOK_VALUE \ -+ (AW87XXX_PID_5A_REG_CPOK_VBGOK_ENABLE_VBGOK << AW87XXX_PID_5A_REG_CPOK_VBGOK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_CPOK_VBGOK_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CPOK_VBGOK_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CPOK_VBGOK_START_BIT) -+ -+/* EN_LOWBAT_ADJ bit 5 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_START_BIT (5) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DISABLE << AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_ENABLE << AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_LOWBAT_ADJ_START_BIT) -+ -+/* EN_ADP_MODE1_DEGLITCH bit 4 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_START_BIT (4) -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DISABLE << AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_ENABLE << AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+/* EN_VCLAMP_MIN_VTH bit 3 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_START_BIT (3) -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DISABLE << AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_ENABLE << AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_VCLAMP_MIN_VTH_START_BIT) -+ -+/* SS_ADP_BIAS bit 2 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_START_BIT (2) -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SS_ADP_BIAS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SS_ADP_BIAS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_4UA (0) -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_4UA_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_4UA << AW87XXX_PID_5A_REG_SS_ADP_BIAS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_8UA (1) -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_8UA_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_ADP_BIAS_SS_ADP_BIAS_8UA << AW87XXX_PID_5A_REG_SS_ADP_BIAS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_SS_ADP_BIAS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SS_ADP_BIAS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SS_ADP_BIAS_START_BIT) -+ -+/* BOOST_VTH1_0P1W_0P2W bit 1 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_START_BIT (1) -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P1W (0) -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P1W_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P1W << AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P2W (1) -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P2W_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_BOOST_VTH1_0P2W << AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BOOST_VTH1_0P1W_0P2W_START_BIT) -+ -+/* EN_LOWBAT_BOOST_VTH1 bit 0 (BOOST_PAR 0x10) */ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_START_BIT (0) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DISABLE << AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_ENABLE << AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_LOWBAT_BOOST_VTH1_START_BIT) -+ -+/* default value of BOOST_PAR (0x10) */ -+/* #define AW87XXX_PID_5A_REG_BOOST_PAR_DEFAULT (0x08) */ -+ -+/* BOOST_VOUT_DET (0x57) detail */ -+/* ADP_BOOST_VOUT bit 4:0 (BOOST_VOUT_DET 0x57) */ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_BITS_LEN (5) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P5V (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P75V (1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_6P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P0V (2) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P25V (3) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P5V (4) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P75V (5) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_7P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P0V (6) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P25V (7) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P5V (8) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P75V (9) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_8P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P0V (10) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P25V (11) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P5V (12) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P75V (13) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_9P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P0V (14) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P25V (15) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P5V (16) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P75V (17) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_10P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P0V (18) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P25V (19) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P5V (20) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P75V (21) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_11P75V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P0V (22) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P0V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P0V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P25V (23) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P25V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P5V (24) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_12P5V << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_DEFAULT_VALUE (0x0C) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_BOOST_VOUT_START_BIT) -+ -+/* default value of BOOST_VOUT_DET (0x57) */ -+/* #define AW87XXX_PID_5A_REG_BOOST_VOUT_DET_DEFAULT (0x0C) */ -+ -+/* SYSST (0x58) detail */ -+/* UVLO_S bit 7 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_UVLO_S_START_BIT (7) -+#define AW87XXX_PID_5A_REG_UVLO_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_UVLO_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_UVLO_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_UVLO_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_UVLO_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_UVLO_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_UVLO_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_S_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_5A_REG_UVLO_S_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_S_VBAT_UNDER_VOLTAGE << AW87XXX_PID_5A_REG_UVLO_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_UVLO_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_UVLO_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_UVLO_S_START_BIT) -+ -+/* LOW_BATT_S bit 6 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_START_BIT (6) -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_LOW_BATT_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_LOW_BATT_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_LOW_BATT_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_LOW_VBAT_DETECTED (1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_LOW_VBAT_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_S_LOW_VBAT_DETECTED << AW87XXX_PID_5A_REG_LOW_BATT_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_LOW_BATT_S_START_BIT) -+ -+/* BST_OVP_S bit 5 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_BST_OVP_S_START_BIT (5) -+#define AW87XXX_PID_5A_REG_BST_OVP_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_OVP_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_OVP_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_5A_REG_BST_OVP_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP_S_START_BIT) -+ -+/* BST_OVP2_S bit 4 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP2_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP2_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_OVP2_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_BST_OVP2_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP2_S_START_BIT) -+ -+/* BST_SCP_S bit 3 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_BST_SCP_S_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_SCP_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_SCP_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SCP_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SCP_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_SCP_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SCP_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_SCP_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_BST_SCP_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_SCP_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SCP_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SCP_S_START_BIT) -+ -+/* PA_OC_S bit 2 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_PA_OC_S_START_BIT (2) -+#define AW87XXX_PID_5A_REG_PA_OC_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_OC_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_OC_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_OC_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_PA_OC_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_PA_OC_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_PA_OC_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_PA_OC_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_OC_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_OC_S_START_BIT) -+ -+/* OT160_S bit 1 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_OT160_S_START_BIT (1) -+#define AW87XXX_PID_5A_REG_OT160_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_OT160_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_OT160_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_OT160_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_OT160_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_OT160_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_OT160_S_NORMAL_OPERATION << AW87XXX_PID_5A_REG_OT160_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_OT160_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OT160_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_OT160_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_OT160_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_OT160_S_START_BIT) -+ -+/* ADP_BOOST_S bit 0 (SYSST 0x58) */ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_START_BIT (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_BOOST_S_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_BOOST_S_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_DIRECT_MODE (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_DIRECT_MODE_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_S_DIRECT_MODE << AW87XXX_PID_5A_REG_ADP_BOOST_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_BOOST_MODE (1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_BOOST_MODE_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_S_BOOST_MODE << AW87XXX_PID_5A_REG_ADP_BOOST_S_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_S_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_S_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_BOOST_S_START_BIT) -+ -+/* default value of SYSST (0x58) */ -+/* #define AW87XXX_PID_5A_REG_SYSST_DEFAULT (0xFF) */ -+ -+/* SYSINT (0x59) detail */ -+/* UVLO_I bit 7 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_UVLO_I_START_BIT (7) -+#define AW87XXX_PID_5A_REG_UVLO_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_UVLO_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_UVLO_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_UVLO_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_UVLO_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_UVLO_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_UVLO_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_I_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_5A_REG_UVLO_I_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_I_VBAT_UNDER_VOLTAGE << AW87XXX_PID_5A_REG_UVLO_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_UVLO_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_UVLO_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_UVLO_I_START_BIT) -+ -+/* LOW_BATT_I bit 6 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_START_BIT (6) -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_LOW_BATT_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_LOW_BATT_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_LOW_BATT_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_LOW_VBAT_DETECTED (1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_LOW_VBAT_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_I_LOW_VBAT_DETECTED << AW87XXX_PID_5A_REG_LOW_BATT_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_LOW_BATT_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_LOW_BATT_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_LOW_BATT_I_START_BIT) -+ -+/* BST_OVP_I bit 5 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_BST_OVP_I_START_BIT (5) -+#define AW87XXX_PID_5A_REG_BST_OVP_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_OVP_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_OVP_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_5A_REG_BST_OVP_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP_I_START_BIT) -+ -+/* BST_OVP2_I bit 4 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP2_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP2_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_OVP2_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_BST_OVP2_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP2_I_START_BIT) -+ -+/* BST_SCP_I bit 3 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_BST_SCP_I_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_SCP_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_SCP_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SCP_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SCP_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_BST_SCP_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SCP_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_BST_SCP_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_BST_SCP_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SCP_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_SCP_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SCP_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SCP_I_START_BIT) -+ -+/* PA_OC_I bit 2 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_PA_OC_I_START_BIT (2) -+#define AW87XXX_PID_5A_REG_PA_OC_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_OC_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_OC_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_OC_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_PA_OC_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_PA_OC_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_PA_OC_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_PA_OC_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_OC_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_OC_I_START_BIT) -+ -+/* OT160_I bit 1 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_OT160_I_START_BIT (1) -+#define AW87XXX_PID_5A_REG_OT160_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_OT160_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_OT160_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_OT160_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_OT160_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_5A_REG_OT160_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_5A_REG_OT160_I_NORMAL_OPERATION << AW87XXX_PID_5A_REG_OT160_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_5A_REG_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_5A_REG_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_5A_REG_OT160_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OT160_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_OT160_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_OT160_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_OT160_I_START_BIT) -+ -+/* ADP_BOOST_I bit 0 (SYSINT 0x59) */ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_START_BIT (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_ADP_BOOST_I_BITS_LEN)-1) << AW87XXX_PID_5A_REG_ADP_BOOST_I_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_DIRECT_MODE (0) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_DIRECT_MODE_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_I_DIRECT_MODE << AW87XXX_PID_5A_REG_ADP_BOOST_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_BOOST_MODE (1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_BOOST_MODE_VALUE \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_I_BOOST_MODE << AW87XXX_PID_5A_REG_ADP_BOOST_I_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_ADP_BOOST_I_DEFAULT \ -+ (AW87XXX_PID_5A_REG_ADP_BOOST_I_DEFAULT_VALUE << AW87XXX_PID_5A_REG_ADP_BOOST_I_START_BIT) -+ -+/* default value of SYSINT (0x59) */ -+/* #define AW87XXX_PID_5A_REG_SYSINT_DEFAULT (0xFF) */ -+ -+/* DFT1R (0x60) detail */ -+/* CP_FREQ bit 7:6 (DFT1R 0x60) */ -+#define AW87XXX_PID_5A_REG_CP_FREQ_START_BIT (6) -+#define AW87XXX_PID_5A_REG_CP_FREQ_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_CP_FREQ_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CP_FREQ_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CP_FREQ_4P8MHZ (0) -+#define AW87XXX_PID_5A_REG_CP_FREQ_4P8MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_FREQ_4P8MHZ << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_FREQ_6P4MHZ (1) -+#define AW87XXX_PID_5A_REG_CP_FREQ_6P4MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_FREQ_6P4MHZ << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_FREQ_8P0MHZ (2) -+#define AW87XXX_PID_5A_REG_CP_FREQ_8P0MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_FREQ_8P0MHZ << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_FREQ_9P6MHZ (3) -+#define AW87XXX_PID_5A_REG_CP_FREQ_9P6MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_FREQ_9P6MHZ << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_FREQ_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_CP_FREQ_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CP_FREQ_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CP_FREQ_START_BIT) -+ -+/* CP_LDO bit 5:4 (DFT1R 0x60) */ -+#define AW87XXX_PID_5A_REG_CP_LDO_START_BIT (4) -+#define AW87XXX_PID_5A_REG_CP_LDO_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_CP_LDO_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CP_LDO_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CP_LDO_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CP_LDO_4P75V (0) -+#define AW87XXX_PID_5A_REG_CP_LDO_4P75V_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_LDO_4P75V << AW87XXX_PID_5A_REG_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_LDO_5V (1) -+#define AW87XXX_PID_5A_REG_CP_LDO_5V_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_LDO_5V << AW87XXX_PID_5A_REG_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_LDO_5P25V (2) -+#define AW87XXX_PID_5A_REG_CP_LDO_5P25V_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_LDO_5P25V << AW87XXX_PID_5A_REG_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_LDO_5P5V (3) -+#define AW87XXX_PID_5A_REG_CP_LDO_5P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_LDO_5P5V << AW87XXX_PID_5A_REG_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_LDO_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_CP_LDO_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CP_LDO_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CP_LDO_START_BIT) -+ -+/* CP_VOS bit 3:2 (DFT1R 0x60) */ -+#define AW87XXX_PID_5A_REG_CP_VOS_START_BIT (2) -+#define AW87XXX_PID_5A_REG_CP_VOS_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_CP_VOS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CP_VOS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CP_VOS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CP_VOS_0MV (0) -+#define AW87XXX_PID_5A_REG_CP_VOS_0MV_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_VOS_0MV << AW87XXX_PID_5A_REG_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_VOS_50MV (1) -+#define AW87XXX_PID_5A_REG_CP_VOS_50MV_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_VOS_50MV << AW87XXX_PID_5A_REG_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_VOS_100MV (2) -+#define AW87XXX_PID_5A_REG_CP_VOS_100MV_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_VOS_100MV << AW87XXX_PID_5A_REG_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_VOS_150MV (3) -+#define AW87XXX_PID_5A_REG_CP_VOS_150MV_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_VOS_150MV << AW87XXX_PID_5A_REG_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_VOS_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_CP_VOS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CP_VOS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CP_VOS_START_BIT) -+ -+/* CPOK_TM bit 1 (DFT1R 0x60) */ -+#define AW87XXX_PID_5A_REG_CPOK_TM_START_BIT (1) -+#define AW87XXX_PID_5A_REG_CPOK_TM_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_CPOK_TM_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CPOK_TM_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CPOK_TM_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CPOK_TM_0P6MS (0) -+#define AW87XXX_PID_5A_REG_CPOK_TM_0P6MS_VALUE \ -+ (AW87XXX_PID_5A_REG_CPOK_TM_0P6MS << AW87XXX_PID_5A_REG_CPOK_TM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CPOK_TM_1MS (1) -+#define AW87XXX_PID_5A_REG_CPOK_TM_1MS_VALUE \ -+ (AW87XXX_PID_5A_REG_CPOK_TM_1MS << AW87XXX_PID_5A_REG_CPOK_TM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CPOK_TM_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_CPOK_TM_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CPOK_TM_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CPOK_TM_START_BIT) -+ -+/* CP_DDT bit 0 (DFT1R 0x60) */ -+#define AW87XXX_PID_5A_REG_CP_DDT_START_BIT (0) -+#define AW87XXX_PID_5A_REG_CP_DDT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_CP_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CP_DDT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CP_DDT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CP_DDT_0NS (0) -+#define AW87XXX_PID_5A_REG_CP_DDT_0NS_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_DDT_0NS << AW87XXX_PID_5A_REG_CP_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_DDT_10NS (1) -+#define AW87XXX_PID_5A_REG_CP_DDT_10NS_VALUE \ -+ (AW87XXX_PID_5A_REG_CP_DDT_10NS << AW87XXX_PID_5A_REG_CP_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CP_DDT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_CP_DDT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CP_DDT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CP_DDT_START_BIT) -+ -+/* default value of DFT1R (0x60) */ -+/* #define AW87XXX_PID_5A_REG_DFT1R_DEFAULT (0x66) */ -+ -+/* DFT2R (0x61) detail */ -+/* BOOST_VCLAMP_SS bit 7:6 (DFT2R 0x61) */ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT (6) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_680MV840MV (0) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_680MV840MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_680MV840MV << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_780MV930MV (1) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_780MV930MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_780MV930MV << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1070MV1225MV (2) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1070MV1225MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1070MV1225MV << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1350MV1500MV (3) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1350MV1500MV_VALUE \ -+ (AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_CLAMP_1350MV1500MV << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BOOST_VCLAMP_SS_START_BIT) -+ -+/* BST_KICK_ITH bit 5:4 (DFT2R 0x61) */ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_KICK_ITH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P5KOHM (0) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P5KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P5KOHM << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P25KOHM (1) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P25KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P25KOHM << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P167KOHM (2) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P167KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P167KOHM << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P125KOHM (3) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P125KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_KICK_ITH_PVDD0P125KOHM << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_KICK_ITH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_KICK_ITH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_KICK_ITH_START_BIT) -+ -+/* BST_EA_CUR bit 3 (DFT2R 0x61) */ -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_EA_CUR_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_EA_CUR_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_1UA (0) -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_1UA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EA_CUR_1UA << AW87XXX_PID_5A_REG_BST_EA_CUR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_4UA (1) -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_4UA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EA_CUR_4UA << AW87XXX_PID_5A_REG_BST_EA_CUR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_EA_CUR_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_EA_CUR_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_EA_CUR_START_BIT) -+ -+/* BST_CK_MODE bit 2 (DFT2R 0x61) */ -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_CK_MODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_CK_MODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_1P6MHZ (0) -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_1P6MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_CK_MODE_1P6MHZ << AW87XXX_PID_5A_REG_BST_CK_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_2P0MHZ (1) -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_2P0MHZ_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_CK_MODE_2P0MHZ << AW87XXX_PID_5A_REG_BST_CK_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_CK_MODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_CK_MODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_CK_MODE_START_BIT) -+ -+/* BST_COMPMAX bit 1:0 (DFT2R 0x61) */ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_COMPMAX_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P2V (0) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P2V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_COMPMAX_2P2V << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P4V (1) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P4V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_COMPMAX_2P4V << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P6V (2) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_COMPMAX_2P6V << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P8V (3) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_2P8V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_COMPMAX_2P8V << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_COMPMAX_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_COMPMAX_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_COMPMAX_START_BIT) -+ -+/* default value of DFT2R (0x61) */ -+/* #define AW87XXX_PID_5A_REG_DFT2R_DEFAULT (0x18) */ -+ -+/* DFT3R (0x62) detail */ -+/* BST_PWM_SHORT bit 7 (DFT3R 0x62) */ -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_START_BIT (7) -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_PWM_SHORT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_PWM_SHORT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDD (0) -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDD_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDD << AW87XXX_PID_5A_REG_BST_PWM_SHORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDDMINUS_VTH (1) -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDDMINUS_VTH_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_PWM_SHORT_VBSTBELOWVDDMINUS_VTH << AW87XXX_PID_5A_REG_BST_PWM_SHORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_PWM_SHORT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_PWM_SHORT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_PWM_SHORT_START_BIT) -+ -+/* BST_SLOPE bit 6:5 (DFT3R 0x62) */ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT (5) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SLOPE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE (0) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P25 (1) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P25_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P25 << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P5 (2) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P5_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P5 << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P75 (3) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P75_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_ISLOPE1P75 << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SLOPE_START_BIT) -+ -+/* BST_LOOPC bit 4 (DFT3R 0x62) */ -+#define AW87XXX_PID_5A_REG_BST_LOOPC_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_LOOPC_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_LOOPC_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_LOOPC_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_LOOPC_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPC_28PF (0) -+#define AW87XXX_PID_5A_REG_BST_LOOPC_28PF_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPC_28PF << AW87XXX_PID_5A_REG_BST_LOOPC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPC_50PF (1) -+#define AW87XXX_PID_5A_REG_BST_LOOPC_50PF_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPC_50PF << AW87XXX_PID_5A_REG_BST_LOOPC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPC_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_LOOPC_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_LOOPC_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_LOOPC_START_BIT) -+ -+/* BST_OS_WIDTH bit 3:2 (DFT3R 0x62) */ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OS_WIDTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_40NS (0) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_40NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OS_WIDTH_40NS << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_30NS (1) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_30NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OS_WIDTH_30NS << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_50NS (2) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_50NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OS_WIDTH_50NS << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_60NS (3) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_60NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OS_WIDTH_60NS << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_OS_WIDTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OS_WIDTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OS_WIDTH_START_BIT) -+ -+/* BST_LOOPR bit 1:0 (DFT3R 0x62) */ -+#define AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_LOOPR_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPR_320K (0) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_320K_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPR_320K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPR_160K (1) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_160K_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPR_160K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LOOPR_480K (2) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_480K_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPR_480K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_BST_LOOPR_320K (3) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_320K_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LOOPR_320K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_BST_LOOPR_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_BST_LOOPR_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_LOOPR_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT) -+ -+/* default value of DFT3R (0x62) */ -+/* #define AW87XXX_PID_5A_REG_DFT3R_DEFAULT (0x02) */ -+ -+/* DFT4R (0x63) detail */ -+/* BST_BURST_IN_DELAY bit 7:6 (DFT4R 0x63) */ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT (6) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_8US (0) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_8US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_8US << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_12US (1) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_12US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_12US << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_4US (2) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_4US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_4US << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_2US (3) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_2US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_2US << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_BURST_IN_DELAY_START_BIT) -+ -+/* BST_BURST_OUT_DELAY bit 5:4 (DFT4R 0x63) */ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_2US (0) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_2US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_2US << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_4US (1) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_4US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_4US << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P3US (2) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P3US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P3US << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P0US (3) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P0US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_1P0US << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_BURST_OUT_DELAY_START_BIT) -+ -+/* BST_EN_DELAY bit 3:2 (DFT4R 0x63) */ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_EN_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_8NS (0) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_8NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_DELAY_8NS << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_80NS (1) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_80NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_DELAY_80NS << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_130NS (2) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_130NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_DELAY_130NS << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_200NS (3) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_200NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_DELAY_200NS << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_BST_EN_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_EN_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_EN_DELAY_START_BIT) -+ -+/* BST_GD_DELAY bit 1:0 (DFT4R 0x63) */ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_GD_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_1P2NS (0) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_1P2NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_1P2NS << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_2P5NS (1) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_2P5NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_1P2NS_LS_2P5NS << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_1P2NS (2) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_1P2NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_1P2NS << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_2P5NS (3) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_2P5NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GD_DELAY_HS_2P5NS_LS_2P5NS << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_GD_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_GD_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_GD_DELAY_START_BIT) -+ -+/* default value of DFT4R (0x63) */ -+/* #define AW87XXX_PID_5A_REG_DFT4R_DEFAULT (0x08) */ -+ -+/* DFT5R (0x64) detail */ -+/* PA_FLT_SR bit 7 (DFT5R 0x64) */ -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_START_BIT (7) -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_FLT_SR_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_FLT_SR_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_ENABLE (0) -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_FLT_SR_ENABLE << AW87XXX_PID_5A_REG_PA_FLT_SR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_DISABLE (1) -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_FLT_SR_DISABLE << AW87XXX_PID_5A_REG_PA_FLT_SR_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_FLT_SR_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_FLT_SR_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_FLT_SR_START_BIT) -+ -+/* AGC1_VTH_SEL bit 6:5 (DFT5R 0x64) */ -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT (5) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_AGC1_VTH_SEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN (0) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_THGEN (1) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_THGEN_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN (2) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN (3) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN_VALUE \ -+ (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT) -+ -+/* BST_OVP2_EN bit 4 (DFT5R 0x64) */ -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP2_EN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP2_EN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_DISABLE (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_EN_DISABLE << AW87XXX_PID_5A_REG_BST_OVP2_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_ENABLE (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_EN_ENABLE << AW87XXX_PID_5A_REG_BST_OVP2_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_EN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_EN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP2_EN_START_BIT) -+ -+/* BST_OVP2_ITH bit 3:2 (DFT5R 0x64) */ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP2_ITH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P5KOHM (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P5KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P5KOHM << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P25KOHM (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P25KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P25KOHM << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P167KOHM (2) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P167KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P167KOHM << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P125KOHM (3) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P125KOHM_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_ITH_PVDD0P125KOHM << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_ITH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_ITH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP2_ITH_START_BIT) -+ -+/* BST_OVP2_VTH bit 1:0 (DFT5R 0x64) */ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP2_VTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_13V_9V (0) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_13V_9V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_VTH_13V_9V << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_13P5V_9P5V (1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_13P5V_9P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_VTH_13P5V_9P5V << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_14V_10V (2) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_14V_10V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_VTH_14V_10V << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_14P5V_10P5V (3) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_14P5V_10P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_VTH_14P5V_10P5V << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_OVP2_VTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP2_VTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP2_VTH_START_BIT) -+ -+/* default value of DFT5R (0x64) */ -+/* #define AW87XXX_PID_5A_REG_DFT5R_DEFAULT (0x45) */ -+ -+/* DFT6R (0x65) detail */ -+/* POWER_SAVE_DLY_SELECT bit 7 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_START_BIT (7) -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_HIGH_VOLTAGE_TRIGGER (0) -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_HIGH_VOLTAGE_TRIGGER_VALUE \ -+ (AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_HIGH_VOLTAGE_TRIGGER << AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_CLK_RISING_EDGE_TRIGGER (1) -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_CLK_RISING_EDGE_TRIGGER_VALUE \ -+ (AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_CLK_RISING_EDGE_TRIGGER << AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_POWER_SAVE_DLY_SELECT_START_BIT) -+ -+/* PA_OPD bit 6 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_PA_OPD_START_BIT (6) -+#define AW87XXX_PID_5A_REG_PA_OPD_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_OPD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_OPD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_OPD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_FLOATING (0) -+#define AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_FLOATING_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_FLOATING << AW87XXX_PID_5A_REG_PA_OPD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_TIED_TO_GND (1) -+#define AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_TIED_TO_GND_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OPD_OUTPUT_TIED_TO_GND << AW87XXX_PID_5A_REG_PA_OPD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OPD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_PA_OPD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_OPD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_OPD_START_BIT) -+ -+/* CLK_OCP_SEL bit 5 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_START_BIT (5) -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_CLK_OCP_SEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_CLK_OCP_SEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_160MS (0) -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_160MS_VALUE \ -+ (AW87XXX_PID_5A_REG_CLK_OCP_SEL_160MS << AW87XXX_PID_5A_REG_CLK_OCP_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_640MS (1) -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_640MS_VALUE \ -+ (AW87XXX_PID_5A_REG_CLK_OCP_SEL_640MS << AW87XXX_PID_5A_REG_CLK_OCP_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_CLK_OCP_SEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_CLK_OCP_SEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_CLK_OCP_SEL_START_BIT) -+ -+/* BST_SKIP_EN bit 4 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SKIP_EN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SKIP_EN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_DISABLE (0) -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SKIP_EN_DISABLE << AW87XXX_PID_5A_REG_BST_SKIP_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_ENABLE (1) -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SKIP_EN_ENABLE << AW87XXX_PID_5A_REG_BST_SKIP_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_SKIP_EN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SKIP_EN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SKIP_EN_START_BIT) -+ -+/* BST_OVP_DEGLITCH_SEL bit 3 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_NO_DEGLITCH (0) -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_NO_DEGLITCH_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_NO_DEGLITCH << AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEGLITCH_300NS (1) -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEGLITCH_300NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEGLITCH_300NS << AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_OVP_DEGLITCH_SEL_START_BIT) -+ -+/* BST_NCD_ITH bit 2:1 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT (1) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_NCD_ITH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_150MA (0) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_150MA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_NCD_ITH_150MA << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_200MA (1) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_200MA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_NCD_ITH_200MA << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_250MA (2) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_250MA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_NCD_ITH_250MA << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_300MA (3) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_300MA_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_NCD_ITH_300MA << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_NCD_ITH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_NCD_ITH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_NCD_ITH_START_BIT) -+ -+/* BST_LMD_VTH bit 0 (DFT6R 0x65) */ -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_LMD_VTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_LMD_VTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_HIGH_SIDE_VDD (0) -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_HIGH_SIDE_VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LMD_VTH_HIGH_SIDE_VDD << AW87XXX_PID_5A_REG_BST_LMD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_LOW_SIDE_VDD (1) -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_LOW_SIDE_VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_LMD_VTH_LOW_SIDE_VDD << AW87XXX_PID_5A_REG_BST_LMD_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_LMD_VTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_LMD_VTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_LMD_VTH_START_BIT) -+ -+/* default value of DFT6R (0x65) */ -+/* #define AW87XXX_PID_5A_REG_DFT6R_DEFAULT (0x53) */ -+ -+/* DFT7R (0x66) detail */ -+ -+/* PA_OC_DT bit 4:3 (DFT7R 0x66) */ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT (3) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_OC_DT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_80NS (0) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_80NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_DT_80NS << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_150NS (1) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_150NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_DT_150NS << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_210NS (2) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_210NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_DT_210NS << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_240NS (3) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_240NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OC_DT_240NS << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OC_DT_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_PA_OC_DT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_OC_DT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_OC_DT_START_BIT) -+ -+/* PA_RAMP_AGC1 bit 2:1 (DFT7R 0x66) */ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT (1) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_RAMP_AGC1_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P8VDD (0) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P8VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P8VDD << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P825VDD (1) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P825VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P825VDD << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P85VDD (2) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P85VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P85VDD << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P875VDD (3) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P875VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_RAMP_AGC1_0P875VDD << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_RAMP_AGC1_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_RAMP_AGC1_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_RAMP_AGC1_START_BIT) -+ -+/* PA_OCSWD bit 0 (DFT7R 0x66) */ -+#define AW87XXX_PID_5A_REG_PA_OCSWD_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PA_OCSWD_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_OCSWD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_OCSWD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_OCSWD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_GATEDRIVER (0) -+#define AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_GATEDRIVER_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_GATEDRIVER << AW87XXX_PID_5A_REG_PA_OCSWD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_SWITCH_MOS (1) -+#define AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_SWITCH_MOS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_OCSWD_THROUGH_SWITCH_MOS << AW87XXX_PID_5A_REG_PA_OCSWD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_OCSWD_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_OCSWD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_OCSWD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_OCSWD_START_BIT) -+ -+/* default value of DFT7R (0x66) */ -+/* #define AW87XXX_PID_5A_REG_DFT7R_DEFAULT (0x70) */ -+ -+/* DFT8R (0x67) detail */ -+/* PA_GD_DELAY bit 7:6 (DFT8R 0x67) */ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT (6) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_GD_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_1P2NS (0) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_1P2NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_1P2NS << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_2P5NS (1) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_2P5NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_1P2NS_LS_2P5NS << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_1P2NS (2) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_1P2NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_1P2NS << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_2P5NS (3) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_2P5NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DELAY_HS_2P5NS_LS_2P5NS << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_GD_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_GD_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_GD_DELAY_START_BIT) -+ -+/* PA_GD_DGT bit 5 (DFT8R 0x67) */ -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_START_BIT (5) -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_GD_DGT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_GD_DGT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_4NS (0) -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_4NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DGT_4NS << AW87XXX_PID_5A_REG_PA_GD_DGT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_5P5NS (1) -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_5P5NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GD_DGT_5P5NS << AW87XXX_PID_5A_REG_PA_GD_DGT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_GD_DGT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_GD_DGT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_GD_DGT_START_BIT) -+ -+/* PA_PORT bit 4:3 (DFT8R 0x67) */ -+#define AW87XXX_PID_5A_REG_PA_PORT_START_BIT (3) -+#define AW87XXX_PID_5A_REG_PA_PORT_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PA_PORT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_PORT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_PORT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_PORT_80MS (0) -+#define AW87XXX_PID_5A_REG_PA_PORT_80MS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_PORT_80MS << AW87XXX_PID_5A_REG_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_PORT_40MS (1) -+#define AW87XXX_PID_5A_REG_PA_PORT_40MS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_PORT_40MS << AW87XXX_PID_5A_REG_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_PORT_20MS (2) -+#define AW87XXX_PID_5A_REG_PA_PORT_20MS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_PORT_20MS << AW87XXX_PID_5A_REG_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_PORT_10MS (3) -+#define AW87XXX_PID_5A_REG_PA_PORT_10MS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_PORT_10MS << AW87XXX_PID_5A_REG_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_PORT_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_PA_PORT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_PORT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_PORT_START_BIT) -+ -+/* EN_AGC1_ADP bit 2 (DFT8R 0x67) */ -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_START_BIT (2) -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_AGC1_ADP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_AGC1_ADP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE (0) -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE << AW87XXX_PID_5A_REG_EN_AGC1_ADP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY (1) -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY << AW87XXX_PID_5A_REG_EN_AGC1_ADP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_AGC1_ADP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_AGC1_ADP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_AGC1_ADP_START_BIT) -+ -+/* PD_CROSSZERO bit 1:0 (DFT8R 0x67) */ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PD_CROSSZERO_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO (0) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC2AGC3_CROSS_ZERO_DISABLE_AGC1_CROSS_ZERO (1) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC2AGC3_CROSS_ZERO_DISABLE_AGC1_CROSS_ZERO_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC2AGC3_CROSS_ZERO_DISABLE_AGC1_CROSS_ZERO << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC3_CROSS_ZERO_DISABLE_AGC1AGC2_CROSS_ZERO (2) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC3_CROSS_ZERO_DISABLE_AGC1AGC2_CROSS_ZERO_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_CROSSZERO_ENABLE_AGC3_CROSS_ZERO_DISABLE_AGC1AGC2_CROSS_ZERO << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_DISABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO (3) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_DISABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_CROSSZERO_DISABLE_AGC1AGC2_AND_AGC3_CROSS_ZERO << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PD_CROSSZERO_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PD_CROSSZERO_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PD_CROSSZERO_START_BIT) -+ -+/* default value of DFT8R (0x67) */ -+/* #define AW87XXX_PID_5A_REG_DFT8R_DEFAULT (0x08) */ -+ -+/* DFT9R (0x68) detail */ -+/* EN_BOOST_VCLAMP_SS bit 7 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_START_BIT (7) -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DISABLE << AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_ENABLE << AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_BOOST_VCLAMP_SS_START_BIT) -+ -+/* EN_BOOST_PLDO bit 6 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_START_BIT (6) -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_BOOST_PLDO_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_BOOST_PLDO_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_VDD (0) -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_VDD << AW87XXX_PID_5A_REG_EN_BOOST_PLDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_PVLDO (1) -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_PVLDO_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_PLDO_SET_PVLDO << AW87XXX_PID_5A_REG_EN_BOOST_PLDO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_BOOST_PLDO_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_BOOST_PLDO_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_BOOST_PLDO_START_BIT) -+ -+/* EN_CLAMP bit 5 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_EN_CLAMP_START_BIT (5) -+#define AW87XXX_PID_5A_REG_EN_CLAMP_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_CLAMP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_CLAMP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_CLAMP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_CLAMP_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_CLAMP_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_CLAMP_DISABLE << AW87XXX_PID_5A_REG_EN_CLAMP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_CLAMP_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_CLAMP_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_CLAMP_ENABLE << AW87XXX_PID_5A_REG_EN_CLAMP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_CLAMP_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_EN_CLAMP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_CLAMP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_CLAMP_START_BIT) -+ -+/* EN_VBG_PASS bit 4 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_START_BIT (4) -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_VBG_PASS_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_VBG_PASS_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_VBG_PASS_DISABLE << AW87XXX_PID_5A_REG_EN_VBG_PASS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_VBG_PASS_ENABLE << AW87XXX_PID_5A_REG_EN_VBG_PASS_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_VBG_PASS_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_VBG_PASS_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_VBG_PASS_START_BIT) -+ -+/* SS_SOFT_IPEAK_ADP bit 3 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_START_BIT (3) -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DISABLE (0) -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DISABLE << AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_ENABLE (1) -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_ENABLE << AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SS_SOFT_IPEAK_ADP_START_BIT) -+ -+/* EN_ADP_IPEAK bit 2 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_START_BIT (2) -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_ADP_IPEAK_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_ADP_IPEAK_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DISABLE << AW87XXX_PID_5A_REG_EN_ADP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_ADP_IPEAK_ENABLE << AW87XXX_PID_5A_REG_EN_ADP_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_ADP_IPEAK_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_ADP_IPEAK_START_BIT) -+ -+/* SEL_FINISH_ID bit 1 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_START_BIT (1) -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SEL_FINISH_ID_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SEL_FINISH_ID_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_MODE1_DELAY (0) -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_MODE1_DELAY_VALUE \ -+ (AW87XXX_PID_5A_REG_SEL_FINISH_ID_MODE1_DELAY << AW87XXX_PID_5A_REG_SEL_FINISH_ID_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_LIMIT_SS_FINISH (1) -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_LIMIT_SS_FINISH_VALUE \ -+ (AW87XXX_PID_5A_REG_SEL_FINISH_ID_LIMIT_SS_FINISH << AW87XXX_PID_5A_REG_SEL_FINISH_ID_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_SEL_FINISH_ID_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SEL_FINISH_ID_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SEL_FINISH_ID_START_BIT) -+ -+/* SS_FINISH_SELECTED bit 0 (DFT9R 0x68) */ -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_START_BIT (0) -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_3US (0) -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_3US_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_3US << AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_0US (1) -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_0US_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_0US << AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SS_FINISH_SELECTED_START_BIT) -+ -+/* default value of DFT9R (0x68) */ -+/* #define AW87XXX_PID_5A_REG_DFT9R_DEFAULT (0x21) */ -+ -+/* DFTAR (0x69) detail */ -+/* HWM_DELAY_INITIAL bit 7:6 (DFTAR 0x69) */ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT (6) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_104NS (0) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_104NS_VALUE \ -+ (AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_104NS << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_63NS (1) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_63NS_VALUE \ -+ (AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_63NS << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_56NS (2) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_56NS_VALUE \ -+ (AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_56NS << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_42NS (3) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_42NS_VALUE \ -+ (AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_42NS << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_HWM_DELAY_INITIAL_START_BIT) -+ -+/* BST_DFPWM bit 5:3 (DFTAR 0x69) */ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_DFPWM_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_2P5US (0) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_2P5US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_2P5US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_5US (1) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_5US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_5US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_10US (2) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_10US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_10US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_20US (3) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_20US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_20US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_40US (4) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_40US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_40US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_80US (5) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_80US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_80US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_160US (6) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_160US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_160US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_320US (7) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_320US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_320US << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_DFPWM_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_5A_REG_BST_DFPWM_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_DFPWM_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_DFPWM_START_BIT) -+ -+/* BST_SOFT_DELAY bit 2:0 (DFTAR 0x69) */ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SOFT_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_40US (0) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_40US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_40US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_80US (1) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_80US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_80US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_160US (2) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_160US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_160US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_320US (3) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_320US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_320US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_1280US (4) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_1280US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_1280US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_2560US (5) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_2560US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_2560US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_5120US (6) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_5120US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_5120US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_10240US (7) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_10240US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_10240US << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_5A_REG_BST_SOFT_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SOFT_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SOFT_DELAY_START_BIT) -+ -+/* default value of DFTAR (0x69) */ -+/* #define AW87XXX_PID_5A_REG_DFTAR_DEFAULT (0xA4) */ -+ -+/* DFTBR (0x70) detail */ -+/* BST_CLK_DIV bit 4 (DFTBR 0x70) */ -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_CLK_DIV_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_CLK_DIV_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_4 (0) -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_4_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_4 << AW87XXX_PID_5A_REG_BST_CLK_DIV_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_2 (1) -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_2_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_CLK_DIV_DIV_BY_2 << AW87XXX_PID_5A_REG_BST_CLK_DIV_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_CLK_DIV_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_CLK_DIV_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_CLK_DIV_START_BIT) -+ -+/* RAMP_1SPW_VC bit 3:2 (DFTBR 0x70) */ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT (2) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_RAMP_1SPW_VC_BITS_LEN)-1) << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P37VDD (0) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P37VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P37VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P39VDD (1) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P39VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P39VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P33VDD (2) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P33VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P33VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P35VDD (3) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P35VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VC_VC0P35VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VC_DEFAULT \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VC_DEFAULT_VALUE << AW87XXX_PID_5A_REG_RAMP_1SPW_VC_START_BIT) -+ -+/* RAMP_1SPW_VL bit 1:0 (DFTBR 0x70) */ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT (0) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_RAMP_1SPW_VL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P16VDD (0) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P16VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P16VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P18VDD (1) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P18VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P18VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P20VDD (2) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P20VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P20VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P14VDD (3) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P14VDD_VALUE \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VL_VC0P14VDD << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_RAMP_1SPW_VL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_RAMP_1SPW_VL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_RAMP_1SPW_VL_START_BIT) -+ -+/* default value of DFTBR (0x70) */ -+/* #define AW87XXX_PID_5A_REG_DFTBR_DEFAULT (0x1C) */ -+ -+/* DFTCR (0x71) detail */ -+/* DT_EN bit 7 (DFTCR 0x71) */ -+#define AW87XXX_PID_5A_REG_DT_EN_START_BIT (7) -+#define AW87XXX_PID_5A_REG_DT_EN_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_DT_EN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_DT_EN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_DT_EN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_DT_EN_DISABLE (0) -+#define AW87XXX_PID_5A_REG_DT_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_DT_EN_DISABLE << AW87XXX_PID_5A_REG_DT_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DT_EN_ENABLE (1) -+#define AW87XXX_PID_5A_REG_DT_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_DT_EN_ENABLE << AW87XXX_PID_5A_REG_DT_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DT_EN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_DT_EN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_DT_EN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_DT_EN_START_BIT) -+ -+/* BST_TD bit 6:4 (DFTCR 0x71) */ -+#define AW87XXX_PID_5A_REG_BST_TD_START_BIT (4) -+#define AW87XXX_PID_5A_REG_BST_TD_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_BST_TD_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_TD_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_TD_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_0P08MS (0) -+#define AW87XXX_PID_5A_REG_BST_TD_0P08MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_0P08MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_0P16MS (1) -+#define AW87XXX_PID_5A_REG_BST_TD_0P16MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_0P16MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_0P32MS (2) -+#define AW87XXX_PID_5A_REG_BST_TD_0P32MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_0P32MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_0P64MS (3) -+#define AW87XXX_PID_5A_REG_BST_TD_0P64MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_0P64MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_1P28MS (4) -+#define AW87XXX_PID_5A_REG_BST_TD_1P28MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_1P28MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_2P56MS (5) -+#define AW87XXX_PID_5A_REG_BST_TD_2P56MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_2P56MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_5P12MS (6) -+#define AW87XXX_PID_5A_REG_BST_TD_5P12MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_5P12MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_10P24MS (7) -+#define AW87XXX_PID_5A_REG_BST_TD_10P24MS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_TD_10P24MS << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_TD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_TD_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_TD_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_TD_START_BIT) -+ -+/* BST_GTDR_DDT bit 3 (DFTCR 0x71) */ -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_GTDR_DDT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_GTDR_DDT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_3NS (0) -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_3NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GTDR_DDT_3NS << AW87XXX_PID_5A_REG_BST_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_6NS (1) -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_6NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_GTDR_DDT_6NS << AW87XXX_PID_5A_REG_BST_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_GTDR_DDT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_GTDR_DDT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_GTDR_DDT_START_BIT) -+ -+/* BST_EN_RSQN_DLY bit 2 (DFTCR 0x71) */ -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_START_BIT (2) -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DISABLE (0) -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DISABLE << AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_ENABLE (1) -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_ENABLE << AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_EN_RSQN_DLY_START_BIT) -+ -+/* BST_RSQN_DLY bit 1:0 (DFTCR 0x71) */ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT (0) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_RSQN_DLY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_15NS (0) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_15NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_RSQN_DLY_15NS << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_25NS (1) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_25NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_RSQN_DLY_25NS << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_35NS (2) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_35NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_RSQN_DLY_35NS << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_45NS (3) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_45NS_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_RSQN_DLY_45NS << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_BST_RSQN_DLY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_RSQN_DLY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_RSQN_DLY_START_BIT) -+ -+/* default value of DFTCR (0x71) */ -+/* #define AW87XXX_PID_5A_REG_DFTCR_DEFAULT (0x10) */ -+ -+/* DFTDR (0x72) detail */ -+/* DLY_EN bit 7 (DFTDR 0x72) */ -+#define AW87XXX_PID_5A_REG_DLY_EN_START_BIT (7) -+#define AW87XXX_PID_5A_REG_DLY_EN_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_DLY_EN_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_DLY_EN_BITS_LEN)-1) << AW87XXX_PID_5A_REG_DLY_EN_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_DLY_EN_NO_DELAY (0) -+#define AW87XXX_PID_5A_REG_DLY_EN_NO_DELAY_VALUE \ -+ (AW87XXX_PID_5A_REG_DLY_EN_NO_DELAY << AW87XXX_PID_5A_REG_DLY_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DLY_EN_DELAY_TWO_CLOCK (1) -+#define AW87XXX_PID_5A_REG_DLY_EN_DELAY_TWO_CLOCK_VALUE \ -+ (AW87XXX_PID_5A_REG_DLY_EN_DELAY_TWO_CLOCK << AW87XXX_PID_5A_REG_DLY_EN_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DLY_EN_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_DLY_EN_DEFAULT \ -+ (AW87XXX_PID_5A_REG_DLY_EN_DEFAULT_VALUE << AW87XXX_PID_5A_REG_DLY_EN_START_BIT) -+ -+/* DOWNSIGNAL_SEL bit 6 (DFTDR 0x72) */ -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_START_BIT (6) -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_160MS (0) -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_160MS_VALUE \ -+ (AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_160MS << AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_640MS (1) -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_640MS_VALUE \ -+ (AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_SET_640MS << AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_DOWNSIGNAL_SEL_START_BIT) -+ -+/* BST_SLOPE_LIMIT bit 5:3 (DFTDR 0x72) */ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT (3) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_BITS_LEN (3) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0SLOPE (0) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P25SLOPE (1) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P25SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE (2) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE (3) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE (4) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE (5) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE (6) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P75SLOPE (7) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P75SLOPE_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P75SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT) -+ -+/* MODEL_START_DELAY bit 2:1 (DFTDR 0x72) */ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT (1) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_MODEL_START_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_20US (0) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_20US_VALUE \ -+ (AW87XXX_PID_5A_REG_MODEL_START_DELAY_20US << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_0US (1) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_0US_VALUE \ -+ (AW87XXX_PID_5A_REG_MODEL_START_DELAY_0US << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_5US (2) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_5US_VALUE \ -+ (AW87XXX_PID_5A_REG_MODEL_START_DELAY_5US << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_2P5US (3) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_2P5US_VALUE \ -+ (AW87XXX_PID_5A_REG_MODEL_START_DELAY_2P5US << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_MODEL_START_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_MODEL_START_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_MODEL_START_DELAY_START_BIT) -+ -+/* PEAK_LIMIT_SS_CAP bit 0 (DFTDR 0x72) */ -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_350FF (0) -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_350FF_VALUE \ -+ (AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_350FF << AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_0FF (1) -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_0FF_VALUE \ -+ (AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_0FF << AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PEAK_LIMIT_SS_CAP_START_BIT) -+ -+/* default value of DFTDR (0x72) */ -+/* #define AW87XXX_PID_5A_REG_DFTDR_DEFAULT (0xA0) */ -+ -+/* DFTER (0x73) detail */ -+/* BST_SS_TIME bit 7:6 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT (6) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_BST_SS_TIME_BITS_LEN)-1) << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_35US (0) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_35US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SS_TIME_35US << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_56US (1) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_56US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SS_TIME_56US << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_76US (2) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_76US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SS_TIME_76US << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_107US (3) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_107US_VALUE \ -+ (AW87XXX_PID_5A_REG_BST_SS_TIME_107US << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_BST_SS_TIME_DEFAULT \ -+ (AW87XXX_PID_5A_REG_BST_SS_TIME_DEFAULT_VALUE << AW87XXX_PID_5A_REG_BST_SS_TIME_START_BIT) -+ -+/* PD_UVLO bit 5 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_PD_UVLO_START_BIT (5) -+#define AW87XXX_PID_5A_REG_PD_UVLO_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PD_UVLO_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PD_UVLO_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PD_UVLO_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PD_UVLO_ENABLE (0) -+#define AW87XXX_PID_5A_REG_PD_UVLO_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_UVLO_ENABLE << AW87XXX_PID_5A_REG_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_UVLO_DISABLE (1) -+#define AW87XXX_PID_5A_REG_PD_UVLO_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_UVLO_DISABLE << AW87XXX_PID_5A_REG_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_UVLO_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PD_UVLO_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PD_UVLO_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PD_UVLO_START_BIT) -+ -+/* UVLO_VTH bit 4:3 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT (3) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_UVLO_VTH_BITS_LEN)-1) << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P6V_VL2P5V (0) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P6V_VL2P5V_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_VTH_VH2P6V_VL2P5V << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P7V_VL2P6V (1) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P7V_VL2P6V_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_VTH_VH2P7V_VL2P6V << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P8V_VL2P7V (2) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P8V_VL2P7V_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_VTH_VH2P8V_VL2P7V << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P9V_VL2P8V (3) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_VH2P9V_VL2P8V_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_VTH_VH2P9V_VL2P8V << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_VTH_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_5A_REG_UVLO_VTH_DEFAULT \ -+ (AW87XXX_PID_5A_REG_UVLO_VTH_DEFAULT_VALUE << AW87XXX_PID_5A_REG_UVLO_VTH_START_BIT) -+ -+/* UVLO_DT bit 2 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_UVLO_DT_START_BIT (2) -+#define AW87XXX_PID_5A_REG_UVLO_DT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_UVLO_DT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_UVLO_DT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_UVLO_DT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_UVLO_DT_3US (0) -+#define AW87XXX_PID_5A_REG_UVLO_DT_3US_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_DT_3US << AW87XXX_PID_5A_REG_UVLO_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_DT_10US (1) -+#define AW87XXX_PID_5A_REG_UVLO_DT_10US_VALUE \ -+ (AW87XXX_PID_5A_REG_UVLO_DT_10US << AW87XXX_PID_5A_REG_UVLO_DT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_UVLO_DT_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_5A_REG_UVLO_DT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_UVLO_DT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_UVLO_DT_START_BIT) -+ -+/* OC_DISABLE bit 1 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_OC_DISABLE_START_BIT (1) -+#define AW87XXX_PID_5A_REG_OC_DISABLE_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_OC_DISABLE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_OC_DISABLE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_OC_DISABLE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_OC_DISABLE_ENABLE (0) -+#define AW87XXX_PID_5A_REG_OC_DISABLE_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_OC_DISABLE_ENABLE << AW87XXX_PID_5A_REG_OC_DISABLE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OC_DISABLE_SHUTDOWN (1) -+#define AW87XXX_PID_5A_REG_OC_DISABLE_SHUTDOWN_VALUE \ -+ (AW87XXX_PID_5A_REG_OC_DISABLE_SHUTDOWN << AW87XXX_PID_5A_REG_OC_DISABLE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_OC_DISABLE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_OC_DISABLE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_OC_DISABLE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_OC_DISABLE_START_BIT) -+ -+/* PD_OT bit 0 (DFTER 0x73) */ -+#define AW87XXX_PID_5A_REG_PD_OT_START_BIT (0) -+#define AW87XXX_PID_5A_REG_PD_OT_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_PD_OT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PD_OT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PD_OT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PD_OT_ENABLE (0) -+#define AW87XXX_PID_5A_REG_PD_OT_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_OT_ENABLE << AW87XXX_PID_5A_REG_PD_OT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_OT_SHUTDOWN (1) -+#define AW87XXX_PID_5A_REG_PD_OT_SHUTDOWN_VALUE \ -+ (AW87XXX_PID_5A_REG_PD_OT_SHUTDOWN << AW87XXX_PID_5A_REG_PD_OT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PD_OT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PD_OT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PD_OT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PD_OT_START_BIT) -+ -+/* default value of DFTER (0x73) */ -+/* #define AW87XXX_PID_5A_REG_DFTER_DEFAULT (0x54) */ -+ -+/* DFTFR (0x74) detail */ -+/* EN_SWF bit 6 (DFTFR 0x74) */ -+#define AW87XXX_PID_5A_REG_EN_SWF_START_BIT (6) -+#define AW87XXX_PID_5A_REG_EN_SWF_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_SWF_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_SWF_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_SWF_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_SWF_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_SWF_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_SWF_DISABLE << AW87XXX_PID_5A_REG_EN_SWF_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_SWF_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_SWF_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_SWF_ENABLE << AW87XXX_PID_5A_REG_EN_SWF_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_SWF_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_SWF_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_SWF_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_SWF_START_BIT) -+ -+/* SS_CONTROL bit 5:4 (DFTFR 0x74) */ -+#define AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT (4) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_SS_CONTROL_BITS_LEN)-1) << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SPREAD_SPECTRUM (0) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SPREAD_SPECTRUM_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_CONTROL_SPREAD_SPECTRUM << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 (1) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20000 (2) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20000_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_CONTROL_SW20000 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT) -+/* -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 (3) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111_VALUE \ -+ (AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT) -+*/ -+#define AW87XXX_PID_5A_REG_SS_CONTROL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_SS_CONTROL_DEFAULT \ -+ (AW87XXX_PID_5A_REG_SS_CONTROL_DEFAULT_VALUE << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT) -+ -+/* PA_GTDR_DDT bit 3:2 (DFTFR 0x74) */ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT (2) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_BITS_LEN (2) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_PA_GTDR_DDT_BITS_LEN)-1) << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_12NS (0) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_12NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GTDR_DDT_12NS << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_13NS (1) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_13NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GTDR_DDT_13NS << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_14NS (2) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_14NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GTDR_DDT_14NS << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_15NS (3) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_15NS_VALUE \ -+ (AW87XXX_PID_5A_REG_PA_GTDR_DDT_15NS << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_PA_GTDR_DDT_DEFAULT \ -+ (AW87XXX_PID_5A_REG_PA_GTDR_DDT_DEFAULT_VALUE << AW87XXX_PID_5A_REG_PA_GTDR_DDT_START_BIT) -+ -+/* EN_HWM_DELAY bit 1 (DFTFR 0x74) */ -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_START_BIT (1) -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_HWM_DELAY_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_HWM_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HWM_DELAY_DISABLE << AW87XXX_PID_5A_REG_EN_HWM_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HWM_DELAY_ENABLE << AW87XXX_PID_5A_REG_EN_HWM_DELAY_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_HWM_DELAY_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_HWM_DELAY_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_HWM_DELAY_START_BIT) -+ -+/* EN_HW_MODE bit 0 (DFTFR 0x74) */ -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_START_BIT (0) -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_BITS_LEN (1) -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_5A_REG_EN_HW_MODE_BITS_LEN)-1) << AW87XXX_PID_5A_REG_EN_HW_MODE_START_BIT)) -+ -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_DISABLE (0) -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HW_MODE_DISABLE << AW87XXX_PID_5A_REG_EN_HW_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_ENABLE (1) -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_5A_REG_EN_HW_MODE_ENABLE << AW87XXX_PID_5A_REG_EN_HW_MODE_START_BIT) -+ -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_5A_REG_EN_HW_MODE_DEFAULT \ -+ (AW87XXX_PID_5A_REG_EN_HW_MODE_DEFAULT_VALUE << AW87XXX_PID_5A_REG_EN_HW_MODE_START_BIT) -+ -+/* default value of DFTFR (0x74) */ -+/* #define AW87XXX_PID_5A_REG_DFTFR_DEFAULT (0x00) */ -+ -+/* detail information of registers end */ -+ -+#endif /* #ifndef __AW87XXX_PID_5A_REG_H__ */ -\ No newline at end of file -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h -new file mode 100644 -index 000000000..b878aad8c ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h -@@ -0,0 +1,5246 @@ -+#ifndef __AW87XXX_PID_60_REG_H__ -+#define __AW87XXX_PID_60_REG_H__ -+ -+/* registers list */ -+#define AW87XXX_PID_60_ID_REG (0x00) -+#define AW87XXX_PID_60_SYSCTRL_REG (0x01) -+#define AW87XXX_PID_60_BSTOVR_REG (0x02) -+#define AW87XXX_PID_60_PEAKLIMIT_REG (0x03) -+#define AW87XXX_PID_60_ADPSET_REG (0x04) -+#define AW87XXX_PID_60_PAG_REG (0x05) -+#define AW87XXX_PID_60_AGC1PA_REG (0x06) -+#define AW87XXX_PID_60_AGC2PA_REG (0x07) -+#define AW87XXX_PID_60_AGC3PA_REG (0x08) -+#define AW87XXX_PID_60_AGC3P_REG (0x09) -+#define AW87XXX_PID_60_LOW_BAT_REG (0x0A) -+#define AW87XXX_PID_60_BSTOUT_REG (0x0B) -+#define AW87XXX_PID_60_SYSST_REG (0x59) -+#define AW87XXX_PID_60_SYSINT_REG (0x60) -+#define AW87XXX_PID_60_BURST_CON_REG (0x61) -+#define AW87XXX_PID_60_BST_BIAS_REG (0x62) -+#define AW87XXX_PID_60_BST_EA_REG (0x63) -+#define AW87XXX_PID_60_BST_DE_SOFT_REG (0x64) -+#define AW87XXX_PID_60_BST_BURST_KICK_REG (0x65) -+#define AW87XXX_PID_60_BST_CON1_REG (0x66) -+#define AW87XXX_PID_60_BST_OVP_REG (0x67) -+#define AW87XXX_PID_60_LINE_MODE_REG (0x68) -+#define AW87XXX_PID_60_BST_ISEN_REG (0x69) -+#define AW87XXX_PID_60_BST_PEAK_REG (0x6A) -+#define AW87XXX_PID_60_BST_PEAK2_REG (0x6B) -+#define AW87XXX_PID_60_OFFTIME_REG (0x6C) -+#define AW87XXX_PID_60_ADPBST_REG (0x6D) -+#define AW87XXX_PID_60_OTA_REG (0x6E) -+#define AW87XXX_PID_60_RAMPGEN_REG (0x6F) -+#define AW87XXX_PID_60_CLASSD_SYSCTRL_REG (0x70) -+#define AW87XXX_PID_60_GTDR_REG (0x71) -+#define AW87XXX_PID_60_OC_REG (0x72) -+#define AW87XXX_PID_60_AGC_CON_REG (0x73) -+#define AW87XXX_PID_60_NG_REG (0x74) -+#define AW87XXX_PID_60_NG2_REG (0x75) -+#define AW87XXX_PID_60_NG3_REG (0x76) -+#define AW87XXX_PID_60_CP_REG (0x77) -+#define AW87XXX_PID_60_TEST_GTDR_REG (0x78) -+#define AW87XXX_PID_60_TEST_BST_REG (0x79) -+#define AW87XXX_PID_60_TEST_MODE_REG (0x7A) -+#define AW87XXX_PID_60_TEST_CON_REG (0x7B) -+#define AW87XXX_PID_60_ENCR_REG (0x7C) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_60_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_60_REG_MAX (0x7D) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+#define AW87XXX_PID_60_ESD_REG_VAL (0x91) -+ -+const unsigned char aw87xxx_pid_60_reg_access[AW87XXX_PID_60_REG_MAX] = { -+ [AW87XXX_PID_60_ID_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_60_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BSTOVR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_PEAKLIMIT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_ADPSET_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_PAG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_AGC1PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_AGC2PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_AGC3PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_AGC3P_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_LOW_BAT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BSTOUT_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_60_SYSST_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_60_SYSINT_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_60_BURST_CON_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_BIAS_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_EA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_DE_SOFT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_BURST_KICK_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_CON1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_OVP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_LINE_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_ISEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_PEAK_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_BST_PEAK2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_OFFTIME_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_ADPBST_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_OTA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_RAMPGEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_CLASSD_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_GTDR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_OC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_AGC_CON_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_NG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_NG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_NG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_TEST_GTDR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_TEST_BST_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_TEST_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_TEST_CON_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_60_ENCR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+/* detail information of registers begin */ -+/* ID (0x00) detail */ -+/* IDCODE bit 7:0 (ID 0x00) */ -+#define AW87XXX_PID_60_IDCODE_START_BIT (0) -+#define AW87XXX_PID_60_IDCODE_BITS_LEN (8) -+#define AW87XXX_PID_60_IDCODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_IDCODE_BITS_LEN)-1) << AW87XXX_PID_60_IDCODE_START_BIT)) -+ -+#define AW87XXX_PID_60_IDCODE_DEFAULT_VALUE (0x60) -+#define AW87XXX_PID_60_IDCODE_DEFAULT \ -+ (AW87XXX_PID_60_IDCODE_DEFAULT_VALUE << AW87XXX_PID_60_IDCODE_START_BIT) -+ -+/* default value of ID (0x00) */ -+/* #define AW87XXX_PID_60_ID_DEFAULT (0x60) */ -+ -+/* SYSCTRL (0x01) detail */ -+/* EN_HVBAT bit 0 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_EN_HVBAT_START_BIT (0) -+#define AW87XXX_PID_60_EN_HVBAT_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_HVBAT_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_HVBAT_BITS_LEN)-1) << AW87XXX_PID_60_EN_HVBAT_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_HVBAT_DISABLE (0) -+#define AW87XXX_PID_60_EN_HVBAT_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_HVBAT_DISABLE << AW87XXX_PID_60_EN_HVBAT_START_BIT) -+ -+#define AW87XXX_PID_60_EN_HVBAT_ENABLE (1) -+#define AW87XXX_PID_60_EN_HVBAT_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_HVBAT_ENABLE << AW87XXX_PID_60_EN_HVBAT_START_BIT) -+ -+#define AW87XXX_PID_60_EN_HVBAT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_HVBAT_DEFAULT \ -+ (AW87XXX_PID_60_EN_HVBAT_DEFAULT_VALUE << AW87XXX_PID_60_EN_HVBAT_START_BIT) -+ -+/* RCV_MODE bit 1 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_RCV_MODE_START_BIT (1) -+#define AW87XXX_PID_60_RCV_MODE_BITS_LEN (1) -+#define AW87XXX_PID_60_RCV_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_RCV_MODE_BITS_LEN)-1) << AW87XXX_PID_60_RCV_MODE_START_BIT)) -+ -+#define AW87XXX_PID_60_RCV_MODE_DISABLE (0) -+#define AW87XXX_PID_60_RCV_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_60_RCV_MODE_DISABLE << AW87XXX_PID_60_RCV_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_RCV_MODE_ENABLE (1) -+#define AW87XXX_PID_60_RCV_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_RCV_MODE_ENABLE << AW87XXX_PID_60_RCV_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_RCV_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_RCV_MODE_DEFAULT \ -+ (AW87XXX_PID_60_RCV_MODE_DEFAULT_VALUE << AW87XXX_PID_60_RCV_MODE_START_BIT) -+ -+/* EN_PA bit 2 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_EN_PA_START_BIT (2) -+#define AW87XXX_PID_60_EN_PA_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_PA_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_PA_BITS_LEN)-1) << AW87XXX_PID_60_EN_PA_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_PA_DISABLE (0) -+#define AW87XXX_PID_60_EN_PA_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_PA_DISABLE << AW87XXX_PID_60_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_60_EN_PA_ENABLE (1) -+#define AW87XXX_PID_60_EN_PA_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_PA_ENABLE << AW87XXX_PID_60_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_60_EN_PA_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_EN_PA_DEFAULT \ -+ (AW87XXX_PID_60_EN_PA_DEFAULT_VALUE << AW87XXX_PID_60_EN_PA_START_BIT) -+ -+/* EN_BOOST bit 3 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_EN_BOOST_START_BIT (3) -+#define AW87XXX_PID_60_EN_BOOST_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_BOOST_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_BOOST_BITS_LEN)-1) << AW87XXX_PID_60_EN_BOOST_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_BOOST_DISABLE (0) -+#define AW87XXX_PID_60_EN_BOOST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_BOOST_DISABLE << AW87XXX_PID_60_EN_BOOST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_BOOST_ENABLE (1) -+#define AW87XXX_PID_60_EN_BOOST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_BOOST_ENABLE << AW87XXX_PID_60_EN_BOOST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_BOOST_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_EN_BOOST_DEFAULT \ -+ (AW87XXX_PID_60_EN_BOOST_DEFAULT_VALUE << AW87XXX_PID_60_EN_BOOST_START_BIT) -+ -+/* EN_CP bit 4 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_EN_CP_START_BIT (4) -+#define AW87XXX_PID_60_EN_CP_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_CP_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_CP_BITS_LEN)-1) << AW87XXX_PID_60_EN_CP_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_CP_DISABLE (0) -+#define AW87XXX_PID_60_EN_CP_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_CP_DISABLE << AW87XXX_PID_60_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_60_EN_CP_ENABLE (1) -+#define AW87XXX_PID_60_EN_CP_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_CP_ENABLE << AW87XXX_PID_60_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_60_EN_CP_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_EN_CP_DEFAULT \ -+ (AW87XXX_PID_60_EN_CP_DEFAULT_VALUE << AW87XXX_PID_60_EN_CP_START_BIT) -+ -+/* EN_SW bit 5 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_60_EN_SW_START_BIT (5) -+#define AW87XXX_PID_60_EN_SW_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_SW_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_SW_BITS_LEN)-1) << AW87XXX_PID_60_EN_SW_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_SW_DISABLE (0) -+#define AW87XXX_PID_60_EN_SW_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_SW_DISABLE << AW87XXX_PID_60_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_60_EN_SW_ENABLE (1) -+#define AW87XXX_PID_60_EN_SW_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_SW_ENABLE << AW87XXX_PID_60_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_60_EN_SW_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_SW_DEFAULT \ -+ (AW87XXX_PID_60_EN_SW_DEFAULT_VALUE << AW87XXX_PID_60_EN_SW_START_BIT) -+ -+/* default value of SYSCTRL (0x01) */ -+/* #define AW87XXX_PID_60_SYSCTRL_DEFAULT (0x1C) */ -+ -+/* BSTOVR (0x02) detail */ -+/* CP_FREQ bit 6:5 (BSTOVR 0x02) */ -+#define AW87XXX_PID_60_CP_FREQ_START_BIT (5) -+#define AW87XXX_PID_60_CP_FREQ_BITS_LEN (2) -+#define AW87XXX_PID_60_CP_FREQ_MASK \ -+ (~(((1<<AW87XXX_PID_60_CP_FREQ_BITS_LEN)-1) << AW87XXX_PID_60_CP_FREQ_START_BIT)) -+ -+#define AW87XXX_PID_60_CP_FREQ_4P8MHZ (0) -+#define AW87XXX_PID_60_CP_FREQ_4P8MHZ_VALUE \ -+ (AW87XXX_PID_60_CP_FREQ_4P8MHZ << AW87XXX_PID_60_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_60_CP_FREQ_6P4MHZ (1) -+#define AW87XXX_PID_60_CP_FREQ_6P4MHZ_VALUE \ -+ (AW87XXX_PID_60_CP_FREQ_6P4MHZ << AW87XXX_PID_60_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_60_CP_FREQ_8P0MHZ (2) -+#define AW87XXX_PID_60_CP_FREQ_8P0MHZ_VALUE \ -+ (AW87XXX_PID_60_CP_FREQ_8P0MHZ << AW87XXX_PID_60_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_60_CP_FREQ_9P6MHZ (3) -+#define AW87XXX_PID_60_CP_FREQ_9P6MHZ_VALUE \ -+ (AW87XXX_PID_60_CP_FREQ_9P6MHZ << AW87XXX_PID_60_CP_FREQ_START_BIT) -+ -+#define AW87XXX_PID_60_CP_FREQ_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_CP_FREQ_DEFAULT \ -+ (AW87XXX_PID_60_CP_FREQ_DEFAULT_VALUE << AW87XXX_PID_60_CP_FREQ_START_BIT) -+ -+/* BST_VOUT bit 4:0 (BSTOVR 0x02) */ -+#define AW87XXX_PID_60_BST_VOUT_START_BIT (0) -+#define AW87XXX_PID_60_BST_VOUT_BITS_LEN (5) -+#define AW87XXX_PID_60_BST_VOUT_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_VOUT_BITS_LEN)-1) << AW87XXX_PID_60_BST_VOUT_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_VOUT_4P75V (0) -+#define AW87XXX_PID_60_BST_VOUT_4P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_4P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_5P0V (1) -+#define AW87XXX_PID_60_BST_VOUT_5P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_5P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_5P25V (2) -+#define AW87XXX_PID_60_BST_VOUT_5P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_5P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_5P5V (3) -+#define AW87XXX_PID_60_BST_VOUT_5P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_5P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_5P75V (4) -+#define AW87XXX_PID_60_BST_VOUT_5P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_5P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_6P0V (5) -+#define AW87XXX_PID_60_BST_VOUT_6P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_6P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_6P25V (6) -+#define AW87XXX_PID_60_BST_VOUT_6P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_6P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_6P5V (7) -+#define AW87XXX_PID_60_BST_VOUT_6P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_6P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_6P75V (8) -+#define AW87XXX_PID_60_BST_VOUT_6P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_6P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_7P0V (9) -+#define AW87XXX_PID_60_BST_VOUT_7P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_7P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_7P25V (10) -+#define AW87XXX_PID_60_BST_VOUT_7P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_7P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_7P5V (11) -+#define AW87XXX_PID_60_BST_VOUT_7P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_7P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_7P75V (12) -+#define AW87XXX_PID_60_BST_VOUT_7P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_7P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_8P0V (13) -+#define AW87XXX_PID_60_BST_VOUT_8P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_8P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_8P25V (14) -+#define AW87XXX_PID_60_BST_VOUT_8P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_8P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_8P5V (15) -+#define AW87XXX_PID_60_BST_VOUT_8P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_8P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_8P75V (16) -+#define AW87XXX_PID_60_BST_VOUT_8P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_8P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_9P0V (17) -+#define AW87XXX_PID_60_BST_VOUT_9P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_9P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_9P25V (18) -+#define AW87XXX_PID_60_BST_VOUT_9P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_9P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_9P5V (19) -+#define AW87XXX_PID_60_BST_VOUT_9P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_9P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_9P75V (20) -+#define AW87XXX_PID_60_BST_VOUT_9P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_9P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_10P0V (21) -+#define AW87XXX_PID_60_BST_VOUT_10P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_10P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_10P25V (22) -+#define AW87XXX_PID_60_BST_VOUT_10P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_10P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_10P5V (23) -+#define AW87XXX_PID_60_BST_VOUT_10P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_10P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_10P75V (24) -+#define AW87XXX_PID_60_BST_VOUT_10P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_10P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_11P0V (25) -+#define AW87XXX_PID_60_BST_VOUT_11P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_11P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_11P25V (26) -+#define AW87XXX_PID_60_BST_VOUT_11P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_11P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_11P5V (27) -+#define AW87XXX_PID_60_BST_VOUT_11P5V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_11P5V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_11P75V (28) -+#define AW87XXX_PID_60_BST_VOUT_11P75V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_11P75V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_12P0V (29) -+#define AW87XXX_PID_60_BST_VOUT_12P0V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_12P0V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_12P25V (30) -+#define AW87XXX_PID_60_BST_VOUT_12P25V_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_12P25V << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_DEFAULT_VALUE (0x11) -+#define AW87XXX_PID_60_BST_VOUT_DEFAULT \ -+ (AW87XXX_PID_60_BST_VOUT_DEFAULT_VALUE << AW87XXX_PID_60_BST_VOUT_START_BIT) -+ -+/* default value of BSTOVR (0x02) */ -+/* #define AW87XXX_PID_60_BSTOVR_DEFAULT (0x31) */ -+ -+/* PEAKLIMIT (0x03) detail */ -+/* BST_OVP2_VTH bit 6:4 (PEAKLIMIT 0x03) */ -+#define AW87XXX_PID_60_BST_OVP2_VTH_START_BIT (4) -+#define AW87XXX_PID_60_BST_OVP2_VTH_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_OVP2_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP2_VTH_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_13P5V (0) -+#define AW87XXX_PID_60_BST_OVP2_VTH_13P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_13P5V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_14P0 (1) -+#define AW87XXX_PID_60_BST_OVP2_VTH_14P0_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_14P0 << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_14P5V (2) -+#define AW87XXX_PID_60_BST_OVP2_VTH_14P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_14P5V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_15P0V (3) -+#define AW87XXX_PID_60_BST_OVP2_VTH_15P0V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_15P0V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_9P0V (4) -+#define AW87XXX_PID_60_BST_OVP2_VTH_9P0V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_9P0V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_9P5V (5) -+#define AW87XXX_PID_60_BST_OVP2_VTH_9P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_9P5V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_10P0V (6) -+#define AW87XXX_PID_60_BST_OVP2_VTH_10P0V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_10P0V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_10P5V (7) -+#define AW87XXX_PID_60_BST_OVP2_VTH_10P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_10P5V << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_VTH_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_OVP2_VTH_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP2_VTH_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP2_VTH_START_BIT) -+ -+/* BST_IPEAK bit 3:0 (PEAKLIMIT 0x03) */ -+#define AW87XXX_PID_60_BST_IPEAK_START_BIT (0) -+#define AW87XXX_PID_60_BST_IPEAK_BITS_LEN (4) -+#define AW87XXX_PID_60_BST_IPEAK_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_1P5A (0) -+#define AW87XXX_PID_60_BST_IPEAK_1P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_1P5A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_1P75A (1) -+#define AW87XXX_PID_60_BST_IPEAK_1P75A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_1P75A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_2P0A (2) -+#define AW87XXX_PID_60_BST_IPEAK_2P0A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_2P0A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_2P25A (3) -+#define AW87XXX_PID_60_BST_IPEAK_2P25A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_2P25A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_2P5A (4) -+#define AW87XXX_PID_60_BST_IPEAK_2P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_2P5A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_2P75A (5) -+#define AW87XXX_PID_60_BST_IPEAK_2P75A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_2P75A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_3P0A (6) -+#define AW87XXX_PID_60_BST_IPEAK_3P0A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_3P0A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_3P25A (7) -+#define AW87XXX_PID_60_BST_IPEAK_3P25A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_3P25A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_3P5A (8) -+#define AW87XXX_PID_60_BST_IPEAK_3P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_3P5A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_3P75A (9) -+#define AW87XXX_PID_60_BST_IPEAK_3P75A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_3P75A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_4A (10) -+#define AW87XXX_PID_60_BST_IPEAK_4A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_4A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_4P25A (11) -+#define AW87XXX_PID_60_BST_IPEAK_4P25A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_4P25A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_4P50A (12) -+#define AW87XXX_PID_60_BST_IPEAK_4P50A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_4P50A << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_DEFAULT_VALUE (9) -+#define AW87XXX_PID_60_BST_IPEAK_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_START_BIT) -+ -+/* default value of PEAKLIMIT (0x03) */ -+/* #define AW87XXX_PID_60_PEAKLIMIT_DEFAULT (0x09) */ -+ -+/* ADPSET (0x04) detail */ -+/* EN_ADP_BST bit 6 (ADPSET 0x04) */ -+#define AW87XXX_PID_60_EN_ADP_BST_START_BIT (6) -+#define AW87XXX_PID_60_EN_ADP_BST_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_ADP_BST_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_ADP_BST_BITS_LEN)-1) << AW87XXX_PID_60_EN_ADP_BST_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_ADP_BST_DISABLE (0) -+#define AW87XXX_PID_60_EN_ADP_BST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_BST_DISABLE << AW87XXX_PID_60_EN_ADP_BST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_BST_ENABLE (1) -+#define AW87XXX_PID_60_EN_ADP_BST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_BST_ENABLE << AW87XXX_PID_60_EN_ADP_BST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_BST_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_EN_ADP_BST_DEFAULT \ -+ (AW87XXX_PID_60_EN_ADP_BST_DEFAULT_VALUE << AW87XXX_PID_60_EN_ADP_BST_START_BIT) -+ -+/* ADP_BOOST_MODE bit 5:3 (ADPSET 0x04) */ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT (3) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_BITS_LEN (3) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_ADP_BOOST_MODE_BITS_LEN)-1) << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT)) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_RCV (0) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_RCV_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_RCV << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_FORCE_BOOST (1) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_FORCE_BOOST_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_FORCE_BOOST << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_OSBOSD (2) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_OSBOSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_OSBOSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_TSBTSD (3) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_TSBTSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_TSBTSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_TSBOSD (4) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_TSBOSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_TSBOSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBOSD (5) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBOSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_MSBOSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBTSD (6) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBTSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_MSBTSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBMSD (7) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_MSBMSD_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_MSBMSD << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_MODE_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_ADP_BOOST_MODE_DEFAULT \ -+ (AW87XXX_PID_60_ADP_BOOST_MODE_DEFAULT_VALUE << AW87XXX_PID_60_ADP_BOOST_MODE_START_BIT) -+ -+/* SET_BOOST_VTH2 bit 2:0 (ADPSET 0x04) */ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT (0) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_BITS_LEN (3) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_MASK \ -+ (~(((1<<AW87XXX_PID_60_SET_BOOST_VTH2_BITS_LEN)-1) << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT)) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P2W (0) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P2W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_1P2W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P4W (1) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P4W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_1P4W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P6W (2) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P6W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_1P6W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P8W (3) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_1P8W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_1P8W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P0W (4) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P0W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_2P0W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P2W (5) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P2W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_2P2W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P4W (6) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P4W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_2P4W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P6W (7) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_2P6W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_2P6W << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH2_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_60_SET_BOOST_VTH2_DEFAULT \ -+ (AW87XXX_PID_60_SET_BOOST_VTH2_DEFAULT_VALUE << AW87XXX_PID_60_SET_BOOST_VTH2_START_BIT) -+ -+/* default value of ADPSET (0x04) */ -+/* #define AW87XXX_PID_60_ADPSET_DEFAULT (0x54) */ -+ -+/* PAG (0x05) detail */ -+/* SET_BOOST_VTH1 bit 6:5 (PAG 0x05) */ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT (5) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_BITS_LEN (2) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_MASK \ -+ (~(((1<<AW87XXX_PID_60_SET_BOOST_VTH1_BITS_LEN)-1) << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT)) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P1W (0) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P1W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH1_0P1W << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P2W (1) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P2W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH1_0P2W << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P3W (2) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P3W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH1_0P3W << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P4W (3) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_0P4W_VALUE \ -+ (AW87XXX_PID_60_SET_BOOST_VTH1_0P4W << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT) -+ -+#define AW87XXX_PID_60_SET_BOOST_VTH1_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_SET_BOOST_VTH1_DEFAULT \ -+ (AW87XXX_PID_60_SET_BOOST_VTH1_DEFAULT_VALUE << AW87XXX_PID_60_SET_BOOST_VTH1_START_BIT) -+ -+/* PA_GAIN bit 4:0 (PAG 0x05) */ -+#define AW87XXX_PID_60_PA_GAIN_START_BIT (0) -+#define AW87XXX_PID_60_PA_GAIN_BITS_LEN (5) -+#define AW87XXX_PID_60_PA_GAIN_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_GAIN_BITS_LEN)-1) << AW87XXX_PID_60_PA_GAIN_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_GAIN_0DB (0) -+#define AW87XXX_PID_60_PA_GAIN_0DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_0DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_1P5DB (1) -+#define AW87XXX_PID_60_PA_GAIN_1P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_1P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_3DB (2) -+#define AW87XXX_PID_60_PA_GAIN_3DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_3DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_4P5DB (3) -+#define AW87XXX_PID_60_PA_GAIN_4P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_4P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_6DB (4) -+#define AW87XXX_PID_60_PA_GAIN_6DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_6DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_7P5DB (5) -+#define AW87XXX_PID_60_PA_GAIN_7P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_7P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_9DB (6) -+#define AW87XXX_PID_60_PA_GAIN_9DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_9DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_10P5DB (7) -+#define AW87XXX_PID_60_PA_GAIN_10P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_10P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_12DB (8) -+#define AW87XXX_PID_60_PA_GAIN_12DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_12DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_13P5DB (9) -+#define AW87XXX_PID_60_PA_GAIN_13P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_13P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_15DB (10) -+#define AW87XXX_PID_60_PA_GAIN_15DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_15DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_16P5DB (11) -+#define AW87XXX_PID_60_PA_GAIN_16P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_16P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_18DB (12) -+#define AW87XXX_PID_60_PA_GAIN_18DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_18DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_19P5DB (13) -+#define AW87XXX_PID_60_PA_GAIN_19P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_19P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_21DB (14) -+#define AW87XXX_PID_60_PA_GAIN_21DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_21DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_22P5DB (15) -+#define AW87XXX_PID_60_PA_GAIN_22P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_22P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_24DB (16) -+#define AW87XXX_PID_60_PA_GAIN_24DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_24DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_25P5DB (17) -+#define AW87XXX_PID_60_PA_GAIN_25P5DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_25P5DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GAIN_27DB (18) -+#define AW87XXX_PID_60_PA_GAIN_27DB_VALUE \ -+ (AW87XXX_PID_60_PA_GAIN_27DB << AW87XXX_PID_60_PA_GAIN_START_BIT) -+/* -+Fix me here: -+reg_addr:0x05, reg_name:PAG, field_name:PA_GAIN, content:when RCV_MODE=0??PA_GAIN default?? 10000 -+maybe need to fix manually -+*/ -+#define AW87XXX_PID_60_PA_GAIN_DEFAULT_VALUE (0x10) -+#define AW87XXX_PID_60_PA_GAIN_DEFAULT \ -+ (AW87XXX_PID_60_PA_GAIN_DEFAULT_VALUE << AW87XXX_PID_60_PA_GAIN_START_BIT) -+ -+/* default value of PAG (0x05) */ -+/* #define AW87XXX_PID_60_PAG_DEFAULT (0x50) */ -+ -+/* AGC1PA (0x06) detail */ -+/* PD_AGC1 bit 7 (AGC1PA 0x06) */ -+#define AW87XXX_PID_60_PD_AGC1_START_BIT (7) -+#define AW87XXX_PID_60_PD_AGC1_BITS_LEN (1) -+#define AW87XXX_PID_60_PD_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_60_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_60_PD_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_60_PD_AGC1_ENABLE (0) -+#define AW87XXX_PID_60_PD_AGC1_ENABLE_VALUE \ -+ (AW87XXX_PID_60_PD_AGC1_ENABLE << AW87XXX_PID_60_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PD_AGC1_DISABLE (1) -+#define AW87XXX_PID_60_PD_AGC1_DISABLE_VALUE \ -+ (AW87XXX_PID_60_PD_AGC1_DISABLE << AW87XXX_PID_60_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PD_AGC1_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PD_AGC1_DEFAULT \ -+ (AW87XXX_PID_60_PD_AGC1_DEFAULT_VALUE << AW87XXX_PID_60_PD_AGC1_START_BIT) -+ -+/* AGC1_OUTPUT_LEVEL bit 6:3 (AGC1PA 0x06) */ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT (3) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_BITS_LEN (4) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_BITS_LEN)-1) << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5V (0) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P2V (1) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P2V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P2V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P4V (2) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P4V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P4V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P6V (3) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P6V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P6V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P8V (4) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P8V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_5P8V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P0V (5) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P0V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P0V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P2V (6) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P2V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P2V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P4V (7) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P4V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P4V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P6V (8) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P6V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P6V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P8V (9) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P8V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_6P8V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7V (10) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P2V (11) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P2V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P2V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P4V (12) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P4V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P4V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P6V (13) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P6V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P6V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P8V (14) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P8V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_7P8V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_8V (15) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_8V_VALUE \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_8V << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_DEFAULT_VALUE (0x9) -+#define AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_DEFAULT \ -+ (AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_DEFAULT_VALUE << AW87XXX_PID_60_AGC1_OUTPUT_LEVEL_START_BIT) -+ -+/* AGC1_ATT_TIME bit 2:0 (AGC1PA 0x06) */ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_BITS_LEN (3) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC1_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P04MSDB (0) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P04MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P04MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P08MSDB (1) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P08MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P08MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P16MSDB (2) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P16MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P16MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P32MSDB (3) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P32MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P32MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P02MSDB (4) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P02MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P02MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P01MSDB (5) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P01MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P01MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB (6) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB (7) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_AGC1_ATT_TIME_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_AGC1_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC1_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC1_ATT_TIME_START_BIT) -+ -+/* default value of AGC1PA (0x06) */ -+/* #define AW87XXX_PID_60_AGC1PA_DEFAULT (0x49) */ -+ -+/* AGC2PA (0x07) detail */ -+/* AGC2_OUTPUT_POWER bit 6:3 (AGC2PA 0x07) */ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT (3) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_BITS_LEN (4) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC2_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P0W4_OHM (0) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P0W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P4W4_OHM (1) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P4W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P4W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P8W4_OHM (2) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P8W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_2P8W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P2W4_OHM (3) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P2W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P2W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P6W4_OHM (4) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_3P6W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P0W4_OHM (5) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P0W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P4W4_OHM (6) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P4W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P4W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P8W4_OHM (7) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P8W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_4P8W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P2W4_OHM (8) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P2W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P2W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P6W4_OHM (9) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_5P6W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_6W4_OHM (10) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_6W4_OHM << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_AGC2_OFF (11) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_AGC2_OFF_VALUE \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_AGC2_OFF << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_AGC2_OUTPUT_POWER_DEFAULT \ -+ (AW87XXX_PID_60_AGC2_OUTPUT_POWER_DEFAULT_VALUE << AW87XXX_PID_60_AGC2_OUTPUT_POWER_START_BIT) -+ -+/* AGC2_ATT_TIME bit 2:0 (AGC2PA 0x07) */ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_BITS_LEN (3) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC2_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P16MSDB (0) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P16MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_0P16MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P32MSDB (1) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P32MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_0P32MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P64MSDB (2) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_0P64MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_0P64MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_2P56MSDB (3) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_2P56MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_2P56MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_10P24MSDB (4) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_10P24MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_40P96MSDB (5) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_40P96MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_82MSDB (6) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_82MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_82MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_164MSDB (7) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_164MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_164MSDB << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_ATT_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_AGC2_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC2_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC2_ATT_TIME_START_BIT) -+ -+/* default value of AGC2PA (0x07) */ -+/* #define AW87XXX_PID_60_AGC2PA_DEFAULT (0x1A) */ -+ -+/* AGC3PA (0x08) detail */ -+/* PD_AGC3 bit 4 (AGC3PA 0x08) */ -+#define AW87XXX_PID_60_PD_AGC3_START_BIT (4) -+#define AW87XXX_PID_60_PD_AGC3_BITS_LEN (1) -+#define AW87XXX_PID_60_PD_AGC3_MASK \ -+ (~(((1<<AW87XXX_PID_60_PD_AGC3_BITS_LEN)-1) << AW87XXX_PID_60_PD_AGC3_START_BIT)) -+ -+#define AW87XXX_PID_60_PD_AGC3_ENABLE (0) -+#define AW87XXX_PID_60_PD_AGC3_ENABLE_VALUE \ -+ (AW87XXX_PID_60_PD_AGC3_ENABLE << AW87XXX_PID_60_PD_AGC3_START_BIT) -+ -+#define AW87XXX_PID_60_PD_AGC3_DISABLE (1) -+#define AW87XXX_PID_60_PD_AGC3_DISABLE_VALUE \ -+ (AW87XXX_PID_60_PD_AGC3_DISABLE << AW87XXX_PID_60_PD_AGC3_START_BIT) -+ -+#define AW87XXX_PID_60_PD_AGC3_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PD_AGC3_DEFAULT \ -+ (AW87XXX_PID_60_PD_AGC3_DEFAULT_VALUE << AW87XXX_PID_60_PD_AGC3_START_BIT) -+ -+/* EN_HW_MODE bit 5 (AGC3PA 0x08) */ -+#define AW87XXX_PID_60_EN_HW_MODE_START_BIT (5) -+#define AW87XXX_PID_60_EN_HW_MODE_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_HW_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_HW_MODE_BITS_LEN)-1) << AW87XXX_PID_60_EN_HW_MODE_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_HW_MODE_DISABLE (0) -+#define AW87XXX_PID_60_EN_HW_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_HW_MODE_DISABLE << AW87XXX_PID_60_EN_HW_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_EN_HW_MODE_ENABLE (1) -+#define AW87XXX_PID_60_EN_HW_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_HW_MODE_ENABLE << AW87XXX_PID_60_EN_HW_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_EN_HW_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_HW_MODE_DEFAULT \ -+ (AW87XXX_PID_60_EN_HW_MODE_DEFAULT_VALUE << AW87XXX_PID_60_EN_HW_MODE_START_BIT) -+ -+/* AGC3_OUTPUT_POWER bit 3:0 (AGC3PA 0x08) */ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT (0) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_BITS_LEN (4) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC3_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P0W4_OHM (0) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P0W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P2W4_OHM (1) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P2W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P2W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P4W4_OHM (2) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P4W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P4W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P6W4_OHM (3) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P6W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P8W4_OHM (4) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P8W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_1P8W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P0W4_OHM (5) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P0W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P2W4_OHM (6) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P2W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P2W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P4W4_OHM (7) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P4W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P4W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P6W4_OHM (8) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P6W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P8W4_OHM (9) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P8W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_2P8W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P0W4_OHM (10) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P0W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P2W4_OHM (11) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P2W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P2W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P4W4_OHM (12) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P4W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P4W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P6W4_OHM (13) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P6W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P6W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P8W4_OHM (14) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P8W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_3P8W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_4P0W4_OHM (15) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_4P0W4_OHM_VALUE \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_4P0W4_OHM << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_AGC3_OUTPUT_POWER_DEFAULT \ -+ (AW87XXX_PID_60_AGC3_OUTPUT_POWER_DEFAULT_VALUE << AW87XXX_PID_60_AGC3_OUTPUT_POWER_START_BIT) -+ -+/* default value of AGC3PA (0x08) */ -+/* #define AW87XXX_PID_60_AGC3PA_DEFAULT (0x03) */ -+ -+/* AGC3P (0x09) detail */ -+/* AGC3_REL_TIME bit 7:5 (AGC3P 0x09) */ -+#define AW87XXX_PID_60_AGC3_REL_TIME_START_BIT (5) -+#define AW87XXX_PID_60_AGC3_REL_TIME_BITS_LEN (3) -+#define AW87XXX_PID_60_AGC3_REL_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC3_REL_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_5P12MSDB (0) -+#define AW87XXX_PID_60_AGC3_REL_TIME_5P12MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_5P12MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_10P24MSDB (1) -+#define AW87XXX_PID_60_AGC3_REL_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_10P24MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_20P48MSDB (2) -+#define AW87XXX_PID_60_AGC3_REL_TIME_20P48MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_20P48MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_40P96MSDB (3) -+#define AW87XXX_PID_60_AGC3_REL_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_40P96MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_81P92MSDB (4) -+#define AW87XXX_PID_60_AGC3_REL_TIME_81P92MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_81P92MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_163P84MSDB (5) -+#define AW87XXX_PID_60_AGC3_REL_TIME_163P84MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_163P84MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_327P68MSDB (6) -+#define AW87XXX_PID_60_AGC3_REL_TIME_327P68MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_327P68MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_655P36MSDB (7) -+#define AW87XXX_PID_60_AGC3_REL_TIME_655P36MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_655P36MSDB << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_REL_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_AGC3_REL_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC3_REL_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC3_REL_TIME_START_BIT) -+ -+/* AGC3_ATT_TIME bit 4:2 (AGC3P 0x09) */ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT (2) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_BITS_LEN (3) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC3_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_1P28MSDB (0) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_1P28MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_1P28MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_2P56MSDB (1) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_2P56MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_2P56MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_10P24MSDB (2) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_10P24MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_10P24MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_40P96MSDB (3) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_40P96MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_40P96MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_82MSDB (4) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_82MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_82MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_164MSDB (5) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_164MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_164MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_328MSDB (6) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_328MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_328MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_656MSDB (7) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_656MSDB_VALUE \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_656MSDB << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_ATT_TIME_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_AGC3_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC3_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC3_ATT_TIME_START_BIT) -+ -+/* AGC3_FIRST_ATT_TIME bit 1:0 (AGC3P 0x09) */ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_BITS_LEN (2) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_5P12MS (0) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_5P12MS_VALUE \ -+ (AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_5P12MS << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_10P24MS (1) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_10P24MS_VALUE \ -+ (AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_10P24MS << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_20P48MS (2) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_20P48MS_VALUE \ -+ (AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_20P48MS << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_41MS (3) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_41MS_VALUE \ -+ (AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_41MS << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC3_FIRST_ATT_TIME_START_BIT) -+ -+/* default value of AGC3P (0x09) */ -+/* #define AW87XXX_PID_60_AGC3P_DEFAULT (0x4E) */ -+ -+/* LOW_BAT (0x0A) detail */ -+/* EN_BAT_SFGD bit 6 (LOW_BAT 0x0A) */ -+#define AW87XXX_PID_60_EN_BAT_SFGD_START_BIT (6) -+#define AW87XXX_PID_60_EN_BAT_SFGD_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_BAT_SFGD_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_BAT_SFGD_BITS_LEN)-1) << AW87XXX_PID_60_EN_BAT_SFGD_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_BAT_SFGD_DISABLE (0) -+#define AW87XXX_PID_60_EN_BAT_SFGD_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_BAT_SFGD_DISABLE << AW87XXX_PID_60_EN_BAT_SFGD_START_BIT) -+ -+#define AW87XXX_PID_60_EN_BAT_SFGD_ENABLE (1) -+#define AW87XXX_PID_60_EN_BAT_SFGD_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_BAT_SFGD_ENABLE << AW87XXX_PID_60_EN_BAT_SFGD_START_BIT) -+ -+#define AW87XXX_PID_60_EN_BAT_SFGD_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_BAT_SFGD_DEFAULT \ -+ (AW87XXX_PID_60_EN_BAT_SFGD_DEFAULT_VALUE << AW87XXX_PID_60_EN_BAT_SFGD_START_BIT) -+ -+/* BAT_SFGD_VTH bit 5:4 (LOW_BAT 0x0A) */ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT (4) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_BITS_LEN (2) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BAT_SFGD_VTH_BITS_LEN)-1) << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P3V (0) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P3V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_VTH_3P3V << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P4V (1) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P4V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_VTH_3P4V << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P5V (2) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P5V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_VTH_3P5V << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P6V (3) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_3P6V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_VTH_3P6V << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_VTH_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BAT_SFGD_VTH_DEFAULT \ -+ (AW87XXX_PID_60_BAT_SFGD_VTH_DEFAULT_VALUE << AW87XXX_PID_60_BAT_SFGD_VTH_START_BIT) -+ -+/* BAT_SFGD_LEVEL bit 3:2 (LOW_BAT 0x0A) */ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT (2) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_BITS_LEN (2) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_BAT_SFGD_LEVEL_BITS_LEN)-1) << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT)) -+ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_5V (0) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_5V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_LEVEL_5V << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_5P5V (1) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_5P5V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_LEVEL_5P5V << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_6V (2) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_6V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_LEVEL_6V << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_6P5V (3) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_6P5V_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_LEVEL_6P5V << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_DEFAULT_VALUE (0x01) -+#define AW87XXX_PID_60_BAT_SFGD_LEVEL_DEFAULT \ -+ (AW87XXX_PID_60_BAT_SFGD_LEVEL_DEFAULT_VALUE << AW87XXX_PID_60_BAT_SFGD_LEVEL_START_BIT) -+ -+/* BAT_SFGD_DEGLITCH bit 1:0 (LOW_BAT 0x0A) */ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT (0) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_BITS_LEN (2) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BAT_SFGD_DEGLITCH_BITS_LEN)-1) << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT)) -+ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_1MS (0) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_1MS_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_DEGLITCH_1MS << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_500US (1) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_500US_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_DEGLITCH_500US << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_200US (2) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_200US_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_DEGLITCH_200US << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DISABLE (3) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DISABLE << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DEFAULT \ -+ (AW87XXX_PID_60_BAT_SFGD_DEGLITCH_DEFAULT_VALUE << AW87XXX_PID_60_BAT_SFGD_DEGLITCH_START_BIT) -+ -+/* default value of LOW_BAT (0x0A) */ -+/* #define AW87XXX_PID_60_LOW_BAT_DEFAULT (0x14) */ -+ -+/* BSTOUT (0x0B) detail */ -+/* ADP_BOOST_VOUT bit 4:0 (BSTOUT 0x0B) */ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT (0) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_BITS_LEN (5) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_MASK \ -+ (~(((1<<AW87XXX_PID_60_ADP_BOOST_VOUT_BITS_LEN)-1) << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT)) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_4P75V (0) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_4P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_4P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P0V (1) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_5P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P25V (2) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_5P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P5V (3) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_5P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P75V (4) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_5P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_5P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P0V (5) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_6P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P25V (6) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_6P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P5V (7) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_6P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P75V (8) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_6P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_6P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P0V (9) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_7P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P25V (10) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_7P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P5V (11) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_7P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P75V (12) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_7P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_7P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P0V (13) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_8P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P25V (14) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_8P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P5V (15) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_8P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P75V (16) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_8P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_8P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P0V (17) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_9P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P25V (18) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_9P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P5V (19) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_9P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P75V (20) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_9P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_9P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P0V (21) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_10P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P25V (22) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_10P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P5V (23) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_10P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P75V (24) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_10P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_10P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P0V (25) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_11P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P25V (26) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_11P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P5V (27) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P5V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_11P5V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P75V (28) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_11P75V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_11P75V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_12P0V (29) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_12P0V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_12P0V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_12P25V (30) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_12P25V_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_12P25V << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_DEFAULT_VALUE (0x11) -+#define AW87XXX_PID_60_ADP_BOOST_VOUT_DEFAULT \ -+ (AW87XXX_PID_60_ADP_BOOST_VOUT_DEFAULT_VALUE << AW87XXX_PID_60_ADP_BOOST_VOUT_START_BIT) -+ -+/* default value of BSTOUT (0x0B) */ -+/* #define AW87XXX_PID_60_BSTOUT_DEFAULT (0x11) */ -+ -+/* SYSST (0x59) detail */ -+/* ADP_BOOST_S bit 0 (SYSST 0x59) */ -+#define AW87XXX_PID_60_ADP_BOOST_S_START_BIT (0) -+#define AW87XXX_PID_60_ADP_BOOST_S_BITS_LEN (1) -+#define AW87XXX_PID_60_ADP_BOOST_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_ADP_BOOST_S_BITS_LEN)-1) << AW87XXX_PID_60_ADP_BOOST_S_START_BIT)) -+ -+#define AW87XXX_PID_60_ADP_BOOST_S_DIRECT_MODE (0) -+#define AW87XXX_PID_60_ADP_BOOST_S_DIRECT_MODE_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_S_DIRECT_MODE << AW87XXX_PID_60_ADP_BOOST_S_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_S_BOOST_MODE (1) -+#define AW87XXX_PID_60_ADP_BOOST_S_BOOST_MODE_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_S_BOOST_MODE << AW87XXX_PID_60_ADP_BOOST_S_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_ADP_BOOST_S_DEFAULT \ -+ (AW87XXX_PID_60_ADP_BOOST_S_DEFAULT_VALUE << AW87XXX_PID_60_ADP_BOOST_S_START_BIT) -+ -+/* OT160_S bit 1 (SYSST 0x59) */ -+#define AW87XXX_PID_60_OT160_S_START_BIT (1) -+#define AW87XXX_PID_60_OT160_S_BITS_LEN (1) -+#define AW87XXX_PID_60_OT160_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_OT160_S_BITS_LEN)-1) << AW87XXX_PID_60_OT160_S_START_BIT)) -+ -+#define AW87XXX_PID_60_OT160_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_OT160_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_OT160_S_NORMAL_OPERATION << AW87XXX_PID_60_OT160_S_START_BIT) -+ -+#define AW87XXX_PID_60_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_60_OT160_S_START_BIT) -+ -+#define AW87XXX_PID_60_OT160_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_OT160_S_DEFAULT \ -+ (AW87XXX_PID_60_OT160_S_DEFAULT_VALUE << AW87XXX_PID_60_OT160_S_START_BIT) -+ -+/* PA_OC_S bit 2 (SYSST 0x59) */ -+#define AW87XXX_PID_60_PA_OC_S_START_BIT (2) -+#define AW87XXX_PID_60_PA_OC_S_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_OC_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OC_S_BITS_LEN)-1) << AW87XXX_PID_60_PA_OC_S_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OC_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_PA_OC_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_PA_OC_S_NORMAL_OPERATION << AW87XXX_PID_60_PA_OC_S_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_60_PA_OC_S_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PA_OC_S_DEFAULT \ -+ (AW87XXX_PID_60_PA_OC_S_DEFAULT_VALUE << AW87XXX_PID_60_PA_OC_S_START_BIT) -+ -+/* BST_SCP_S bit 3 (SYSST 0x59) */ -+#define AW87XXX_PID_60_BST_SCP_S_START_BIT (3) -+#define AW87XXX_PID_60_BST_SCP_S_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SCP_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SCP_S_BITS_LEN)-1) << AW87XXX_PID_60_BST_SCP_S_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SCP_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_SCP_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_S_NORMAL_OPERATION << AW87XXX_PID_60_BST_SCP_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_60_BST_SCP_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_SCP_S_DEFAULT \ -+ (AW87XXX_PID_60_BST_SCP_S_DEFAULT_VALUE << AW87XXX_PID_60_BST_SCP_S_START_BIT) -+ -+/* BST_OVP2_S bit 4 (SYSST 0x59) */ -+#define AW87XXX_PID_60_BST_OVP2_S_START_BIT (4) -+#define AW87XXX_PID_60_BST_OVP2_S_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP2_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP2_S_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP2_S_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP2_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_OVP2_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_S_NORMAL_OPERATION << AW87XXX_PID_60_BST_OVP2_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_60_BST_OVP2_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_OVP2_S_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP2_S_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP2_S_START_BIT) -+ -+/* BST_OVP_S bit 5 (SYSST 0x59) */ -+#define AW87XXX_PID_60_BST_OVP_S_START_BIT (5) -+#define AW87XXX_PID_60_BST_OVP_S_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP_S_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP_S_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_OVP_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_S_NORMAL_OPERATION << AW87XXX_PID_60_BST_OVP_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION (1) -+#define AW87XXX_PID_60_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_60_BST_OVP_S_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_OVP_S_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP_S_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP_S_START_BIT) -+ -+/* LOW_BATT_S bit 6 (SYSST 0x59) */ -+#define AW87XXX_PID_60_LOW_BATT_S_START_BIT (6) -+#define AW87XXX_PID_60_LOW_BATT_S_BITS_LEN (1) -+#define AW87XXX_PID_60_LOW_BATT_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_LOW_BATT_S_BITS_LEN)-1) << AW87XXX_PID_60_LOW_BATT_S_START_BIT)) -+ -+#define AW87XXX_PID_60_LOW_BATT_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_LOW_BATT_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_LOW_BATT_S_NORMAL_OPERATION << AW87XXX_PID_60_LOW_BATT_S_START_BIT) -+ -+#define AW87XXX_PID_60_LOW_BATT_S_LOW_VBAT_DETECTED (1) -+#define AW87XXX_PID_60_LOW_BATT_S_LOW_VBAT_DETECTED_VALUE \ -+ (AW87XXX_PID_60_LOW_BATT_S_LOW_VBAT_DETECTED << AW87XXX_PID_60_LOW_BATT_S_START_BIT) -+ -+#define AW87XXX_PID_60_LOW_BATT_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_LOW_BATT_S_DEFAULT \ -+ (AW87XXX_PID_60_LOW_BATT_S_DEFAULT_VALUE << AW87XXX_PID_60_LOW_BATT_S_START_BIT) -+ -+/* UVLO_S bit 7 (SYSST 0x59) */ -+#define AW87XXX_PID_60_UVLO_S_START_BIT (7) -+#define AW87XXX_PID_60_UVLO_S_BITS_LEN (1) -+#define AW87XXX_PID_60_UVLO_S_MASK \ -+ (~(((1<<AW87XXX_PID_60_UVLO_S_BITS_LEN)-1) << AW87XXX_PID_60_UVLO_S_START_BIT)) -+ -+#define AW87XXX_PID_60_UVLO_S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_UVLO_S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_UVLO_S_NORMAL_OPERATION << AW87XXX_PID_60_UVLO_S_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_S_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_60_UVLO_S_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_60_UVLO_S_VBAT_UNDER_VOLTAGE << AW87XXX_PID_60_UVLO_S_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_S_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_UVLO_S_DEFAULT \ -+ (AW87XXX_PID_60_UVLO_S_DEFAULT_VALUE << AW87XXX_PID_60_UVLO_S_START_BIT) -+ -+/* default value of SYSST (0x59) */ -+/* #define AW87XXX_PID_60_SYSST_DEFAULT (0xFF) */ -+ -+/* SYSINT (0x60) detail */ -+/* ADP_BOOST_I bit 0 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_ADP_BOOST_I_START_BIT (0) -+#define AW87XXX_PID_60_ADP_BOOST_I_BITS_LEN (1) -+#define AW87XXX_PID_60_ADP_BOOST_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_ADP_BOOST_I_BITS_LEN)-1) << AW87XXX_PID_60_ADP_BOOST_I_START_BIT)) -+ -+#define AW87XXX_PID_60_ADP_BOOST_I_DIRECT_MODE (0) -+#define AW87XXX_PID_60_ADP_BOOST_I_DIRECT_MODE_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_I_DIRECT_MODE << AW87XXX_PID_60_ADP_BOOST_I_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_I_BOOST_MODE (1) -+#define AW87XXX_PID_60_ADP_BOOST_I_BOOST_MODE_VALUE \ -+ (AW87XXX_PID_60_ADP_BOOST_I_BOOST_MODE << AW87XXX_PID_60_ADP_BOOST_I_START_BIT) -+ -+#define AW87XXX_PID_60_ADP_BOOST_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_ADP_BOOST_I_DEFAULT \ -+ (AW87XXX_PID_60_ADP_BOOST_I_DEFAULT_VALUE << AW87XXX_PID_60_ADP_BOOST_I_START_BIT) -+ -+/* OT160_I bit 1 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_OT160_I_START_BIT (1) -+#define AW87XXX_PID_60_OT160_I_BITS_LEN (1) -+#define AW87XXX_PID_60_OT160_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_OT160_I_BITS_LEN)-1) << AW87XXX_PID_60_OT160_I_START_BIT)) -+ -+#define AW87XXX_PID_60_OT160_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_OT160_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_OT160_I_NORMAL_OPERATION << AW87XXX_PID_60_OT160_I_START_BIT) -+ -+#define AW87XXX_PID_60_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_60_OT160_I_START_BIT) -+ -+#define AW87XXX_PID_60_OT160_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_OT160_I_DEFAULT \ -+ (AW87XXX_PID_60_OT160_I_DEFAULT_VALUE << AW87XXX_PID_60_OT160_I_START_BIT) -+ -+/* PA_OC_I bit 2 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_PA_OC_I_START_BIT (2) -+#define AW87XXX_PID_60_PA_OC_I_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_OC_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OC_I_BITS_LEN)-1) << AW87XXX_PID_60_PA_OC_I_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OC_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_PA_OC_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_PA_OC_I_NORMAL_OPERATION << AW87XXX_PID_60_PA_OC_I_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_60_PA_OC_I_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PA_OC_I_DEFAULT \ -+ (AW87XXX_PID_60_PA_OC_I_DEFAULT_VALUE << AW87XXX_PID_60_PA_OC_I_START_BIT) -+ -+/* BST_SCP_I bit 3 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_BST_SCP_I_START_BIT (3) -+#define AW87XXX_PID_60_BST_SCP_I_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SCP_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SCP_I_BITS_LEN)-1) << AW87XXX_PID_60_BST_SCP_I_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SCP_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_SCP_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_I_NORMAL_OPERATION << AW87XXX_PID_60_BST_SCP_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_60_BST_SCP_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_SCP_I_DEFAULT \ -+ (AW87XXX_PID_60_BST_SCP_I_DEFAULT_VALUE << AW87XXX_PID_60_BST_SCP_I_START_BIT) -+ -+/* BST_OVP2_I bit 4 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_BST_OVP2_I_START_BIT (4) -+#define AW87XXX_PID_60_BST_OVP2_I_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP2_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP2_I_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP2_I_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP2_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_OVP2_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_I_NORMAL_OPERATION << AW87XXX_PID_60_BST_OVP2_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1) -+#define AW87XXX_PID_60_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_60_BST_OVP2_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_OVP2_I_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP2_I_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP2_I_START_BIT) -+ -+/* BST_OVP_I bit 5 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_BST_OVP_I_START_BIT (5) -+#define AW87XXX_PID_60_BST_OVP_I_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP_I_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP_I_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_BST_OVP_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_I_NORMAL_OPERATION << AW87XXX_PID_60_BST_OVP_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION (1) -+#define AW87XXX_PID_60_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_60_BST_OVP_I_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_OVP_I_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP_I_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP_I_START_BIT) -+ -+/* LOW_BATT_I bit 6 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_LOW_BATT_I_START_BIT (6) -+#define AW87XXX_PID_60_LOW_BATT_I_BITS_LEN (1) -+#define AW87XXX_PID_60_LOW_BATT_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_LOW_BATT_I_BITS_LEN)-1) << AW87XXX_PID_60_LOW_BATT_I_START_BIT)) -+ -+#define AW87XXX_PID_60_LOW_BATT_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_LOW_BATT_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_LOW_BATT_I_NORMAL_OPERATION << AW87XXX_PID_60_LOW_BATT_I_START_BIT) -+ -+#define AW87XXX_PID_60_LOW_BATT_I_LOW_VBAT_DETECTED (1) -+#define AW87XXX_PID_60_LOW_BATT_I_LOW_VBAT_DETECTED_VALUE \ -+ (AW87XXX_PID_60_LOW_BATT_I_LOW_VBAT_DETECTED << AW87XXX_PID_60_LOW_BATT_I_START_BIT) -+ -+#define AW87XXX_PID_60_LOW_BATT_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_LOW_BATT_I_DEFAULT \ -+ (AW87XXX_PID_60_LOW_BATT_I_DEFAULT_VALUE << AW87XXX_PID_60_LOW_BATT_I_START_BIT) -+ -+/* UVLO_I bit 7 (SYSINT 0x60) */ -+#define AW87XXX_PID_60_UVLO_I_START_BIT (7) -+#define AW87XXX_PID_60_UVLO_I_BITS_LEN (1) -+#define AW87XXX_PID_60_UVLO_I_MASK \ -+ (~(((1<<AW87XXX_PID_60_UVLO_I_BITS_LEN)-1) << AW87XXX_PID_60_UVLO_I_START_BIT)) -+ -+#define AW87XXX_PID_60_UVLO_I_NORMAL_OPERATION (0) -+#define AW87XXX_PID_60_UVLO_I_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_60_UVLO_I_NORMAL_OPERATION << AW87XXX_PID_60_UVLO_I_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_I_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_60_UVLO_I_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_60_UVLO_I_VBAT_UNDER_VOLTAGE << AW87XXX_PID_60_UVLO_I_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_I_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_UVLO_I_DEFAULT \ -+ (AW87XXX_PID_60_UVLO_I_DEFAULT_VALUE << AW87XXX_PID_60_UVLO_I_START_BIT) -+ -+/* default value of SYSINT (0x60) */ -+/* #define AW87XXX_PID_60_SYSINT_DEFAULT (0xFF) */ -+ -+/* BURST_CON (0x61) detail */ -+/* BURST_PEAK bit 7:5 (BURST_CON 0x61) */ -+#define AW87XXX_PID_60_BURST_PEAK_START_BIT (5) -+#define AW87XXX_PID_60_BURST_PEAK_BITS_LEN (3) -+#define AW87XXX_PID_60_BURST_PEAK_MASK \ -+ (~(((1<<AW87XXX_PID_60_BURST_PEAK_BITS_LEN)-1) << AW87XXX_PID_60_BURST_PEAK_START_BIT)) -+ -+#define AW87XXX_PID_60_BURST_PEAK_10MA (0) -+#define AW87XXX_PID_60_BURST_PEAK_10MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_10MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_20MA (1) -+#define AW87XXX_PID_60_BURST_PEAK_20MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_20MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_30MA (2) -+#define AW87XXX_PID_60_BURST_PEAK_30MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_30MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_50MA (3) -+#define AW87XXX_PID_60_BURST_PEAK_50MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_50MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_70MA (4) -+#define AW87XXX_PID_60_BURST_PEAK_70MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_70MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_130MA (5) -+#define AW87XXX_PID_60_BURST_PEAK_130MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_130MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_160MA (7) -+#define AW87XXX_PID_60_BURST_PEAK_160MA_VALUE \ -+ (AW87XXX_PID_60_BURST_PEAK_160MA << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_PEAK_DEFAULT_VALUE (2) -+#define AW87XXX_PID_60_BURST_PEAK_DEFAULT \ -+ (AW87XXX_PID_60_BURST_PEAK_DEFAULT_VALUE << AW87XXX_PID_60_BURST_PEAK_START_BIT) -+ -+/* BST_BURST_SS bit 4:2 (BURST_CON 0x61) */ -+#define AW87XXX_PID_60_BST_BURST_SS_START_BIT (2) -+#define AW87XXX_PID_60_BST_BURST_SS_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_BURST_SS_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_SS_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_SS_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_700MV (0) -+#define AW87XXX_PID_60_BST_BURST_SS_700MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_700MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_760MV (1) -+#define AW87XXX_PID_60_BST_BURST_SS_760MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_760MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_820MV (2) -+#define AW87XXX_PID_60_BST_BURST_SS_820MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_820MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_880MV (3) -+#define AW87XXX_PID_60_BST_BURST_SS_880MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_880MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_940MV (4) -+#define AW87XXX_PID_60_BST_BURST_SS_940MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_940MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_1000MV (5) -+#define AW87XXX_PID_60_BST_BURST_SS_1000MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_1000MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_1060MV (6) -+#define AW87XXX_PID_60_BST_BURST_SS_1060MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_1060MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_1120MV (7) -+#define AW87XXX_PID_60_BST_BURST_SS_1120MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SS_1120MV << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_BURST_SS_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_SS_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_SS_START_BIT) -+ -+/* BST_COMPMAX bit 1:0 (BURST_CON 0x61) */ -+#define AW87XXX_PID_60_BST_COMPMAX_START_BIT (0) -+#define AW87XXX_PID_60_BST_COMPMAX_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_COMPMAX_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_COMPMAX_BITS_LEN)-1) << AW87XXX_PID_60_BST_COMPMAX_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_COMPMAX_2P0V (0) -+#define AW87XXX_PID_60_BST_COMPMAX_2P0V_VALUE \ -+ (AW87XXX_PID_60_BST_COMPMAX_2P0V << AW87XXX_PID_60_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_60_BST_COMPMAX_2P2V (1) -+#define AW87XXX_PID_60_BST_COMPMAX_2P2V_VALUE \ -+ (AW87XXX_PID_60_BST_COMPMAX_2P2V << AW87XXX_PID_60_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_60_BST_COMPMAX_2P3V (2) -+#define AW87XXX_PID_60_BST_COMPMAX_2P3V_VALUE \ -+ (AW87XXX_PID_60_BST_COMPMAX_2P3V << AW87XXX_PID_60_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_60_BST_COMPMAX_2P4V (3) -+#define AW87XXX_PID_60_BST_COMPMAX_2P4V_VALUE \ -+ (AW87XXX_PID_60_BST_COMPMAX_2P4V << AW87XXX_PID_60_BST_COMPMAX_START_BIT) -+ -+#define AW87XXX_PID_60_BST_COMPMAX_DEFAULT_VALUE (3) -+#define AW87XXX_PID_60_BST_COMPMAX_DEFAULT \ -+ (AW87XXX_PID_60_BST_COMPMAX_DEFAULT_VALUE << AW87XXX_PID_60_BST_COMPMAX_START_BIT) -+ -+/* default value of BURST_CON (0x61) */ -+/* #define AW87XXX_PID_60_BURST_CON_DEFAULT (0x47) */ -+ -+/* BST_BIAS (0x62) detail */ -+/* BST_EA_CUR bit 0 (BST_BIAS 0x62) */ -+#define AW87XXX_PID_60_BST_EA_CUR_START_BIT (0) -+#define AW87XXX_PID_60_BST_EA_CUR_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_EA_CUR_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_EA_CUR_BITS_LEN)-1) << AW87XXX_PID_60_BST_EA_CUR_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_EA_CUR_1UA (0) -+#define AW87XXX_PID_60_BST_EA_CUR_1UA_VALUE \ -+ (AW87XXX_PID_60_BST_EA_CUR_1UA << AW87XXX_PID_60_BST_EA_CUR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EA_CUR_2UA (1) -+#define AW87XXX_PID_60_BST_EA_CUR_2UA_VALUE \ -+ (AW87XXX_PID_60_BST_EA_CUR_2UA << AW87XXX_PID_60_BST_EA_CUR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EA_CUR_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_EA_CUR_DEFAULT \ -+ (AW87XXX_PID_60_BST_EA_CUR_DEFAULT_VALUE << AW87XXX_PID_60_BST_EA_CUR_START_BIT) -+ -+/* BST_BURST_SSMD bit 5 (BST_BIAS 0x62) */ -+#define AW87XXX_PID_60_BST_BURST_SSMD_START_BIT (5) -+#define AW87XXX_PID_60_BST_BURST_SSMD_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_BURST_SSMD_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_SSMD_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_SSMD_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_SSMD_SLOW (0) -+#define AW87XXX_PID_60_BST_BURST_SSMD_SLOW_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SSMD_SLOW << AW87XXX_PID_60_BST_BURST_SSMD_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SSMD_FAST (1) -+#define AW87XXX_PID_60_BST_BURST_SSMD_FAST_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_SSMD_FAST << AW87XXX_PID_60_BST_BURST_SSMD_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_SSMD_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_BURST_SSMD_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_SSMD_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_SSMD_START_BIT) -+ -+/* BST_NCD_ITH bit 7:6 (BST_BIAS 0x62) */ -+#define AW87XXX_PID_60_BST_NCD_ITH_START_BIT (6) -+#define AW87XXX_PID_60_BST_NCD_ITH_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_NCD_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_NCD_ITH_BITS_LEN)-1) << AW87XXX_PID_60_BST_NCD_ITH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_NCD_ITH_170MA (0) -+#define AW87XXX_PID_60_BST_NCD_ITH_170MA_VALUE \ -+ (AW87XXX_PID_60_BST_NCD_ITH_170MA << AW87XXX_PID_60_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_NCD_ITH_220MA (1) -+#define AW87XXX_PID_60_BST_NCD_ITH_220MA_VALUE \ -+ (AW87XXX_PID_60_BST_NCD_ITH_220MA << AW87XXX_PID_60_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_NCD_ITH_280MA (2) -+#define AW87XXX_PID_60_BST_NCD_ITH_280MA_VALUE \ -+ (AW87XXX_PID_60_BST_NCD_ITH_280MA << AW87XXX_PID_60_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_NCD_ITH_340MA (3) -+#define AW87XXX_PID_60_BST_NCD_ITH_340MA_VALUE \ -+ (AW87XXX_PID_60_BST_NCD_ITH_340MA << AW87XXX_PID_60_BST_NCD_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_NCD_ITH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_NCD_ITH_DEFAULT \ -+ (AW87XXX_PID_60_BST_NCD_ITH_DEFAULT_VALUE << AW87XXX_PID_60_BST_NCD_ITH_START_BIT) -+ -+/* BST_VOUT_TRIM bit 4:3 (BST_BIAS 0x62) */ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT (3) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_VOUT_TRIM_BITS_LEN)-1) << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_25UA (0) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_25UA_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_TRIM_25UA << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_24UA (1) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_24UA_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_TRIM_24UA << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_25P5UA (2) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_25P5UA_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_TRIM_25P5UA << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_24P5UA (3) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_24P5UA_VALUE \ -+ (AW87XXX_PID_60_BST_VOUT_TRIM_24P5UA << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VOUT_TRIM_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_VOUT_TRIM_DEFAULT \ -+ (AW87XXX_PID_60_BST_VOUT_TRIM_DEFAULT_VALUE << AW87XXX_PID_60_BST_VOUT_TRIM_START_BIT) -+ -+/* BST_BURST_IN bit 2:1 (BST_BIAS 0x62) */ -+#define AW87XXX_PID_60_BST_BURST_IN_START_BIT (1) -+#define AW87XXX_PID_60_BST_BURST_IN_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_BURST_IN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_IN_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_IN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_3MV (0) -+#define AW87XXX_PID_60_BST_BURST_IN_3MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_3MV << AW87XXX_PID_60_BST_BURST_IN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_5MV (1) -+#define AW87XXX_PID_60_BST_BURST_IN_5MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_5MV << AW87XXX_PID_60_BST_BURST_IN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_7MV (2) -+#define AW87XXX_PID_60_BST_BURST_IN_7MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_7MV << AW87XXX_PID_60_BST_BURST_IN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_9MV (3) -+#define AW87XXX_PID_60_BST_BURST_IN_9MV_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_9MV << AW87XXX_PID_60_BST_BURST_IN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_BURST_IN_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_IN_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_IN_START_BIT) -+ -+/* default value of BST_BIAS (0x62) */ -+/* #define AW87XXX_PID_60_BST_BIAS_DEFAULT (0x60) */ -+ -+/* BST_EA (0x63) detail */ -+/* BST_LOW_CLAMP_EN bit 2 (BST_EA 0x63) */ -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_START_BIT (2) -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_LOW_CLAMP_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_LOW_CLAMP_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_DISABLE (0) -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_LOW_CLAMP_EN_DISABLE << AW87XXX_PID_60_BST_LOW_CLAMP_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_LOW_CLAMP_EN_ENABLE << AW87XXX_PID_60_BST_LOW_CLAMP_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_LOW_CLAMP_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_LOW_CLAMP_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_LOW_CLAMP_EN_START_BIT) -+ -+/* EN_VOUT_DIV bit 7 (BST_EA 0x63) */ -+#define AW87XXX_PID_60_EN_VOUT_DIV_START_BIT (7) -+#define AW87XXX_PID_60_EN_VOUT_DIV_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_VOUT_DIV_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_VOUT_DIV_BITS_LEN)-1) << AW87XXX_PID_60_EN_VOUT_DIV_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_VOUT_DIV_DISABLE (0) -+#define AW87XXX_PID_60_EN_VOUT_DIV_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_VOUT_DIV_DISABLE << AW87XXX_PID_60_EN_VOUT_DIV_START_BIT) -+ -+#define AW87XXX_PID_60_EN_VOUT_DIV_ENABLE (1) -+#define AW87XXX_PID_60_EN_VOUT_DIV_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_VOUT_DIV_ENABLE << AW87XXX_PID_60_EN_VOUT_DIV_START_BIT) -+ -+#define AW87XXX_PID_60_EN_VOUT_DIV_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_EN_VOUT_DIV_DEFAULT \ -+ (AW87XXX_PID_60_EN_VOUT_DIV_DEFAULT_VALUE << AW87XXX_PID_60_EN_VOUT_DIV_START_BIT) -+ -+/* BST_BURST_OUT_DELAY bit 6:5 (BST_EA 0x63) */ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT (5) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_OUT_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_2P8US (0) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_2P8US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_OUT_DELAY_2P8US << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_8P1US (1) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_8P1US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_OUT_DELAY_8P1US << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P2US (2) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P2US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P2US << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P8US (3) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P8US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_OUT_DELAY_1P8US << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_BURST_OUT_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_OUT_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_OUT_DELAY_START_BIT) -+ -+/* BST_BURST_IN_DELAY bit 4:3 (BST_EA 0x63) */ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT (3) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_IN_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_7P4US (0) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_7P4US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_DELAY_7P4US << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_14P6US (1) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_14P6US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_DELAY_14P6US << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_3P7US (2) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_3P7US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_DELAY_3P7US << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_5US (3) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_5US_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_IN_DELAY_5US << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_BURST_IN_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_IN_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_IN_DELAY_START_BIT) -+ -+/* BST_LOOPR bit 1:0 (BST_EA 0x63) */ -+#define AW87XXX_PID_60_BST_LOOPR_START_BIT (0) -+#define AW87XXX_PID_60_BST_LOOPR_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_LOOPR_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_LOOPR_BITS_LEN)-1) << AW87XXX_PID_60_BST_LOOPR_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_LOOPR_100K (0) -+#define AW87XXX_PID_60_BST_LOOPR_100K_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPR_100K << AW87XXX_PID_60_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPR_200K (1) -+#define AW87XXX_PID_60_BST_LOOPR_200K_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPR_200K << AW87XXX_PID_60_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPR_400K (2) -+#define AW87XXX_PID_60_BST_LOOPR_400K_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPR_400K << AW87XXX_PID_60_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPR_500K (3) -+#define AW87XXX_PID_60_BST_LOOPR_500K_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPR_500K << AW87XXX_PID_60_BST_LOOPR_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPR_DEFAULT_VALUE (2) -+#define AW87XXX_PID_60_BST_LOOPR_DEFAULT \ -+ (AW87XXX_PID_60_BST_LOOPR_DEFAULT_VALUE << AW87XXX_PID_60_BST_LOOPR_START_BIT) -+ -+/* default value of BST_EA (0x63) */ -+/* #define AW87XXX_PID_60_BST_EA_DEFAULT (0x86) */ -+ -+/* BST_DE_SOFT (0x64) detail */ -+/* EN_ADP_PEAK bit 0 (BST_DE_SOFT 0x64) */ -+#define AW87XXX_PID_60_EN_ADP_PEAK_START_BIT (0) -+#define AW87XXX_PID_60_EN_ADP_PEAK_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_ADP_PEAK_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_ADP_PEAK_BITS_LEN)-1) << AW87XXX_PID_60_EN_ADP_PEAK_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_ADP_PEAK_DISABLE (0) -+#define AW87XXX_PID_60_EN_ADP_PEAK_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_PEAK_DISABLE << AW87XXX_PID_60_EN_ADP_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_PEAK_ENABLE (1) -+#define AW87XXX_PID_60_EN_ADP_PEAK_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_PEAK_ENABLE << AW87XXX_PID_60_EN_ADP_PEAK_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_PEAK_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_EN_ADP_PEAK_DEFAULT \ -+ (AW87XXX_PID_60_EN_ADP_PEAK_DEFAULT_VALUE << AW87XXX_PID_60_EN_ADP_PEAK_START_BIT) -+ -+/* BST_SOFT_MODE_EN bit 7 (BST_DE_SOFT 0x64) */ -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_START_BIT (7) -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SOFT_MODE_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_SOFT_MODE_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_DISABLE (0) -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_MODE_EN_DISABLE << AW87XXX_PID_60_BST_SOFT_MODE_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_MODE_EN_ENABLE << AW87XXX_PID_60_BST_SOFT_MODE_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SOFT_MODE_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_SOFT_MODE_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_SOFT_MODE_EN_START_BIT) -+ -+/* BST_LOOPC bit 6:5 (BST_DE_SOFT 0x64) */ -+#define AW87XXX_PID_60_BST_LOOPC_START_BIT (5) -+#define AW87XXX_PID_60_BST_LOOPC_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_LOOPC_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_LOOPC_BITS_LEN)-1) << AW87XXX_PID_60_BST_LOOPC_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_LOOPC_30PF (0) -+#define AW87XXX_PID_60_BST_LOOPC_30PF_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPC_30PF << AW87XXX_PID_60_BST_LOOPC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPC_40PF (1) -+#define AW87XXX_PID_60_BST_LOOPC_40PF_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPC_40PF << AW87XXX_PID_60_BST_LOOPC_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_BST_LOOPC_40PF (2) -+#define AW87XXX_PID_60_BST_LOOPC_40PF_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPC_40PF << AW87XXX_PID_60_BST_LOOPC_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_BST_LOOPC_50PF (3) -+#define AW87XXX_PID_60_BST_LOOPC_50PF_VALUE \ -+ (AW87XXX_PID_60_BST_LOOPC_50PF << AW87XXX_PID_60_BST_LOOPC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LOOPC_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_LOOPC_DEFAULT \ -+ (AW87XXX_PID_60_BST_LOOPC_DEFAULT_VALUE << AW87XXX_PID_60_BST_LOOPC_START_BIT) -+ -+/* BST_SEL_DFPWM bit 4:3 (BST_DE_SOFT 0x64) */ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT (3) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SEL_DFPWM_BITS_LEN)-1) << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_32US_00_2US (0) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_32US_00_2US_VALUE \ -+ (AW87XXX_PID_60_BST_SEL_DFPWM_32US_00_2US << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_64US_01_CLK (1) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_64US_01_CLK_VALUE \ -+ (AW87XXX_PID_60_BST_SEL_DFPWM_64US_01_CLK << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_128US_10_4US (2) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_128US_10_4US_VALUE \ -+ (AW87XXX_PID_60_BST_SEL_DFPWM_128US_10_4US << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_256US_11_8US (3) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_256US_11_8US_VALUE \ -+ (AW87XXX_PID_60_BST_SEL_DFPWM_256US_11_8US << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SEL_DFPWM_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_SEL_DFPWM_DEFAULT \ -+ (AW87XXX_PID_60_BST_SEL_DFPWM_DEFAULT_VALUE << AW87XXX_PID_60_BST_SEL_DFPWM_START_BIT) -+ -+/* BST_SOFT_DELAY bit 2:1 (BST_DE_SOFT 0x64) */ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT (1) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SOFT_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_40US_001280U (0) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_40US_001280U_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_DELAY_40US_001280U << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_80US_012560U (1) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_80US_012560U_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_DELAY_80US_012560U << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_160US_105120U (2) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_160US_105120U_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_DELAY_160US_105120U << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_320US_1110240U (3) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_320US_1110240U_VALUE \ -+ (AW87XXX_PID_60_BST_SOFT_DELAY_320US_1110240U << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SOFT_DELAY_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SOFT_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_BST_SOFT_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_BST_SOFT_DELAY_START_BIT) -+ -+/* default value of BST_DE_SOFT (0x64) */ -+/* #define AW87XXX_PID_60_BST_DE_SOFT_DEFAULT (0x09) */ -+ -+/* BST_BURST_KICK (0x65) detail */ -+/* EN_TRANS_ERROR bit 0 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_EN_TRANS_ERROR_START_BIT (0) -+#define AW87XXX_PID_60_EN_TRANS_ERROR_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_TRANS_ERROR_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_TRANS_ERROR_BITS_LEN)-1) << AW87XXX_PID_60_EN_TRANS_ERROR_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_TRANS_ERROR_DISABLE (0) -+#define AW87XXX_PID_60_EN_TRANS_ERROR_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_TRANS_ERROR_DISABLE << AW87XXX_PID_60_EN_TRANS_ERROR_START_BIT) -+ -+#define AW87XXX_PID_60_EN_TRANS_ERROR_ENABLE (1) -+#define AW87XXX_PID_60_EN_TRANS_ERROR_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_TRANS_ERROR_ENABLE << AW87XXX_PID_60_EN_TRANS_ERROR_START_BIT) -+ -+#define AW87XXX_PID_60_EN_TRANS_ERROR_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_EN_TRANS_ERROR_DEFAULT \ -+ (AW87XXX_PID_60_EN_TRANS_ERROR_DEFAULT_VALUE << AW87XXX_PID_60_EN_TRANS_ERROR_START_BIT) -+ -+/* BST_SCP_VTH bit 1 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_BST_SCP_VTH_START_BIT (1) -+#define AW87XXX_PID_60_BST_SCP_VTH_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SCP_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SCP_VTH_BITS_LEN)-1) << AW87XXX_PID_60_BST_SCP_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SCP_VTH_HIGH_SIDE_VDD (0) -+#define AW87XXX_PID_60_BST_SCP_VTH_HIGH_SIDE_VDD_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_VTH_HIGH_SIDE_VDD << AW87XXX_PID_60_BST_SCP_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_VTH_LOW_SIDE_VDD (1) -+#define AW87XXX_PID_60_BST_SCP_VTH_LOW_SIDE_VDD_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_VTH_LOW_SIDE_VDD << AW87XXX_PID_60_BST_SCP_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_VTH_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SCP_VTH_DEFAULT \ -+ (AW87XXX_PID_60_BST_SCP_VTH_DEFAULT_VALUE << AW87XXX_PID_60_BST_SCP_VTH_START_BIT) -+ -+/* BST_SKIP_EN bit 6 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_BST_SKIP_EN_START_BIT (6) -+#define AW87XXX_PID_60_BST_SKIP_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SKIP_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SKIP_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_SKIP_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SKIP_EN_ENABLE (0) -+#define AW87XXX_PID_60_BST_SKIP_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SKIP_EN_ENABLE << AW87XXX_PID_60_BST_SKIP_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SKIP_EN_DISABLE (1) -+#define AW87XXX_PID_60_BST_SKIP_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SKIP_EN_DISABLE << AW87XXX_PID_60_BST_SKIP_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SKIP_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SKIP_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_SKIP_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_SKIP_EN_START_BIT) -+ -+/* BST_ADBK_COMP_ADJ bit 7 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_START_BIT (7) -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_ADBK_COMP_ADJ_BITS_LEN)-1) << AW87XXX_PID_60_BST_ADBK_COMP_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_14UA (0) -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_14UA_VALUE \ -+ (AW87XXX_PID_60_BST_ADBK_COMP_ADJ_14UA << AW87XXX_PID_60_BST_ADBK_COMP_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_10UA (1) -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_10UA_VALUE \ -+ (AW87XXX_PID_60_BST_ADBK_COMP_ADJ_10UA << AW87XXX_PID_60_BST_ADBK_COMP_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_ADBK_COMP_ADJ_DEFAULT \ -+ (AW87XXX_PID_60_BST_ADBK_COMP_ADJ_DEFAULT_VALUE << AW87XXX_PID_60_BST_ADBK_COMP_ADJ_START_BIT) -+ -+/* BST_OVP2_ITH bit 5:4 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_BST_OVP2_ITH_START_BIT (4) -+#define AW87XXX_PID_60_BST_OVP2_ITH_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_OVP2_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP2_ITH_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP2_ITH_32MA (0) -+#define AW87XXX_PID_60_BST_OVP2_ITH_32MA_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_ITH_32MA << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_ITH_48MA (1) -+#define AW87XXX_PID_60_BST_OVP2_ITH_48MA_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_ITH_48MA << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_ITH_64MA (2) -+#define AW87XXX_PID_60_BST_OVP2_ITH_64MA_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_ITH_64MA << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_BST_OVP2_ITH_64MA (3) -+#define AW87XXX_PID_60_BST_OVP2_ITH_64MA_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_ITH_64MA << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_BST_OVP2_ITH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_OVP2_ITH_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP2_ITH_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP2_ITH_START_BIT) -+ -+/* BST_KICK_ITH bit 3:2 (BST_BURST_KICK 0x65) */ -+#define AW87XXX_PID_60_BST_KICK_ITH_START_BIT (2) -+#define AW87XXX_PID_60_BST_KICK_ITH_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_KICK_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_KICK_ITH_BITS_LEN)-1) << AW87XXX_PID_60_BST_KICK_ITH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_KICK_ITH_32MA (0) -+#define AW87XXX_PID_60_BST_KICK_ITH_32MA_VALUE \ -+ (AW87XXX_PID_60_BST_KICK_ITH_32MA << AW87XXX_PID_60_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_KICK_ITH_48MA (1) -+#define AW87XXX_PID_60_BST_KICK_ITH_48MA_VALUE \ -+ (AW87XXX_PID_60_BST_KICK_ITH_48MA << AW87XXX_PID_60_BST_KICK_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_KICK_ITH_64MA (2) -+#define AW87XXX_PID_60_BST_KICK_ITH_64MA_VALUE \ -+ (AW87XXX_PID_60_BST_KICK_ITH_64MA << AW87XXX_PID_60_BST_KICK_ITH_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_BST_KICK_ITH_64MA (3) -+#define AW87XXX_PID_60_BST_KICK_ITH_64MA_VALUE \ -+ (AW87XXX_PID_60_BST_KICK_ITH_64MA << AW87XXX_PID_60_BST_KICK_ITH_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_BST_KICK_ITH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_KICK_ITH_DEFAULT \ -+ (AW87XXX_PID_60_BST_KICK_ITH_DEFAULT_VALUE << AW87XXX_PID_60_BST_KICK_ITH_START_BIT) -+ -+/* default value of BST_BURST_KICK (0x65) */ -+/* #define AW87XXX_PID_60_BST_BURST_KICK_DEFAULT (0x14) */ -+ -+/* BST_CON1 (0x66) detail */ -+/* BST_GTDR_DDT bit 2 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_BST_GTDR_DDT_START_BIT (2) -+#define AW87XXX_PID_60_BST_GTDR_DDT_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_GTDR_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_GTDR_DDT_BITS_LEN)-1) << AW87XXX_PID_60_BST_GTDR_DDT_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_GTDR_DDT_9NS (0) -+#define AW87XXX_PID_60_BST_GTDR_DDT_9NS_VALUE \ -+ (AW87XXX_PID_60_BST_GTDR_DDT_9NS << AW87XXX_PID_60_BST_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_GTDR_DDT_12NS (1) -+#define AW87XXX_PID_60_BST_GTDR_DDT_12NS_VALUE \ -+ (AW87XXX_PID_60_BST_GTDR_DDT_12NS << AW87XXX_PID_60_BST_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_GTDR_DDT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_GTDR_DDT_DEFAULT \ -+ (AW87XXX_PID_60_BST_GTDR_DDT_DEFAULT_VALUE << AW87XXX_PID_60_BST_GTDR_DDT_START_BIT) -+ -+/* EN_ADP_MODE1_DEGLITCH bit 3 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_START_BIT (3) -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_BITS_LEN)-1) << AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DISABLE (0) -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DISABLE << AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_ENABLE (1) -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_ENABLE << AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DEFAULT \ -+ (AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_DEFAULT_VALUE << AW87XXX_PID_60_EN_ADP_MODE1_DEGLITCH_START_BIT) -+ -+/* SS_FINISH_SELECT bit 6 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_SS_FINISH_SELECT_START_BIT (6) -+#define AW87XXX_PID_60_SS_FINISH_SELECT_BITS_LEN (1) -+#define AW87XXX_PID_60_SS_FINISH_SELECT_MASK \ -+ (~(((1<<AW87XXX_PID_60_SS_FINISH_SELECT_BITS_LEN)-1) << AW87XXX_PID_60_SS_FINISH_SELECT_START_BIT)) -+ -+#define AW87XXX_PID_60_SS_FINISH_SELECT_NOT_USE (0) -+#define AW87XXX_PID_60_SS_FINISH_SELECT_NOT_USE_VALUE \ -+ (AW87XXX_PID_60_SS_FINISH_SELECT_NOT_USE << AW87XXX_PID_60_SS_FINISH_SELECT_START_BIT) -+ -+#define AW87XXX_PID_60_SS_FINISH_SELECT_USE (1) -+#define AW87XXX_PID_60_SS_FINISH_SELECT_USE_VALUE \ -+ (AW87XXX_PID_60_SS_FINISH_SELECT_USE << AW87XXX_PID_60_SS_FINISH_SELECT_START_BIT) -+ -+#define AW87XXX_PID_60_SS_FINISH_SELECT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_SS_FINISH_SELECT_DEFAULT \ -+ (AW87XXX_PID_60_SS_FINISH_SELECT_DEFAULT_VALUE << AW87XXX_PID_60_SS_FINISH_SELECT_START_BIT) -+ -+/* BST_GDRV_TEST bit 7 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_BST_GDRV_TEST_START_BIT (7) -+#define AW87XXX_PID_60_BST_GDRV_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_GDRV_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_GDRV_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_GDRV_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_GDRV_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_GDRV_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_GDRV_TEST_DIABLE << AW87XXX_PID_60_BST_GDRV_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_GDRV_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_GDRV_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_GDRV_TEST_ENABLE << AW87XXX_PID_60_BST_GDRV_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_GDRV_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_GDRV_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_GDRV_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_GDRV_TEST_START_BIT) -+ -+/* BST_EN_DELAY bit 5:4 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_BST_EN_DELAY_START_BIT (4) -+#define AW87XXX_PID_60_BST_EN_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_EN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_EN_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_BST_EN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_EN_DELAY_8N (0) -+#define AW87XXX_PID_60_BST_EN_DELAY_8N_VALUE \ -+ (AW87XXX_PID_60_BST_EN_DELAY_8N << AW87XXX_PID_60_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_DELAY_80N (1) -+#define AW87XXX_PID_60_BST_EN_DELAY_80N_VALUE \ -+ (AW87XXX_PID_60_BST_EN_DELAY_80N << AW87XXX_PID_60_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_DELAY_130N (2) -+#define AW87XXX_PID_60_BST_EN_DELAY_130N_VALUE \ -+ (AW87XXX_PID_60_BST_EN_DELAY_130N << AW87XXX_PID_60_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_DELAY_200N (3) -+#define AW87XXX_PID_60_BST_EN_DELAY_200N_VALUE \ -+ (AW87XXX_PID_60_BST_EN_DELAY_200N << AW87XXX_PID_60_BST_EN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_DELAY_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_EN_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_BST_EN_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_BST_EN_DELAY_START_BIT) -+ -+/* BST_SRC bit 1:0 (BST_CON1 0x66) */ -+#define AW87XXX_PID_60_BST_SRC_START_BIT (0) -+#define AW87XXX_PID_60_BST_SRC_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_SRC_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SRC_BITS_LEN)-1) << AW87XXX_PID_60_BST_SRC_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SRC_3NS (0) -+#define AW87XXX_PID_60_BST_SRC_3NS_VALUE \ -+ (AW87XXX_PID_60_BST_SRC_3NS << AW87XXX_PID_60_BST_SRC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SRC_4NS (1) -+#define AW87XXX_PID_60_BST_SRC_4NS_VALUE \ -+ (AW87XXX_PID_60_BST_SRC_4NS << AW87XXX_PID_60_BST_SRC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SRC_7NS (2) -+#define AW87XXX_PID_60_BST_SRC_7NS_VALUE \ -+ (AW87XXX_PID_60_BST_SRC_7NS << AW87XXX_PID_60_BST_SRC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SRC_15NS (3) -+#define AW87XXX_PID_60_BST_SRC_15NS_VALUE \ -+ (AW87XXX_PID_60_BST_SRC_15NS << AW87XXX_PID_60_BST_SRC_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SRC_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SRC_DEFAULT \ -+ (AW87XXX_PID_60_BST_SRC_DEFAULT_VALUE << AW87XXX_PID_60_BST_SRC_START_BIT) -+ -+/* default value of BST_CON1 (0x66) */ -+/* #define AW87XXX_PID_60_BST_CON1_DEFAULT (0x10) */ -+ -+/* BST_OVP (0x67) detail */ -+/* BST_OVP_VTH bit 0 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_OVP_VTH_START_BIT (0) -+#define AW87XXX_PID_60_BST_OVP_VTH_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP_VTH_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP_VTH_3MINUS6P875V (0) -+#define AW87XXX_PID_60_BST_OVP_VTH_3MINUS6P875V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_VTH_3MINUS6P875V << AW87XXX_PID_60_BST_OVP_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_VTH_7MINUS11V (1) -+#define AW87XXX_PID_60_BST_OVP_VTH_7MINUS11V_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_VTH_7MINUS11V << AW87XXX_PID_60_BST_OVP_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_VTH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_OVP_VTH_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP_VTH_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP_VTH_START_BIT) -+ -+/* BST_VFB_EN bit 1 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_VFB_EN_START_BIT (1) -+#define AW87XXX_PID_60_BST_VFB_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_VFB_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_VFB_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_VFB_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_VFB_EN_DISABLE (0) -+#define AW87XXX_PID_60_BST_VFB_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_VFB_EN_DISABLE << AW87XXX_PID_60_BST_VFB_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VFB_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_VFB_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_VFB_EN_ENABLE << AW87XXX_PID_60_BST_VFB_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_VFB_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_VFB_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_VFB_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_VFB_EN_START_BIT) -+ -+/* BST_FORCE_PWM bit 2 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_FORCE_PWM_START_BIT (2) -+#define AW87XXX_PID_60_BST_FORCE_PWM_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_FORCE_PWM_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_FORCE_PWM_BITS_LEN)-1) << AW87XXX_PID_60_BST_FORCE_PWM_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_FORCE_PWM_DISABLE (0) -+#define AW87XXX_PID_60_BST_FORCE_PWM_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_FORCE_PWM_DISABLE << AW87XXX_PID_60_BST_FORCE_PWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_FORCE_PWM_ENABLE (1) -+#define AW87XXX_PID_60_BST_FORCE_PWM_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_FORCE_PWM_ENABLE << AW87XXX_PID_60_BST_FORCE_PWM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_FORCE_PWM_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_FORCE_PWM_DEFAULT \ -+ (AW87XXX_PID_60_BST_FORCE_PWM_DEFAULT_VALUE << AW87XXX_PID_60_BST_FORCE_PWM_START_BIT) -+ -+/* BST_OVP2_EN bit 5 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_OVP2_EN_START_BIT (5) -+#define AW87XXX_PID_60_BST_OVP2_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP2_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP2_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP2_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP2_EN_DISABLE (0) -+#define AW87XXX_PID_60_BST_OVP2_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_EN_DISABLE << AW87XXX_PID_60_BST_OVP2_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_OVP2_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_OVP2_EN_ENABLE << AW87XXX_PID_60_BST_OVP2_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP2_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_OVP2_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP2_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP2_EN_START_BIT) -+ -+/* BST_OVP_DEGLI_SEL bit 6 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_START_BIT (6) -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP_DEGLI_SEL_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP_DEGLI_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_NO_DEGLITCH (0) -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_NO_DEGLITCH_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_DEGLI_SEL_NO_DEGLITCH << AW87XXX_PID_60_BST_OVP_DEGLI_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEGLITCH (1) -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEGLITCH_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEGLITCH << AW87XXX_PID_60_BST_OVP_DEGLI_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP_DEGLI_SEL_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP_DEGLI_SEL_START_BIT) -+ -+/* BST_CLK_DIV bit 7 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BST_CLK_DIV_START_BIT (7) -+#define AW87XXX_PID_60_BST_CLK_DIV_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_CLK_DIV_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_CLK_DIV_BITS_LEN)-1) << AW87XXX_PID_60_BST_CLK_DIV_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_4 (0) -+#define AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_4_VALUE \ -+ (AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_4 << AW87XXX_PID_60_BST_CLK_DIV_START_BIT) -+ -+#define AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_2 (1) -+#define AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_2_VALUE \ -+ (AW87XXX_PID_60_BST_CLK_DIV_DIV_BY_2 << AW87XXX_PID_60_BST_CLK_DIV_START_BIT) -+ -+#define AW87XXX_PID_60_BST_CLK_DIV_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_CLK_DIV_DEFAULT \ -+ (AW87XXX_PID_60_BST_CLK_DIV_DEFAULT_VALUE << AW87XXX_PID_60_BST_CLK_DIV_START_BIT) -+ -+/* BURST_HYS_EN bit 4:3 (BST_OVP 0x67) */ -+#define AW87XXX_PID_60_BURST_HYS_EN_START_BIT (3) -+#define AW87XXX_PID_60_BURST_HYS_EN_BITS_LEN (2) -+#define AW87XXX_PID_60_BURST_HYS_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BURST_HYS_EN_BITS_LEN)-1) << AW87XXX_PID_60_BURST_HYS_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BURST_HYS_EN_OUT (0) -+#define AW87XXX_PID_60_BURST_HYS_EN_OUT_VALUE \ -+ (AW87XXX_PID_60_BURST_HYS_EN_OUT << AW87XXX_PID_60_BURST_HYS_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_HYS_EN_IN (1) -+#define AW87XXX_PID_60_BURST_HYS_EN_IN_VALUE \ -+ (AW87XXX_PID_60_BURST_HYS_EN_IN << AW87XXX_PID_60_BURST_HYS_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_HYS_EN_OUT_AND_IN (3) -+#define AW87XXX_PID_60_BURST_HYS_EN_OUT_AND_IN_VALUE \ -+ (AW87XXX_PID_60_BURST_HYS_EN_OUT_AND_IN << AW87XXX_PID_60_BURST_HYS_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BURST_HYS_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BURST_HYS_EN_DEFAULT \ -+ (AW87XXX_PID_60_BURST_HYS_EN_DEFAULT_VALUE << AW87XXX_PID_60_BURST_HYS_EN_START_BIT) -+ -+/* default value of BST_OVP (0x67) */ -+/* #define AW87XXX_PID_60_BST_OVP_DEFAULT (0x81) */ -+ -+/* LINE_MODE (0x68) detail */ -+/* BST_EN_RSQN_DLY bit 0 (LINE_MODE 0x68) */ -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_START_BIT (0) -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_EN_RSQN_DLY_BITS_LEN)-1) << AW87XXX_PID_60_BST_EN_RSQN_DLY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_DISABLE (0) -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_EN_RSQN_DLY_DISABLE << AW87XXX_PID_60_BST_EN_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_ENABLE (1) -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_EN_RSQN_DLY_ENABLE << AW87XXX_PID_60_BST_EN_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_EN_RSQN_DLY_DEFAULT \ -+ (AW87XXX_PID_60_BST_EN_RSQN_DLY_DEFAULT_VALUE << AW87XXX_PID_60_BST_EN_RSQN_DLY_START_BIT) -+ -+/* BST_FORCE_BOOST bit 1 (LINE_MODE 0x68) */ -+#define AW87XXX_PID_60_BST_FORCE_BOOST_START_BIT (1) -+#define AW87XXX_PID_60_BST_FORCE_BOOST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_FORCE_BOOST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_FORCE_BOOST_BITS_LEN)-1) << AW87XXX_PID_60_BST_FORCE_BOOST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_FORCE_BOOST_DISABLE (0) -+#define AW87XXX_PID_60_BST_FORCE_BOOST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_FORCE_BOOST_DISABLE << AW87XXX_PID_60_BST_FORCE_BOOST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_FORCE_BOOST_ENABLE (1) -+#define AW87XXX_PID_60_BST_FORCE_BOOST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_FORCE_BOOST_ENABLE << AW87XXX_PID_60_BST_FORCE_BOOST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_FORCE_BOOST_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_FORCE_BOOST_DEFAULT \ -+ (AW87XXX_PID_60_BST_FORCE_BOOST_DEFAULT_VALUE << AW87XXX_PID_60_BST_FORCE_BOOST_START_BIT) -+ -+/* BST_PWM_SHORT bit 2 (LINE_MODE 0x68) */ -+#define AW87XXX_PID_60_BST_PWM_SHORT_START_BIT (2) -+#define AW87XXX_PID_60_BST_PWM_SHORT_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_PWM_SHORT_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_PWM_SHORT_BITS_LEN)-1) << AW87XXX_PID_60_BST_PWM_SHORT_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDD (0) -+#define AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDD_VALUE \ -+ (AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDD << AW87XXX_PID_60_BST_PWM_SHORT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDDMINUSVTH (1) -+#define AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDDMINUSVTH_VALUE \ -+ (AW87XXX_PID_60_BST_PWM_SHORT_VBSTBELOWVDDMINUSVTH << AW87XXX_PID_60_BST_PWM_SHORT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_PWM_SHORT_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_PWM_SHORT_DEFAULT \ -+ (AW87XXX_PID_60_BST_PWM_SHORT_DEFAULT_VALUE << AW87XXX_PID_60_BST_PWM_SHORT_START_BIT) -+ -+/* BST_OS_WIDTH bit 7:5 (LINE_MODE 0x68) */ -+#define AW87XXX_PID_60_BST_OS_WIDTH_START_BIT (5) -+#define AW87XXX_PID_60_BST_OS_WIDTH_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_OS_WIDTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OS_WIDTH_BITS_LEN)-1) << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_10NS (0) -+#define AW87XXX_PID_60_BST_OS_WIDTH_10NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_10NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_20NS (1) -+#define AW87XXX_PID_60_BST_OS_WIDTH_20NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_20NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_30NS (2) -+#define AW87XXX_PID_60_BST_OS_WIDTH_30NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_30NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_40NS (3) -+#define AW87XXX_PID_60_BST_OS_WIDTH_40NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_40NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_50NS (4) -+#define AW87XXX_PID_60_BST_OS_WIDTH_50NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_50NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_60NS (5) -+#define AW87XXX_PID_60_BST_OS_WIDTH_60NS_VALUE \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_60NS << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OS_WIDTH_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_OS_WIDTH_DEFAULT \ -+ (AW87XXX_PID_60_BST_OS_WIDTH_DEFAULT_VALUE << AW87XXX_PID_60_BST_OS_WIDTH_START_BIT) -+ -+/* MODE1_START_DELAY bit 4:3 (LINE_MODE 0x68) */ -+#define AW87XXX_PID_60_MODE1_START_DELAY_START_BIT (3) -+#define AW87XXX_PID_60_MODE1_START_DELAY_BITS_LEN (2) -+#define AW87XXX_PID_60_MODE1_START_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_MODE1_START_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_MODE1_START_DELAY_15P6US (0) -+#define AW87XXX_PID_60_MODE1_START_DELAY_15P6US_VALUE \ -+ (AW87XXX_PID_60_MODE1_START_DELAY_15P6US << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_MODE1_START_DELAY_11P4US (1) -+#define AW87XXX_PID_60_MODE1_START_DELAY_11P4US_VALUE \ -+ (AW87XXX_PID_60_MODE1_START_DELAY_11P4US << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_MODE1_START_DELAY_7P3US (2) -+#define AW87XXX_PID_60_MODE1_START_DELAY_7P3US_VALUE \ -+ (AW87XXX_PID_60_MODE1_START_DELAY_7P3US << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_MODE1_START_DELAY_3US (3) -+#define AW87XXX_PID_60_MODE1_START_DELAY_3US_VALUE \ -+ (AW87XXX_PID_60_MODE1_START_DELAY_3US << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_MODE1_START_DELAY_DEFAULT_VALUE (3) -+#define AW87XXX_PID_60_MODE1_START_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_MODE1_START_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_MODE1_START_DELAY_START_BIT) -+ -+/* default value of LINE_MODE (0x68) */ -+/* #define AW87XXX_PID_60_LINE_MODE_DEFAULT (0x3F) */ -+ -+/* BST_ISEN (0x69) detail */ -+/* BST_RSQN_DLY bit 7:5 (BST_ISEN 0x69) */ -+#define AW87XXX_PID_60_BST_RSQN_DLY_START_BIT (5) -+#define AW87XXX_PID_60_BST_RSQN_DLY_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_RSQN_DLY_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_RSQN_DLY_BITS_LEN)-1) << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_15NS (0) -+#define AW87XXX_PID_60_BST_RSQN_DLY_15NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_15NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_25NS (1) -+#define AW87XXX_PID_60_BST_RSQN_DLY_25NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_25NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_35NS (2) -+#define AW87XXX_PID_60_BST_RSQN_DLY_35NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_35NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_45NS (3) -+#define AW87XXX_PID_60_BST_RSQN_DLY_45NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_45NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_70NS (4) -+#define AW87XXX_PID_60_BST_RSQN_DLY_70NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_70NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_80NS (5) -+#define AW87XXX_PID_60_BST_RSQN_DLY_80NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_80NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_90NS (6) -+#define AW87XXX_PID_60_BST_RSQN_DLY_90NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_90NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_100NS (7) -+#define AW87XXX_PID_60_BST_RSQN_DLY_100NS_VALUE \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_100NS << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+#define AW87XXX_PID_60_BST_RSQN_DLY_DEFAULT_VALUE (2) -+#define AW87XXX_PID_60_BST_RSQN_DLY_DEFAULT \ -+ (AW87XXX_PID_60_BST_RSQN_DLY_DEFAULT_VALUE << AW87XXX_PID_60_BST_RSQN_DLY_START_BIT) -+ -+/* BST_SLOPE bit 4:3 (BST_ISEN 0x69) */ -+#define AW87XXX_PID_60_BST_SLOPE_START_BIT (3) -+#define AW87XXX_PID_60_BST_SLOPE_BITS_LEN (2) -+#define AW87XXX_PID_60_BST_SLOPE_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SLOPE_BITS_LEN)-1) << AW87XXX_PID_60_BST_SLOPE_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1 (0) -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_ISLOPE1 << AW87XXX_PID_60_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P25 (1) -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P25_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_ISLOPE1P25 << AW87XXX_PID_60_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P5 (2) -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P5_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_ISLOPE1P5 << AW87XXX_PID_60_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P75 (3) -+#define AW87XXX_PID_60_BST_SLOPE_ISLOPE1P75_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_ISLOPE1P75 << AW87XXX_PID_60_BST_SLOPE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SLOPE_DEFAULT \ -+ (AW87XXX_PID_60_BST_SLOPE_DEFAULT_VALUE << AW87XXX_PID_60_BST_SLOPE_START_BIT) -+ -+/* BST_SLOPE_LIMIT bit 2:0 (BST_ISEN 0x69) */ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT (0) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SLOPE_LIMIT_BITS_LEN)-1) << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_0P50ISLOPE (0) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_0P50ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_0P50ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_0P75ISLOPE (1) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_0P75ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_0P75ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P00ISLOPE (2) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P00ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_1P00ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P25ISLOPE (3) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P25ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_1P25ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P50ISLOPE (4) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P50ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_1P50ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P75ISLOPE (5) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_1P75ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_1P75ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_2P00ISLOPE (6) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_2P00ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_2P00ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_2P25ISLOPE (7) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_2P25ISLOPE_VALUE \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_2P25ISLOPE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_DEFAULT_VALUE (2) -+#define AW87XXX_PID_60_BST_SLOPE_LIMIT_DEFAULT \ -+ (AW87XXX_PID_60_BST_SLOPE_LIMIT_DEFAULT_VALUE << AW87XXX_PID_60_BST_SLOPE_LIMIT_START_BIT) -+ -+/* default value of BST_ISEN (0x69) */ -+/* #define AW87XXX_PID_60_BST_ISEN_DEFAULT (0x42) */ -+ -+/* BST_PEAK (0x6A) detail */ -+/* BST_IPEAK_LOWBAT bit 3 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_START_BIT (3) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_LOWBAT_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_LOWBAT_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P5A (0) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P5A << AW87XXX_PID_60_BST_IPEAK_LOWBAT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P75A (1) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P75A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_2P75A << AW87XXX_PID_60_BST_IPEAK_LOWBAT_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_LOWBAT_START_BIT) -+ -+/* BST_IPEAK_LOWBAT_EN bit 4 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_START_BIT (4) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DISABLE (0) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DISABLE << AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_ENABLE << AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_LOWBAT_EN_START_BIT) -+ -+/* BST_IPEAK_ADJ bit 5 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_START_BIT (5) -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_ADJ_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK (0) -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK << AW87XXX_PID_60_BST_IPEAK_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK0P5A (1) -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK0P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_ADJ_IPEAK0P5A << AW87XXX_PID_60_BST_IPEAK_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_IPEAK_ADJ_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_ADJ_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_ADJ_START_BIT) -+ -+/* BACK_ADPT_R400K bit 6 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_BACK_ADPT_R400K_START_BIT (6) -+#define AW87XXX_PID_60_BACK_ADPT_R400K_BITS_LEN (1) -+#define AW87XXX_PID_60_BACK_ADPT_R400K_MASK \ -+ (~(((1<<AW87XXX_PID_60_BACK_ADPT_R400K_BITS_LEN)-1) << AW87XXX_PID_60_BACK_ADPT_R400K_START_BIT)) -+ -+#define AW87XXX_PID_60_BACK_ADPT_R400K_DISABLE (0) -+#define AW87XXX_PID_60_BACK_ADPT_R400K_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BACK_ADPT_R400K_DISABLE << AW87XXX_PID_60_BACK_ADPT_R400K_START_BIT) -+ -+#define AW87XXX_PID_60_BACK_ADPT_R400K_ENABALE (1) -+#define AW87XXX_PID_60_BACK_ADPT_R400K_ENABALE_VALUE \ -+ (AW87XXX_PID_60_BACK_ADPT_R400K_ENABALE << AW87XXX_PID_60_BACK_ADPT_R400K_START_BIT) -+ -+#define AW87XXX_PID_60_BACK_ADPT_R400K_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BACK_ADPT_R400K_DEFAULT \ -+ (AW87XXX_PID_60_BACK_ADPT_R400K_DEFAULT_VALUE << AW87XXX_PID_60_BACK_ADPT_R400K_START_BIT) -+ -+/* SEL_FINISH_ID bit 7 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_SEL_FINISH_ID_START_BIT (7) -+#define AW87XXX_PID_60_SEL_FINISH_ID_BITS_LEN (1) -+#define AW87XXX_PID_60_SEL_FINISH_ID_MASK \ -+ (~(((1<<AW87XXX_PID_60_SEL_FINISH_ID_BITS_LEN)-1) << AW87XXX_PID_60_SEL_FINISH_ID_START_BIT)) -+ -+#define AW87XXX_PID_60_SEL_FINISH_ID_MODE1START (0) -+#define AW87XXX_PID_60_SEL_FINISH_ID_MODE1START_VALUE \ -+ (AW87XXX_PID_60_SEL_FINISH_ID_MODE1START << AW87XXX_PID_60_SEL_FINISH_ID_START_BIT) -+ -+#define AW87XXX_PID_60_SEL_FINISH_ID_LIMITSSFINISH (1) -+#define AW87XXX_PID_60_SEL_FINISH_ID_LIMITSSFINISH_VALUE \ -+ (AW87XXX_PID_60_SEL_FINISH_ID_LIMITSSFINISH << AW87XXX_PID_60_SEL_FINISH_ID_START_BIT) -+ -+#define AW87XXX_PID_60_SEL_FINISH_ID_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_SEL_FINISH_ID_DEFAULT \ -+ (AW87XXX_PID_60_SEL_FINISH_ID_DEFAULT_VALUE << AW87XXX_PID_60_SEL_FINISH_ID_START_BIT) -+ -+/* BST_IPEAK_SS bit 2:0 (BST_PEAK 0x6A) */ -+#define AW87XXX_PID_60_BST_IPEAK_SS_START_BIT (0) -+#define AW87XXX_PID_60_BST_IPEAK_SS_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_IPEAK_SS_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_SS_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_0P8A (0) -+#define AW87XXX_PID_60_BST_IPEAK_SS_0P8A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_0P8A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P0A (1) -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P0A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_1P0A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P25A (2) -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P25A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_1P25A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P5A (3) -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_1P5A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P75A (4) -+#define AW87XXX_PID_60_BST_IPEAK_SS_1P75A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_1P75A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_2A (5) -+#define AW87XXX_PID_60_BST_IPEAK_SS_2A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_2A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_2P25A (6) -+#define AW87XXX_PID_60_BST_IPEAK_SS_2P25A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_2P25A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_2P50A (7) -+#define AW87XXX_PID_60_BST_IPEAK_SS_2P50A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_2P50A << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_SS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_60_BST_IPEAK_SS_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_SS_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_SS_START_BIT) -+ -+/* default value of BST_PEAK (0x6A) */ -+/* #define AW87XXX_PID_60_BST_PEAK_DEFAULT (0x01) */ -+ -+/* BST_PEAK2 (0x6B) detail */ -+/* BST_BACK_EN bit 2 (BST_PEAK2 0x6B) */ -+#define AW87XXX_PID_60_BST_BACK_EN_START_BIT (2) -+#define AW87XXX_PID_60_BST_BACK_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_BACK_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BACK_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_BACK_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BACK_EN_ENABLE (0) -+#define AW87XXX_PID_60_BST_BACK_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_BACK_EN_ENABLE << AW87XXX_PID_60_BST_BACK_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BACK_EN_DIABALE (1) -+#define AW87XXX_PID_60_BST_BACK_EN_DIABALE_VALUE \ -+ (AW87XXX_PID_60_BST_BACK_EN_DIABALE << AW87XXX_PID_60_BST_BACK_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BACK_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_BACK_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_BACK_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_BACK_EN_START_BIT) -+ -+/* BST_IPEAK_ITH_EN bit 3 (BST_PEAK2 0x6B) */ -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_START_BIT (3) -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_ITH_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_ITH_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAK (0) -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAK_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAK << AW87XXX_PID_60_BST_IPEAK_ITH_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAKMINUS0P5A (1) -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAKMINUS0P5A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_ITH_EN_IPEAKMINUS0P5A << AW87XXX_PID_60_BST_IPEAK_ITH_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_IPEAK_ITH_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_ITH_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_ITH_EN_START_BIT) -+ -+/* BST_IPEAK_TRIM bit 7:4 (BST_PEAK2 0x6B) */ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT (4) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_BITS_LEN (4) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_IPEAK_TRIM_BITS_LEN)-1) << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0A (0) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_0A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P2A (1) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P2A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_0P2A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P4A (2) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P4A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_0P4A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P6A (3) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_0P6A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_0P6A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P6A (8) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P6A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P6A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P4A (9) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P4A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P4A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P2A (10) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P2A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1P2A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1A (11) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS1A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P8A (12) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P8A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P8A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P6A (13) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P6A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P6A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P4A (14) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P4A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P4A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P2A (15) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P2A_VALUE \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_MINUS0P2A << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_IPEAK_TRIM_DEFAULT \ -+ (AW87XXX_PID_60_BST_IPEAK_TRIM_DEFAULT_VALUE << AW87XXX_PID_60_BST_IPEAK_TRIM_START_BIT) -+ -+/* OFFTIME_OUT_C bit 1:0 (BST_PEAK2 0x6B) */ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT (0) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_BITS_LEN (2) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_MASK \ -+ (~(((1<<AW87XXX_PID_60_OFFTIME_OUT_C_BITS_LEN)-1) << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT)) -+ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_0 (0) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_0_VALUE \ -+ (AW87XXX_PID_60_OFFTIME_OUT_C_0 << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT) -+ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_1 (1) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_1_VALUE \ -+ (AW87XXX_PID_60_OFFTIME_OUT_C_1 << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT) -+ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_2 (2) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_2_VALUE \ -+ (AW87XXX_PID_60_OFFTIME_OUT_C_2 << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT) -+ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_3 (3) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_3_VALUE \ -+ (AW87XXX_PID_60_OFFTIME_OUT_C_3 << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT) -+ -+#define AW87XXX_PID_60_OFFTIME_OUT_C_DEFAULT_VALUE (2) -+#define AW87XXX_PID_60_OFFTIME_OUT_C_DEFAULT \ -+ (AW87XXX_PID_60_OFFTIME_OUT_C_DEFAULT_VALUE << AW87XXX_PID_60_OFFTIME_OUT_C_START_BIT) -+ -+/* default value of BST_PEAK2 (0x6B) */ -+/* #define AW87XXX_PID_60_BST_PEAK2_DEFAULT (0x02) */ -+ -+/* OFFTIME (0x6C) detail */ -+/* HEAD_ROOM bit 3 (OFFTIME 0x6C) */ -+#define AW87XXX_PID_60_HEAD_ROOM_START_BIT (3) -+#define AW87XXX_PID_60_HEAD_ROOM_BITS_LEN (1) -+#define AW87XXX_PID_60_HEAD_ROOM_MASK \ -+ (~(((1<<AW87XXX_PID_60_HEAD_ROOM_BITS_LEN)-1) << AW87XXX_PID_60_HEAD_ROOM_START_BIT)) -+ -+#define AW87XXX_PID_60_HEAD_ROOM_1P5V (0) -+#define AW87XXX_PID_60_HEAD_ROOM_1P5V_VALUE \ -+ (AW87XXX_PID_60_HEAD_ROOM_1P5V << AW87XXX_PID_60_HEAD_ROOM_START_BIT) -+ -+#define AW87XXX_PID_60_HEAD_ROOM_2P0V (1) -+#define AW87XXX_PID_60_HEAD_ROOM_2P0V_VALUE \ -+ (AW87XXX_PID_60_HEAD_ROOM_2P0V << AW87XXX_PID_60_HEAD_ROOM_START_BIT) -+ -+#define AW87XXX_PID_60_HEAD_ROOM_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_HEAD_ROOM_DEFAULT \ -+ (AW87XXX_PID_60_HEAD_ROOM_DEFAULT_VALUE << AW87XXX_PID_60_HEAD_ROOM_START_BIT) -+ -+/* BST_OFFTIME_EN bit 7 (OFFTIME 0x6C) */ -+#define AW87XXX_PID_60_BST_OFFTIME_EN_START_BIT (7) -+#define AW87XXX_PID_60_BST_OFFTIME_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OFFTIME_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OFFTIME_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_OFFTIME_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_EN_ENABLE (0) -+#define AW87XXX_PID_60_BST_OFFTIME_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_EN_ENABLE << AW87XXX_PID_60_BST_OFFTIME_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_EN_DIABALE (1) -+#define AW87XXX_PID_60_BST_OFFTIME_EN_DIABALE_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_EN_DIABALE << AW87XXX_PID_60_BST_OFFTIME_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_OFFTIME_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_OFFTIME_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_OFFTIME_EN_START_BIT) -+ -+/* BST_OFFTIME bit 6:4 (OFFTIME 0x6C) */ -+#define AW87XXX_PID_60_BST_OFFTIME_START_BIT (4) -+#define AW87XXX_PID_60_BST_OFFTIME_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_OFFTIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OFFTIME_BITS_LEN)-1) << AW87XXX_PID_60_BST_OFFTIME_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_4 (0) -+#define AW87XXX_PID_60_BST_OFFTIME_4_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_4 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_3 (1) -+#define AW87XXX_PID_60_BST_OFFTIME_3_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_3 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_2 (2) -+#define AW87XXX_PID_60_BST_OFFTIME_2_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_2 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_1 (3) -+#define AW87XXX_PID_60_BST_OFFTIME_1_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_1 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_0 (4) -+#define AW87XXX_PID_60_BST_OFFTIME_0_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_0 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS1 (5) -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS1_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_MINUS1 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS2 (6) -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS2_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_MINUS2 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS3 (7) -+#define AW87XXX_PID_60_BST_OFFTIME_MINUS3_VALUE \ -+ (AW87XXX_PID_60_BST_OFFTIME_MINUS3 << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OFFTIME_DEFAULT_VALUE (4) -+#define AW87XXX_PID_60_BST_OFFTIME_DEFAULT \ -+ (AW87XXX_PID_60_BST_OFFTIME_DEFAULT_VALUE << AW87XXX_PID_60_BST_OFFTIME_START_BIT) -+ -+/* BST_OUT_VTH0 bit 2:0 (OFFTIME 0x6C) */ -+#define AW87XXX_PID_60_BST_OUT_VTH0_START_BIT (0) -+#define AW87XXX_PID_60_BST_OUT_VTH0_BITS_LEN (3) -+#define AW87XXX_PID_60_BST_OUT_VTH0_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OUT_VTH0_BITS_LEN)-1) << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_6P5V (0) -+#define AW87XXX_PID_60_BST_OUT_VTH0_6P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_6P5V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_6P75V (1) -+#define AW87XXX_PID_60_BST_OUT_VTH0_6P75V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_6P75V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P0V (2) -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P0V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_7P0V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P25V (3) -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P25V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_7P25V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P5V (4) -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P5V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_7P5V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P75V (5) -+#define AW87XXX_PID_60_BST_OUT_VTH0_7P75V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_7P75V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_8P0V (6) -+#define AW87XXX_PID_60_BST_OUT_VTH0_8P0V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_8P0V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_8P25V (7) -+#define AW87XXX_PID_60_BST_OUT_VTH0_8P25V_VALUE \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_8P25V << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OUT_VTH0_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_BST_OUT_VTH0_DEFAULT \ -+ (AW87XXX_PID_60_BST_OUT_VTH0_DEFAULT_VALUE << AW87XXX_PID_60_BST_OUT_VTH0_START_BIT) -+ -+/* default value of OFFTIME (0x6C) */ -+/* #define AW87XXX_PID_60_OFFTIME_DEFAULT (0x41) */ -+ -+/* ADPBST (0x6D) detail */ -+/* REG_CLK_CP_OTA bit 0 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_START_BIT (0) -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_CLK_CP_OTA_BITS_LEN)-1) << AW87XXX_PID_60_REG_CLK_CP_OTA_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_200KHZ (0) -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_200KHZ_VALUE \ -+ (AW87XXX_PID_60_REG_CLK_CP_OTA_200KHZ << AW87XXX_PID_60_REG_CLK_CP_OTA_START_BIT) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_400KHZ (1) -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_400KHZ_VALUE \ -+ (AW87XXX_PID_60_REG_CLK_CP_OTA_400KHZ << AW87XXX_PID_60_REG_CLK_CP_OTA_START_BIT) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_CLK_CP_OTA_DEFAULT \ -+ (AW87XXX_PID_60_REG_CLK_CP_OTA_DEFAULT_VALUE << AW87XXX_PID_60_REG_CLK_CP_OTA_START_BIT) -+ -+/* OTA_MD2 bit 1 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_OTA_MD2_START_BIT (1) -+#define AW87XXX_PID_60_OTA_MD2_BITS_LEN (1) -+#define AW87XXX_PID_60_OTA_MD2_MASK \ -+ (~(((1<<AW87XXX_PID_60_OTA_MD2_BITS_LEN)-1) << AW87XXX_PID_60_OTA_MD2_START_BIT)) -+ -+#define AW87XXX_PID_60_OTA_MD2_DISABLE (0) -+#define AW87XXX_PID_60_OTA_MD2_DISABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_MD2_DISABLE << AW87XXX_PID_60_OTA_MD2_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_MD2_ENABLE (1) -+#define AW87XXX_PID_60_OTA_MD2_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_MD2_ENABLE << AW87XXX_PID_60_OTA_MD2_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_MD2_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_OTA_MD2_DEFAULT \ -+ (AW87XXX_PID_60_OTA_MD2_DEFAULT_VALUE << AW87XXX_PID_60_OTA_MD2_START_BIT) -+ -+/* OTA_RCV bit 2 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_OTA_RCV_START_BIT (2) -+#define AW87XXX_PID_60_OTA_RCV_BITS_LEN (1) -+#define AW87XXX_PID_60_OTA_RCV_MASK \ -+ (~(((1<<AW87XXX_PID_60_OTA_RCV_BITS_LEN)-1) << AW87XXX_PID_60_OTA_RCV_START_BIT)) -+ -+#define AW87XXX_PID_60_OTA_RCV_DISABLE (0) -+#define AW87XXX_PID_60_OTA_RCV_DISABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_RCV_DISABLE << AW87XXX_PID_60_OTA_RCV_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_RCV_ENABLE (1) -+#define AW87XXX_PID_60_OTA_RCV_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_RCV_ENABLE << AW87XXX_PID_60_OTA_RCV_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_RCV_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_OTA_RCV_DEFAULT \ -+ (AW87XXX_PID_60_OTA_RCV_DEFAULT_VALUE << AW87XXX_PID_60_OTA_RCV_START_BIT) -+ -+/* MSBM_VDD_SEL bit 3 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_MSBM_VDD_SEL_START_BIT (3) -+#define AW87XXX_PID_60_MSBM_VDD_SEL_BITS_LEN (1) -+#define AW87XXX_PID_60_MSBM_VDD_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_MSBM_VDD_SEL_BITS_LEN)-1) << AW87XXX_PID_60_MSBM_VDD_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_MSBM_VDD_SEL_VDDBELOW4P5V (0) -+#define AW87XXX_PID_60_MSBM_VDD_SEL_VDDBELOW4P5V_VALUE \ -+ (AW87XXX_PID_60_MSBM_VDD_SEL_VDDBELOW4P5V << AW87XXX_PID_60_MSBM_VDD_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_MSBM_VDD_SEL_VDDABOVE4P5V (1) -+#define AW87XXX_PID_60_MSBM_VDD_SEL_VDDABOVE4P5V_VALUE \ -+ (AW87XXX_PID_60_MSBM_VDD_SEL_VDDABOVE4P5V << AW87XXX_PID_60_MSBM_VDD_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_MSBM_VDD_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_MSBM_VDD_SEL_DEFAULT \ -+ (AW87XXX_PID_60_MSBM_VDD_SEL_DEFAULT_VALUE << AW87XXX_PID_60_MSBM_VDD_SEL_START_BIT) -+ -+/* DLY_EN bit 4 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_DLY_EN_START_BIT (4) -+#define AW87XXX_PID_60_DLY_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_DLY_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_DLY_EN_BITS_LEN)-1) << AW87XXX_PID_60_DLY_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_DLY_EN_DISABLE (0) -+#define AW87XXX_PID_60_DLY_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_DLY_EN_DISABLE << AW87XXX_PID_60_DLY_EN_START_BIT) -+ -+#define AW87XXX_PID_60_DLY_EN_ENABLE (1) -+#define AW87XXX_PID_60_DLY_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_DLY_EN_ENABLE << AW87XXX_PID_60_DLY_EN_START_BIT) -+ -+#define AW87XXX_PID_60_DLY_EN_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_DLY_EN_DEFAULT \ -+ (AW87XXX_PID_60_DLY_EN_DEFAULT_VALUE << AW87XXX_PID_60_DLY_EN_START_BIT) -+ -+/* DLY_CLK_EN bit 5 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_DLY_CLK_EN_START_BIT (5) -+#define AW87XXX_PID_60_DLY_CLK_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_DLY_CLK_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_DLY_CLK_EN_BITS_LEN)-1) << AW87XXX_PID_60_DLY_CLK_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_DLY_CLK_EN_DISABLE (0) -+#define AW87XXX_PID_60_DLY_CLK_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_DLY_CLK_EN_DISABLE << AW87XXX_PID_60_DLY_CLK_EN_START_BIT) -+ -+#define AW87XXX_PID_60_DLY_CLK_EN_ENABLE (1) -+#define AW87XXX_PID_60_DLY_CLK_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_DLY_CLK_EN_ENABLE << AW87XXX_PID_60_DLY_CLK_EN_START_BIT) -+ -+#define AW87XXX_PID_60_DLY_CLK_EN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_DLY_CLK_EN_DEFAULT \ -+ (AW87XXX_PID_60_DLY_CLK_EN_DEFAULT_VALUE << AW87XXX_PID_60_DLY_CLK_EN_START_BIT) -+ -+/* ADPBST_FALL_TIME bit 7:6 (ADPBST 0x6D) */ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT (6) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_BITS_LEN (2) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_ADPBST_FALL_TIME_BITS_LEN)-1) << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_5MS (0) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_5MS_VALUE \ -+ (AW87XXX_PID_60_ADPBST_FALL_TIME_5MS << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_10MS (1) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_10MS_VALUE \ -+ (AW87XXX_PID_60_ADPBST_FALL_TIME_10MS << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_20MS (2) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_20MS_VALUE \ -+ (AW87XXX_PID_60_ADPBST_FALL_TIME_20MS << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_40MS (3) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_40MS_VALUE \ -+ (AW87XXX_PID_60_ADPBST_FALL_TIME_40MS << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_ADPBST_FALL_TIME_DEFAULT \ -+ (AW87XXX_PID_60_ADPBST_FALL_TIME_DEFAULT_VALUE << AW87XXX_PID_60_ADPBST_FALL_TIME_START_BIT) -+ -+/* default value of ADPBST (0x6D) */ -+/* #define AW87XXX_PID_60_ADPBST_DEFAULT (0x50) */ -+ -+/* OTA (0x6E) detail */ -+/* EN_SWF bit 0 (OTA 0x6E) */ -+#define AW87XXX_PID_60_EN_SWF_START_BIT (0) -+#define AW87XXX_PID_60_EN_SWF_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_SWF_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_SWF_BITS_LEN)-1) << AW87XXX_PID_60_EN_SWF_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_SWF_DISABLE (0) -+#define AW87XXX_PID_60_EN_SWF_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_SWF_DISABLE << AW87XXX_PID_60_EN_SWF_START_BIT) -+ -+#define AW87XXX_PID_60_EN_SWF_ENABLE (1) -+#define AW87XXX_PID_60_EN_SWF_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_SWF_ENABLE << AW87XXX_PID_60_EN_SWF_START_BIT) -+ -+#define AW87XXX_PID_60_EN_SWF_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_SWF_DEFAULT \ -+ (AW87XXX_PID_60_EN_SWF_DEFAULT_VALUE << AW87XXX_PID_60_EN_SWF_START_BIT) -+ -+/* BST_CK_MODE bit 1 (OTA 0x6E) */ -+#define AW87XXX_PID_60_BST_CK_MODE_START_BIT (1) -+#define AW87XXX_PID_60_BST_CK_MODE_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_CK_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_CK_MODE_BITS_LEN)-1) << AW87XXX_PID_60_BST_CK_MODE_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_CK_MODE_1P6MHZ (0) -+#define AW87XXX_PID_60_BST_CK_MODE_1P6MHZ_VALUE \ -+ (AW87XXX_PID_60_BST_CK_MODE_1P6MHZ << AW87XXX_PID_60_BST_CK_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_CK_MODE_2P0MHZ (1) -+#define AW87XXX_PID_60_BST_CK_MODE_2P0MHZ_VALUE \ -+ (AW87XXX_PID_60_BST_CK_MODE_2P0MHZ << AW87XXX_PID_60_BST_CK_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_CK_MODE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_BST_CK_MODE_DEFAULT \ -+ (AW87XXX_PID_60_BST_CK_MODE_DEFAULT_VALUE << AW87XXX_PID_60_BST_CK_MODE_START_BIT) -+ -+/* EN_LOOP_GBW_REDUCE bit 2 (OTA 0x6E) */ -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_START_BIT (2) -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_BITS_LEN)-1) << AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DISABLE (0) -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DISABLE << AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_START_BIT) -+ -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_ENABLE (1) -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_ENABLE << AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_START_BIT) -+ -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DEFAULT \ -+ (AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_DEFAULT_VALUE << AW87XXX_PID_60_EN_LOOP_GBW_REDUCE_START_BIT) -+ -+/* EN_DEM_POWER bit 3 (OTA 0x6E) */ -+#define AW87XXX_PID_60_EN_DEM_POWER_START_BIT (3) -+#define AW87XXX_PID_60_EN_DEM_POWER_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_DEM_POWER_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_DEM_POWER_BITS_LEN)-1) << AW87XXX_PID_60_EN_DEM_POWER_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_DEM_POWER_DISABLE (0) -+#define AW87XXX_PID_60_EN_DEM_POWER_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_DEM_POWER_DISABLE << AW87XXX_PID_60_EN_DEM_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_EN_DEM_POWER_ENABLE (1) -+#define AW87XXX_PID_60_EN_DEM_POWER_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_DEM_POWER_ENABLE << AW87XXX_PID_60_EN_DEM_POWER_START_BIT) -+ -+#define AW87XXX_PID_60_EN_DEM_POWER_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_DEM_POWER_DEFAULT \ -+ (AW87XXX_PID_60_EN_DEM_POWER_DEFAULT_VALUE << AW87XXX_PID_60_EN_DEM_POWER_START_BIT) -+ -+/* REG_CLK_CP_RIN bit 4 (OTA 0x6E) */ -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_START_BIT (4) -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_CLK_CP_RIN_BITS_LEN)-1) << AW87XXX_PID_60_REG_CLK_CP_RIN_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_200KHZ (0) -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_200KHZ_VALUE \ -+ (AW87XXX_PID_60_REG_CLK_CP_RIN_200KHZ << AW87XXX_PID_60_REG_CLK_CP_RIN_START_BIT) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_400KHZ (1) -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_400KHZ_VALUE \ -+ (AW87XXX_PID_60_REG_CLK_CP_RIN_400KHZ << AW87XXX_PID_60_REG_CLK_CP_RIN_START_BIT) -+ -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_CLK_CP_RIN_DEFAULT \ -+ (AW87XXX_PID_60_REG_CLK_CP_RIN_DEFAULT_VALUE << AW87XXX_PID_60_REG_CLK_CP_RIN_START_BIT) -+ -+/* EN_DEM bit 5 (OTA 0x6E) */ -+#define AW87XXX_PID_60_EN_DEM_START_BIT (5) -+#define AW87XXX_PID_60_EN_DEM_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_DEM_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_DEM_BITS_LEN)-1) << AW87XXX_PID_60_EN_DEM_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_DEM_DISABLE (0) -+#define AW87XXX_PID_60_EN_DEM_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_DEM_DISABLE << AW87XXX_PID_60_EN_DEM_START_BIT) -+ -+#define AW87XXX_PID_60_EN_DEM_ENABLE (1) -+#define AW87XXX_PID_60_EN_DEM_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_DEM_ENABLE << AW87XXX_PID_60_EN_DEM_START_BIT) -+ -+#define AW87XXX_PID_60_EN_DEM_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_DEM_DEFAULT \ -+ (AW87XXX_PID_60_EN_DEM_DEFAULT_VALUE << AW87XXX_PID_60_EN_DEM_START_BIT) -+ -+/* OTA_NG bit 6 (OTA 0x6E) */ -+#define AW87XXX_PID_60_OTA_NG_START_BIT (6) -+#define AW87XXX_PID_60_OTA_NG_BITS_LEN (1) -+#define AW87XXX_PID_60_OTA_NG_MASK \ -+ (~(((1<<AW87XXX_PID_60_OTA_NG_BITS_LEN)-1) << AW87XXX_PID_60_OTA_NG_START_BIT)) -+ -+#define AW87XXX_PID_60_OTA_NG_DISABLE (0) -+#define AW87XXX_PID_60_OTA_NG_DISABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_NG_DISABLE << AW87XXX_PID_60_OTA_NG_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_NG_ENABLE (1) -+#define AW87XXX_PID_60_OTA_NG_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_NG_ENABLE << AW87XXX_PID_60_OTA_NG_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_NG_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_OTA_NG_DEFAULT \ -+ (AW87XXX_PID_60_OTA_NG_DEFAULT_VALUE << AW87XXX_PID_60_OTA_NG_START_BIT) -+ -+/* OTA_CP bit 7 (OTA 0x6E) */ -+#define AW87XXX_PID_60_OTA_CP_START_BIT (7) -+#define AW87XXX_PID_60_OTA_CP_BITS_LEN (1) -+#define AW87XXX_PID_60_OTA_CP_MASK \ -+ (~(((1<<AW87XXX_PID_60_OTA_CP_BITS_LEN)-1) << AW87XXX_PID_60_OTA_CP_START_BIT)) -+ -+#define AW87XXX_PID_60_OTA_CP_DISABLE (0) -+#define AW87XXX_PID_60_OTA_CP_DISABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_CP_DISABLE << AW87XXX_PID_60_OTA_CP_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_CP_ENABLE (1) -+#define AW87XXX_PID_60_OTA_CP_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OTA_CP_ENABLE << AW87XXX_PID_60_OTA_CP_START_BIT) -+ -+#define AW87XXX_PID_60_OTA_CP_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_OTA_CP_DEFAULT \ -+ (AW87XXX_PID_60_OTA_CP_DEFAULT_VALUE << AW87XXX_PID_60_OTA_CP_START_BIT) -+ -+/* default value of OTA (0x6E) */ -+/* #define AW87XXX_PID_60_OTA_DEFAULT (0xC0) */ -+ -+/* RAMPGEN (0x6F) detail */ -+/* RAMP_1SPW_VL bit 7:6 (RAMPGEN 0x6F) */ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT (6) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_BITS_LEN (2) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_MASK \ -+ (~(((1<<AW87XXX_PID_60_RAMP_1SPW_VL_BITS_LEN)-1) << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT)) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P16VDD (0) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P16VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VL_0P16VDD << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P18VDD (1) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P18VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VL_0P18VDD << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P20VDD (2) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P20VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VL_0P20VDD << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P14VDD (3) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_0P14VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VL_0P14VDD << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_RAMP_1SPW_VL_DEFAULT \ -+ (AW87XXX_PID_60_RAMP_1SPW_VL_DEFAULT_VALUE << AW87XXX_PID_60_RAMP_1SPW_VL_START_BIT) -+ -+/* PA_RAMP_AGC1 bit 5:4 (RAMPGEN 0x6F) */ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT (4) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_BITS_LEN (2) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_RAMP_AGC1_BITS_LEN)-1) << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P8VDD (0) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P8VDD_VALUE \ -+ (AW87XXX_PID_60_PA_RAMP_AGC1_0P8VDD << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P825VDD (1) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P825VDD_VALUE \ -+ (AW87XXX_PID_60_PA_RAMP_AGC1_0P825VDD << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P85VDD (2) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P85VDD_VALUE \ -+ (AW87XXX_PID_60_PA_RAMP_AGC1_0P85VDD << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P875VDD (3) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_0P875VDD_VALUE \ -+ (AW87XXX_PID_60_PA_RAMP_AGC1_0P875VDD << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT) -+ -+#define AW87XXX_PID_60_PA_RAMP_AGC1_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PA_RAMP_AGC1_DEFAULT \ -+ (AW87XXX_PID_60_PA_RAMP_AGC1_DEFAULT_VALUE << AW87XXX_PID_60_PA_RAMP_AGC1_START_BIT) -+ -+/* RAMP_1SPW_VC bit 3:2 (RAMPGEN 0x6F) */ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT (2) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_BITS_LEN (2) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_MASK \ -+ (~(((1<<AW87XXX_PID_60_RAMP_1SPW_VC_BITS_LEN)-1) << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT)) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P37VDD (0) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P37VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VC_0P37VDD << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P39VDD (1) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P39VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VC_0P39VDD << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P33VDD (2) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P33VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VC_0P33VDD << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P35VDD (3) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_0P35VDD_VALUE \ -+ (AW87XXX_PID_60_RAMP_1SPW_VC_0P35VDD << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT) -+ -+#define AW87XXX_PID_60_RAMP_1SPW_VC_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_RAMP_1SPW_VC_DEFAULT \ -+ (AW87XXX_PID_60_RAMP_1SPW_VC_DEFAULT_VALUE << AW87XXX_PID_60_RAMP_1SPW_VC_START_BIT) -+ -+/* SS_CONTROL bit 1:0 (RAMPGEN 0x6F) */ -+#define AW87XXX_PID_60_SS_CONTROL_START_BIT (0) -+#define AW87XXX_PID_60_SS_CONTROL_BITS_LEN (2) -+#define AW87XXX_PID_60_SS_CONTROL_MASK \ -+ (~(((1<<AW87XXX_PID_60_SS_CONTROL_BITS_LEN)-1) << AW87XXX_PID_60_SS_CONTROL_START_BIT)) -+ -+#define AW87XXX_PID_60_SS_CONTROL_SS_MODE (0) -+#define AW87XXX_PID_60_SS_CONTROL_SS_MODE_VALUE \ -+ (AW87XXX_PID_60_SS_CONTROL_SS_MODE << AW87XXX_PID_60_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE111 (1) -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE111_VALUE \ -+ (AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE111 << AW87XXX_PID_60_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE000 (2) -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE000_VALUE \ -+ (AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE000 << AW87XXX_PID_60_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE011 (3) -+#define AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE011_VALUE \ -+ (AW87XXX_PID_60_SS_CONTROL_SWBELOW20ABOVE011 << AW87XXX_PID_60_SS_CONTROL_START_BIT) -+ -+#define AW87XXX_PID_60_SS_CONTROL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_SS_CONTROL_DEFAULT \ -+ (AW87XXX_PID_60_SS_CONTROL_DEFAULT_VALUE << AW87XXX_PID_60_SS_CONTROL_START_BIT) -+ -+/* default value of RAMPGEN (0x6F) */ -+/* #define AW87XXX_PID_60_RAMPGEN_DEFAULT (0x0C) */ -+ -+/* CLASSD_SYSCTRL (0x70) detail */ -+/* SEL_VCOM1 bit 0 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_SEL_VCOM1_START_BIT (0) -+#define AW87XXX_PID_60_SEL_VCOM1_BITS_LEN (1) -+#define AW87XXX_PID_60_SEL_VCOM1_MASK \ -+ (~(((1<<AW87XXX_PID_60_SEL_VCOM1_BITS_LEN)-1) << AW87XXX_PID_60_SEL_VCOM1_START_BIT)) -+ -+#define AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V (0) -+#define AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V_VALUE \ -+ (AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V << AW87XXX_PID_60_SEL_VCOM1_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V (1) -+#define AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V_VALUE \ -+ (AW87XXX_PID_60_SEL_VCOM1_VCOM11P4V << AW87XXX_PID_60_SEL_VCOM1_START_BIT) -+*/ -+/* -+Fix me here: -+reg_addr:0x70, reg_name:CLASSD_SYSCTRL, field_name:SEL_VCOM1, content:When ENOTA=0: -+maybe need to fix manually -+*/ -+#define AW87XXX_PID_60_SEL_VCOM1_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_SEL_VCOM1_DEFAULT \ -+ (AW87XXX_PID_60_SEL_VCOM1_DEFAULT_VALUE << AW87XXX_PID_60_SEL_VCOM1_START_BIT) -+ -+/* PA_OPD bit 1 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_PA_OPD_START_BIT (1) -+#define AW87XXX_PID_60_PA_OPD_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_OPD_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OPD_BITS_LEN)-1) << AW87XXX_PID_60_PA_OPD_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OPD_FLOATING (0) -+#define AW87XXX_PID_60_PA_OPD_FLOATING_VALUE \ -+ (AW87XXX_PID_60_PA_OPD_FLOATING << AW87XXX_PID_60_PA_OPD_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OPD_TIED_TO_GND (1) -+#define AW87XXX_PID_60_PA_OPD_TIED_TO_GND_VALUE \ -+ (AW87XXX_PID_60_PA_OPD_TIED_TO_GND << AW87XXX_PID_60_PA_OPD_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OPD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PA_OPD_DEFAULT \ -+ (AW87XXX_PID_60_PA_OPD_DEFAULT_VALUE << AW87XXX_PID_60_PA_OPD_START_BIT) -+ -+/* CLK_OCP_SEL bit 4 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_CLK_OCP_SEL_START_BIT (4) -+#define AW87XXX_PID_60_CLK_OCP_SEL_BITS_LEN (1) -+#define AW87XXX_PID_60_CLK_OCP_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_CLK_OCP_SEL_BITS_LEN)-1) << AW87XXX_PID_60_CLK_OCP_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_CLK_OCP_SEL_160MS (0) -+#define AW87XXX_PID_60_CLK_OCP_SEL_160MS_VALUE \ -+ (AW87XXX_PID_60_CLK_OCP_SEL_160MS << AW87XXX_PID_60_CLK_OCP_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_CLK_OCP_SEL_SHUTDOWN (1) -+#define AW87XXX_PID_60_CLK_OCP_SEL_SHUTDOWN_VALUE \ -+ (AW87XXX_PID_60_CLK_OCP_SEL_SHUTDOWN << AW87XXX_PID_60_CLK_OCP_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_CLK_OCP_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_CLK_OCP_SEL_DEFAULT \ -+ (AW87XXX_PID_60_CLK_OCP_SEL_DEFAULT_VALUE << AW87XXX_PID_60_CLK_OCP_SEL_START_BIT) -+ -+/* PD_OT bit 5 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_PD_OT_START_BIT (5) -+#define AW87XXX_PID_60_PD_OT_BITS_LEN (1) -+#define AW87XXX_PID_60_PD_OT_MASK \ -+ (~(((1<<AW87XXX_PID_60_PD_OT_BITS_LEN)-1) << AW87XXX_PID_60_PD_OT_START_BIT)) -+ -+#define AW87XXX_PID_60_PD_OT_ENABLE (0) -+#define AW87XXX_PID_60_PD_OT_ENABLE_VALUE \ -+ (AW87XXX_PID_60_PD_OT_ENABLE << AW87XXX_PID_60_PD_OT_START_BIT) -+ -+#define AW87XXX_PID_60_PD_OT_SHUTDOWN (1) -+#define AW87XXX_PID_60_PD_OT_SHUTDOWN_VALUE \ -+ (AW87XXX_PID_60_PD_OT_SHUTDOWN << AW87XXX_PID_60_PD_OT_START_BIT) -+ -+#define AW87XXX_PID_60_PD_OT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PD_OT_DEFAULT \ -+ (AW87XXX_PID_60_PD_OT_DEFAULT_VALUE << AW87XXX_PID_60_PD_OT_START_BIT) -+ -+/* PA_FLT_SR bit 6 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_PA_FLT_SR_START_BIT (6) -+#define AW87XXX_PID_60_PA_FLT_SR_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_FLT_SR_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_FLT_SR_BITS_LEN)-1) << AW87XXX_PID_60_PA_FLT_SR_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_FLT_SR_ADD_RC (0) -+#define AW87XXX_PID_60_PA_FLT_SR_ADD_RC_VALUE \ -+ (AW87XXX_PID_60_PA_FLT_SR_ADD_RC << AW87XXX_PID_60_PA_FLT_SR_START_BIT) -+ -+#define AW87XXX_PID_60_PA_FLT_SR_NO_RC (1) -+#define AW87XXX_PID_60_PA_FLT_SR_NO_RC_VALUE \ -+ (AW87XXX_PID_60_PA_FLT_SR_NO_RC << AW87XXX_PID_60_PA_FLT_SR_START_BIT) -+ -+#define AW87XXX_PID_60_PA_FLT_SR_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PA_FLT_SR_DEFAULT \ -+ (AW87XXX_PID_60_PA_FLT_SR_DEFAULT_VALUE << AW87XXX_PID_60_PA_FLT_SR_START_BIT) -+ -+/* PA_PORT bit 3:2 (CLASSD_SYSCTRL 0x70) */ -+#define AW87XXX_PID_60_PA_PORT_START_BIT (2) -+#define AW87XXX_PID_60_PA_PORT_BITS_LEN (2) -+#define AW87XXX_PID_60_PA_PORT_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_PORT_BITS_LEN)-1) << AW87XXX_PID_60_PA_PORT_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_PORT_80MS (0) -+#define AW87XXX_PID_60_PA_PORT_80MS_VALUE \ -+ (AW87XXX_PID_60_PA_PORT_80MS << AW87XXX_PID_60_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_PORT_40MS (1) -+#define AW87XXX_PID_60_PA_PORT_40MS_VALUE \ -+ (AW87XXX_PID_60_PA_PORT_40MS << AW87XXX_PID_60_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_PORT_20MS (2) -+#define AW87XXX_PID_60_PA_PORT_20MS_VALUE \ -+ (AW87XXX_PID_60_PA_PORT_20MS << AW87XXX_PID_60_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_PORT_10MS (3) -+#define AW87XXX_PID_60_PA_PORT_10MS_VALUE \ -+ (AW87XXX_PID_60_PA_PORT_10MS << AW87XXX_PID_60_PA_PORT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_PORT_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PA_PORT_DEFAULT \ -+ (AW87XXX_PID_60_PA_PORT_DEFAULT_VALUE << AW87XXX_PID_60_PA_PORT_START_BIT) -+ -+/* default value of CLASSD_SYSCTRL (0x70) */ -+/* #define AW87XXX_PID_60_CLASSD_SYSCTRL_DEFAULT (0x07) */ -+ -+/* GTDR (0x71) detail */ -+/* REG_DUTY_T bit 0 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_DUTY_T_START_BIT (0) -+#define AW87XXX_PID_60_REG_DUTY_T_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_DUTY_T_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_DUTY_T_BITS_LEN)-1) << AW87XXX_PID_60_REG_DUTY_T_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_DUTY_T_DISABLE (0) -+#define AW87XXX_PID_60_REG_DUTY_T_DISABLE_VALUE \ -+ (AW87XXX_PID_60_REG_DUTY_T_DISABLE << AW87XXX_PID_60_REG_DUTY_T_START_BIT) -+ -+#define AW87XXX_PID_60_REG_DUTY_T_ENALBE (1) -+#define AW87XXX_PID_60_REG_DUTY_T_ENALBE_VALUE \ -+ (AW87XXX_PID_60_REG_DUTY_T_ENALBE << AW87XXX_PID_60_REG_DUTY_T_START_BIT) -+ -+#define AW87XXX_PID_60_REG_DUTY_T_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_REG_DUTY_T_DEFAULT \ -+ (AW87XXX_PID_60_REG_DUTY_T_DEFAULT_VALUE << AW87XXX_PID_60_REG_DUTY_T_START_BIT) -+ -+/* LN_DELAY bit 1 (GTDR 0x71) */ -+#define AW87XXX_PID_60_LN_DELAY_START_BIT (1) -+#define AW87XXX_PID_60_LN_DELAY_BITS_LEN (1) -+#define AW87XXX_PID_60_LN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_LN_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_LN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_LN_DELAY_DISABLE (0) -+#define AW87XXX_PID_60_LN_DELAY_DISABLE_VALUE \ -+ (AW87XXX_PID_60_LN_DELAY_DISABLE << AW87XXX_PID_60_LN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_LN_DELAY_ENABLE (1) -+#define AW87XXX_PID_60_LN_DELAY_ENABLE_VALUE \ -+ (AW87XXX_PID_60_LN_DELAY_ENABLE << AW87XXX_PID_60_LN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_LN_DELAY_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_LN_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_LN_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_LN_DELAY_START_BIT) -+ -+/* HN_DELAY bit 2 (GTDR 0x71) */ -+#define AW87XXX_PID_60_HN_DELAY_START_BIT (2) -+#define AW87XXX_PID_60_HN_DELAY_BITS_LEN (1) -+#define AW87XXX_PID_60_HN_DELAY_MASK \ -+ (~(((1<<AW87XXX_PID_60_HN_DELAY_BITS_LEN)-1) << AW87XXX_PID_60_HN_DELAY_START_BIT)) -+ -+#define AW87XXX_PID_60_HN_DELAY_DISABLE (0) -+#define AW87XXX_PID_60_HN_DELAY_DISABLE_VALUE \ -+ (AW87XXX_PID_60_HN_DELAY_DISABLE << AW87XXX_PID_60_HN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_HN_DELAY_ENABLE (1) -+#define AW87XXX_PID_60_HN_DELAY_ENABLE_VALUE \ -+ (AW87XXX_PID_60_HN_DELAY_ENABLE << AW87XXX_PID_60_HN_DELAY_START_BIT) -+ -+#define AW87XXX_PID_60_HN_DELAY_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_HN_DELAY_DEFAULT \ -+ (AW87XXX_PID_60_HN_DELAY_DEFAULT_VALUE << AW87XXX_PID_60_HN_DELAY_START_BIT) -+ -+/* REG_T_EDGE bit 3 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_T_EDGE_START_BIT (3) -+#define AW87XXX_PID_60_REG_T_EDGE_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_T_EDGE_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_T_EDGE_BITS_LEN)-1) << AW87XXX_PID_60_REG_T_EDGE_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_T_EDGE_5NS (0) -+#define AW87XXX_PID_60_REG_T_EDGE_5NS_VALUE \ -+ (AW87XXX_PID_60_REG_T_EDGE_5NS << AW87XXX_PID_60_REG_T_EDGE_START_BIT) -+ -+#define AW87XXX_PID_60_REG_T_EDGE_15NS (1) -+#define AW87XXX_PID_60_REG_T_EDGE_15NS_VALUE \ -+ (AW87XXX_PID_60_REG_T_EDGE_15NS << AW87XXX_PID_60_REG_T_EDGE_START_BIT) -+ -+#define AW87XXX_PID_60_REG_T_EDGE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_T_EDGE_DEFAULT \ -+ (AW87XXX_PID_60_REG_T_EDGE_DEFAULT_VALUE << AW87XXX_PID_60_REG_T_EDGE_START_BIT) -+ -+/* REG_L_PULL bit 4 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_L_PULL_START_BIT (4) -+#define AW87XXX_PID_60_REG_L_PULL_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_L_PULL_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_L_PULL_BITS_LEN)-1) << AW87XXX_PID_60_REG_L_PULL_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_L_PULL_7NS (0) -+#define AW87XXX_PID_60_REG_L_PULL_7NS_VALUE \ -+ (AW87XXX_PID_60_REG_L_PULL_7NS << AW87XXX_PID_60_REG_L_PULL_START_BIT) -+ -+#define AW87XXX_PID_60_REG_L_PULL_14NS (1) -+#define AW87XXX_PID_60_REG_L_PULL_14NS_VALUE \ -+ (AW87XXX_PID_60_REG_L_PULL_14NS << AW87XXX_PID_60_REG_L_PULL_START_BIT) -+ -+#define AW87XXX_PID_60_REG_L_PULL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_L_PULL_DEFAULT \ -+ (AW87XXX_PID_60_REG_L_PULL_DEFAULT_VALUE << AW87XXX_PID_60_REG_L_PULL_START_BIT) -+ -+/* REG_L_PUD bit 5 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_L_PUD_START_BIT (5) -+#define AW87XXX_PID_60_REG_L_PUD_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_L_PUD_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_L_PUD_BITS_LEN)-1) << AW87XXX_PID_60_REG_L_PUD_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_L_PUD_0NS (0) -+#define AW87XXX_PID_60_REG_L_PUD_0NS_VALUE \ -+ (AW87XXX_PID_60_REG_L_PUD_0NS << AW87XXX_PID_60_REG_L_PUD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_L_PUD_3NS (1) -+#define AW87XXX_PID_60_REG_L_PUD_3NS_VALUE \ -+ (AW87XXX_PID_60_REG_L_PUD_3NS << AW87XXX_PID_60_REG_L_PUD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_L_PUD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_REG_L_PUD_DEFAULT \ -+ (AW87XXX_PID_60_REG_L_PUD_DEFAULT_VALUE << AW87XXX_PID_60_REG_L_PUD_START_BIT) -+ -+/* REG_HNG_PULL bit 6 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_HNG_PULL_START_BIT (6) -+#define AW87XXX_PID_60_REG_HNG_PULL_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_HNG_PULL_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_HNG_PULL_BITS_LEN)-1) << AW87XXX_PID_60_REG_HNG_PULL_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_HNG_PULL_DISABLE (0) -+#define AW87XXX_PID_60_REG_HNG_PULL_DISABLE_VALUE \ -+ (AW87XXX_PID_60_REG_HNG_PULL_DISABLE << AW87XXX_PID_60_REG_HNG_PULL_START_BIT) -+ -+#define AW87XXX_PID_60_REG_HNG_PULL_ENABLE (1) -+#define AW87XXX_PID_60_REG_HNG_PULL_ENABLE_VALUE \ -+ (AW87XXX_PID_60_REG_HNG_PULL_ENABLE << AW87XXX_PID_60_REG_HNG_PULL_START_BIT) -+ -+#define AW87XXX_PID_60_REG_HNG_PULL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_HNG_PULL_DEFAULT \ -+ (AW87XXX_PID_60_REG_HNG_PULL_DEFAULT_VALUE << AW87XXX_PID_60_REG_HNG_PULL_START_BIT) -+ -+/* REG_DUTY_VTH bit 7 (GTDR 0x71) */ -+#define AW87XXX_PID_60_REG_DUTY_VTH_START_BIT (7) -+#define AW87XXX_PID_60_REG_DUTY_VTH_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_DUTY_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_DUTY_VTH_BITS_LEN)-1) << AW87XXX_PID_60_REG_DUTY_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_DUTY_VTH_POVTH0 (0) -+#define AW87XXX_PID_60_REG_DUTY_VTH_POVTH0_VALUE \ -+ (AW87XXX_PID_60_REG_DUTY_VTH_POVTH0 << AW87XXX_PID_60_REG_DUTY_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_REG_DUTY_VTH_POVTH4 (1) -+#define AW87XXX_PID_60_REG_DUTY_VTH_POVTH4_VALUE \ -+ (AW87XXX_PID_60_REG_DUTY_VTH_POVTH4 << AW87XXX_PID_60_REG_DUTY_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_REG_DUTY_VTH_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_REG_DUTY_VTH_DEFAULT \ -+ (AW87XXX_PID_60_REG_DUTY_VTH_DEFAULT_VALUE << AW87XXX_PID_60_REG_DUTY_VTH_START_BIT) -+ -+/* default value of GTDR (0x71) */ -+/* #define AW87XXX_PID_60_GTDR_DEFAULT (0x27) */ -+ -+/* OC (0x72) detail */ -+/* REG_SHORT_GUARD bit 7 (OC 0x72) */ -+#define AW87XXX_PID_60_REG_SHORT_GUARD_START_BIT (7) -+#define AW87XXX_PID_60_REG_SHORT_GUARD_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_SHORT_GUARD_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_SHORT_GUARD_BITS_LEN)-1) << AW87XXX_PID_60_REG_SHORT_GUARD_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_SHORT_GUARD_DISABLE (0) -+#define AW87XXX_PID_60_REG_SHORT_GUARD_DISABLE_VALUE \ -+ (AW87XXX_PID_60_REG_SHORT_GUARD_DISABLE << AW87XXX_PID_60_REG_SHORT_GUARD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_SHORT_GUARD_ENALBE (1) -+#define AW87XXX_PID_60_REG_SHORT_GUARD_ENALBE_VALUE \ -+ (AW87XXX_PID_60_REG_SHORT_GUARD_ENALBE << AW87XXX_PID_60_REG_SHORT_GUARD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_SHORT_GUARD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_REG_SHORT_GUARD_DEFAULT \ -+ (AW87XXX_PID_60_REG_SHORT_GUARD_DEFAULT_VALUE << AW87XXX_PID_60_REG_SHORT_GUARD_START_BIT) -+ -+/* PA_GTDR_DDT bit 6:5 (OC 0x72) */ -+#define AW87XXX_PID_60_PA_GTDR_DDT_START_BIT (5) -+#define AW87XXX_PID_60_PA_GTDR_DDT_BITS_LEN (2) -+#define AW87XXX_PID_60_PA_GTDR_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_GTDR_DDT_BITS_LEN)-1) << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_GTDR_DDT_12NS (0) -+#define AW87XXX_PID_60_PA_GTDR_DDT_12NS_VALUE \ -+ (AW87XXX_PID_60_PA_GTDR_DDT_12NS << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GTDR_DDT_13NS (1) -+#define AW87XXX_PID_60_PA_GTDR_DDT_13NS_VALUE \ -+ (AW87XXX_PID_60_PA_GTDR_DDT_13NS << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GTDR_DDT_14NS (2) -+#define AW87XXX_PID_60_PA_GTDR_DDT_14NS_VALUE \ -+ (AW87XXX_PID_60_PA_GTDR_DDT_14NS << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GTDR_DDT_15NS (3) -+#define AW87XXX_PID_60_PA_GTDR_DDT_15NS_VALUE \ -+ (AW87XXX_PID_60_PA_GTDR_DDT_15NS << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_GTDR_DDT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PA_GTDR_DDT_DEFAULT \ -+ (AW87XXX_PID_60_PA_GTDR_DDT_DEFAULT_VALUE << AW87XXX_PID_60_PA_GTDR_DDT_START_BIT) -+ -+/* PA_OC_ITH bit 4:2 (OC 0x72) */ -+#define AW87XXX_PID_60_PA_OC_ITH_START_BIT (2) -+#define AW87XXX_PID_60_PA_OC_ITH_BITS_LEN (3) -+#define AW87XXX_PID_60_PA_OC_ITH_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OC_ITH_BITS_LEN)-1) << AW87XXX_PID_60_PA_OC_ITH_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_3P4A (0) -+#define AW87XXX_PID_60_PA_OC_ITH_3P4A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_3P4A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_3P8A (1) -+#define AW87XXX_PID_60_PA_OC_ITH_3P8A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_3P8A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_4P2A (2) -+#define AW87XXX_PID_60_PA_OC_ITH_4P2A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_4P2A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_4P6A (3) -+#define AW87XXX_PID_60_PA_OC_ITH_4P6A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_4P6A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_5P0A (4) -+#define AW87XXX_PID_60_PA_OC_ITH_5P0A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_5P0A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_5P4A (5) -+#define AW87XXX_PID_60_PA_OC_ITH_5P4A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_5P4A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_5P7A (6) -+#define AW87XXX_PID_60_PA_OC_ITH_5P7A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_5P7A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_6P0A (7) -+#define AW87XXX_PID_60_PA_OC_ITH_6P0A_VALUE \ -+ (AW87XXX_PID_60_PA_OC_ITH_6P0A << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_ITH_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_PA_OC_ITH_DEFAULT \ -+ (AW87XXX_PID_60_PA_OC_ITH_DEFAULT_VALUE << AW87XXX_PID_60_PA_OC_ITH_START_BIT) -+ -+/* PA_OC_DT bit 1:0 (OC 0x72) */ -+#define AW87XXX_PID_60_PA_OC_DT_START_BIT (0) -+#define AW87XXX_PID_60_PA_OC_DT_BITS_LEN (2) -+#define AW87XXX_PID_60_PA_OC_DT_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OC_DT_BITS_LEN)-1) << AW87XXX_PID_60_PA_OC_DT_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OC_DT_20NS (0) -+#define AW87XXX_PID_60_PA_OC_DT_20NS_VALUE \ -+ (AW87XXX_PID_60_PA_OC_DT_20NS << AW87XXX_PID_60_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_DT_40NS (1) -+#define AW87XXX_PID_60_PA_OC_DT_40NS_VALUE \ -+ (AW87XXX_PID_60_PA_OC_DT_40NS << AW87XXX_PID_60_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_DT_60NS (2) -+#define AW87XXX_PID_60_PA_OC_DT_60NS_VALUE \ -+ (AW87XXX_PID_60_PA_OC_DT_60NS << AW87XXX_PID_60_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_DT_80NS (3) -+#define AW87XXX_PID_60_PA_OC_DT_80NS_VALUE \ -+ (AW87XXX_PID_60_PA_OC_DT_80NS << AW87XXX_PID_60_PA_OC_DT_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OC_DT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PA_OC_DT_DEFAULT \ -+ (AW87XXX_PID_60_PA_OC_DT_DEFAULT_VALUE << AW87XXX_PID_60_PA_OC_DT_START_BIT) -+ -+/* default value of OC (0x72) */ -+/* #define AW87XXX_PID_60_OC_DEFAULT (0x8C) */ -+ -+/* AGC_CON (0x73) detail */ -+/* PA_OCSWD bit 6 (AGC_CON 0x73) */ -+#define AW87XXX_PID_60_PA_OCSWD_START_BIT (6) -+#define AW87XXX_PID_60_PA_OCSWD_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_OCSWD_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_OCSWD_BITS_LEN)-1) << AW87XXX_PID_60_PA_OCSWD_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_OCSWD_FAST (0) -+#define AW87XXX_PID_60_PA_OCSWD_FAST_VALUE \ -+ (AW87XXX_PID_60_PA_OCSWD_FAST << AW87XXX_PID_60_PA_OCSWD_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OCSWD_SLOW (1) -+#define AW87XXX_PID_60_PA_OCSWD_SLOW_VALUE \ -+ (AW87XXX_PID_60_PA_OCSWD_SLOW << AW87XXX_PID_60_PA_OCSWD_START_BIT) -+ -+#define AW87XXX_PID_60_PA_OCSWD_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PA_OCSWD_DEFAULT \ -+ (AW87XXX_PID_60_PA_OCSWD_DEFAULT_VALUE << AW87XXX_PID_60_PA_OCSWD_START_BIT) -+ -+/* PD_CROSSZERO bit 5:4 (AGC_CON 0x73) */ -+#define AW87XXX_PID_60_PD_CROSSZERO_START_BIT (4) -+#define AW87XXX_PID_60_PD_CROSSZERO_BITS_LEN (2) -+#define AW87XXX_PID_60_PD_CROSSZERO_MASK \ -+ (~(((1<<AW87XXX_PID_60_PD_CROSSZERO_BITS_LEN)-1) << AW87XXX_PID_60_PD_CROSSZERO_START_BIT)) -+ -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC2_3_CROSSZERO (0) -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC2_3_CROSSZERO_VALUE \ -+ (AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC2_3_CROSSZERO << AW87XXX_PID_60_PD_CROSSZERO_START_BIT) -+ -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO (1) -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO_VALUE \ -+ (AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO << AW87XXX_PID_60_PD_CROSSZERO_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO (2) -+#define AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO_VALUE \ -+ (AW87XXX_PID_60_PD_CROSSZERO_ENABLE_AGC1_WHEN_PVDD_IS_RISINGAGC23_CROSSZERO << AW87XXX_PID_60_PD_CROSSZERO_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_PD_CROSSZERO_AGC123_CROSSZERO (3) -+#define AW87XXX_PID_60_PD_CROSSZERO_AGC123_CROSSZERO_VALUE \ -+ (AW87XXX_PID_60_PD_CROSSZERO_AGC123_CROSSZERO << AW87XXX_PID_60_PD_CROSSZERO_START_BIT) -+/* -+Fix me here: -+reg_addr:0x73, reg_name:AGC_CON, field_name:PD_CROSSZERO, content:AGC cross_zero adaptively When EN_AGC1_ADP=1 -+maybe need to fix manually -+*/ -+#define AW87XXX_PID_60_PD_CROSSZERO_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PD_CROSSZERO_DEFAULT \ -+ (AW87XXX_PID_60_PD_CROSSZERO_DEFAULT_VALUE << AW87XXX_PID_60_PD_CROSSZERO_START_BIT) -+ -+/* AGC1_VTH_SEL bit 3:2 (AGC_CON 0x73) */ -+#define AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT (2) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_BITS_LEN (2) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC1_VTH_SEL_BITS_LEN)-1) << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC1_VTH_SEL_RAMPGEN (0) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_RAMPGEN_VALUE \ -+ (AW87XXX_PID_60_AGC1_VTH_SEL_RAMPGEN << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_VTH_SEL_THGEN (1) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_THGEN_VALUE \ -+ (AW87XXX_PID_60_AGC1_VTH_SEL_THGEN << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN (2) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN_VALUE \ -+ (AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN (3) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN_VALUE \ -+ (AW87XXX_PID_60_AGC1_VTH_SEL_BOTH_MIN << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_AGC1_VTH_SEL_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_AGC1_VTH_SEL_DEFAULT \ -+ (AW87XXX_PID_60_AGC1_VTH_SEL_DEFAULT_VALUE << AW87XXX_PID_60_AGC1_VTH_SEL_START_BIT) -+ -+/* AGC2_FIRST_ATT_TIME bit 1:0 (AGC_CON 0x73) */ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT (0) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_BITS_LEN (2) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_MASK \ -+ (~(((1<<AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT)) -+ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P08MS (0) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P08MS_VALUE \ -+ (AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P08MS << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P32MS (1) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P32MS_VALUE \ -+ (AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_0P32MS << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_1P28MS (2) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_1P28MS_VALUE \ -+ (AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_1P28MS << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_5P12MS (3) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_5P12MS_VALUE \ -+ (AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_5P12MS << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_DEFAULT \ -+ (AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_DEFAULT_VALUE << AW87XXX_PID_60_AGC2_FIRST_ATT_TIME_START_BIT) -+ -+/* default value of AGC_CON (0x73) */ -+/* #define AW87XXX_PID_60_AGC_CON_DEFAULT (0x48) */ -+ -+/* NG (0x74) detail */ -+/* NG_MODE bit 2 (NG 0x74) */ -+#define AW87XXX_PID_60_NG_MODE_START_BIT (2) -+#define AW87XXX_PID_60_NG_MODE_BITS_LEN (1) -+#define AW87XXX_PID_60_NG_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_MODE_BITS_LEN)-1) << AW87XXX_PID_60_NG_MODE_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_MODE_MODE1 (0) -+#define AW87XXX_PID_60_NG_MODE_MODE1_VALUE \ -+ (AW87XXX_PID_60_NG_MODE_MODE1 << AW87XXX_PID_60_NG_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_NG_MODE_MODE2 (1) -+#define AW87XXX_PID_60_NG_MODE_MODE2_VALUE \ -+ (AW87XXX_PID_60_NG_MODE_MODE2 << AW87XXX_PID_60_NG_MODE_START_BIT) -+ -+#define AW87XXX_PID_60_NG_MODE_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_NG_MODE_DEFAULT \ -+ (AW87XXX_PID_60_NG_MODE_DEFAULT_VALUE << AW87XXX_PID_60_NG_MODE_START_BIT) -+ -+/* EN_NG bit 3 (NG 0x74) */ -+#define AW87XXX_PID_60_EN_NG_START_BIT (3) -+#define AW87XXX_PID_60_EN_NG_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_NG_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_NG_BITS_LEN)-1) << AW87XXX_PID_60_EN_NG_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_NG_DISABLE (0) -+#define AW87XXX_PID_60_EN_NG_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_NG_DISABLE << AW87XXX_PID_60_EN_NG_START_BIT) -+ -+#define AW87XXX_PID_60_EN_NG_ENABLE (1) -+#define AW87XXX_PID_60_EN_NG_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_NG_ENABLE << AW87XXX_PID_60_EN_NG_START_BIT) -+ -+#define AW87XXX_PID_60_EN_NG_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_NG_DEFAULT \ -+ (AW87XXX_PID_60_EN_NG_DEFAULT_VALUE << AW87XXX_PID_60_EN_NG_START_BIT) -+ -+/* EN_AGC1_ADP bit 7 (NG 0x74) */ -+#define AW87XXX_PID_60_EN_AGC1_ADP_START_BIT (7) -+#define AW87XXX_PID_60_EN_AGC1_ADP_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_AGC1_ADP_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_AGC1_ADP_BITS_LEN)-1) << AW87XXX_PID_60_EN_AGC1_ADP_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE (0) -+#define AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE_VALUE \ -+ (AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_AS_BEFORE << AW87XXX_PID_60_EN_AGC1_ADP_START_BIT) -+ -+#define AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY (1) -+#define AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY_VALUE \ -+ (AW87XXX_PID_60_EN_AGC1_ADP_AGC_CROSSZERO_ADAPTIVELY << AW87XXX_PID_60_EN_AGC1_ADP_START_BIT) -+ -+#define AW87XXX_PID_60_EN_AGC1_ADP_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_AGC1_ADP_DEFAULT \ -+ (AW87XXX_PID_60_EN_AGC1_ADP_DEFAULT_VALUE << AW87XXX_PID_60_EN_AGC1_ADP_START_BIT) -+ -+/* PAVG_ADJ bit 6:4 (NG 0x74) */ -+#define AW87XXX_PID_60_PAVG_ADJ_START_BIT (4) -+#define AW87XXX_PID_60_PAVG_ADJ_BITS_LEN (3) -+#define AW87XXX_PID_60_PAVG_ADJ_MASK \ -+ (~(((1<<AW87XXX_PID_60_PAVG_ADJ_BITS_LEN)-1) << AW87XXX_PID_60_PAVG_ADJ_START_BIT)) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_0P94 (0) -+#define AW87XXX_PID_60_PAVG_ADJ_0P94_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_0P94 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_0P97 (1) -+#define AW87XXX_PID_60_PAVG_ADJ_0P97_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_0P97 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_1P0 (2) -+#define AW87XXX_PID_60_PAVG_ADJ_1P0_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_1P0 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_1P03 (3) -+#define AW87XXX_PID_60_PAVG_ADJ_1P03_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_1P03 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_1P06 (4) -+#define AW87XXX_PID_60_PAVG_ADJ_1P06_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_1P06 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_1P09 (5) -+#define AW87XXX_PID_60_PAVG_ADJ_1P09_VALUE \ -+ (AW87XXX_PID_60_PAVG_ADJ_1P09 << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+#define AW87XXX_PID_60_PAVG_ADJ_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_PAVG_ADJ_DEFAULT \ -+ (AW87XXX_PID_60_PAVG_ADJ_DEFAULT_VALUE << AW87XXX_PID_60_PAVG_ADJ_START_BIT) -+ -+/* NG_GAIN bit 1:0 (NG 0x74) */ -+#define AW87XXX_PID_60_NG_GAIN_START_BIT (0) -+#define AW87XXX_PID_60_NG_GAIN_BITS_LEN (2) -+#define AW87XXX_PID_60_NG_GAIN_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_GAIN_BITS_LEN)-1) << AW87XXX_PID_60_NG_GAIN_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_GAIN_MINUS6DB (0) -+#define AW87XXX_PID_60_NG_GAIN_MINUS6DB_VALUE \ -+ (AW87XXX_PID_60_NG_GAIN_MINUS6DB << AW87XXX_PID_60_NG_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_NG_GAIN_MINUS7P5DB (1) -+#define AW87XXX_PID_60_NG_GAIN_MINUS7P5DB_VALUE \ -+ (AW87XXX_PID_60_NG_GAIN_MINUS7P5DB << AW87XXX_PID_60_NG_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_NG_GAIN_MINUS9DB (2) -+#define AW87XXX_PID_60_NG_GAIN_MINUS9DB_VALUE \ -+ (AW87XXX_PID_60_NG_GAIN_MINUS9DB << AW87XXX_PID_60_NG_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_NG_GAIN_MINUS12DB (3) -+#define AW87XXX_PID_60_NG_GAIN_MINUS12DB_VALUE \ -+ (AW87XXX_PID_60_NG_GAIN_MINUS12DB << AW87XXX_PID_60_NG_GAIN_START_BIT) -+ -+#define AW87XXX_PID_60_NG_GAIN_DEFAULT_VALUE (0x3) -+#define AW87XXX_PID_60_NG_GAIN_DEFAULT \ -+ (AW87XXX_PID_60_NG_GAIN_DEFAULT_VALUE << AW87XXX_PID_60_NG_GAIN_START_BIT) -+ -+/* default value of NG (0x74) */ -+/* #define AW87XXX_PID_60_NG_DEFAULT (0x27) */ -+ -+/* NG2 (0x75) detail */ -+/* NG_CLK0_SEL bit 0 (NG2 0x75) */ -+#define AW87XXX_PID_60_NG_CLK0_SEL_START_BIT (0) -+#define AW87XXX_PID_60_NG_CLK0_SEL_BITS_LEN (1) -+#define AW87XXX_PID_60_NG_CLK0_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_CLK0_SEL_BITS_LEN)-1) << AW87XXX_PID_60_NG_CLK0_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_CLK0_SEL_5US (0) -+#define AW87XXX_PID_60_NG_CLK0_SEL_5US_VALUE \ -+ (AW87XXX_PID_60_NG_CLK0_SEL_5US << AW87XXX_PID_60_NG_CLK0_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_NG_CLK0_SEL_10US (1) -+#define AW87XXX_PID_60_NG_CLK0_SEL_10US_VALUE \ -+ (AW87XXX_PID_60_NG_CLK0_SEL_10US << AW87XXX_PID_60_NG_CLK0_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_NG_CLK0_SEL_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_NG_CLK0_SEL_DEFAULT \ -+ (AW87XXX_PID_60_NG_CLK0_SEL_DEFAULT_VALUE << AW87XXX_PID_60_NG_CLK0_SEL_START_BIT) -+ -+/* NG_DEGLITCH_CTRL bit 7 (NG2 0x75) */ -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_START_BIT (7) -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_BITS_LEN (1) -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_DEGLITCH_CTRL_BITS_LEN)-1) << AW87XXX_PID_60_NG_DEGLITCH_CTRL_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_8P6N (0) -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_8P6N_VALUE \ -+ (AW87XXX_PID_60_NG_DEGLITCH_CTRL_8P6N << AW87XXX_PID_60_NG_DEGLITCH_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_14P2N (1) -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_14P2N_VALUE \ -+ (AW87XXX_PID_60_NG_DEGLITCH_CTRL_14P2N << AW87XXX_PID_60_NG_DEGLITCH_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_NG_DEGLITCH_CTRL_DEFAULT \ -+ (AW87XXX_PID_60_NG_DEGLITCH_CTRL_DEFAULT_VALUE << AW87XXX_PID_60_NG_DEGLITCH_CTRL_START_BIT) -+ -+/* NGVTH bit 6:4 (NG2 0x75) */ -+#define AW87XXX_PID_60_NGVTH_START_BIT (4) -+#define AW87XXX_PID_60_NGVTH_BITS_LEN (3) -+#define AW87XXX_PID_60_NGVTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_NGVTH_BITS_LEN)-1) << AW87XXX_PID_60_NGVTH_START_BIT)) -+ -+#define AW87XXX_PID_60_NGVTH_5MV (0) -+#define AW87XXX_PID_60_NGVTH_5MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_5MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_8MV (1) -+#define AW87XXX_PID_60_NGVTH_8MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_8MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_10MV (2) -+#define AW87XXX_PID_60_NGVTH_10MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_10MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_12MV (3) -+#define AW87XXX_PID_60_NGVTH_12MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_12MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_14MV (4) -+#define AW87XXX_PID_60_NGVTH_14MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_14MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_16MV (5) -+#define AW87XXX_PID_60_NGVTH_16MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_16MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+/* -+#define AW87XXX_PID_60_NGVTH_16MV (6) -+#define AW87XXX_PID_60_NGVTH_16MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_16MV << AW87XXX_PID_60_NGVTH_START_BIT) -+*/ -+ -+#define AW87XXX_PID_60_NGVTH_25MV (7) -+#define AW87XXX_PID_60_NGVTH_25MV_VALUE \ -+ (AW87XXX_PID_60_NGVTH_25MV << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+#define AW87XXX_PID_60_NGVTH_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_NGVTH_DEFAULT \ -+ (AW87XXX_PID_60_NGVTH_DEFAULT_VALUE << AW87XXX_PID_60_NGVTH_START_BIT) -+ -+/* NG_ACK bit 3:1 (NG2 0x75) */ -+#define AW87XXX_PID_60_NG_ACK_START_BIT (1) -+#define AW87XXX_PID_60_NG_ACK_BITS_LEN (3) -+#define AW87XXX_PID_60_NG_ACK_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_ACK_BITS_LEN)-1) << AW87XXX_PID_60_NG_ACK_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_ACK_10MS (0) -+#define AW87XXX_PID_60_NG_ACK_10MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_10MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_20MS (1) -+#define AW87XXX_PID_60_NG_ACK_20MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_20MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_40MS (2) -+#define AW87XXX_PID_60_NG_ACK_40MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_40MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_80MS (3) -+#define AW87XXX_PID_60_NG_ACK_80MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_80MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_160MS (4) -+#define AW87XXX_PID_60_NG_ACK_160MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_160MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_320MS (5) -+#define AW87XXX_PID_60_NG_ACK_320MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_320MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_640MS (6) -+#define AW87XXX_PID_60_NG_ACK_640MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_640MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_1280MS (7) -+#define AW87XXX_PID_60_NG_ACK_1280MS_VALUE \ -+ (AW87XXX_PID_60_NG_ACK_1280MS << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_ACK_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_60_NG_ACK_DEFAULT \ -+ (AW87XXX_PID_60_NG_ACK_DEFAULT_VALUE << AW87XXX_PID_60_NG_ACK_START_BIT) -+ -+/* default value of NG2 (0x75) */ -+/* #define AW87XXX_PID_60_NG2_DEFAULT (0xA9) */ -+ -+/* NG3 (0x76) detail */ -+/* NG_RCK bit 7:5 (NG3 0x76) */ -+#define AW87XXX_PID_60_NG_RCK_START_BIT (5) -+#define AW87XXX_PID_60_NG_RCK_BITS_LEN (3) -+#define AW87XXX_PID_60_NG_RCK_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_RCK_BITS_LEN)-1) << AW87XXX_PID_60_NG_RCK_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_RCK_90US (0) -+#define AW87XXX_PID_60_NG_RCK_90US_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_90US << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_180US (1) -+#define AW87XXX_PID_60_NG_RCK_180US_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_180US << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_360US (2) -+#define AW87XXX_PID_60_NG_RCK_360US_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_360US << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_720US (3) -+#define AW87XXX_PID_60_NG_RCK_720US_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_720US << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_1P44M (4) -+#define AW87XXX_PID_60_NG_RCK_1P44M_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_1P44M << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_2P88MS (5) -+#define AW87XXX_PID_60_NG_RCK_2P88MS_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_2P88MS << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_5P76MS (6) -+#define AW87XXX_PID_60_NG_RCK_5P76MS_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_5P76MS << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_11P52MS (7) -+#define AW87XXX_PID_60_NG_RCK_11P52MS_VALUE \ -+ (AW87XXX_PID_60_NG_RCK_11P52MS << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_RCK_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_60_NG_RCK_DEFAULT \ -+ (AW87XXX_PID_60_NG_RCK_DEFAULT_VALUE << AW87XXX_PID_60_NG_RCK_START_BIT) -+ -+/* NG_WCK bit 4:2 (NG3 0x76) */ -+#define AW87XXX_PID_60_NG_WCK_START_BIT (2) -+#define AW87XXX_PID_60_NG_WCK_BITS_LEN (3) -+#define AW87XXX_PID_60_NG_WCK_MASK \ -+ (~(((1<<AW87XXX_PID_60_NG_WCK_BITS_LEN)-1) << AW87XXX_PID_60_NG_WCK_START_BIT)) -+ -+#define AW87XXX_PID_60_NG_WCK_20MS (0) -+#define AW87XXX_PID_60_NG_WCK_20MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_20MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_40MS (1) -+#define AW87XXX_PID_60_NG_WCK_40MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_40MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_80MS (2) -+#define AW87XXX_PID_60_NG_WCK_80MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_80MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_160MS (3) -+#define AW87XXX_PID_60_NG_WCK_160MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_160MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_320MS (4) -+#define AW87XXX_PID_60_NG_WCK_320MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_320MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_640MS (5) -+#define AW87XXX_PID_60_NG_WCK_640MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_640MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_1280MS (6) -+#define AW87XXX_PID_60_NG_WCK_1280MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_1280MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_2556MS (7) -+#define AW87XXX_PID_60_NG_WCK_2556MS_VALUE \ -+ (AW87XXX_PID_60_NG_WCK_2556MS << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+#define AW87XXX_PID_60_NG_WCK_DEFAULT_VALUE (0x4) -+#define AW87XXX_PID_60_NG_WCK_DEFAULT \ -+ (AW87XXX_PID_60_NG_WCK_DEFAULT_VALUE << AW87XXX_PID_60_NG_WCK_START_BIT) -+ -+/* CP_VOS bit 1:0 (NG3 0x76) */ -+#define AW87XXX_PID_60_CP_VOS_START_BIT (0) -+#define AW87XXX_PID_60_CP_VOS_BITS_LEN (2) -+#define AW87XXX_PID_60_CP_VOS_MASK \ -+ (~(((1<<AW87XXX_PID_60_CP_VOS_BITS_LEN)-1) << AW87XXX_PID_60_CP_VOS_START_BIT)) -+ -+#define AW87XXX_PID_60_CP_VOS_0MV (0) -+#define AW87XXX_PID_60_CP_VOS_0MV_VALUE \ -+ (AW87XXX_PID_60_CP_VOS_0MV << AW87XXX_PID_60_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_60_CP_VOS_50MV (1) -+#define AW87XXX_PID_60_CP_VOS_50MV_VALUE \ -+ (AW87XXX_PID_60_CP_VOS_50MV << AW87XXX_PID_60_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_60_CP_VOS_100MV (2) -+#define AW87XXX_PID_60_CP_VOS_100MV_VALUE \ -+ (AW87XXX_PID_60_CP_VOS_100MV << AW87XXX_PID_60_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_60_CP_VOS_150MV (3) -+#define AW87XXX_PID_60_CP_VOS_150MV_VALUE \ -+ (AW87XXX_PID_60_CP_VOS_150MV << AW87XXX_PID_60_CP_VOS_START_BIT) -+ -+#define AW87XXX_PID_60_CP_VOS_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_CP_VOS_DEFAULT \ -+ (AW87XXX_PID_60_CP_VOS_DEFAULT_VALUE << AW87XXX_PID_60_CP_VOS_START_BIT) -+ -+/* default value of NG3 (0x76) */ -+/* #define AW87XXX_PID_60_NG3_DEFAULT (0x91) */ -+ -+/* CP (0x77) detail */ -+/* CP_DDT bit 0 (CP 0x77) */ -+#define AW87XXX_PID_60_CP_DDT_START_BIT (0) -+#define AW87XXX_PID_60_CP_DDT_BITS_LEN (1) -+#define AW87XXX_PID_60_CP_DDT_MASK \ -+ (~(((1<<AW87XXX_PID_60_CP_DDT_BITS_LEN)-1) << AW87XXX_PID_60_CP_DDT_START_BIT)) -+ -+#define AW87XXX_PID_60_CP_DDT_0NS (0) -+#define AW87XXX_PID_60_CP_DDT_0NS_VALUE \ -+ (AW87XXX_PID_60_CP_DDT_0NS << AW87XXX_PID_60_CP_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_CP_DDT_10NS (1) -+#define AW87XXX_PID_60_CP_DDT_10NS_VALUE \ -+ (AW87XXX_PID_60_CP_DDT_10NS << AW87XXX_PID_60_CP_DDT_START_BIT) -+ -+#define AW87XXX_PID_60_CP_DDT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_CP_DDT_DEFAULT \ -+ (AW87XXX_PID_60_CP_DDT_DEFAULT_VALUE << AW87XXX_PID_60_CP_DDT_START_BIT) -+ -+/* CPOK_TM bit 1 (CP 0x77) */ -+#define AW87XXX_PID_60_CPOK_TM_START_BIT (1) -+#define AW87XXX_PID_60_CPOK_TM_BITS_LEN (1) -+#define AW87XXX_PID_60_CPOK_TM_MASK \ -+ (~(((1<<AW87XXX_PID_60_CPOK_TM_BITS_LEN)-1) << AW87XXX_PID_60_CPOK_TM_START_BIT)) -+ -+#define AW87XXX_PID_60_CPOK_TM_0P6MS (0) -+#define AW87XXX_PID_60_CPOK_TM_0P6MS_VALUE \ -+ (AW87XXX_PID_60_CPOK_TM_0P6MS << AW87XXX_PID_60_CPOK_TM_START_BIT) -+ -+#define AW87XXX_PID_60_CPOK_TM_1MS (1) -+#define AW87XXX_PID_60_CPOK_TM_1MS_VALUE \ -+ (AW87XXX_PID_60_CPOK_TM_1MS << AW87XXX_PID_60_CPOK_TM_START_BIT) -+ -+#define AW87XXX_PID_60_CPOK_TM_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_CPOK_TM_DEFAULT \ -+ (AW87XXX_PID_60_CPOK_TM_DEFAULT_VALUE << AW87XXX_PID_60_CPOK_TM_START_BIT) -+ -+/* UVLO_DT bit 4 (CP 0x77) */ -+#define AW87XXX_PID_60_UVLO_DT_START_BIT (4) -+#define AW87XXX_PID_60_UVLO_DT_BITS_LEN (1) -+#define AW87XXX_PID_60_UVLO_DT_MASK \ -+ (~(((1<<AW87XXX_PID_60_UVLO_DT_BITS_LEN)-1) << AW87XXX_PID_60_UVLO_DT_START_BIT)) -+ -+#define AW87XXX_PID_60_UVLO_DT_3US (0) -+#define AW87XXX_PID_60_UVLO_DT_3US_VALUE \ -+ (AW87XXX_PID_60_UVLO_DT_3US << AW87XXX_PID_60_UVLO_DT_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_DT_10US (1) -+#define AW87XXX_PID_60_UVLO_DT_10US_VALUE \ -+ (AW87XXX_PID_60_UVLO_DT_10US << AW87XXX_PID_60_UVLO_DT_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_DT_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_UVLO_DT_DEFAULT \ -+ (AW87XXX_PID_60_UVLO_DT_DEFAULT_VALUE << AW87XXX_PID_60_UVLO_DT_START_BIT) -+ -+/* PD_UVLO bit 7 (CP 0x77) */ -+#define AW87XXX_PID_60_PD_UVLO_START_BIT (7) -+#define AW87XXX_PID_60_PD_UVLO_BITS_LEN (1) -+#define AW87XXX_PID_60_PD_UVLO_MASK \ -+ (~(((1<<AW87XXX_PID_60_PD_UVLO_BITS_LEN)-1) << AW87XXX_PID_60_PD_UVLO_START_BIT)) -+ -+#define AW87XXX_PID_60_PD_UVLO_ENABLE (0) -+#define AW87XXX_PID_60_PD_UVLO_ENABLE_VALUE \ -+ (AW87XXX_PID_60_PD_UVLO_ENABLE << AW87XXX_PID_60_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_60_PD_UVLO_DISABLE (1) -+#define AW87XXX_PID_60_PD_UVLO_DISABLE_VALUE \ -+ (AW87XXX_PID_60_PD_UVLO_DISABLE << AW87XXX_PID_60_PD_UVLO_START_BIT) -+ -+#define AW87XXX_PID_60_PD_UVLO_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PD_UVLO_DEFAULT \ -+ (AW87XXX_PID_60_PD_UVLO_DEFAULT_VALUE << AW87XXX_PID_60_PD_UVLO_START_BIT) -+ -+/* UVLO_VTH bit 6:5 (CP 0x77) */ -+#define AW87XXX_PID_60_UVLO_VTH_START_BIT (5) -+#define AW87XXX_PID_60_UVLO_VTH_BITS_LEN (2) -+#define AW87XXX_PID_60_UVLO_VTH_MASK \ -+ (~(((1<<AW87XXX_PID_60_UVLO_VTH_BITS_LEN)-1) << AW87XXX_PID_60_UVLO_VTH_START_BIT)) -+ -+#define AW87XXX_PID_60_UVLO_VTH_VH2P6V_VL2P5V (0) -+#define AW87XXX_PID_60_UVLO_VTH_VH2P6V_VL2P5V_VALUE \ -+ (AW87XXX_PID_60_UVLO_VTH_VH2P6V_VL2P5V << AW87XXX_PID_60_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_VTH_VH2P7V_VL2P6V (1) -+#define AW87XXX_PID_60_UVLO_VTH_VH2P7V_VL2P6V_VALUE \ -+ (AW87XXX_PID_60_UVLO_VTH_VH2P7V_VL2P6V << AW87XXX_PID_60_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_VTH_VH2P8V_VL2P7V (2) -+#define AW87XXX_PID_60_UVLO_VTH_VH2P8V_VL2P7V_VALUE \ -+ (AW87XXX_PID_60_UVLO_VTH_VH2P8V_VL2P7V << AW87XXX_PID_60_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_VTH_VH2P9V_VL2P8V (3) -+#define AW87XXX_PID_60_UVLO_VTH_VH2P9V_VL2P8V_VALUE \ -+ (AW87XXX_PID_60_UVLO_VTH_VH2P9V_VL2P8V << AW87XXX_PID_60_UVLO_VTH_START_BIT) -+ -+#define AW87XXX_PID_60_UVLO_VTH_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_UVLO_VTH_DEFAULT \ -+ (AW87XXX_PID_60_UVLO_VTH_DEFAULT_VALUE << AW87XXX_PID_60_UVLO_VTH_START_BIT) -+ -+/* CP_LDO bit 3:2 (CP 0x77) */ -+#define AW87XXX_PID_60_CP_LDO_START_BIT (2) -+#define AW87XXX_PID_60_CP_LDO_BITS_LEN (2) -+#define AW87XXX_PID_60_CP_LDO_MASK \ -+ (~(((1<<AW87XXX_PID_60_CP_LDO_BITS_LEN)-1) << AW87XXX_PID_60_CP_LDO_START_BIT)) -+ -+#define AW87XXX_PID_60_CP_LDO_4P75V (0) -+#define AW87XXX_PID_60_CP_LDO_4P75V_VALUE \ -+ (AW87XXX_PID_60_CP_LDO_4P75V << AW87XXX_PID_60_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_60_CP_LDO_5V (1) -+#define AW87XXX_PID_60_CP_LDO_5V_VALUE \ -+ (AW87XXX_PID_60_CP_LDO_5V << AW87XXX_PID_60_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_60_CP_LDO_5P25V (2) -+#define AW87XXX_PID_60_CP_LDO_5P25V_VALUE \ -+ (AW87XXX_PID_60_CP_LDO_5P25V << AW87XXX_PID_60_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_60_CP_LDO_5P5V (3) -+#define AW87XXX_PID_60_CP_LDO_5P5V_VALUE \ -+ (AW87XXX_PID_60_CP_LDO_5P5V << AW87XXX_PID_60_CP_LDO_START_BIT) -+ -+#define AW87XXX_PID_60_CP_LDO_DEFAULT_VALUE (0x2) -+#define AW87XXX_PID_60_CP_LDO_DEFAULT \ -+ (AW87XXX_PID_60_CP_LDO_DEFAULT_VALUE << AW87XXX_PID_60_CP_LDO_START_BIT) -+ -+/* default value of CP (0x77) */ -+/* #define AW87XXX_PID_60_CP_DEFAULT (0x5A) */ -+ -+/* TEST_GTDR (0x78) detail */ -+/* TEST_OC bit 0 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_TEST_OC_START_BIT (0) -+#define AW87XXX_PID_60_TEST_OC_BITS_LEN (1) -+#define AW87XXX_PID_60_TEST_OC_MASK \ -+ (~(((1<<AW87XXX_PID_60_TEST_OC_BITS_LEN)-1) << AW87XXX_PID_60_TEST_OC_START_BIT)) -+ -+#define AW87XXX_PID_60_TEST_OC_DISABLE (0) -+#define AW87XXX_PID_60_TEST_OC_DISABLE_VALUE \ -+ (AW87XXX_PID_60_TEST_OC_DISABLE << AW87XXX_PID_60_TEST_OC_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_OC_ENABLE (1) -+#define AW87XXX_PID_60_TEST_OC_ENABLE_VALUE \ -+ (AW87XXX_PID_60_TEST_OC_ENABLE << AW87XXX_PID_60_TEST_OC_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_OC_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_TEST_OC_DEFAULT \ -+ (AW87XXX_PID_60_TEST_OC_DEFAULT_VALUE << AW87XXX_PID_60_TEST_OC_START_BIT) -+ -+/* OC_DEBUG_EN bit 1 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_OC_DEBUG_EN_START_BIT (1) -+#define AW87XXX_PID_60_OC_DEBUG_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_OC_DEBUG_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_OC_DEBUG_EN_BITS_LEN)-1) << AW87XXX_PID_60_OC_DEBUG_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_OC_DEBUG_EN_DISABLE (0) -+#define AW87XXX_PID_60_OC_DEBUG_EN_DISABLE_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_EN_DISABLE << AW87XXX_PID_60_OC_DEBUG_EN_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_EN_ENABLE (1) -+#define AW87XXX_PID_60_OC_DEBUG_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_EN_ENABLE << AW87XXX_PID_60_OC_DEBUG_EN_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_EN_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_OC_DEBUG_EN_DEFAULT \ -+ (AW87XXX_PID_60_OC_DEBUG_EN_DEFAULT_VALUE << AW87XXX_PID_60_OC_DEBUG_EN_START_BIT) -+ -+/* LN_RON_T_N bit 4 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_LN_RON_T_N_START_BIT (4) -+#define AW87XXX_PID_60_LN_RON_T_N_BITS_LEN (1) -+#define AW87XXX_PID_60_LN_RON_T_N_MASK \ -+ (~(((1<<AW87XXX_PID_60_LN_RON_T_N_BITS_LEN)-1) << AW87XXX_PID_60_LN_RON_T_N_START_BIT)) -+ -+#define AW87XXX_PID_60_LN_RON_T_N_DISABLE (0) -+#define AW87XXX_PID_60_LN_RON_T_N_DISABLE_VALUE \ -+ (AW87XXX_PID_60_LN_RON_T_N_DISABLE << AW87XXX_PID_60_LN_RON_T_N_START_BIT) -+ -+#define AW87XXX_PID_60_LN_RON_T_N_ENALBE (1) -+#define AW87XXX_PID_60_LN_RON_T_N_ENALBE_VALUE \ -+ (AW87XXX_PID_60_LN_RON_T_N_ENALBE << AW87XXX_PID_60_LN_RON_T_N_START_BIT) -+ -+#define AW87XXX_PID_60_LN_RON_T_N_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_LN_RON_T_N_DEFAULT \ -+ (AW87XXX_PID_60_LN_RON_T_N_DEFAULT_VALUE << AW87XXX_PID_60_LN_RON_T_N_START_BIT) -+ -+/* LN_RON_T_P bit 5 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_LN_RON_T_P_START_BIT (5) -+#define AW87XXX_PID_60_LN_RON_T_P_BITS_LEN (1) -+#define AW87XXX_PID_60_LN_RON_T_P_MASK \ -+ (~(((1<<AW87XXX_PID_60_LN_RON_T_P_BITS_LEN)-1) << AW87XXX_PID_60_LN_RON_T_P_START_BIT)) -+ -+#define AW87XXX_PID_60_LN_RON_T_P_DISABLE (0) -+#define AW87XXX_PID_60_LN_RON_T_P_DISABLE_VALUE \ -+ (AW87XXX_PID_60_LN_RON_T_P_DISABLE << AW87XXX_PID_60_LN_RON_T_P_START_BIT) -+ -+#define AW87XXX_PID_60_LN_RON_T_P_ENALBE (1) -+#define AW87XXX_PID_60_LN_RON_T_P_ENALBE_VALUE \ -+ (AW87XXX_PID_60_LN_RON_T_P_ENALBE << AW87XXX_PID_60_LN_RON_T_P_START_BIT) -+ -+#define AW87XXX_PID_60_LN_RON_T_P_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_LN_RON_T_P_DEFAULT \ -+ (AW87XXX_PID_60_LN_RON_T_P_DEFAULT_VALUE << AW87XXX_PID_60_LN_RON_T_P_START_BIT) -+ -+/* HN_RON_T_N bit 6 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_HN_RON_T_N_START_BIT (6) -+#define AW87XXX_PID_60_HN_RON_T_N_BITS_LEN (1) -+#define AW87XXX_PID_60_HN_RON_T_N_MASK \ -+ (~(((1<<AW87XXX_PID_60_HN_RON_T_N_BITS_LEN)-1) << AW87XXX_PID_60_HN_RON_T_N_START_BIT)) -+ -+#define AW87XXX_PID_60_HN_RON_T_N_DISABLE (0) -+#define AW87XXX_PID_60_HN_RON_T_N_DISABLE_VALUE \ -+ (AW87XXX_PID_60_HN_RON_T_N_DISABLE << AW87XXX_PID_60_HN_RON_T_N_START_BIT) -+ -+#define AW87XXX_PID_60_HN_RON_T_N_ENALBE (1) -+#define AW87XXX_PID_60_HN_RON_T_N_ENALBE_VALUE \ -+ (AW87XXX_PID_60_HN_RON_T_N_ENALBE << AW87XXX_PID_60_HN_RON_T_N_START_BIT) -+ -+#define AW87XXX_PID_60_HN_RON_T_N_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_HN_RON_T_N_DEFAULT \ -+ (AW87XXX_PID_60_HN_RON_T_N_DEFAULT_VALUE << AW87XXX_PID_60_HN_RON_T_N_START_BIT) -+ -+/* HN_RON_T_P bit 7 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_HN_RON_T_P_START_BIT (7) -+#define AW87XXX_PID_60_HN_RON_T_P_BITS_LEN (1) -+#define AW87XXX_PID_60_HN_RON_T_P_MASK \ -+ (~(((1<<AW87XXX_PID_60_HN_RON_T_P_BITS_LEN)-1) << AW87XXX_PID_60_HN_RON_T_P_START_BIT)) -+ -+#define AW87XXX_PID_60_HN_RON_T_P_DISABLE (0) -+#define AW87XXX_PID_60_HN_RON_T_P_DISABLE_VALUE \ -+ (AW87XXX_PID_60_HN_RON_T_P_DISABLE << AW87XXX_PID_60_HN_RON_T_P_START_BIT) -+ -+#define AW87XXX_PID_60_HN_RON_T_P_ENALBE (1) -+#define AW87XXX_PID_60_HN_RON_T_P_ENALBE_VALUE \ -+ (AW87XXX_PID_60_HN_RON_T_P_ENALBE << AW87XXX_PID_60_HN_RON_T_P_START_BIT) -+ -+#define AW87XXX_PID_60_HN_RON_T_P_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_HN_RON_T_P_DEFAULT \ -+ (AW87XXX_PID_60_HN_RON_T_P_DEFAULT_VALUE << AW87XXX_PID_60_HN_RON_T_P_START_BIT) -+ -+/* OC_DEBUG_SEL bit 3:2 (TEST_GTDR 0x78) */ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT (2) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_BITS_LEN (2) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_MASK \ -+ (~(((1<<AW87XXX_PID_60_OC_DEBUG_SEL_BITS_LEN)-1) << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT)) -+ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VOPP (0) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VOPP_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_SEL_VOPP << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VOPN (1) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VOPN_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_SEL_VOPN << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VONP (2) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VONP_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_SEL_VONP << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VONN (3) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_VONN_VALUE \ -+ (AW87XXX_PID_60_OC_DEBUG_SEL_VONN << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DEBUG_SEL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_OC_DEBUG_SEL_DEFAULT \ -+ (AW87XXX_PID_60_OC_DEBUG_SEL_DEFAULT_VALUE << AW87XXX_PID_60_OC_DEBUG_SEL_START_BIT) -+ -+/* default value of TEST_GTDR (0x78) */ -+/* #define AW87XXX_PID_60_TEST_GTDR_DEFAULT (0x00) */ -+ -+/* TEST_BST (0x79) detail */ -+/* BST_LNMOS_TEST bit 0 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_LNMOS_TEST_START_BIT (0) -+#define AW87XXX_PID_60_BST_LNMOS_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_LNMOS_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_LNMOS_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_LNMOS_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_LNMOS_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_LNMOS_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_LNMOS_TEST_DIABLE << AW87XXX_PID_60_BST_LNMOS_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LNMOS_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_LNMOS_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_LNMOS_TEST_ENABLE << AW87XXX_PID_60_BST_LNMOS_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_LNMOS_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_LNMOS_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_LNMOS_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_LNMOS_TEST_START_BIT) -+ -+/* BST_HNMOS_TEST bit 1 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_HNMOS_TEST_START_BIT (1) -+#define AW87XXX_PID_60_BST_HNMOS_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_HNMOS_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_HNMOS_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_HNMOS_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_HNMOS_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_HNMOS_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_HNMOS_TEST_DIABLE << AW87XXX_PID_60_BST_HNMOS_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_HNMOS_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_HNMOS_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_HNMOS_TEST_ENABLE << AW87XXX_PID_60_BST_HNMOS_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_HNMOS_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_HNMOS_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_HNMOS_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_HNMOS_TEST_START_BIT) -+ -+/* BST_SCP_TEST bit 2 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_SCP_TEST_START_BIT (2) -+#define AW87XXX_PID_60_BST_SCP_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_SCP_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_SCP_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_SCP_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_SCP_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_SCP_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_TEST_DIABLE << AW87XXX_PID_60_BST_SCP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_SCP_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_SCP_TEST_ENABLE << AW87XXX_PID_60_BST_SCP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_SCP_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_SCP_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_SCP_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_SCP_TEST_START_BIT) -+ -+/* ANTIR_TEST bit 3 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_ANTIR_TEST_START_BIT (3) -+#define AW87XXX_PID_60_ANTIR_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_ANTIR_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_ANTIR_TEST_BITS_LEN)-1) << AW87XXX_PID_60_ANTIR_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_ANTIR_TEST_DIABLE (0) -+#define AW87XXX_PID_60_ANTIR_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_ANTIR_TEST_DIABLE << AW87XXX_PID_60_ANTIR_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_ANTIR_TEST_ENABLE (1) -+#define AW87XXX_PID_60_ANTIR_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_ANTIR_TEST_ENABLE << AW87XXX_PID_60_ANTIR_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_ANTIR_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_ANTIR_TEST_DEFAULT \ -+ (AW87XXX_PID_60_ANTIR_TEST_DEFAULT_VALUE << AW87XXX_PID_60_ANTIR_TEST_START_BIT) -+ -+/* BST_PEAK_TEST bit 4 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_PEAK_TEST_START_BIT (4) -+#define AW87XXX_PID_60_BST_PEAK_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_PEAK_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_PEAK_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_PEAK_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_PEAK_TEST_DISABLE (0) -+#define AW87XXX_PID_60_BST_PEAK_TEST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_PEAK_TEST_DISABLE << AW87XXX_PID_60_BST_PEAK_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_PEAK_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_PEAK_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_PEAK_TEST_ENABLE << AW87XXX_PID_60_BST_PEAK_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_PEAK_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_PEAK_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_PEAK_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_PEAK_TEST_START_BIT) -+ -+/* BST_OVP_TEST bit 5 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_OVP_TEST_START_BIT (5) -+#define AW87XXX_PID_60_BST_OVP_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_OVP_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_OVP_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_OVP_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_OVP_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_OVP_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_TEST_DIABLE << AW87XXX_PID_60_BST_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_OVP_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_OVP_TEST_ENABLE << AW87XXX_PID_60_BST_OVP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_OVP_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_OVP_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_OVP_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_OVP_TEST_START_BIT) -+ -+/* BST_TEST_EN bit 6 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_BST_TEST_EN_START_BIT (6) -+#define AW87XXX_PID_60_BST_TEST_EN_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_TEST_EN_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_TEST_EN_BITS_LEN)-1) << AW87XXX_PID_60_BST_TEST_EN_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_TEST_EN_DIABLE (0) -+#define AW87XXX_PID_60_BST_TEST_EN_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_TEST_EN_DIABLE << AW87XXX_PID_60_BST_TEST_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_TEST_EN_ENABLE (1) -+#define AW87XXX_PID_60_BST_TEST_EN_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_TEST_EN_ENABLE << AW87XXX_PID_60_BST_TEST_EN_START_BIT) -+ -+#define AW87XXX_PID_60_BST_TEST_EN_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_TEST_EN_DEFAULT \ -+ (AW87XXX_PID_60_BST_TEST_EN_DEFAULT_VALUE << AW87XXX_PID_60_BST_TEST_EN_START_BIT) -+ -+/* OC_DISABLE bit 7 (TEST_BST 0x79) */ -+#define AW87XXX_PID_60_OC_DISABLE_START_BIT (7) -+#define AW87XXX_PID_60_OC_DISABLE_BITS_LEN (1) -+#define AW87XXX_PID_60_OC_DISABLE_MASK \ -+ (~(((1<<AW87XXX_PID_60_OC_DISABLE_BITS_LEN)-1) << AW87XXX_PID_60_OC_DISABLE_START_BIT)) -+ -+#define AW87XXX_PID_60_OC_DISABLE_ENABLE (0) -+#define AW87XXX_PID_60_OC_DISABLE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_OC_DISABLE_ENABLE << AW87XXX_PID_60_OC_DISABLE_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DISABLE_SHUTDOWN (1) -+#define AW87XXX_PID_60_OC_DISABLE_SHUTDOWN_VALUE \ -+ (AW87XXX_PID_60_OC_DISABLE_SHUTDOWN << AW87XXX_PID_60_OC_DISABLE_START_BIT) -+ -+#define AW87XXX_PID_60_OC_DISABLE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_OC_DISABLE_DEFAULT \ -+ (AW87XXX_PID_60_OC_DISABLE_DEFAULT_VALUE << AW87XXX_PID_60_OC_DISABLE_START_BIT) -+ -+/* default value of TEST_BST (0x79) */ -+/* #define AW87XXX_PID_60_TEST_BST_DEFAULT (0x00) */ -+ -+/* TEST_MODE (0x7A) detail */ -+/* PA_TEST_FORCE bit 3 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_PA_TEST_FORCE_START_BIT (3) -+#define AW87XXX_PID_60_PA_TEST_FORCE_BITS_LEN (1) -+#define AW87XXX_PID_60_PA_TEST_FORCE_MASK \ -+ (~(((1<<AW87XXX_PID_60_PA_TEST_FORCE_BITS_LEN)-1) << AW87XXX_PID_60_PA_TEST_FORCE_START_BIT)) -+ -+#define AW87XXX_PID_60_PA_TEST_FORCE_DISABLE (0) -+#define AW87XXX_PID_60_PA_TEST_FORCE_DISABLE_VALUE \ -+ (AW87XXX_PID_60_PA_TEST_FORCE_DISABLE << AW87XXX_PID_60_PA_TEST_FORCE_START_BIT) -+ -+#define AW87XXX_PID_60_PA_TEST_FORCE_ENABLE (1) -+#define AW87XXX_PID_60_PA_TEST_FORCE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_PA_TEST_FORCE_ENABLE << AW87XXX_PID_60_PA_TEST_FORCE_START_BIT) -+ -+#define AW87XXX_PID_60_PA_TEST_FORCE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_PA_TEST_FORCE_DEFAULT \ -+ (AW87XXX_PID_60_PA_TEST_FORCE_DEFAULT_VALUE << AW87XXX_PID_60_PA_TEST_FORCE_START_BIT) -+ -+/* BST_TEST_FORCE bit 4 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_BST_TEST_FORCE_START_BIT (4) -+#define AW87XXX_PID_60_BST_TEST_FORCE_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_TEST_FORCE_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_TEST_FORCE_BITS_LEN)-1) << AW87XXX_PID_60_BST_TEST_FORCE_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_TEST_FORCE_DISABLE (0) -+#define AW87XXX_PID_60_BST_TEST_FORCE_DISABLE_VALUE \ -+ (AW87XXX_PID_60_BST_TEST_FORCE_DISABLE << AW87XXX_PID_60_BST_TEST_FORCE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_TEST_FORCE_ENABLE (1) -+#define AW87XXX_PID_60_BST_TEST_FORCE_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_TEST_FORCE_ENABLE << AW87XXX_PID_60_BST_TEST_FORCE_START_BIT) -+ -+#define AW87XXX_PID_60_BST_TEST_FORCE_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_BST_TEST_FORCE_DEFAULT \ -+ (AW87XXX_PID_60_BST_TEST_FORCE_DEFAULT_VALUE << AW87XXX_PID_60_BST_TEST_FORCE_START_BIT) -+ -+/* EN_OT_TEST bit 5 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_EN_OT_TEST_START_BIT (5) -+#define AW87XXX_PID_60_EN_OT_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_OT_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_OT_TEST_BITS_LEN)-1) << AW87XXX_PID_60_EN_OT_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_OT_TEST_DISABLE (0) -+#define AW87XXX_PID_60_EN_OT_TEST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_OT_TEST_DISABLE << AW87XXX_PID_60_EN_OT_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_OT_TEST_ENABLE (1) -+#define AW87XXX_PID_60_EN_OT_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_OT_TEST_ENABLE << AW87XXX_PID_60_EN_OT_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_OT_TEST_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_OT_TEST_DEFAULT \ -+ (AW87XXX_PID_60_EN_OT_TEST_DEFAULT_VALUE << AW87XXX_PID_60_EN_OT_TEST_START_BIT) -+ -+/* EN_TEST bit 6 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_EN_TEST_START_BIT (6) -+#define AW87XXX_PID_60_EN_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_TEST_BITS_LEN)-1) << AW87XXX_PID_60_EN_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_TEST_DISABLE (0) -+#define AW87XXX_PID_60_EN_TEST_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_TEST_DISABLE << AW87XXX_PID_60_EN_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_TEST_ENABLE (1) -+#define AW87XXX_PID_60_EN_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_TEST_ENABLE << AW87XXX_PID_60_EN_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_EN_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_EN_TEST_DEFAULT \ -+ (AW87XXX_PID_60_EN_TEST_DEFAULT_VALUE << AW87XXX_PID_60_EN_TEST_START_BIT) -+ -+/* BST_BURST_TEST bit 7 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_BST_BURST_TEST_START_BIT (7) -+#define AW87XXX_PID_60_BST_BURST_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_BST_BURST_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_BST_BURST_TEST_BITS_LEN)-1) << AW87XXX_PID_60_BST_BURST_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_BST_BURST_TEST_DIABLE (0) -+#define AW87XXX_PID_60_BST_BURST_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_TEST_DIABLE << AW87XXX_PID_60_BST_BURST_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_TEST_ENABLE (1) -+#define AW87XXX_PID_60_BST_BURST_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_BST_BURST_TEST_ENABLE << AW87XXX_PID_60_BST_BURST_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_BST_BURST_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_BST_BURST_TEST_DEFAULT \ -+ (AW87XXX_PID_60_BST_BURST_TEST_DEFAULT_VALUE << AW87XXX_PID_60_BST_BURST_TEST_START_BIT) -+ -+/* TEST_ANALOG_CTRL bit 2:0 (TEST_MODE 0x7A) */ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT (0) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_BITS_LEN (3) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_MASK \ -+ (~(((1<<AW87XXX_PID_60_TEST_ANALOG_CTRL_BITS_LEN)-1) << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT)) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VBG (0) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VBG_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_VBG << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_COMPT (1) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_COMPT_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_COMPT << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_HALFVDD (2) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_HALFVDD_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_HALFVDD << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VCSEL (3) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VCSEL_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_VCSEL << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VLSEL (4) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VLSEL_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_VLSEL << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH1T (5) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH1T_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH1T << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH4T (6) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH4T_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_MSBMVTH4T << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VCM2T (7) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_VCM2T_VALUE \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_VCM2T << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_TEST_ANALOG_CTRL_DEFAULT \ -+ (AW87XXX_PID_60_TEST_ANALOG_CTRL_DEFAULT_VALUE << AW87XXX_PID_60_TEST_ANALOG_CTRL_START_BIT) -+ -+/* default value of TEST_MODE (0x7A) */ -+/* #define AW87XXX_PID_60_TEST_MODE_DEFAULT (0x00) */ -+ -+/* TEST_CON (0x7B) detail */ -+/* COMP_TEST bit 5 (TEST_CON 0x7B) */ -+#define AW87XXX_PID_60_COMP_TEST_START_BIT (5) -+#define AW87XXX_PID_60_COMP_TEST_BITS_LEN (1) -+#define AW87XXX_PID_60_COMP_TEST_MASK \ -+ (~(((1<<AW87XXX_PID_60_COMP_TEST_BITS_LEN)-1) << AW87XXX_PID_60_COMP_TEST_START_BIT)) -+ -+#define AW87XXX_PID_60_COMP_TEST_DIABLE (0) -+#define AW87XXX_PID_60_COMP_TEST_DIABLE_VALUE \ -+ (AW87XXX_PID_60_COMP_TEST_DIABLE << AW87XXX_PID_60_COMP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_COMP_TEST_ENABLE (1) -+#define AW87XXX_PID_60_COMP_TEST_ENABLE_VALUE \ -+ (AW87XXX_PID_60_COMP_TEST_ENABLE << AW87XXX_PID_60_COMP_TEST_START_BIT) -+ -+#define AW87XXX_PID_60_COMP_TEST_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_COMP_TEST_DEFAULT \ -+ (AW87XXX_PID_60_COMP_TEST_DEFAULT_VALUE << AW87XXX_PID_60_COMP_TEST_START_BIT) -+ -+/* REG_EN_ESD bit 6 (TEST_CON 0x7B) */ -+#define AW87XXX_PID_60_REG_EN_ESD_START_BIT (6) -+#define AW87XXX_PID_60_REG_EN_ESD_BITS_LEN (1) -+#define AW87XXX_PID_60_REG_EN_ESD_MASK \ -+ (~(((1<<AW87XXX_PID_60_REG_EN_ESD_BITS_LEN)-1) << AW87XXX_PID_60_REG_EN_ESD_START_BIT)) -+ -+#define AW87XXX_PID_60_REG_EN_ESD_DISABLE (0) -+#define AW87XXX_PID_60_REG_EN_ESD_DISABLE_VALUE \ -+ (AW87XXX_PID_60_REG_EN_ESD_DISABLE << AW87XXX_PID_60_REG_EN_ESD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_EN_ESD_ENABLE (1) -+#define AW87XXX_PID_60_REG_EN_ESD_ENABLE_VALUE \ -+ (AW87XXX_PID_60_REG_EN_ESD_ENABLE << AW87XXX_PID_60_REG_EN_ESD_START_BIT) -+ -+#define AW87XXX_PID_60_REG_EN_ESD_DEFAULT_VALUE (0) -+#define AW87XXX_PID_60_REG_EN_ESD_DEFAULT \ -+ (AW87XXX_PID_60_REG_EN_ESD_DEFAULT_VALUE << AW87XXX_PID_60_REG_EN_ESD_START_BIT) -+ -+/* EN_POWER_MT bit 7 (TEST_CON 0x7B) */ -+#define AW87XXX_PID_60_EN_POWER_MT_START_BIT (7) -+#define AW87XXX_PID_60_EN_POWER_MT_BITS_LEN (1) -+#define AW87XXX_PID_60_EN_POWER_MT_MASK \ -+ (~(((1<<AW87XXX_PID_60_EN_POWER_MT_BITS_LEN)-1) << AW87XXX_PID_60_EN_POWER_MT_START_BIT)) -+ -+#define AW87XXX_PID_60_EN_POWER_MT_DISABLE (0) -+#define AW87XXX_PID_60_EN_POWER_MT_DISABLE_VALUE \ -+ (AW87XXX_PID_60_EN_POWER_MT_DISABLE << AW87XXX_PID_60_EN_POWER_MT_START_BIT) -+ -+#define AW87XXX_PID_60_EN_POWER_MT_ENABLE (1) -+#define AW87XXX_PID_60_EN_POWER_MT_ENABLE_VALUE \ -+ (AW87XXX_PID_60_EN_POWER_MT_ENABLE << AW87XXX_PID_60_EN_POWER_MT_START_BIT) -+ -+#define AW87XXX_PID_60_EN_POWER_MT_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_EN_POWER_MT_DEFAULT \ -+ (AW87XXX_PID_60_EN_POWER_MT_DEFAULT_VALUE << AW87XXX_PID_60_EN_POWER_MT_START_BIT) -+ -+/* TEST_DIGITAL_CTRL bit 4:0 (TEST_CON 0x7B) */ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT (0) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BITS_LEN (5) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_MASK \ -+ (~(((1<<AW87XXX_PID_60_TEST_DIGITAL_CTRL_BITS_LEN)-1) << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT)) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVPS (0) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVPS_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVPS << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVP2 (1) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVP2_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTOVP2 << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTHNMOS (2) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTHNMOS_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTHNMOS << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTLNMOS (3) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTLNMOS_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTLNMOS << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTPEAK (4) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTPEAK_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTPEAK << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTRSQ (5) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTRSQ_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTRSQ << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTBURST (6) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTBURST_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTBURST << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSSFINISH (7) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSSFINISH_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSSFINISH << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSCP (8) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSCP_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTSCP << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTENCLAMP (9) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTENCLAMP_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTENCLAMP << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTNCD (10) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTNCD_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_BSTNCD << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENSYNC (11) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENSYNC_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENSYNC << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENOTA (12) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENOTA_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_ENOTA << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_NGDET (13) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_NGDET_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_NGDET << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTN (14) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTN_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTN << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTN (15) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTN_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTN << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEN (16) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEN_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEN << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTP (17) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTP_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_HNGTP << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTP (18) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTP_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_LNGTP << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEP (19) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEP_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_GATESENSEP << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ADPBOOST (20) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_ADPBOOST_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_ADPBOOST << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW0ABOVE (21) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW0ABOVE_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW0ABOVE << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW3ABOVE (22) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW3ABOVE_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_POVTHBELOW3ABOVE << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_AMPOC (23) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_AMPOC_VALUE \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_AMPOC << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_TEST_DIGITAL_CTRL_DEFAULT \ -+ (AW87XXX_PID_60_TEST_DIGITAL_CTRL_DEFAULT_VALUE << AW87XXX_PID_60_TEST_DIGITAL_CTRL_START_BIT) -+ -+/* default value of TEST_CON (0x7B) */ -+/* #define AW87XXX_PID_60_TEST_CON_DEFAULT (0x00) */ -+ -+/* ENCR (0x7C) detail */ -+/* TEST_REG_ENCRY bit 7:6 (ENCR 0x7C) */ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT (6) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_BITS_LEN (2) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_MASK \ -+ (~(((1<<AW87XXX_PID_60_TEST_REG_ENCRY_BITS_LEN)-1) << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT)) -+ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE0 (0) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE0_VALUE \ -+ (AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE0 << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE1 (1) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE1_VALUE \ -+ (AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE1 << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE2 (2) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE2_VALUE \ -+ (AW87XXX_PID_60_TEST_REG_ENCRY_CANNOT_WRITE2 << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CAN_BE_WRITE (3) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_CAN_BE_WRITE_VALUE \ -+ (AW87XXX_PID_60_TEST_REG_ENCRY_CAN_BE_WRITE << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT) -+/* -+Fix me here: -+reg_addr:0x7C, reg_name:ENCR, field_name:TEST_REG_ENCRY, content:Encryption bits for test registers(78h~7Ch) , when0x7D=7a & test_Reg_Encry=11 -+maybe need to fix manually -+*/ -+#define AW87XXX_PID_60_TEST_REG_ENCRY_DEFAULT_VALUE (0x0) -+#define AW87XXX_PID_60_TEST_REG_ENCRY_DEFAULT \ -+ (AW87XXX_PID_60_TEST_REG_ENCRY_DEFAULT_VALUE << AW87XXX_PID_60_TEST_REG_ENCRY_START_BIT) -+ -+/* PRODUCT_REG_ENCRY bit 5:0 (ENCR 0x7C) */ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT (0) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_BITS_LEN (6) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_MASK \ -+ (~(((1<<AW87XXX_PID_60_PRODUCT_REG_ENCRY_BITS_LEN)-1) << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT)) -+ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87560 (1) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87560_VALUE \ -+ (AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87560 << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87561 (2) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87561_VALUE \ -+ (AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87561 << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87562 (4) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87562_VALUE \ -+ (AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87562 << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT) -+ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87501 (8) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87501_VALUE \ -+ (AW87XXX_PID_60_PRODUCT_REG_ENCRY_AW87501 << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT) -+/* -+Fix me here: -+reg_addr:0x7C, reg_name:ENCR, field_name:PRODUCT_REG_ENCRY, content:Production encryption register (when0x7D=7a & test_Reg_Encry=11 ?? -+maybe need to fix manually -+*/ -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_DEFAULT_VALUE (0x1) -+#define AW87XXX_PID_60_PRODUCT_REG_ENCRY_DEFAULT \ -+ (AW87XXX_PID_60_PRODUCT_REG_ENCRY_DEFAULT_VALUE << AW87XXX_PID_60_PRODUCT_REG_ENCRY_START_BIT) -+ -+/* default value of ENCR (0x7C) */ -+/* #define AW87XXX_PID_60_ENCR_DEFAULT (0x01) */ -+ -+/* detail information of registers end */ -+ -+#endif /* #ifndef __AW87XXX_PID_60_REG_H__ */ -\ No newline at end of file -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h -new file mode 100644 -index 000000000..00af86e5d ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h -@@ -0,0 +1,1205 @@ -+#ifndef __AW87XXX_PID_76_REG_H__ -+#define __AW87XXX_PID_76_REG_H__ -+ -+/* registers list */ -+#define AW87XXX_PID_76_ID_REG (0x00) -+#define AW87XXX_PID_76_SYSCTRL_REG (0x01) -+#define AW87XXX_PID_76_MDCTRL_REG (0x02) -+#define AW87XXX_PID_76_CPOVP_REG (0x03) -+#define AW87XXX_PID_76_CPP_REG (0x04) -+#define AW87XXX_PID_76_PAG_REG (0x05) -+#define AW87XXX_PID_76_AGC3P_REG (0x06) -+#define AW87XXX_PID_76_AGC3PA_REG (0x07) -+#define AW87XXX_PID_76_AGC2P_REG (0x08) -+#define AW87XXX_PID_76_AGC2PA_REG (0x09) -+#define AW87XXX_PID_76_AGC1PA_REG (0x0A) -+#define AW87XXX_PID_76_SYSST_REG (0x59) -+#define AW87XXX_PID_76_SYSINT_REG (0x60) -+#define AW87XXX_PID_76_DFT_SYSCTRL_REG (0x61) -+#define AW87XXX_PID_76_DFT_MDCTRL_REG (0x62) -+#define AW87XXX_PID_76_DFT_CPADP_REG (0x63) -+#define AW87XXX_PID_76_DFT_AGCPA_REG (0x64) -+#define AW87XXX_PID_76_DFT_POFR_REG (0x65) -+#define AW87XXX_PID_76_DFT_OC_REG (0x66) -+#define AW87XXX_PID_76_DFT_ADP1_REG (0x67) -+#define AW87XXX_PID_76_DFT_REF_REG (0x68) -+#define AW87XXX_PID_76_DFT_LDO_REG (0x69) -+#define AW87XXX_PID_76_ADP1_REG (0x70) -+#define AW87XXX_PID_76_ADP2_REG (0x71) -+#define AW87XXX_PID_76_NG1_REG (0x72) -+#define AW87XXX_PID_76_NG2_REG (0x73) -+#define AW87XXX_PID_76_NG3_REG (0x74) -+#define AW87XXX_PID_76_CP_REG (0x75) -+#define AW87XXX_PID_76_AB_REG (0x76) -+#define AW87XXX_PID_76_TEST_REG (0x77) -+#define AW87XXX_PID_76_ENCR_REG (0x78) -+#define AW87XXX_PID_76_DFT_ADP1_CHECK (0x04) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_76_softrst_access[2] = {0x00, 0xaa}; -+ -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_76_REG_MAX (0x79) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_76_reg_access[AW87XXX_PID_76_REG_MAX] = { -+ [AW87XXX_PID_76_ID_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_76_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_MDCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_CPOVP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_CPP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_PAG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AGC3P_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AGC3PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AGC2P_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AGC2PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AGC1PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_SYSST_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_76_SYSINT_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_76_DFT_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_MDCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_CPADP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_AGCPA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_POFR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_OC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_ADP1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_REF_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_DFT_LDO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_ADP1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_ADP2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_NG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_NG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_NG3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_AB_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_TEST_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_76_ENCR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+/* detail information of registers begin */ -+/* ID (0x00) detail */ -+/* IDCODE bit 7:0 (ID 0x00) */ -+#define AW87XXX_PID_76_IDCODE_START_BIT (0) -+#define AW87XXX_PID_76_IDCODE_BITS_LEN (8) -+#define AW87XXX_PID_76_IDCODE_MASK \ -+ (~(((1<<AW87XXX_PID_76_IDCODE_BITS_LEN)-1) << AW87XXX_PID_76_IDCODE_START_BIT)) -+ -+#define AW87XXX_PID_76_IDCODE_DEFAULT_VALUE (0x76) -+#define AW87XXX_PID_76_IDCODE_DEFAULT \ -+ (AW87XXX_PID_76_IDCODE_DEFAULT_VALUE << AW87XXX_PID_76_IDCODE_START_BIT) -+ -+/* default value of ID (0x00) */ -+/* #define AW87XXX_PID_76_ID_DEFAULT (0x76) */ -+ -+/* SYSCTRL (0x01) detail */ -+/* EN_PA bit 2 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_76_EN_PA_START_BIT (2) -+#define AW87XXX_PID_76_EN_PA_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_PA_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_PA_BITS_LEN)-1) << AW87XXX_PID_76_EN_PA_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_PA_DISABLE (0) -+#define AW87XXX_PID_76_EN_PA_DISABLE_VALUE \ -+ (AW87XXX_PID_76_EN_PA_DISABLE << AW87XXX_PID_76_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_76_EN_PA_ENABLE_DEPENDS_ON_EN_AB (1) -+#define AW87XXX_PID_76_EN_PA_ENABLE_DEPENDS_ON_EN_AB_VALUE \ -+ (AW87XXX_PID_76_EN_PA_ENABLE_DEPENDS_ON_EN_AB << AW87XXX_PID_76_EN_PA_START_BIT) -+ -+#define AW87XXX_PID_76_EN_PA_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_EN_PA_DEFAULT \ -+ (AW87XXX_PID_76_EN_PA_DEFAULT_VALUE << AW87XXX_PID_76_EN_PA_START_BIT) -+ -+/* EN_CP bit 1 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_76_EN_CP_START_BIT (1) -+#define AW87XXX_PID_76_EN_CP_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_CP_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_CP_BITS_LEN)-1) << AW87XXX_PID_76_EN_CP_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_CP_DISABLE_PVDD0 (0) -+#define AW87XXX_PID_76_EN_CP_DISABLE_PVDD0_VALUE \ -+ (AW87XXX_PID_76_EN_CP_DISABLE_PVDD0 << AW87XXX_PID_76_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_76_EN_CP_ENABLE_DEPENDS_ON_EN_2X (1) -+#define AW87XXX_PID_76_EN_CP_ENABLE_DEPENDS_ON_EN_2X_VALUE \ -+ (AW87XXX_PID_76_EN_CP_ENABLE_DEPENDS_ON_EN_2X << AW87XXX_PID_76_EN_CP_START_BIT) -+ -+#define AW87XXX_PID_76_EN_CP_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_EN_CP_DEFAULT \ -+ (AW87XXX_PID_76_EN_CP_DEFAULT_VALUE << AW87XXX_PID_76_EN_CP_START_BIT) -+ -+/* PU_CPPA bit 0 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_76_PU_CPPA_START_BIT (0) -+#define AW87XXX_PID_76_PU_CPPA_BITS_LEN (1) -+#define AW87XXX_PID_76_PU_CPPA_MASK \ -+ (~(((1<<AW87XXX_PID_76_PU_CPPA_BITS_LEN)-1) << AW87XXX_PID_76_PU_CPPA_START_BIT)) -+ -+#define AW87XXX_PID_76_PU_CPPA_POWERMINUS_DOWN (0) -+#define AW87XXX_PID_76_PU_CPPA_POWERMINUS_DOWN_VALUE \ -+ (AW87XXX_PID_76_PU_CPPA_POWERMINUS_DOWN << AW87XXX_PID_76_PU_CPPA_START_BIT) -+ -+#define AW87XXX_PID_76_PU_CPPA_POWERMINUS_UP (1) -+#define AW87XXX_PID_76_PU_CPPA_POWERMINUS_UP_VALUE \ -+ (AW87XXX_PID_76_PU_CPPA_POWERMINUS_UP << AW87XXX_PID_76_PU_CPPA_START_BIT) -+ -+#define AW87XXX_PID_76_PU_CPPA_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_PU_CPPA_DEFAULT \ -+ (AW87XXX_PID_76_PU_CPPA_DEFAULT_VALUE << AW87XXX_PID_76_PU_CPPA_START_BIT) -+ -+/* default value of SYSCTRL (0x01) */ -+/* #define AW87XXX_PID_76_SYSCTRL_DEFAULT (0x06) */ -+ -+/* MDCTRL (0x02) detail */ -+/* EN_ADAP bit 4 (MDCTRL 0x02) */ -+#define AW87XXX_PID_76_EN_ADAP_START_BIT (4) -+#define AW87XXX_PID_76_EN_ADAP_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_ADAP_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_ADAP_BITS_LEN)-1) << AW87XXX_PID_76_EN_ADAP_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_ADAP_DISABLEDEFAULT (0) -+#define AW87XXX_PID_76_EN_ADAP_DISABLEDEFAULT_VALUE \ -+ (AW87XXX_PID_76_EN_ADAP_DISABLEDEFAULT << AW87XXX_PID_76_EN_ADAP_START_BIT) -+ -+#define AW87XXX_PID_76_EN_ADAP_ENABLE (1) -+#define AW87XXX_PID_76_EN_ADAP_ENABLE_VALUE \ -+ (AW87XXX_PID_76_EN_ADAP_ENABLE << AW87XXX_PID_76_EN_ADAP_START_BIT) -+ -+#define AW87XXX_PID_76_EN_ADAP_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_EN_ADAP_DEFAULT \ -+ (AW87XXX_PID_76_EN_ADAP_DEFAULT_VALUE << AW87XXX_PID_76_EN_ADAP_START_BIT) -+ -+/* EN_2X bit 3 (MDCTRL 0x02) */ -+#define AW87XXX_PID_76_EN_2X_START_BIT (3) -+#define AW87XXX_PID_76_EN_2X_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_2X_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_2X_BITS_LEN)-1) << AW87XXX_PID_76_EN_2X_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_2X_DISABLE (0) -+#define AW87XXX_PID_76_EN_2X_DISABLE_VALUE \ -+ (AW87XXX_PID_76_EN_2X_DISABLE << AW87XXX_PID_76_EN_2X_START_BIT) -+ -+#define AW87XXX_PID_76_EN_2X_ENABLE (1) -+#define AW87XXX_PID_76_EN_2X_ENABLE_VALUE \ -+ (AW87XXX_PID_76_EN_2X_ENABLE << AW87XXX_PID_76_EN_2X_START_BIT) -+ -+#define AW87XXX_PID_76_EN_2X_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_EN_2X_DEFAULT \ -+ (AW87XXX_PID_76_EN_2X_DEFAULT_VALUE << AW87XXX_PID_76_EN_2X_START_BIT) -+ -+/* EN_SPK bit 2 (MDCTRL 0x02) */ -+#define AW87XXX_PID_76_EN_SPK_START_BIT (2) -+#define AW87XXX_PID_76_EN_SPK_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_SPK_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_SPK_BITS_LEN)-1) << AW87XXX_PID_76_EN_SPK_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_SPK_DISABLE (0) -+#define AW87XXX_PID_76_EN_SPK_DISABLE_VALUE \ -+ (AW87XXX_PID_76_EN_SPK_DISABLE << AW87XXX_PID_76_EN_SPK_START_BIT) -+ -+#define AW87XXX_PID_76_EN_SPK_ENABLE (1) -+#define AW87XXX_PID_76_EN_SPK_ENABLE_VALUE \ -+ (AW87XXX_PID_76_EN_SPK_ENABLE << AW87XXX_PID_76_EN_SPK_START_BIT) -+ -+#define AW87XXX_PID_76_EN_SPK_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_EN_SPK_DEFAULT \ -+ (AW87XXX_PID_76_EN_SPK_DEFAULT_VALUE << AW87XXX_PID_76_EN_SPK_START_BIT) -+ -+/* EN_LG bit 1 (MDCTRL 0x02) */ -+#define AW87XXX_PID_76_EN_LG_START_BIT (1) -+#define AW87XXX_PID_76_EN_LG_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_LG_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_LG_BITS_LEN)-1) << AW87XXX_PID_76_EN_LG_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_LG_DISABLE (0) -+#define AW87XXX_PID_76_EN_LG_DISABLE_VALUE \ -+ (AW87XXX_PID_76_EN_LG_DISABLE << AW87XXX_PID_76_EN_LG_START_BIT) -+ -+#define AW87XXX_PID_76_EN_LG_ENABLE (1) -+#define AW87XXX_PID_76_EN_LG_ENABLE_VALUE \ -+ (AW87XXX_PID_76_EN_LG_ENABLE << AW87XXX_PID_76_EN_LG_START_BIT) -+ -+#define AW87XXX_PID_76_EN_LG_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_EN_LG_DEFAULT \ -+ (AW87XXX_PID_76_EN_LG_DEFAULT_VALUE << AW87XXX_PID_76_EN_LG_START_BIT) -+ -+/* EN_AB bit 0 (MDCTRL 0x02) */ -+#define AW87XXX_PID_76_EN_AB_START_BIT (0) -+#define AW87XXX_PID_76_EN_AB_BITS_LEN (1) -+#define AW87XXX_PID_76_EN_AB_MASK \ -+ (~(((1<<AW87XXX_PID_76_EN_AB_BITS_LEN)-1) << AW87XXX_PID_76_EN_AB_START_BIT)) -+ -+#define AW87XXX_PID_76_EN_AB_DISABLE (0) -+#define AW87XXX_PID_76_EN_AB_DISABLE_VALUE \ -+ (AW87XXX_PID_76_EN_AB_DISABLE << AW87XXX_PID_76_EN_AB_START_BIT) -+ -+#define AW87XXX_PID_76_EN_AB_ENABLE (1) -+#define AW87XXX_PID_76_EN_AB_ENABLE_VALUE \ -+ (AW87XXX_PID_76_EN_AB_ENABLE << AW87XXX_PID_76_EN_AB_START_BIT) -+ -+#define AW87XXX_PID_76_EN_AB_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_EN_AB_DEFAULT \ -+ (AW87XXX_PID_76_EN_AB_DEFAULT_VALUE << AW87XXX_PID_76_EN_AB_START_BIT) -+ -+/* default value of MDCTRL (0x02) */ -+/* #define AW87XXX_PID_76_MDCTRL_DEFAULT (0x0C) */ -+ -+/* CPOVP (0x03) detail */ -+/* CP_OVP1 bit 3:0 (CPOVP 0x03) */ -+#define AW87XXX_PID_76_CP_OVP1_START_BIT (0) -+#define AW87XXX_PID_76_CP_OVP1_BITS_LEN (4) -+#define AW87XXX_PID_76_CP_OVP1_MASK \ -+ (~(((1<<AW87XXX_PID_76_CP_OVP1_BITS_LEN)-1) << AW87XXX_PID_76_CP_OVP1_START_BIT)) -+ -+#define AW87XXX_PID_76_CP_OVP1_6P0V (0) -+#define AW87XXX_PID_76_CP_OVP1_6P0V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_6P0V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_6P25V (1) -+#define AW87XXX_PID_76_CP_OVP1_6P25V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_6P25V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_6P5V (2) -+#define AW87XXX_PID_76_CP_OVP1_6P5V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_6P5V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_6P75V (3) -+#define AW87XXX_PID_76_CP_OVP1_6P75V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_6P75V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_7V (4) -+#define AW87XXX_PID_76_CP_OVP1_7V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_7V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_7P25V (5) -+#define AW87XXX_PID_76_CP_OVP1_7P25V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_7P25V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_7P5V (6) -+#define AW87XXX_PID_76_CP_OVP1_7P5V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_7P5V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_7P75V (7) -+#define AW87XXX_PID_76_CP_OVP1_7P75V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_7P75V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_8V (8) -+#define AW87XXX_PID_76_CP_OVP1_8V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_8V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_8P25V (9) -+#define AW87XXX_PID_76_CP_OVP1_8P25V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_8P25V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_8P5V (10) -+#define AW87XXX_PID_76_CP_OVP1_8P5V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_8P5V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_8P75V (11) -+#define AW87XXX_PID_76_CP_OVP1_8P75V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_8P75V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_9V (12) -+#define AW87XXX_PID_76_CP_OVP1_9V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_9V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_9P25V (13) -+#define AW87XXX_PID_76_CP_OVP1_9P25V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_9P25V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_9P5V (14) -+#define AW87XXX_PID_76_CP_OVP1_9P5V_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_9P5V << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_RESERVEDP_IF_SET_TURNS_TO_DEFAULTP (15) -+#define AW87XXX_PID_76_CP_OVP1_RESERVEDP_IF_SET_TURNS_TO_DEFAULTP_VALUE \ -+ (AW87XXX_PID_76_CP_OVP1_RESERVEDP_IF_SET_TURNS_TO_DEFAULTP << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+#define AW87XXX_PID_76_CP_OVP1_DEFAULT_VALUE (8) -+#define AW87XXX_PID_76_CP_OVP1_DEFAULT \ -+ (AW87XXX_PID_76_CP_OVP1_DEFAULT_VALUE << AW87XXX_PID_76_CP_OVP1_START_BIT) -+ -+/* default value of CPOVP (0x03) */ -+/* #define AW87XXX_PID_76_CPOVP_DEFAULT (0x08) */ -+ -+/* CPP (0x04) detail */ -+/* CP_PEAK_CUR bit 4:2 (CPP 0x04) */ -+#define AW87XXX_PID_76_CP_PEAK_CUR_START_BIT (2) -+#define AW87XXX_PID_76_CP_PEAK_CUR_BITS_LEN (3) -+#define AW87XXX_PID_76_CP_PEAK_CUR_MASK \ -+ (~(((1<<AW87XXX_PID_76_CP_PEAK_CUR_BITS_LEN)-1) << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT)) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_2A (0) -+#define AW87XXX_PID_76_CP_PEAK_CUR_2A_VALUE \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_2A << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_2P5A (1) -+#define AW87XXX_PID_76_CP_PEAK_CUR_2P5A_VALUE \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_2P5A << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_3A (2) -+#define AW87XXX_PID_76_CP_PEAK_CUR_3A_VALUE \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_3A << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_3P5A (3) -+#define AW87XXX_PID_76_CP_PEAK_CUR_3P5A_VALUE \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_3P5A << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_4A (4) -+#define AW87XXX_PID_76_CP_PEAK_CUR_4A_VALUE \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_4A << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_PEAK_CUR_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_CP_PEAK_CUR_DEFAULT \ -+ (AW87XXX_PID_76_CP_PEAK_CUR_DEFAULT_VALUE << AW87XXX_PID_76_CP_PEAK_CUR_START_BIT) -+ -+/* CP_SOFT_CUR bit 1:0 (CPP 0x04) */ -+#define AW87XXX_PID_76_CP_SOFT_CUR_START_BIT (0) -+#define AW87XXX_PID_76_CP_SOFT_CUR_BITS_LEN (2) -+#define AW87XXX_PID_76_CP_SOFT_CUR_MASK \ -+ (~(((1<<AW87XXX_PID_76_CP_SOFT_CUR_BITS_LEN)-1) << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT)) -+ -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P2A (0) -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P2A_VALUE \ -+ (AW87XXX_PID_76_CP_SOFT_CUR_0P2A << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P3A (1) -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P3A_VALUE \ -+ (AW87XXX_PID_76_CP_SOFT_CUR_0P3A << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P4A (2) -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P4A_VALUE \ -+ (AW87XXX_PID_76_CP_SOFT_CUR_0P4A << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P5A (3) -+#define AW87XXX_PID_76_CP_SOFT_CUR_0P5A_VALUE \ -+ (AW87XXX_PID_76_CP_SOFT_CUR_0P5A << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SOFT_CUR_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_CP_SOFT_CUR_DEFAULT \ -+ (AW87XXX_PID_76_CP_SOFT_CUR_DEFAULT_VALUE << AW87XXX_PID_76_CP_SOFT_CUR_START_BIT) -+ -+/* default value of CPP (0x04) */ -+/* #define AW87XXX_PID_76_CPP_DEFAULT (0x05) */ -+ -+/* PAG (0x05) detail */ -+/* GAIN bit 4:0 (PAG 0x05) */ -+#define AW87XXX_PID_76_GAIN_START_BIT (0) -+#define AW87XXX_PID_76_GAIN_BITS_LEN (5) -+#define AW87XXX_PID_76_GAIN_MASK \ -+ (~(((1<<AW87XXX_PID_76_GAIN_BITS_LEN)-1) << AW87XXX_PID_76_GAIN_START_BIT)) -+ -+#define AW87XXX_PID_76_GAIN_0DB (0) -+#define AW87XXX_PID_76_GAIN_0DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_0DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_1P5DB (1) -+#define AW87XXX_PID_76_GAIN_1P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_1P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_3DB (2) -+#define AW87XXX_PID_76_GAIN_3DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_3DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_4P5DB (3) -+#define AW87XXX_PID_76_GAIN_4P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_4P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_6DB (4) -+#define AW87XXX_PID_76_GAIN_6DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_6DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_7P5DB (5) -+#define AW87XXX_PID_76_GAIN_7P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_7P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_9DB (6) -+#define AW87XXX_PID_76_GAIN_9DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_9DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_10P5DB (7) -+#define AW87XXX_PID_76_GAIN_10P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_10P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_12DB (8) -+#define AW87XXX_PID_76_GAIN_12DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_12DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_13P5DB (9) -+#define AW87XXX_PID_76_GAIN_13P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_13P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_15DB (10) -+#define AW87XXX_PID_76_GAIN_15DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_15DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_16P5DB (11) -+#define AW87XXX_PID_76_GAIN_16P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_16P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_18DB (12) -+#define AW87XXX_PID_76_GAIN_18DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_18DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_19P5DB (13) -+#define AW87XXX_PID_76_GAIN_19P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_19P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_21DB (14) -+#define AW87XXX_PID_76_GAIN_21DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_21DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_22P5DB (15) -+#define AW87XXX_PID_76_GAIN_22P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_22P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_24DB (16) -+#define AW87XXX_PID_76_GAIN_24DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_24DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_25P5DB (17) -+#define AW87XXX_PID_76_GAIN_25P5DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_25P5DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_27DB (18) -+#define AW87XXX_PID_76_GAIN_27DB_VALUE \ -+ (AW87XXX_PID_76_GAIN_27DB << AW87XXX_PID_76_GAIN_START_BIT) -+ -+#define AW87XXX_PID_76_GAIN_DEFAULT_VALUE (12) -+#define AW87XXX_PID_76_GAIN_DEFAULT \ -+ (AW87XXX_PID_76_GAIN_DEFAULT_VALUE << AW87XXX_PID_76_GAIN_START_BIT) -+ -+/* default value of PAG (0x05) */ -+/* #define AW87XXX_PID_76_PAG_DEFAULT (0x0C) */ -+ -+/* AGC3P (0x06) detail */ -+/* AGC3PO bit 3:0 (AGC3P 0x06) */ -+#define AW87XXX_PID_76_AGC3PO_START_BIT (0) -+#define AW87XXX_PID_76_AGC3PO_BITS_LEN (4) -+#define AW87XXX_PID_76_AGC3PO_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC3PO_BITS_LEN)-1) << AW87XXX_PID_76_AGC3PO_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC3PO_0P2W4 (0) -+#define AW87XXX_PID_76_AGC3PO_0P2W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_0P2W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_0P4W4 (1) -+#define AW87XXX_PID_76_AGC3PO_0P4W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_0P4W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_0P6W4 (2) -+#define AW87XXX_PID_76_AGC3PO_0P6W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_0P6W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_0P8W4 (3) -+#define AW87XXX_PID_76_AGC3PO_0P8W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_0P8W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_1P0W4 (4) -+#define AW87XXX_PID_76_AGC3PO_1P0W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_1P0W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_1P2W4 (5) -+#define AW87XXX_PID_76_AGC3PO_1P2W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_1P2W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_1P4W4 (6) -+#define AW87XXX_PID_76_AGC3PO_1P4W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_1P4W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_1P6W4 (7) -+#define AW87XXX_PID_76_AGC3PO_1P6W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_1P6W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_1P8W4 (8) -+#define AW87XXX_PID_76_AGC3PO_1P8W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_1P8W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_2P0W4 (9) -+#define AW87XXX_PID_76_AGC3PO_2P0W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_2P0W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_2P2W4 (10) -+#define AW87XXX_PID_76_AGC3PO_2P2W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_2P2W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_2P4W4 (11) -+#define AW87XXX_PID_76_AGC3PO_2P4W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_2P4W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_2P6W4 (12) -+#define AW87XXX_PID_76_AGC3PO_2P6W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_2P6W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_2P8W4 (13) -+#define AW87XXX_PID_76_AGC3PO_2P8W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_2P8W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_3P0W4 (14) -+#define AW87XXX_PID_76_AGC3PO_3P0W4_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_3P0W4 << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_AGC3_OFF (15) -+#define AW87XXX_PID_76_AGC3PO_AGC3_OFF_VALUE \ -+ (AW87XXX_PID_76_AGC3PO_AGC3_OFF << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3PO_DEFAULT_VALUE (7) -+#define AW87XXX_PID_76_AGC3PO_DEFAULT \ -+ (AW87XXX_PID_76_AGC3PO_DEFAULT_VALUE << AW87XXX_PID_76_AGC3PO_START_BIT) -+ -+/* default value of AGC3P (0x06) */ -+/* #define AW87XXX_PID_76_AGC3P_DEFAULT (0x07) */ -+ -+/* AGC3PA (0x07) detail */ -+/* AGC3RT bit 7:5 (AGC3PA 0x07) */ -+#define AW87XXX_PID_76_AGC3RT_START_BIT (5) -+#define AW87XXX_PID_76_AGC3RT_BITS_LEN (3) -+#define AW87XXX_PID_76_AGC3RT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC3RT_BITS_LEN)-1) << AW87XXX_PID_76_AGC3RT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC3RT_5P12MSDB (0) -+#define AW87XXX_PID_76_AGC3RT_5P12MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_5P12MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_10P24MSDB (1) -+#define AW87XXX_PID_76_AGC3RT_10P24MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_10P24MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_20P48MSDB (2) -+#define AW87XXX_PID_76_AGC3RT_20P48MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_20P48MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_41MSDB (3) -+#define AW87XXX_PID_76_AGC3RT_41MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_41MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_82MSDB (4) -+#define AW87XXX_PID_76_AGC3RT_82MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_82MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_164MSDB (5) -+#define AW87XXX_PID_76_AGC3RT_164MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_164MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_328MSDB (6) -+#define AW87XXX_PID_76_AGC3RT_328MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_328MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_656MSDB (7) -+#define AW87XXX_PID_76_AGC3RT_656MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3RT_656MSDB << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3RT_DEFAULT_VALUE (2) -+#define AW87XXX_PID_76_AGC3RT_DEFAULT \ -+ (AW87XXX_PID_76_AGC3RT_DEFAULT_VALUE << AW87XXX_PID_76_AGC3RT_START_BIT) -+ -+/* AGC3AT bit 4:2 (AGC3PA 0x07) */ -+#define AW87XXX_PID_76_AGC3AT_START_BIT (2) -+#define AW87XXX_PID_76_AGC3AT_BITS_LEN (3) -+#define AW87XXX_PID_76_AGC3AT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC3AT_BITS_LEN)-1) << AW87XXX_PID_76_AGC3AT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC3AT_1P28MSDB (0) -+#define AW87XXX_PID_76_AGC3AT_1P28MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_1P28MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_2P56MSDB (1) -+#define AW87XXX_PID_76_AGC3AT_2P56MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_2P56MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_10P24MSDB (2) -+#define AW87XXX_PID_76_AGC3AT_10P24MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_10P24MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_41MSDB (3) -+#define AW87XXX_PID_76_AGC3AT_41MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_41MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_82MSDB (4) -+#define AW87XXX_PID_76_AGC3AT_82MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_82MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_164MSDB (5) -+#define AW87XXX_PID_76_AGC3AT_164MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_164MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_328MSDB (6) -+#define AW87XXX_PID_76_AGC3AT_328MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_328MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_656MSDB (7) -+#define AW87XXX_PID_76_AGC3AT_656MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3AT_656MSDB << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3AT_DEFAULT_VALUE (3) -+#define AW87XXX_PID_76_AGC3AT_DEFAULT \ -+ (AW87XXX_PID_76_AGC3AT_DEFAULT_VALUE << AW87XXX_PID_76_AGC3AT_START_BIT) -+ -+/* AGC3FSAT bit 1:0 (AGC3PA 0x07) */ -+#define AW87XXX_PID_76_AGC3FSAT_START_BIT (0) -+#define AW87XXX_PID_76_AGC3FSAT_BITS_LEN (2) -+#define AW87XXX_PID_76_AGC3FSAT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC3FSAT_BITS_LEN)-1) << AW87XXX_PID_76_AGC3FSAT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC3FSAT_10P24MSDB (0) -+#define AW87XXX_PID_76_AGC3FSAT_10P24MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3FSAT_10P24MSDB << AW87XXX_PID_76_AGC3FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3FSAT_20P48MSDB (1) -+#define AW87XXX_PID_76_AGC3FSAT_20P48MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3FSAT_20P48MSDB << AW87XXX_PID_76_AGC3FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3FSAT_41MSDB (2) -+#define AW87XXX_PID_76_AGC3FSAT_41MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3FSAT_41MSDB << AW87XXX_PID_76_AGC3FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3FSAT_82MSDB (3) -+#define AW87XXX_PID_76_AGC3FSAT_82MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC3FSAT_82MSDB << AW87XXX_PID_76_AGC3FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC3FSAT_DEFAULT_VALUE (2) -+#define AW87XXX_PID_76_AGC3FSAT_DEFAULT \ -+ (AW87XXX_PID_76_AGC3FSAT_DEFAULT_VALUE << AW87XXX_PID_76_AGC3FSAT_START_BIT) -+ -+/* default value of AGC3PA (0x07) */ -+/* #define AW87XXX_PID_76_AGC3PA_DEFAULT (0x4E) */ -+ -+/* AGC2P (0x08) detail */ -+/* AGC2PO bit 3:0 (AGC2P 0x08) */ -+#define AW87XXX_PID_76_AGC2PO_START_BIT (0) -+#define AW87XXX_PID_76_AGC2PO_BITS_LEN (4) -+#define AW87XXX_PID_76_AGC2PO_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC2PO_BITS_LEN)-1) << AW87XXX_PID_76_AGC2PO_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC2PO_0P8W4 (0) -+#define AW87XXX_PID_76_AGC2PO_0P8W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_0P8W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_1P2W4 (1) -+#define AW87XXX_PID_76_AGC2PO_1P2W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_1P2W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_1P6W4 (2) -+#define AW87XXX_PID_76_AGC2PO_1P6W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_1P6W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_2P0W4 (3) -+#define AW87XXX_PID_76_AGC2PO_2P0W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_2P0W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_2P4W4 (4) -+#define AW87XXX_PID_76_AGC2PO_2P4W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_2P4W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_2P8W4 (5) -+#define AW87XXX_PID_76_AGC2PO_2P8W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_2P8W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_3P2W4 (6) -+#define AW87XXX_PID_76_AGC2PO_3P2W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_3P2W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_3P6W4 (7) -+#define AW87XXX_PID_76_AGC2PO_3P6W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_3P6W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_4P0W4 (8) -+#define AW87XXX_PID_76_AGC2PO_4P0W4_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_4P0W4 << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_AGC2_OFF (9) -+#define AW87XXX_PID_76_AGC2PO_AGC2_OFF_VALUE \ -+ (AW87XXX_PID_76_AGC2PO_AGC2_OFF << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2PO_DEFAULT_VALUE (6) -+#define AW87XXX_PID_76_AGC2PO_DEFAULT \ -+ (AW87XXX_PID_76_AGC2PO_DEFAULT_VALUE << AW87XXX_PID_76_AGC2PO_START_BIT) -+ -+/* default value of AGC2P (0x08) */ -+/* #define AW87XXX_PID_76_AGC2P_DEFAULT (0x06) */ -+ -+/* AGC2PA (0x09) detail */ -+/* AGC2AT bit 4:2 (AGC2PA 0x09) */ -+#define AW87XXX_PID_76_AGC2AT_START_BIT (2) -+#define AW87XXX_PID_76_AGC2AT_BITS_LEN (3) -+#define AW87XXX_PID_76_AGC2AT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC2AT_BITS_LEN)-1) << AW87XXX_PID_76_AGC2AT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC2AT_0P16MSDB (0) -+#define AW87XXX_PID_76_AGC2AT_0P16MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_0P16MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_0P32MSDB (1) -+#define AW87XXX_PID_76_AGC2AT_0P32MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_0P32MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_0P64MSDB (2) -+#define AW87XXX_PID_76_AGC2AT_0P64MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_0P64MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_2P56MSDB (3) -+#define AW87XXX_PID_76_AGC2AT_2P56MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_2P56MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_10P24MSDB (4) -+#define AW87XXX_PID_76_AGC2AT_10P24MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_10P24MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_41MSDB (5) -+#define AW87XXX_PID_76_AGC2AT_41MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_41MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_82MSDB (6) -+#define AW87XXX_PID_76_AGC2AT_82MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_82MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_164MSDB (7) -+#define AW87XXX_PID_76_AGC2AT_164MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2AT_164MSDB << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2AT_DEFAULT_VALUE (2) -+#define AW87XXX_PID_76_AGC2AT_DEFAULT \ -+ (AW87XXX_PID_76_AGC2AT_DEFAULT_VALUE << AW87XXX_PID_76_AGC2AT_START_BIT) -+ -+/* AGC2FSAT bit 1:0 (AGC2PA 0x09) */ -+#define AW87XXX_PID_76_AGC2FSAT_START_BIT (0) -+#define AW87XXX_PID_76_AGC2FSAT_BITS_LEN (2) -+#define AW87XXX_PID_76_AGC2FSAT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC2FSAT_BITS_LEN)-1) << AW87XXX_PID_76_AGC2FSAT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC2FSAT_0P16MSDB (0) -+#define AW87XXX_PID_76_AGC2FSAT_0P16MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2FSAT_0P16MSDB << AW87XXX_PID_76_AGC2FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2FSAT_0P64MSDB (1) -+#define AW87XXX_PID_76_AGC2FSAT_0P64MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2FSAT_0P64MSDB << AW87XXX_PID_76_AGC2FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2FSAT_2P56MSDB (2) -+#define AW87XXX_PID_76_AGC2FSAT_2P56MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2FSAT_2P56MSDB << AW87XXX_PID_76_AGC2FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2FSAT_10P24MSDB (3) -+#define AW87XXX_PID_76_AGC2FSAT_10P24MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC2FSAT_10P24MSDB << AW87XXX_PID_76_AGC2FSAT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC2FSAT_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_AGC2FSAT_DEFAULT \ -+ (AW87XXX_PID_76_AGC2FSAT_DEFAULT_VALUE << AW87XXX_PID_76_AGC2FSAT_START_BIT) -+ -+/* default value of AGC2PA (0x09) */ -+/* #define AW87XXX_PID_76_AGC2PA_DEFAULT (0x08) */ -+ -+/* AGC1PA (0x0A) detail */ -+/* AGC1THVTH bit 6:3 (AGC1PA 0x0A) */ -+#define AW87XXX_PID_76_AGC1THVTH_START_BIT (3) -+#define AW87XXX_PID_76_AGC1THVTH_BITS_LEN (4) -+#define AW87XXX_PID_76_AGC1THVTH_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC1THVTH_BITS_LEN)-1) << AW87XXX_PID_76_AGC1THVTH_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC1THVTH_5V (0) -+#define AW87XXX_PID_76_AGC1THVTH_5V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_5V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_5P2V (1) -+#define AW87XXX_PID_76_AGC1THVTH_5P2V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_5P2V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_5P4V (2) -+#define AW87XXX_PID_76_AGC1THVTH_5P4V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_5P4V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_5P6V (3) -+#define AW87XXX_PID_76_AGC1THVTH_5P6V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_5P6V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_5P8V (4) -+#define AW87XXX_PID_76_AGC1THVTH_5P8V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_5P8V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_6P0V (5) -+#define AW87XXX_PID_76_AGC1THVTH_6P0V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_6P0V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_6P2V (6) -+#define AW87XXX_PID_76_AGC1THVTH_6P2V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_6P2V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_6P4V (7) -+#define AW87XXX_PID_76_AGC1THVTH_6P4V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_6P4V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_6P6V (8) -+#define AW87XXX_PID_76_AGC1THVTH_6P6V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_6P6V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_6P8V (9) -+#define AW87XXX_PID_76_AGC1THVTH_6P8V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_6P8V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_7V (10) -+#define AW87XXX_PID_76_AGC1THVTH_7V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_7V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_7P2V (11) -+#define AW87XXX_PID_76_AGC1THVTH_7P2V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_7P2V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_7P4V (12) -+#define AW87XXX_PID_76_AGC1THVTH_7P4V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_7P4V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_7P6V (13) -+#define AW87XXX_PID_76_AGC1THVTH_7P6V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_7P6V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_7P8V (14) -+#define AW87XXX_PID_76_AGC1THVTH_7P8V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_7P8V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_8V (15) -+#define AW87XXX_PID_76_AGC1THVTH_8V_VALUE \ -+ (AW87XXX_PID_76_AGC1THVTH_8V << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1THVTH_DEFAULT_VALUE (9) -+#define AW87XXX_PID_76_AGC1THVTH_DEFAULT \ -+ (AW87XXX_PID_76_AGC1THVTH_DEFAULT_VALUE << AW87XXX_PID_76_AGC1THVTH_START_BIT) -+ -+/* AGC1AT bit 2:1 (AGC1PA 0x0A) */ -+#define AW87XXX_PID_76_AGC1AT_START_BIT (1) -+#define AW87XXX_PID_76_AGC1AT_BITS_LEN (2) -+#define AW87XXX_PID_76_AGC1AT_MASK \ -+ (~(((1<<AW87XXX_PID_76_AGC1AT_BITS_LEN)-1) << AW87XXX_PID_76_AGC1AT_START_BIT)) -+ -+#define AW87XXX_PID_76_AGC1AT_0P04MSDB (0) -+#define AW87XXX_PID_76_AGC1AT_0P04MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC1AT_0P04MSDB << AW87XXX_PID_76_AGC1AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1AT_0P08MSDB (1) -+#define AW87XXX_PID_76_AGC1AT_0P08MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC1AT_0P08MSDB << AW87XXX_PID_76_AGC1AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1AT_0P16MSDB (2) -+#define AW87XXX_PID_76_AGC1AT_0P16MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC1AT_0P16MSDB << AW87XXX_PID_76_AGC1AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1AT_0P32MSDB (3) -+#define AW87XXX_PID_76_AGC1AT_0P32MSDB_VALUE \ -+ (AW87XXX_PID_76_AGC1AT_0P32MSDB << AW87XXX_PID_76_AGC1AT_START_BIT) -+ -+#define AW87XXX_PID_76_AGC1AT_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_AGC1AT_DEFAULT \ -+ (AW87XXX_PID_76_AGC1AT_DEFAULT_VALUE << AW87XXX_PID_76_AGC1AT_START_BIT) -+ -+/* PD_AGC1 bit 0 (AGC1PA 0x0A) */ -+#define AW87XXX_PID_76_PD_AGC1_START_BIT (0) -+#define AW87XXX_PID_76_PD_AGC1_BITS_LEN (1) -+#define AW87XXX_PID_76_PD_AGC1_MASK \ -+ (~(((1<<AW87XXX_PID_76_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_76_PD_AGC1_START_BIT)) -+ -+#define AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_UP (0) -+#define AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_UP_VALUE \ -+ (AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_UP << AW87XXX_PID_76_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_DOWN (1) -+#define AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_DOWN_VALUE \ -+ (AW87XXX_PID_76_PD_AGC1_AGC1_FUNCTION_POWERMINUS_DOWN << AW87XXX_PID_76_PD_AGC1_START_BIT) -+ -+#define AW87XXX_PID_76_PD_AGC1_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_PD_AGC1_DEFAULT \ -+ (AW87XXX_PID_76_PD_AGC1_DEFAULT_VALUE << AW87XXX_PID_76_PD_AGC1_START_BIT) -+ -+/* default value of AGC1PA (0x0A) */ -+/* #define AW87XXX_PID_76_AGC1PA_DEFAULT (0x4A) */ -+ -+/* SYSST (0x59) detail */ -+/* UVLOS bit 7 (SYSST 0x59) */ -+#define AW87XXX_PID_76_UVLOS_START_BIT (7) -+#define AW87XXX_PID_76_UVLOS_BITS_LEN (1) -+#define AW87XXX_PID_76_UVLOS_MASK \ -+ (~(((1<<AW87XXX_PID_76_UVLOS_BITS_LEN)-1) << AW87XXX_PID_76_UVLOS_START_BIT)) -+ -+#define AW87XXX_PID_76_UVLOS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_76_UVLOS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_UVLOS_NORMAL_OPERATION << AW87XXX_PID_76_UVLOS_START_BIT) -+ -+#define AW87XXX_PID_76_UVLOS_VBAT_UNDER_VOLTAGE (1) -+#define AW87XXX_PID_76_UVLOS_VBAT_UNDER_VOLTAGE_VALUE \ -+ (AW87XXX_PID_76_UVLOS_VBAT_UNDER_VOLTAGE << AW87XXX_PID_76_UVLOS_START_BIT) -+ -+#define AW87XXX_PID_76_UVLOS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_UVLOS_DEFAULT \ -+ (AW87XXX_PID_76_UVLOS_DEFAULT_VALUE << AW87XXX_PID_76_UVLOS_START_BIT) -+ -+/* OTNS bit 6 (SYSST 0x59) */ -+#define AW87XXX_PID_76_OTNS_START_BIT (6) -+#define AW87XXX_PID_76_OTNS_BITS_LEN (1) -+#define AW87XXX_PID_76_OTNS_MASK \ -+ (~(((1<<AW87XXX_PID_76_OTNS_BITS_LEN)-1) << AW87XXX_PID_76_OTNS_START_BIT)) -+ -+#define AW87XXX_PID_76_OTNS_DETECTED (0) -+#define AW87XXX_PID_76_OTNS_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OTNS_DETECTED << AW87XXX_PID_76_OTNS_START_BIT) -+ -+#define AW87XXX_PID_76_OTNS_NORMAL_OPERATION (1) -+#define AW87XXX_PID_76_OTNS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_OTNS_NORMAL_OPERATION << AW87XXX_PID_76_OTNS_START_BIT) -+ -+#define AW87XXX_PID_76_OTNS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_OTNS_DEFAULT \ -+ (AW87XXX_PID_76_OTNS_DEFAULT_VALUE << AW87XXX_PID_76_OTNS_START_BIT) -+ -+/* OC_FLAGS bit 5 (SYSST 0x59) */ -+#define AW87XXX_PID_76_OC_FLAGS_START_BIT (5) -+#define AW87XXX_PID_76_OC_FLAGS_BITS_LEN (1) -+#define AW87XXX_PID_76_OC_FLAGS_MASK \ -+ (~(((1<<AW87XXX_PID_76_OC_FLAGS_BITS_LEN)-1) << AW87XXX_PID_76_OC_FLAGS_START_BIT)) -+ -+#define AW87XXX_PID_76_OC_FLAGS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_76_OC_FLAGS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_OC_FLAGS_NORMAL_OPERATION << AW87XXX_PID_76_OC_FLAGS_START_BIT) -+ -+#define AW87XXX_PID_76_OC_FLAGS_DETECTED (1) -+#define AW87XXX_PID_76_OC_FLAGS_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OC_FLAGS_DETECTED << AW87XXX_PID_76_OC_FLAGS_START_BIT) -+ -+#define AW87XXX_PID_76_OC_FLAGS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_OC_FLAGS_DEFAULT \ -+ (AW87XXX_PID_76_OC_FLAGS_DEFAULT_VALUE << AW87XXX_PID_76_OC_FLAGS_START_BIT) -+ -+/* ADAP_CPS bit 4 (SYSST 0x59) */ -+#define AW87XXX_PID_76_ADAP_CPS_START_BIT (4) -+#define AW87XXX_PID_76_ADAP_CPS_BITS_LEN (1) -+#define AW87XXX_PID_76_ADAP_CPS_MASK \ -+ (~(((1<<AW87XXX_PID_76_ADAP_CPS_BITS_LEN)-1) << AW87XXX_PID_76_ADAP_CPS_START_BIT)) -+ -+#define AW87XXX_PID_76_ADAP_CPS_1X_MODE (0) -+#define AW87XXX_PID_76_ADAP_CPS_1X_MODE_VALUE \ -+ (AW87XXX_PID_76_ADAP_CPS_1X_MODE << AW87XXX_PID_76_ADAP_CPS_START_BIT) -+ -+#define AW87XXX_PID_76_ADAP_CPS_2X_MODE (1) -+#define AW87XXX_PID_76_ADAP_CPS_2X_MODE_VALUE \ -+ (AW87XXX_PID_76_ADAP_CPS_2X_MODE << AW87XXX_PID_76_ADAP_CPS_START_BIT) -+ -+#define AW87XXX_PID_76_ADAP_CPS_DEFAULT_VALUE (1) -+#define AW87XXX_PID_76_ADAP_CPS_DEFAULT \ -+ (AW87XXX_PID_76_ADAP_CPS_DEFAULT_VALUE << AW87XXX_PID_76_ADAP_CPS_START_BIT) -+ -+/* STARTOKS bit 3 (SYSST 0x59) */ -+#define AW87XXX_PID_76_STARTOKS_START_BIT (3) -+#define AW87XXX_PID_76_STARTOKS_BITS_LEN (1) -+#define AW87XXX_PID_76_STARTOKS_MASK \ -+ (~(((1<<AW87XXX_PID_76_STARTOKS_BITS_LEN)-1) << AW87XXX_PID_76_STARTOKS_START_BIT)) -+ -+#define AW87XXX_PID_76_STARTOKS_CP_START_FAIL_DECTECTED (0) -+#define AW87XXX_PID_76_STARTOKS_CP_START_FAIL_DECTECTED_VALUE \ -+ (AW87XXX_PID_76_STARTOKS_CP_START_FAIL_DECTECTED << AW87XXX_PID_76_STARTOKS_START_BIT) -+ -+#define AW87XXX_PID_76_STARTOKS_NORMAL_OPERATION (1) -+#define AW87XXX_PID_76_STARTOKS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_STARTOKS_NORMAL_OPERATION << AW87XXX_PID_76_STARTOKS_START_BIT) -+ -+#define AW87XXX_PID_76_STARTOKS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_STARTOKS_DEFAULT \ -+ (AW87XXX_PID_76_STARTOKS_DEFAULT_VALUE << AW87XXX_PID_76_STARTOKS_START_BIT) -+ -+/* OVP1S bit 2 (SYSST 0x59) */ -+#define AW87XXX_PID_76_OVP1S_START_BIT (2) -+#define AW87XXX_PID_76_OVP1S_BITS_LEN (1) -+#define AW87XXX_PID_76_OVP1S_MASK \ -+ (~(((1<<AW87XXX_PID_76_OVP1S_BITS_LEN)-1) << AW87XXX_PID_76_OVP1S_START_BIT)) -+ -+#define AW87XXX_PID_76_OVP1S_NORMAL_OPERATION (0) -+#define AW87XXX_PID_76_OVP1S_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_OVP1S_NORMAL_OPERATION << AW87XXX_PID_76_OVP1S_START_BIT) -+ -+#define AW87XXX_PID_76_OVP1S_CP_OVP_DETECTED (1) -+#define AW87XXX_PID_76_OVP1S_CP_OVP_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OVP1S_CP_OVP_DETECTED << AW87XXX_PID_76_OVP1S_START_BIT) -+ -+#define AW87XXX_PID_76_OVP1S_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_OVP1S_DEFAULT \ -+ (AW87XXX_PID_76_OVP1S_DEFAULT_VALUE << AW87XXX_PID_76_OVP1S_START_BIT) -+ -+/* PORNS bit 1 (SYSST 0x59) */ -+#define AW87XXX_PID_76_PORNS_START_BIT (1) -+#define AW87XXX_PID_76_PORNS_BITS_LEN (1) -+#define AW87XXX_PID_76_PORNS_MASK \ -+ (~(((1<<AW87XXX_PID_76_PORNS_BITS_LEN)-1) << AW87XXX_PID_76_PORNS_START_BIT)) -+ -+#define AW87XXX_PID_76_PORNS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_PORNS_DEFAULT \ -+ (AW87XXX_PID_76_PORNS_DEFAULT_VALUE << AW87XXX_PID_76_PORNS_START_BIT) -+ -+/* CP_SHORTS bit 0 (SYSST 0x59) */ -+#define AW87XXX_PID_76_CP_SHORTS_START_BIT (0) -+#define AW87XXX_PID_76_CP_SHORTS_BITS_LEN (1) -+#define AW87XXX_PID_76_CP_SHORTS_MASK \ -+ (~(((1<<AW87XXX_PID_76_CP_SHORTS_BITS_LEN)-1) << AW87XXX_PID_76_CP_SHORTS_START_BIT)) -+ -+#define AW87XXX_PID_76_CP_SHORTS_NORMAL_OPERATION (0) -+#define AW87XXX_PID_76_CP_SHORTS_NORMAL_OPERATION_VALUE \ -+ (AW87XXX_PID_76_CP_SHORTS_NORMAL_OPERATION << AW87XXX_PID_76_CP_SHORTS_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SHORTS_CHARGE_PUMP_SHORT_DECTECTED (1) -+#define AW87XXX_PID_76_CP_SHORTS_CHARGE_PUMP_SHORT_DECTECTED_VALUE \ -+ (AW87XXX_PID_76_CP_SHORTS_CHARGE_PUMP_SHORT_DECTECTED << AW87XXX_PID_76_CP_SHORTS_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SHORTS_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_CP_SHORTS_DEFAULT \ -+ (AW87XXX_PID_76_CP_SHORTS_DEFAULT_VALUE << AW87XXX_PID_76_CP_SHORTS_START_BIT) -+ -+/* default value of SYSST (0x59) */ -+/* #define AW87XXX_PID_76_SYSST_DEFAULT (0xD0) */ -+ -+/* SYSINT (0x60) detail */ -+/* UVLOI bit 7 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_UVLOI_START_BIT (7) -+#define AW87XXX_PID_76_UVLOI_BITS_LEN (1) -+#define AW87XXX_PID_76_UVLOI_MASK \ -+ (~(((1<<AW87XXX_PID_76_UVLOI_BITS_LEN)-1) << AW87XXX_PID_76_UVLOI_START_BIT)) -+ -+#define AW87XXX_PID_76_UVLOI_NOT_CHANGE (0) -+#define AW87XXX_PID_76_UVLOI_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_UVLOI_NOT_CHANGE << AW87XXX_PID_76_UVLOI_START_BIT) -+ -+#define AW87XXX_PID_76_UVLOI_DETECTED (1) -+#define AW87XXX_PID_76_UVLOI_DETECTED_VALUE \ -+ (AW87XXX_PID_76_UVLOI_DETECTED << AW87XXX_PID_76_UVLOI_START_BIT) -+ -+#define AW87XXX_PID_76_UVLOI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_UVLOI_DEFAULT \ -+ (AW87XXX_PID_76_UVLOI_DEFAULT_VALUE << AW87XXX_PID_76_UVLOI_START_BIT) -+ -+/* OTNI bit 6 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_OTNI_START_BIT (6) -+#define AW87XXX_PID_76_OTNI_BITS_LEN (1) -+#define AW87XXX_PID_76_OTNI_MASK \ -+ (~(((1<<AW87XXX_PID_76_OTNI_BITS_LEN)-1) << AW87XXX_PID_76_OTNI_START_BIT)) -+ -+#define AW87XXX_PID_76_OTNI_NOT_CHANGE (0) -+#define AW87XXX_PID_76_OTNI_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_OTNI_NOT_CHANGE << AW87XXX_PID_76_OTNI_START_BIT) -+ -+#define AW87XXX_PID_76_OTNI_DETECTED (1) -+#define AW87XXX_PID_76_OTNI_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OTNI_DETECTED << AW87XXX_PID_76_OTNI_START_BIT) -+ -+#define AW87XXX_PID_76_OTNI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_OTNI_DEFAULT \ -+ (AW87XXX_PID_76_OTNI_DEFAULT_VALUE << AW87XXX_PID_76_OTNI_START_BIT) -+ -+/* OC_FLAGI bit 5 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_OC_FLAGI_START_BIT (5) -+#define AW87XXX_PID_76_OC_FLAGI_BITS_LEN (1) -+#define AW87XXX_PID_76_OC_FLAGI_MASK \ -+ (~(((1<<AW87XXX_PID_76_OC_FLAGI_BITS_LEN)-1) << AW87XXX_PID_76_OC_FLAGI_START_BIT)) -+ -+#define AW87XXX_PID_76_OC_FLAGI_NOT_CHANGE (0) -+#define AW87XXX_PID_76_OC_FLAGI_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_OC_FLAGI_NOT_CHANGE << AW87XXX_PID_76_OC_FLAGI_START_BIT) -+ -+#define AW87XXX_PID_76_OC_FLAGI_DETECTED (1) -+#define AW87XXX_PID_76_OC_FLAGI_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OC_FLAGI_DETECTED << AW87XXX_PID_76_OC_FLAGI_START_BIT) -+ -+#define AW87XXX_PID_76_OC_FLAGI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_OC_FLAGI_DEFAULT \ -+ (AW87XXX_PID_76_OC_FLAGI_DEFAULT_VALUE << AW87XXX_PID_76_OC_FLAGI_START_BIT) -+ -+/* ADAP_CPI bit 4 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_ADAP_CPI_START_BIT (4) -+#define AW87XXX_PID_76_ADAP_CPI_BITS_LEN (1) -+#define AW87XXX_PID_76_ADAP_CPI_MASK \ -+ (~(((1<<AW87XXX_PID_76_ADAP_CPI_BITS_LEN)-1) << AW87XXX_PID_76_ADAP_CPI_START_BIT)) -+ -+#define AW87XXX_PID_76_ADAP_CPI_1X_MODE (0) -+#define AW87XXX_PID_76_ADAP_CPI_1X_MODE_VALUE \ -+ (AW87XXX_PID_76_ADAP_CPI_1X_MODE << AW87XXX_PID_76_ADAP_CPI_START_BIT) -+ -+#define AW87XXX_PID_76_ADAP_CPI_2X_MODE (1) -+#define AW87XXX_PID_76_ADAP_CPI_2X_MODE_VALUE \ -+ (AW87XXX_PID_76_ADAP_CPI_2X_MODE << AW87XXX_PID_76_ADAP_CPI_START_BIT) -+ -+#define AW87XXX_PID_76_ADAP_CPI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_ADAP_CPI_DEFAULT \ -+ (AW87XXX_PID_76_ADAP_CPI_DEFAULT_VALUE << AW87XXX_PID_76_ADAP_CPI_START_BIT) -+ -+/* STARTOKI bit 3 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_STARTOKI_START_BIT (3) -+#define AW87XXX_PID_76_STARTOKI_BITS_LEN (1) -+#define AW87XXX_PID_76_STARTOKI_MASK \ -+ (~(((1<<AW87XXX_PID_76_STARTOKI_BITS_LEN)-1) << AW87XXX_PID_76_STARTOKI_START_BIT)) -+ -+#define AW87XXX_PID_76_STARTOKI_NOT_CHANGE (0) -+#define AW87XXX_PID_76_STARTOKI_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_STARTOKI_NOT_CHANGE << AW87XXX_PID_76_STARTOKI_START_BIT) -+ -+#define AW87XXX_PID_76_STARTOKI_DECTECTED (1) -+#define AW87XXX_PID_76_STARTOKI_DECTECTED_VALUE \ -+ (AW87XXX_PID_76_STARTOKI_DECTECTED << AW87XXX_PID_76_STARTOKI_START_BIT) -+ -+#define AW87XXX_PID_76_STARTOKI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_STARTOKI_DEFAULT \ -+ (AW87XXX_PID_76_STARTOKI_DEFAULT_VALUE << AW87XXX_PID_76_STARTOKI_START_BIT) -+ -+/* OVP1I bit 2 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_OVP1I_START_BIT (2) -+#define AW87XXX_PID_76_OVP1I_BITS_LEN (1) -+#define AW87XXX_PID_76_OVP1I_MASK \ -+ (~(((1<<AW87XXX_PID_76_OVP1I_BITS_LEN)-1) << AW87XXX_PID_76_OVP1I_START_BIT)) -+ -+#define AW87XXX_PID_76_OVP1I_NOT_CHANGE (0) -+#define AW87XXX_PID_76_OVP1I_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_OVP1I_NOT_CHANGE << AW87XXX_PID_76_OVP1I_START_BIT) -+ -+#define AW87XXX_PID_76_OVP1I_DETECTED (1) -+#define AW87XXX_PID_76_OVP1I_DETECTED_VALUE \ -+ (AW87XXX_PID_76_OVP1I_DETECTED << AW87XXX_PID_76_OVP1I_START_BIT) -+ -+#define AW87XXX_PID_76_OVP1I_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_OVP1I_DEFAULT \ -+ (AW87XXX_PID_76_OVP1I_DEFAULT_VALUE << AW87XXX_PID_76_OVP1I_START_BIT) -+ -+/* PORNI bit 1 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_PORNI_START_BIT (1) -+#define AW87XXX_PID_76_PORNI_BITS_LEN (1) -+#define AW87XXX_PID_76_PORNI_MASK \ -+ (~(((1<<AW87XXX_PID_76_PORNI_BITS_LEN)-1) << AW87XXX_PID_76_PORNI_START_BIT)) -+ -+#define AW87XXX_PID_76_PORNI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_PORNI_DEFAULT \ -+ (AW87XXX_PID_76_PORNI_DEFAULT_VALUE << AW87XXX_PID_76_PORNI_START_BIT) -+ -+/* CP_SHORTI bit 0 (SYSINT 0x60) */ -+#define AW87XXX_PID_76_CP_SHORTI_START_BIT (0) -+#define AW87XXX_PID_76_CP_SHORTI_BITS_LEN (1) -+#define AW87XXX_PID_76_CP_SHORTI_MASK \ -+ (~(((1<<AW87XXX_PID_76_CP_SHORTI_BITS_LEN)-1) << AW87XXX_PID_76_CP_SHORTI_START_BIT)) -+ -+#define AW87XXX_PID_76_CP_SHORTI_NOT_CHANGE (0) -+#define AW87XXX_PID_76_CP_SHORTI_NOT_CHANGE_VALUE \ -+ (AW87XXX_PID_76_CP_SHORTI_NOT_CHANGE << AW87XXX_PID_76_CP_SHORTI_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SHORTI_SHORT_DECTECTED (1) -+#define AW87XXX_PID_76_CP_SHORTI_SHORT_DECTECTED_VALUE \ -+ (AW87XXX_PID_76_CP_SHORTI_SHORT_DECTECTED << AW87XXX_PID_76_CP_SHORTI_START_BIT) -+ -+#define AW87XXX_PID_76_CP_SHORTI_DEFAULT_VALUE (0) -+#define AW87XXX_PID_76_CP_SHORTI_DEFAULT \ -+ (AW87XXX_PID_76_CP_SHORTI_DEFAULT_VALUE << AW87XXX_PID_76_CP_SHORTI_START_BIT) -+ -+/* default value of SYSINT (0x60) */ -+/* #define AW87XXX_PID_76_SYSINT_DEFAULT (0x00) */ -+ -+/* detail information of registers end */ -+ -+#endif /* #ifndef __AW87XXX_PID_76_REG_H__ */ -\ No newline at end of file -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h b/sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h -new file mode 100644 -index 000000000..c8d146ef5 ---- /dev/null -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h -@@ -0,0 +1,81 @@ -+#ifndef __AW87XXX_PID_9B_REG_H__ -+#define __AW87XXX_PID_9B_REG_H__ -+ -+#define AW87XXX_PID_9B_CHIPID_REG (0x00) -+#define AW87XXX_PID_9B_SYSCTRL_REG (0x01) -+#define AW87XXX_PID_9B_BATSAFE_REG (0x02) -+#define AW87XXX_PID_9B_BOV_REG (0x03) -+#define AW87XXX_PID_9B_BP_REG (0x04) -+#define AW87XXX_PID_9B_GAIN_REG (0x05) -+#define AW87XXX_PID_9B_AGC3_PO_REG (0x06) -+#define AW87XXX_PID_9B_AGC3_REG (0x07) -+#define AW87XXX_PID_9B_AGC2_REG (0x08) -+#define AW87XXX_PID_9B_AGC1_REG (0x09) -+ -+#define AW87XXX_PID_9B_SYSCTRL_DEFAULT (0x03) -+ -+/******************************************** -+ * soft control info -+ * If you need to update this file, add this information manually -+ *******************************************/ -+unsigned char aw87xxx_pid_9b_softrst_access[2] = {0x00, 0xaa}; -+ -+/******************************************** -+ * Register Access -+ *******************************************/ -+#define AW87XXX_PID_9B_REG_MAX (0x64) -+ -+#define REG_NONE_ACCESS (0) -+#define REG_RD_ACCESS (1 << 0) -+#define REG_WR_ACCESS (1 << 1) -+ -+const unsigned char aw87xxx_pid_9b_reg_access[AW87XXX_PID_9B_REG_MAX] = { -+ [AW87XXX_PID_9B_CHIPID_REG] = (REG_RD_ACCESS), -+ [AW87XXX_PID_9B_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_BATSAFE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_BOV_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_BP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_GAIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_AGC3_PO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_AGC3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_AGC2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+ [AW87XXX_PID_9B_AGC1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS), -+}; -+ -+ -+#define AW87XXX_PID_9B_ENCRYPTION_REG (0x64) -+#define AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET (0x2C) -+ -+/* REG_EN_SW bit 2 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_9B_REG_EN_SW_START_BIT (2) -+#define AW87XXX_PID_9B_REG_EN_SW_BITS_LEN (1) -+#define AW87XXX_PID_9B_REG_EN_SW_MASK \ -+ (~(((1<<AW87XXX_PID_9B_REG_EN_SW_BITS_LEN)-1) << AW87XXX_PID_9B_REG_EN_SW_START_BIT)) -+ -+#define AW87XXX_PID_9B_REG_EN_SW_DISABLE (0) -+#define AW87XXX_PID_9B_REG_EN_SW_DISABLE_VALUE \ -+ (AW87XXX_PID_9B_REG_EN_SW_DISABLE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_9B_REG_EN_SW_ENABLE (1) -+#define AW87XXX_PID_9B_REG_EN_SW_ENABLE_VALUE \ -+ (AW87XXX_PID_9B_REG_EN_SW_ENABLE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) -+ -+#define AW87XXX_PID_9B_REG_EN_SW_DEFAULT_VALUE (1) -+#define AW87XXX_PID_9B_REG_EN_SW_DEFAULT \ -+ (AW87XXX_PID_9B_REG_EN_SW_DEFAULT_VALUE << AW87XXX_PID_9B_REG_EN_SW_START_BIT) -+ -+/* SPK_MODE bit 0 (SYSCTRL 0x01) */ -+#define AW87XXX_PID_9B_SPK_MODE_START_BIT (0) -+#define AW87XXX_PID_9B_SPK_MODE_BITS_LEN (1) -+#define AW87XXX_PID_9B_SPK_MODE_MASK \ -+ (~(((1<<AW87XXX_PID_9B_SPK_MODE_BITS_LEN)-1) << AW87XXX_PID_9B_SPK_MODE_START_BIT)) -+ -+#define AW87XXX_PID_9B_SPK_MODE_DISABLE (0) -+#define AW87XXX_PID_9B_SPK_MODE_DISABLE_VALUE \ -+ (AW87XXX_PID_9B_SPK_MODE_DISABLE << AW87XXX_PID_9B_SPK_MODE_START_BIT) -+ -+#define AW87XXX_PID_9B_SPK_MODE_ENABLE (1) -+#define AW87XXX_PID_9B_SPK_MODE_ENABLE_VALUE \ -+ (AW87XXX_PID_9B_SPK_MODE_ENABLE << AW87XXX_PID_9B_SPK_MODE_START_BIT) -+ -+#endif --- -2.45.2 - - -From 79fc3fdbc30a0deaedd987b5e71e850cfc442f7d Mon Sep 17 00:00:00 2001 -From: CVMagic <546352+CVMagic@users.noreply.github.com> -Date: Thu, 16 May 2024 04:57:32 +0000 -Subject: [PATCH 2/8] Updated AW87xxx driver to be more verbose for debugging - purposes, but also fixed Reset Pin GPIO initialization issue with Ayn Loki - Mini - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/soc/codecs/aw87xxx/aw87xxx.c | 2923 +++++++++++---------- - sound/soc/codecs/aw87xxx/aw87xxx_device.c | 8 +- - 2 files changed, 1470 insertions(+), 1461 deletions(-) - -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx.c b/sound/soc/codecs/aw87xxx/aw87xxx.c -index eddb01695..7f44d9b9d 100644 ---- a/sound/soc/codecs/aw87xxx/aw87xxx.c -+++ b/sound/soc/codecs/aw87xxx/aw87xxx.c -@@ -1,1457 +1,1466 @@ --/* -- * aw87xxx.c aw87xxx pa module -- * -- * Copyright (c) 2021 AWINIC Technology CO., LTD -- * -- * Author: Barry <zhaozhongbo@awinic.com> -- * -- * This program is free software; you can redistribute it and/or modify it -- * under the terms of the GNU General Public License as published by the -- * Free Software Foundation; either version 2 of the License, or (at your -- * option) any later version. -- * -- */ -- --#include <linux/i2c.h> --#include <sound/pcm.h> --#include <sound/pcm_params.h> --#include <linux/gpio.h> --#include <linux/of_gpio.h> --#include <linux/gpio/consumer.h> --#include <linux/interrupt.h> --#include <linux/delay.h> --#include <linux/module.h> --#include <linux/kernel.h> --#include <linux/device.h> --#include <linux/irq.h> --#include <linux/firmware.h> --#include <linux/platform_device.h> --#include <linux/slab.h> --#include <linux/fs.h> --#include <linux/proc_fs.h> --#include <linux/uaccess.h> --#include <linux/io.h> --#include <linux/init.h> --#include <linux/pci.h> --#include <linux/dma-mapping.h> --#include <linux/gameport.h> --#include <linux/moduleparam.h> --#include <linux/mutex.h> --#include <linux/timer.h> --#include <linux/workqueue.h> --#include <linux/hrtimer.h> --#include <linux/ktime.h> --#include <linux/kthread.h> --#include <uapi/sound/asound.h> --#include <sound/control.h> --#include <sound/soc.h> --#include "aw87xxx.h" --#include "aw87xxx_device.h" --#include "aw87xxx_log.h" --#include "aw87xxx_monitor.h" --#include "aw87xxx_acf_bin.h" --#include "aw87xxx_bin_parse.h" --#include "aw87xxx_dsp.h" -- --/***************************************************************** --* aw87xxx marco --******************************************************************/ --#define AW87XXX_I2C_NAME "aw87xxx_pa" --#define AW87XXX_DRIVER_VERSION "v2.7.0" --#define AW87XXX_FW_BIN_NAME "aw87xxx_acf.bin" --#define AW87XXX_PROF_MUSIC "Music" --/************************************************************************* -- * aw87xxx variable -- ************************************************************************/ --static LIST_HEAD(g_aw87xxx_list); --static DEFINE_MUTEX(g_aw87xxx_mutex_lock); --unsigned int g_aw87xxx_dev_cnt = 0; -- --static const char *const aw87xxx_monitor_switch[] = {"Disable", "Enable"}; --static const char *const aw87xxx_spin_switch[] = {"spin_0", "spin_90", -- "spin_180", "spin_270"}; --#ifdef AW_KERNEL_VER_OVER_4_19_1 --static struct aw_componet_codec_ops aw_componet_codec_ops = { -- .add_codec_controls = snd_soc_add_component_controls, -- .unregister_codec = snd_soc_unregister_component, --}; --#else --static struct aw_componet_codec_ops aw_componet_codec_ops = { -- .add_codec_controls = snd_soc_add_codec_controls, -- .unregister_codec = snd_soc_unregister_codec, --}; --#endif -- -- --/************************************************************************ -- * -- * aw87xxx device update profile -- * -- ************************************************************************/ --static int aw87xxx_power_down(struct aw87xxx *aw87xxx, char *profile) --{ -- int ret = 0; -- struct aw_prof_desc *prof_desc = NULL; -- struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -- struct aw_data_container *data_container = NULL; -- struct aw_device *aw_dev = &aw87xxx->aw_dev; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- -- if (!prof_info->status) { -- AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -- return -EINVAL; -- } -- -- prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -- if (prof_desc == NULL) -- goto no_bin_pwr_off; -- -- if (!prof_desc->prof_st) -- goto no_bin_pwr_off; -- -- -- data_container = &prof_desc->data_container; -- AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -- profile, data_container->len); -- -- if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -- AW_DEV_LOGI(aw87xxx->dev, "profile[%s] has already load ", profile); -- } else { -- if (aw_dev->ops.pwr_off_func) { -- ret = aw_dev->ops.pwr_off_func(aw_dev, data_container); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -- goto pwr_off_failed; -- } -- } else { -- ret = aw87xxx_dev_default_pwr_off(aw_dev, data_container); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -- goto pwr_off_failed; -- } -- } -- } -- -- aw87xxx->current_profile = prof_desc->prof_name; -- return 0; -- --pwr_off_failed: --no_bin_pwr_off: -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -- aw87xxx->current_profile = aw87xxx->prof_off_name; -- return ret; --} -- --static int aw87xxx_power_on(struct aw87xxx *aw87xxx, char *profile) --{ -- int ret = -EINVAL; -- struct aw_prof_desc *prof_desc = NULL; -- struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -- struct aw_data_container *data_container = NULL; -- struct aw_device *aw_dev = &aw87xxx->aw_dev; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- -- if (!prof_info->status) { -- AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -- return -EINVAL; -- } -- -- if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -- return aw87xxx_power_down(aw87xxx, profile); -- -- prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -- if (prof_desc == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "not found [%s] parameter", profile); -- return -EINVAL; -- } -- -- if (!prof_desc->prof_st) { -- AW_DEV_LOGE(aw87xxx->dev, "not found data container"); -- return -EINVAL; -- } -- -- data_container = &prof_desc->data_container; -- AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -- profile, data_container->len); -- -- if (aw_dev->ops.pwr_on_func) { -- ret = aw_dev->ops.pwr_on_func(aw_dev, data_container); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -- profile); -- return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -- } -- } else { -- ret = aw87xxx_dev_default_pwr_on(aw_dev, data_container); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -- profile); -- return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -- } -- } -- -- aw87xxx->current_profile = prof_desc->prof_name; -- AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] succeed", profile); -- -- return 0; --} -- -- -- --int aw87xxx_update_profile(struct aw87xxx *aw87xxx, char *profile) --{ -- int ret = -1; -- -- AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] enter", profile); -- mutex_lock(&aw87xxx->reg_lock); -- aw87xxx_monitor_stop(&aw87xxx->monitor); -- if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) { -- ret = aw87xxx_power_down(aw87xxx, profile); -- } else { -- ret = aw87xxx_power_on(aw87xxx, profile); -- if (!ret) -- aw87xxx_monitor_start(&aw87xxx->monitor); -- } -- mutex_unlock(&aw87xxx->reg_lock); -- -- return ret; --} -- --int aw87xxx_update_profile_esd(struct aw87xxx *aw87xxx, char *profile) --{ -- int ret = -1; -- -- if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -- ret = aw87xxx_power_down(aw87xxx, profile); -- else -- ret = aw87xxx_power_on(aw87xxx, profile); -- -- return ret; --} -- --char *aw87xxx_show_current_profile(int dev_index) --{ -- struct list_head *pos = NULL; -- struct aw87xxx *aw87xxx = NULL; -- -- list_for_each(pos, &g_aw87xxx_list) { -- aw87xxx = list_entry(pos, struct aw87xxx, list); -- if (aw87xxx->dev_index == dev_index) { -- AW_DEV_LOGI(aw87xxx->dev, "current profile is [%s]", -- aw87xxx->current_profile); -- return aw87xxx->current_profile; -- } -- } -- -- AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -- return NULL; --} --EXPORT_SYMBOL(aw87xxx_show_current_profile); -- --int aw87xxx_set_profile(int dev_index, char *profile) --{ -- struct list_head *pos = NULL; -- struct aw87xxx *aw87xxx = NULL; -- -- list_for_each(pos, &g_aw87xxx_list) { -- aw87xxx = list_entry(pos, struct aw87xxx, list); -- if (profile && aw87xxx->dev_index == dev_index) { -- AW_DEV_LOGD(aw87xxx->dev, "set dev_index = %d, profile = %s", -- dev_index, profile); -- return aw87xxx_update_profile(aw87xxx, profile); -- } -- } -- -- AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -- return -EINVAL; --} --EXPORT_SYMBOL(aw87xxx_set_profile); -- --int aw87xxx_set_profile_by_id(int dev_index, int profile_id) --{ -- char *profile = NULL; -- -- profile = aw87xxx_ctos_get_prof_name(profile_id); -- if (profile == NULL) { -- AW_LOGE("aw87xxx, dev_index[%d] profile[%d] not support!", -- dev_index, profile_id); -- return -EINVAL; -- } -- -- AW_LOGI("aw87xxx, dev_index[%d] set profile[%s] by id[%d]", -- dev_index, profile, profile_id); -- return aw87xxx_set_profile(dev_index, profile); --} --EXPORT_SYMBOL(aw87xxx_set_profile_by_id); -- --/**************************************************************************** -- * -- * aw87xxx Kcontrols -- * -- ****************************************************************************/ --static int aw87xxx_profile_switch_info(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_info *uinfo) --{ -- int count = 0; -- char *name = NULL; -- char *profile_name = NULL; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- -- if (aw87xxx == NULL) { -- AW_LOGE("get struct aw87xxx failed"); -- return -EINVAL; -- } -- -- uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -- uinfo->count = 1; -- -- /*make sure have prof */ -- count = aw87xxx_acf_get_profile_count(aw87xxx->dev, &aw87xxx->acf_info); -- if (count <= 0) { -- uinfo->value.enumerated.items = 0; -- AW_DEV_LOGE(aw87xxx->dev, "get count[%d] failed", count); -- return 0; -- } -- -- uinfo->value.enumerated.items = count; -- if (uinfo->value.enumerated.item >= count) -- uinfo->value.enumerated.item = count - 1; -- -- name = uinfo->value.enumerated.name; -- count = uinfo->value.enumerated.item; -- profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, -- &aw87xxx->acf_info, count); -- if (profile_name == NULL) { -- strscpy(uinfo->value.enumerated.name, "NULL", -- strlen("NULL") + 1); -- return 0; -- } -- -- strscpy(name, profile_name, sizeof(uinfo->value.enumerated.name)); -- -- return 0; --} -- --static int aw87xxx_profile_switch_put(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- int ret = -1; -- char *profile_name = NULL; -- int index = ucontrol->value.integer.value[0]; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- struct acf_bin_info *acf_info = NULL; -- -- if (aw87xxx == NULL) { -- AW_LOGE("get struct aw87xxx failed"); -- return -EINVAL; -- } -- -- acf_info = &aw87xxx->acf_info; -- -- profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, acf_info, index); -- if (!profile_name) { -- AW_DEV_LOGE(aw87xxx->dev, "not found profile name,index=[%d]", -- index); -- return -EINVAL; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "set profile [%s]", profile_name); -- -- ret = aw87xxx_update_profile(aw87xxx, profile_name); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "set dev_index[%d] profile failed, profile = %s", -- aw87xxx->dev_index, profile_name); -- return ret; -- } -- -- return 0; --} -- --static int aw87xxx_profile_switch_get(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- int index = 0; -- char *profile; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- -- if (aw87xxx == NULL) { -- AW_LOGE("get struct aw87xxx failed"); -- return -EINVAL; -- } -- -- if (!aw87xxx->current_profile) { -- AW_DEV_LOGE(aw87xxx->dev, "profile not init"); -- return -EINVAL; -- } -- -- profile = aw87xxx->current_profile; -- AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", -- aw87xxx->current_profile); -- -- -- index = aw87xxx_acf_get_prof_index_form_name(aw87xxx->dev, -- &aw87xxx->acf_info, aw87xxx->current_profile); -- if (index < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "get profile index failed"); -- return index; -- } -- -- ucontrol->value.integer.value[0] = index; -- -- return 0; --} -- --static int aw87xxx_vmax_get_info(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_info *uinfo) --{ -- uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; -- uinfo->count = 1; -- uinfo->value.integer.min = INT_MIN; -- uinfo->value.integer.max = AW_VMAX_MAX; -- -- return 0; --} -- --static int aw87xxx_vmax_get(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- int ret = -1; -- int vmax_val = 0; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- -- if (aw87xxx == NULL) { -- AW_LOGE("get struct aw87xxx failed"); -- return -EINVAL; -- } -- -- ret = aw87xxx_monitor_no_dsp_get_vmax(&aw87xxx->monitor, &vmax_val); -- if (ret < 0) -- return ret; -- -- ucontrol->value.integer.value[0] = vmax_val; -- AW_DEV_LOGI(aw87xxx->dev, "get vmax = [0x%x]", vmax_val); -- -- return 0; --} -- --static int aw87xxx_monitor_switch_info(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_info *uinfo) --{ -- int count; -- -- uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -- uinfo->count = 1; -- count = ARRAY_SIZE(aw87xxx_monitor_switch); -- -- uinfo->value.enumerated.items = count; -- -- if (uinfo->value.enumerated.item >= count) -- uinfo->value.enumerated.item = count - 1; -- -- strscpy(uinfo->value.enumerated.name, -- aw87xxx_monitor_switch[uinfo->value.enumerated.item], -- strlen(aw87xxx_monitor_switch[uinfo->value.enumerated.item]) + 1); -- -- return 0; --} -- --static int aw87xxx_monitor_switch_put(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- uint32_t ctrl_value = ucontrol->value.integer.value[0]; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- struct aw_monitor *aw_monitor = &aw87xxx->monitor; -- int ret = -1; -- -- ret = aw87xxx_dev_monitor_switch_set(aw_monitor, ctrl_value); -- if (ret) -- return ret; -- -- return 0; --} -- --static int aw87xxx_monitor_switch_get(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- struct aw_monitor *aw_monitor = &aw87xxx->monitor; -- -- ucontrol->value.integer.value[0] = aw_monitor->monitor_hdr.monitor_switch; -- -- AW_DEV_LOGI(aw87xxx->dev, "monitor switch is %ld", ucontrol->value.integer.value[0]); -- return 0; --} -- --static int aw87xxx_spin_switch_info(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_info *uinfo) --{ -- int count; -- -- uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -- uinfo->count = 1; -- count = ARRAY_SIZE(aw87xxx_spin_switch); -- -- uinfo->value.enumerated.items = count; -- -- if (uinfo->value.enumerated.item >= count) -- uinfo->value.enumerated.item = count - 1; -- -- strscpy(uinfo->value.enumerated.name, -- aw87xxx_spin_switch[uinfo->value.enumerated.item], -- strlen(aw87xxx_spin_switch[uinfo->value.enumerated.item]) + 1); -- -- return 0; --} -- --static int aw87xxx_spin_switch_put(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- uint32_t ctrl_value = 0; -- int ret = 0; -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- ctrl_value = ucontrol->value.integer.value[0]; -- -- ret = aw87xxx_dsp_set_spin(ctrl_value); -- if (ret) { -- AW_DEV_LOGE(aw87xxx->dev, "write spin failed"); -- return ret; -- } -- AW_DEV_LOGD(aw87xxx->dev, "write spin done ctrl_value=%d", ctrl_value); -- return 0; --} -- --static int aw87xxx_spin_switch_get(struct snd_kcontrol *kcontrol, -- struct snd_ctl_elem_value *ucontrol) --{ -- struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -- -- ucontrol->value.integer.value[0] = aw87xxx_dsp_get_spin(); -- AW_DEV_LOGD(aw87xxx->dev, "current spin is %ld", ucontrol->value.integer.value[0]); -- -- return 0; --} -- -- --static int aw87xxx_kcontrol_dynamic_create(struct aw87xxx *aw87xxx, -- void *codec) --{ -- struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -- aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -- char *kctl_name[AW87XXX_PRIVATE_KCONTROL_NUM]; -- int kcontrol_num = AW87XXX_PRIVATE_KCONTROL_NUM; -- int ret = -1; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- aw87xxx->codec = soc_codec; -- -- aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -- sizeof(struct snd_kcontrol_new) * kcontrol_num, -- GFP_KERNEL); -- if (aw87xxx_kcontrol == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -- return -ENOMEM; -- } -- -- kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -- GFP_KERNEL); -- if (kctl_name[0] == NULL) -- return -ENOMEM; -- -- snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_profile_switch_%d", -- aw87xxx->dev_index); -- -- aw87xxx_kcontrol[0].name = kctl_name[0]; -- aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -- aw87xxx_kcontrol[0].info = aw87xxx_profile_switch_info; -- aw87xxx_kcontrol[0].get = aw87xxx_profile_switch_get; -- aw87xxx_kcontrol[0].put = aw87xxx_profile_switch_put; -- aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -- -- kctl_name[1] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -- GFP_KERNEL); -- if (kctl_name[1] == NULL) -- return -ENOMEM; -- -- snprintf(kctl_name[1], AW_NAME_BUF_MAX, "aw87xxx_vmax_get_%d", -- aw87xxx->dev_index); -- -- aw87xxx_kcontrol[1].name = kctl_name[1]; -- aw87xxx_kcontrol[1].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -- aw87xxx_kcontrol[1].access = SNDRV_CTL_ELEM_ACCESS_READ; -- aw87xxx_kcontrol[1].info = aw87xxx_vmax_get_info; -- aw87xxx_kcontrol[1].get = aw87xxx_vmax_get; -- aw87xxx_kcontrol[1].private_value = (unsigned long)aw87xxx; -- -- kctl_name[2] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -- GFP_KERNEL); -- if (kctl_name[2] == NULL) -- return -ENOMEM; -- -- snprintf(kctl_name[2], AW_NAME_BUF_MAX, "aw87xxx_monitor_switch_%d", -- aw87xxx->dev_index); -- -- aw87xxx_kcontrol[2].name = kctl_name[2]; -- aw87xxx_kcontrol[2].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -- aw87xxx_kcontrol[2].info = aw87xxx_monitor_switch_info; -- aw87xxx_kcontrol[2].get = aw87xxx_monitor_switch_get; -- aw87xxx_kcontrol[2].put = aw87xxx_monitor_switch_put; -- aw87xxx_kcontrol[2].private_value = (unsigned long)aw87xxx; -- -- ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -- aw87xxx_kcontrol, kcontrol_num); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -- ret); -- return ret; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "add codec controls[%s,%s,%s]", -- aw87xxx_kcontrol[0].name, -- aw87xxx_kcontrol[1].name, -- aw87xxx_kcontrol[2].name); -- -- return 0; --} -- --static int aw87xxx_public_kcontrol_create(struct aw87xxx *aw87xxx, -- void *codec) --{ -- struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -- aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -- char *kctl_name[AW87XXX_PUBLIC_KCONTROL_NUM]; -- int kcontrol_num = AW87XXX_PUBLIC_KCONTROL_NUM; -- int ret = -1; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- aw87xxx->codec = soc_codec; -- -- aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -- sizeof(struct snd_kcontrol_new) * kcontrol_num, -- GFP_KERNEL); -- if (aw87xxx_kcontrol == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -- return -ENOMEM; -- } -- -- kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -- GFP_KERNEL); -- if (kctl_name[0] == NULL) -- return -ENOMEM; -- -- snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_spin_switch"); -- -- aw87xxx_kcontrol[0].name = kctl_name[0]; -- aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -- aw87xxx_kcontrol[0].info = aw87xxx_spin_switch_info; -- aw87xxx_kcontrol[0].get = aw87xxx_spin_switch_get; -- aw87xxx_kcontrol[0].put = aw87xxx_spin_switch_put; -- aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -- -- ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -- aw87xxx_kcontrol, kcontrol_num); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -- ret); -- return ret; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "add public codec controls[%s]", -- aw87xxx_kcontrol[0].name); -- -- return 0; --} -- --/**************************************************************************** -- * -- *aw87xxx kcontrol create -- * -- ****************************************************************************/ --int aw87xxx_add_codec_controls(void *codec) --{ -- struct list_head *pos = NULL; -- struct aw87xxx *aw87xxx = NULL; -- int ret = -1; -- -- list_for_each(pos, &g_aw87xxx_list) { -- aw87xxx = list_entry(pos, struct aw87xxx, list); -- ret = aw87xxx_kcontrol_dynamic_create(aw87xxx, codec); -- if (ret < 0) -- return ret; -- -- if (aw87xxx->dev_index == 0) { -- ret = aw87xxx_public_kcontrol_create(aw87xxx, codec); -- if (ret < 0) -- return ret; -- } -- } -- -- return 0; --} --EXPORT_SYMBOL(aw87xxx_add_codec_controls); -- -- --/**************************************************************************** -- * -- * aw87xxx firmware cfg load -- * -- ***************************************************************************/ --static void aw87xxx_fw_cfg_free(struct aw87xxx *aw87xxx) --{ -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- aw87xxx_acf_profile_free(aw87xxx->dev, &aw87xxx->acf_info); -- aw87xxx_monitor_cfg_free(&aw87xxx->monitor); --} -- --static int aw87xxx_init_default_prof(struct aw87xxx *aw87xxx) --{ -- char *profile = NULL; -- -- profile = aw87xxx_acf_get_prof_off_name(aw87xxx->dev, &aw87xxx->acf_info); -- if (profile == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "get profile off name failed"); -- return -EINVAL; -- } -- -- snprintf(aw87xxx->prof_off_name, AW_PROFILE_STR_MAX, "%s", profile); -- aw87xxx->current_profile = profile; -- AW_DEV_LOGI(aw87xxx->dev, "init profile name [%s]", -- aw87xxx->current_profile); -- -- return 0; --} -- --static void aw87xxx_fw_load_retry(struct aw87xxx *aw87xxx) --{ -- struct acf_bin_info *acf_info = &aw87xxx->acf_info; -- int ram_timer_val = 2000; -- -- AW_DEV_LOGD(aw87xxx->dev, "failed to read [%s]", -- aw87xxx->fw_name); -- -- if (acf_info->load_count < AW_LOAD_FW_RETRIES) { -- AW_DEV_LOGD(aw87xxx->dev, -- "restart hrtimer to load firmware"); -- schedule_delayed_work(&aw87xxx->fw_load_work, -- msecs_to_jiffies(ram_timer_val)); -- } else { -- acf_info->load_count = 0; -- AW_DEV_LOGE(aw87xxx->dev, -- "can not load firmware,please check name or file exists"); -- return; -- } -- acf_info->load_count++; --} -- --static void aw87xxx_fw_load(const struct firmware *fw, void *context) --{ -- int ret = -1; -- struct aw87xxx *aw87xxx = context; -- struct acf_bin_info *acf_info = &aw87xxx->acf_info; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- -- if (!fw) { -- aw87xxx_fw_load_retry(aw87xxx); -- return; -- } -- -- AW_DEV_LOGD(aw87xxx->dev, "loaded %s - size: %ld", -- aw87xxx->fw_name, (u_long)(fw ? fw->size : 0)); -- -- mutex_lock(&aw87xxx->reg_lock); -- acf_info->fw_data = vmalloc(fw->size); -- if (!acf_info->fw_data) { -- AW_DEV_LOGE(aw87xxx->dev, "fw_data kzalloc memory failed"); -- goto exit_vmalloc_failed; -- } -- memset(acf_info->fw_data, 0, fw->size); -- memcpy(acf_info->fw_data, fw->data, fw->size); -- acf_info->fw_size = fw->size; -- -- ret = aw87xxx_acf_parse(aw87xxx->dev, &aw87xxx->acf_info); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "fw_data parse failed"); -- goto exit_acf_parse_failed; -- } -- -- ret = aw87xxx_init_default_prof(aw87xxx); -- if (ret < 0) { -- aw87xxx_fw_cfg_free(aw87xxx); -- goto exit_acf_parse_failed; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "acf parse succeed"); -- mutex_unlock(&aw87xxx->reg_lock); -- release_firmware(fw); -- // Updating profile to "Music" because the firmware is set to "off" during init -- aw87xxx_update_profile(aw87xxx, AW87XXX_PROF_MUSIC); -- -- return; -- --exit_acf_parse_failed: --exit_vmalloc_failed: -- release_firmware(fw); -- mutex_unlock(&aw87xxx->reg_lock); --} -- --static void aw87xxx_fw_load_work_routine(struct work_struct *work) --{ -- struct aw87xxx *aw87xxx = container_of(work, -- struct aw87xxx, fw_load_work.work); -- struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- -- if (prof_info->status == AW_ACF_WAIT) { -- request_firmware_nowait(THIS_MODULE, --// FW_ACTION_HOTPLUG, -- FW_ACTION_UEVENT, -- aw87xxx->fw_name, -- aw87xxx->dev, -- GFP_KERNEL, aw87xxx, -- aw87xxx_fw_load); -- } --} -- --static void aw87xxx_fw_load_init(struct aw87xxx *aw87xxx) --{ --#ifdef AW_CFG_UPDATE_DELAY -- int cfg_timer_val = AW_CFG_UPDATE_DELAY_TIMER; --#else -- int cfg_timer_val = 0; --#endif -- AW_DEV_LOGI(aw87xxx->dev, "enter"); -- snprintf(aw87xxx->fw_name, AW87XXX_FW_NAME_MAX, "%s", AW87XXX_FW_BIN_NAME); -- aw87xxx_acf_init(&aw87xxx->aw_dev, &aw87xxx->acf_info, aw87xxx->dev_index); -- -- INIT_DELAYED_WORK(&aw87xxx->fw_load_work, aw87xxx_fw_load_work_routine); -- schedule_delayed_work(&aw87xxx->fw_load_work, -- msecs_to_jiffies(cfg_timer_val)); --} -- --/**************************************************************************** -- * -- *aw87xxx attribute node -- * -- ****************************************************************************/ --static ssize_t aw87xxx_attr_get_reg(struct device *dev, -- struct device_attribute *attr, char *buf) --{ -- ssize_t len = 0; -- int ret = 0; -- unsigned int i = 0; -- unsigned char reg_val = 0; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- struct aw_device *aw_dev = &aw87xxx->aw_dev; -- -- mutex_lock(&aw87xxx->reg_lock); -- for (i = 0; i < aw_dev->reg_max_addr; i++) { -- if (!(aw_dev->reg_access[i] & AW_DEV_REG_RD_ACCESS)) -- continue; -- ret = aw87xxx_dev_i2c_read_byte(&aw87xxx->aw_dev, i, ®_val); -- if (ret < 0) { -- len += snprintf(buf + len, PAGE_SIZE - len, -- "read reg [0x%x] failed\n", i); -- AW_DEV_LOGE(aw87xxx->dev, "read reg [0x%x] failed", i); -- } else { -- len += snprintf(buf + len, PAGE_SIZE - len, -- "reg:0x%02X=0x%02X\n", i, reg_val); -- AW_DEV_LOGD(aw87xxx->dev, "reg:0x%02X=0x%02X", -- i, reg_val); -- } -- } -- mutex_unlock(&aw87xxx->reg_lock); -- -- return len; --} -- --static ssize_t aw87xxx_attr_set_reg(struct device *dev, -- struct device_attribute *attr, const char *buf, -- size_t len) --{ -- unsigned int databuf[2] = { 0 }; -- int ret = 0; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- -- mutex_lock(&aw87xxx->reg_lock); -- if (sscanf(buf, "0x%x 0x%x", &databuf[0], &databuf[1]) == 2) { -- if (databuf[0] >= aw87xxx->aw_dev.reg_max_addr) { -- AW_DEV_LOGE(aw87xxx->dev, "set reg[0x%x] error,is out of reg_addr_max[0x%x]", -- databuf[0], aw87xxx->aw_dev.reg_max_addr); -- mutex_unlock(&aw87xxx->reg_lock); -- return -EINVAL; -- } -- -- ret = aw87xxx_dev_i2c_write_byte(&aw87xxx->aw_dev, -- databuf[0], databuf[1]); -- if (ret < 0) -- AW_DEV_LOGE(aw87xxx->dev, "set [0x%x]=0x%x failed", -- databuf[0], databuf[1]); -- else -- AW_DEV_LOGD(aw87xxx->dev, "set [0x%x]=0x%x succeed", -- databuf[0], databuf[1]); -- } else { -- AW_DEV_LOGE(aw87xxx->dev, "i2c write cmd input error"); -- } -- mutex_unlock(&aw87xxx->reg_lock); -- -- return len; --} -- --static ssize_t aw87xxx_attr_get_profile(struct device *dev, -- struct device_attribute *attr, char *buf) --{ -- ssize_t len = 0; -- unsigned int i = 0; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -- -- if (!prof_info->status) { -- len += snprintf(buf + len, PAGE_SIZE - len, -- "profile_cfg not load\n"); -- return len; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", aw87xxx->current_profile); -- -- for (i = 0; i < prof_info->count; i++) { -- if (!strncmp(aw87xxx->current_profile, prof_info->prof_name_list[i], -- AW_PROFILE_STR_MAX)) -- len += snprintf(buf + len, PAGE_SIZE - len, -- ">%s\n", prof_info->prof_name_list[i]); -- else -- len += snprintf(buf + len, PAGE_SIZE - len, -- " %s\n", prof_info->prof_name_list[i]); -- } -- -- return len; --} -- --static ssize_t aw87xxx_attr_set_profile(struct device *dev, -- struct device_attribute *attr, const char *buf, -- size_t len) --{ -- char profile[AW_PROFILE_STR_MAX] = {0}; -- int ret = 0; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- -- if (strlen(buf) > AW_PROFILE_STR_MAX) { -- AW_DEV_LOGE(aw87xxx->dev, "input profile_str_len is out of max[%d]", -- AW_PROFILE_STR_MAX); -- return -EINVAL; -- } -- -- if (sscanf(buf, "%s", profile) == 1) { -- AW_DEV_LOGD(aw87xxx->dev, "set profile [%s]", profile); -- ret = aw87xxx_update_profile(aw87xxx, profile); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "set profile[%s] failed", -- profile); -- return ret; -- } -- } -- -- return len; --} -- --static ssize_t aw87xxx_attr_get_hwen(struct device *dev, -- struct device_attribute *attr, char *buf) --{ -- ssize_t len = 0; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- int hwen = aw87xxx->aw_dev.hwen_status; -- -- if (hwen >= AW_DEV_HWEN_INVALID) -- len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: invalid\n"); -- else if (hwen == AW_DEV_HWEN_ON) -- len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: on\n"); -- else if (hwen == AW_DEV_HWEN_OFF) -- len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: off\n"); -- -- return len; --} -- --static ssize_t aw87xxx_attr_set_hwen(struct device *dev, -- struct device_attribute *attr, const char *buf, -- size_t len) --{ -- int ret = -1; -- unsigned int state; -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- -- ret = kstrtouint(buf, 0, &state); -- if (ret) { -- AW_DEV_LOGE(aw87xxx->dev, "fail to channelge str to int"); -- return ret; -- } -- -- mutex_lock(&aw87xxx->reg_lock); -- if (state == AW_DEV_HWEN_OFF) -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); /*OFF*/ -- else if (state == AW_DEV_HWEN_ON) -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); /*ON*/ -- else -- AW_DEV_LOGE(aw87xxx->dev, "input [%d] error, hwen_on=[%d],hwen_off=[%d]", -- state, AW_DEV_HWEN_ON, AW_DEV_HWEN_OFF); -- mutex_unlock(&aw87xxx->reg_lock); -- return len; --} -- --int aw87xxx_awrw_write(struct aw87xxx *aw87xxx, -- const char *buf, size_t count) --{ -- int i = 0, ret = -1; -- char *data_buf = NULL; -- int buf_len = 0; -- int temp_data = 0; -- int data_str_size = 0; -- char *reg_data; -- struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -- -- AW_DEV_LOGD(aw87xxx->dev, "enter"); -- /* one addr or one data string Composition of Contains two bytes of symbol(0X)*/ -- /* and two byte of hexadecimal data*/ -- data_str_size = 2 + 2 * AWRW_DATA_BYTES; -- -- /* The buf includes the first address of the register to be written and all data */ -- buf_len = AWRW_ADDR_BYTES + packet->reg_num * AWRW_DATA_BYTES; -- AW_DEV_LOGI(aw87xxx->dev, "buf_len = %d,reg_num = %d", buf_len, packet->reg_num); -- data_buf = vmalloc(buf_len); -- if (data_buf == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "alloc memory failed"); -- return -ENOMEM; -- } -- memset(data_buf, 0, buf_len); -- -- data_buf[0] = packet->reg_addr; -- reg_data = data_buf + 1; -- -- AW_DEV_LOGD(aw87xxx->dev, "reg_addr: 0x%02x", data_buf[0]); -- -- /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -- for (i = 0; i < packet->reg_num; i++) { -- ret = sscanf(buf + AWRW_HDR_LEN + 1 + i * (data_str_size + 1), -- "0x%x", &temp_data); -- if (ret != 1) { -- AW_DEV_LOGE(aw87xxx->dev, "sscanf failed,ret=%d", ret); -- vfree(data_buf); -- data_buf = NULL; -- return ret; -- } -- reg_data[i] = temp_data; -- AW_DEV_LOGD(aw87xxx->dev, "[%d] : 0x%02x", i, reg_data[i]); -- } -- -- mutex_lock(&aw87xxx->reg_lock); -- ret = i2c_master_send(aw87xxx->aw_dev.i2c, data_buf, buf_len); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "write failed"); -- vfree(data_buf); -- data_buf = NULL; -- return -EFAULT; -- } -- mutex_unlock(&aw87xxx->reg_lock); -- -- vfree(data_buf); -- data_buf = NULL; -- -- AW_DEV_LOGD(aw87xxx->dev, "down"); -- return 0; --} -- --static int aw87xxx_awrw_data_check(struct aw87xxx *aw87xxx, -- int *data, size_t count) --{ -- struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -- int req_data_len = 0; -- int act_data_len = 0; -- int data_str_size = 0; -- -- if ((data[AWRW_HDR_ADDR_BYTES] != AWRW_ADDR_BYTES) || -- (data[AWRW_HDR_DATA_BYTES] != AWRW_DATA_BYTES)) { -- AW_DEV_LOGE(aw87xxx->dev, "addr_bytes [%d] or data_bytes [%d] unsupport", -- data[AWRW_HDR_ADDR_BYTES], data[AWRW_HDR_DATA_BYTES]); -- return -EINVAL; -- } -- -- /* one data string Composition of Contains two bytes of symbol(0x)*/ -- /* and two byte of hexadecimal data*/ -- data_str_size = 2 + 2 * AWRW_DATA_BYTES; -- act_data_len = count - AWRW_HDR_LEN - 1; -- -- /* There is a comma(,) or space between each piece of data */ -- if (data[AWRW_HDR_WR_FLAG] == AWRW_FLAG_WRITE) { -- /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -- req_data_len = (data_str_size + 1) * packet->reg_num; -- if (req_data_len > act_data_len) { -- AW_DEV_LOGE(aw87xxx->dev, "data_len checkfailed,requeset data_len [%d],actaul data_len [%d]", -- req_data_len, act_data_len); -- return -EINVAL; -- } -- } -- -- return 0; --} -- --/* flag addr_bytes data_bytes reg_num reg_addr*/ --static int aw87xxx_awrw_parse_buf(struct aw87xxx *aw87xxx, -- const char *buf, size_t count, int *wr_status) --{ -- int data[AWRW_HDR_MAX] = {0}; -- struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -- int ret = -1; -- -- if (sscanf(buf, "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", -- &data[AWRW_HDR_WR_FLAG], &data[AWRW_HDR_ADDR_BYTES], -- &data[AWRW_HDR_DATA_BYTES], &data[AWRW_HDR_REG_NUM], -- &data[AWRW_HDR_REG_ADDR]) == 5) { -- -- packet->reg_addr = data[AWRW_HDR_REG_ADDR]; -- packet->reg_num = data[AWRW_HDR_REG_NUM]; -- *wr_status = data[AWRW_HDR_WR_FLAG]; -- ret = aw87xxx_awrw_data_check(aw87xxx, data, count); -- if (ret < 0) -- return ret; -- -- return 0; -- } -- -- return -EINVAL; --} -- --static ssize_t aw87xxx_attr_awrw_store(struct device *dev, -- struct device_attribute *attr, const char *buf, size_t count) --{ -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -- int wr_status = 0; -- int ret = -1; -- -- if (count < AWRW_HDR_LEN) { -- AW_DEV_LOGE(aw87xxx->dev, "data count too smaller, please check write format"); -- AW_DEV_LOGE(aw87xxx->dev, "string %s,count=%ld", -- buf, (u_long)count); -- return -EINVAL; -- } -- -- AW_DEV_LOGI(aw87xxx->dev, "string:[%s],count=%ld", buf, (u_long)count); -- ret = aw87xxx_awrw_parse_buf(aw87xxx, buf, count, &wr_status); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "can not parse string"); -- return ret; -- } -- -- if (wr_status == AWRW_FLAG_WRITE) { -- ret = aw87xxx_awrw_write(aw87xxx, buf, count); -- if (ret < 0) -- return ret; -- } else if (wr_status == AWRW_FLAG_READ) { -- packet->status = AWRW_I2C_ST_READ; -- AW_DEV_LOGI(aw87xxx->dev, "read_cmd:reg_addr[0x%02x], reg_num[%d]", -- packet->reg_addr, packet->reg_num); -- } else { -- AW_DEV_LOGE(aw87xxx->dev, "please check str format, unsupport read_write_status: %d", -- wr_status); -- return -EINVAL; -- } -- -- return count; --} -- --static ssize_t aw87xxx_attr_awrw_show(struct device *dev, -- struct device_attribute *attr, char *buf) --{ -- struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -- struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -- int data_len = 0; -- size_t len = 0; -- int ret = -1, i = 0; -- char *reg_data = NULL; -- -- if (packet->status != AWRW_I2C_ST_READ) { -- AW_DEV_LOGE(aw87xxx->dev, "please write read cmd first"); -- return -EINVAL; -- } -- -- data_len = AWRW_DATA_BYTES * packet->reg_num; -- reg_data = (char *)vmalloc(data_len); -- if (reg_data == NULL) { -- AW_DEV_LOGE(aw87xxx->dev, "memory alloc failed"); -- ret = -EINVAL; -- goto exit; -- } -- -- mutex_lock(&aw87xxx->reg_lock); -- ret = aw87xxx_dev_i2c_read_msg(&aw87xxx->aw_dev, packet->reg_addr, -- (char *)reg_data, data_len); -- if (ret < 0) { -- ret = -EFAULT; -- mutex_unlock(&aw87xxx->reg_lock); -- goto exit; -- } -- mutex_unlock(&aw87xxx->reg_lock); -- -- AW_DEV_LOGI(aw87xxx->dev, "reg_addr 0x%02x, reg_num %d", -- packet->reg_addr, packet->reg_num); -- -- for (i = 0; i < data_len; i++) { -- len += snprintf(buf + len, PAGE_SIZE - len, -- "0x%02x,", reg_data[i]); -- AW_DEV_LOGI(aw87xxx->dev, "0x%02x", reg_data[i]); -- } -- -- ret = len; -- --exit: -- if (reg_data) { -- vfree(reg_data); -- reg_data = NULL; -- } -- packet->status = AWRW_I2C_ST_NONE; -- return ret; --} -- --static ssize_t aw87xxx_drv_ver_show(struct device *dev, -- struct device_attribute *attr, char *buf) --{ -- ssize_t len = 0; -- -- len += snprintf(buf + len, PAGE_SIZE - len, -- "driver_ver: %s \n", AW87XXX_DRIVER_VERSION); -- -- return len; --} -- --static DEVICE_ATTR(reg, S_IWUSR | S_IRUGO, -- aw87xxx_attr_get_reg, aw87xxx_attr_set_reg); --static DEVICE_ATTR(profile, S_IWUSR | S_IRUGO, -- aw87xxx_attr_get_profile, aw87xxx_attr_set_profile); --static DEVICE_ATTR(hwen, S_IWUSR | S_IRUGO, -- aw87xxx_attr_get_hwen, aw87xxx_attr_set_hwen); --static DEVICE_ATTR(awrw, S_IWUSR | S_IRUGO, -- aw87xxx_attr_awrw_show, aw87xxx_attr_awrw_store); --static DEVICE_ATTR(drv_ver, S_IRUGO, aw87xxx_drv_ver_show, NULL); -- --static struct attribute *aw87xxx_attributes[] = { -- &dev_attr_reg.attr, -- &dev_attr_profile.attr, -- &dev_attr_hwen.attr, -- &dev_attr_awrw.attr, -- &dev_attr_drv_ver.attr, -- NULL --}; -- --static struct attribute_group aw87xxx_attribute_group = { -- .attrs = aw87xxx_attributes --}; -- --/**************************************************************************** -- * -- *aw87xxx device probe -- * -- ****************************************************************************/ --static const struct acpi_gpio_params reset_gpio = { 0, 0, false }; --static const struct acpi_gpio_mapping reset_acpi_gpios[] = { -- { "reset-gpios", &reset_gpio, 1 }, -- { } --}; -- --static struct aw87xxx *aw87xxx_malloc_init(struct i2c_client *client) --{ -- struct aw87xxx *aw87xxx = NULL; -- -- aw87xxx = devm_kzalloc(&client->dev, sizeof(struct aw87xxx), -- GFP_KERNEL); -- if (aw87xxx == NULL) { -- AW_DEV_LOGE(&client->dev, "failed to devm_kzalloc aw87xxx"); -- return NULL; -- } -- memset(aw87xxx, 0, sizeof(struct aw87xxx)); -- -- aw87xxx->dev = &client->dev; -- aw87xxx->aw_dev.dev = &client->dev; -- aw87xxx->aw_dev.i2c_bus = client->adapter->nr; -- aw87xxx->aw_dev.i2c_addr = client->addr; -- aw87xxx->aw_dev.i2c = client; -- aw87xxx->aw_dev.hwen_status = false; -- aw87xxx->aw_dev.reg_access = NULL; -- aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -- aw87xxx->off_bin_status = AW87XXX_NO_OFF_BIN; -- aw87xxx->codec = NULL; -- aw87xxx->current_profile = aw87xxx->prof_off_name; -- -- mutex_init(&aw87xxx->reg_lock); -- -- AW_DEV_LOGI(&client->dev, "struct aw87xxx devm_kzalloc and init down"); -- return aw87xxx; --} -- --static int aw87xxx_i2c_probe(struct i2c_client *client) --{ -- struct device_node *dev_node = client->dev.of_node; -- struct aw87xxx *aw87xxx = NULL; -- struct gpio_desc *gpiod = NULL; -- int ret = -1; -- -- --// To do, add this function --//acpi_dev_add_driver_gpios() -- -- if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { -- AW_DEV_LOGE(&client->dev, "check_functionality failed"); -- ret = -ENODEV; -- goto exit_check_functionality_failed; -- } -- -- /* aw87xxx i2c_dev struct init */ -- aw87xxx = aw87xxx_malloc_init(client); -- if (aw87xxx == NULL) -- goto exit_malloc_init_failed; -- -- i2c_set_clientdata(client, aw87xxx); -- -- aw87xxx_device_parse_port_id_dt(&aw87xxx->aw_dev); -- aw87xxx_device_parse_topo_id_dt(&aw87xxx->aw_dev); -- -- /* aw87xxx Get ACPI GPIO */ --/* -- ret = devm_acpi_dev_add_driver_gpios(aw87xxx->dev, reset_acpi_gpios); -- if(ret){ -- AW_DEV_LOGE(aw87xxx->dev, "Unable to add GPIO mapping table"); -- goto exit_device_init_failed; -- } -- -- gpiod = gpiod_get_optional(aw87xxx->dev, "reset", GPIOD_OUT_LOW); -- if (IS_ERR(gpiod)){ -- AW_DEV_LOGE(aw87xxx->dev, "Get gpiod failed"); -- goto exit_device_init_failed; -- } -- -- aw87xxx->aw_dev.rst_gpio = desc_to_gpio(gpiod); -- aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_OFF; -- AW_DEV_LOGI(aw87xxx->dev, "reset gpio[%d] parse succeed", aw87xxx->aw_dev.rst_gpio); -- if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio)) { -- ret = devm_gpio_request_one(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio, GPIOF_OUT_INIT_LOW, "aw87xxx_reset"); -- if (ret < 0) { -- AW_DEV_LOGE(aw87xxx->dev, "reset request failed"); -- goto exit_device_init_failed; -- } -- } --*/ -- -- /*Disabling RESET GPIO*/ -- AW_DEV_LOGI(aw87xxx->dev, "no reset gpio provided, hardware reset unavailable"); -- aw87xxx->aw_dev.rst_gpio = AW_NO_RESET_GPIO; -- aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -- -- -- /*hw power on PA*/ -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -- -- /* aw87xxx devices private attributes init */ -- ret = aw87xxx_dev_init(&aw87xxx->aw_dev); -- if (ret < 0) -- goto exit_device_init_failed; -- -- /*product register reset */ -- aw87xxx_dev_soft_reset(&aw87xxx->aw_dev); -- -- /*hw power off */ -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -- -- /* create debug attrbute nodes */ -- ret = sysfs_create_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -- if (ret < 0) -- AW_DEV_LOGE(aw87xxx->dev, "failed to create sysfs nodes, will not allowed to use"); -- -- /* cfg_load init */ -- aw87xxx_fw_load_init(aw87xxx); -- -- /*monitor init*/ -- aw87xxx_monitor_init(aw87xxx->dev, &aw87xxx->monitor, dev_node); -- -- /*add device to total list */ -- mutex_lock(&g_aw87xxx_mutex_lock); -- g_aw87xxx_dev_cnt++; -- list_add(&aw87xxx->list, &g_aw87xxx_list); -- aw87xxx->dev_index = g_aw87xxx_dev_cnt; -- -- mutex_unlock(&g_aw87xxx_mutex_lock); -- AW_DEV_LOGI(aw87xxx->dev, "succeed, dev_index=[%d], g_aw87xxx_dev_cnt= [%d]", -- aw87xxx->dev_index, g_aw87xxx_dev_cnt); -- -- return 0; -- --exit_device_init_failed: -- AW_DEV_LOGE(aw87xxx->dev, "pa init failed"); -- -- devm_kfree(&client->dev, aw87xxx); -- aw87xxx = NULL; --exit_malloc_init_failed: --exit_check_functionality_failed: -- return ret; --} -- --static void aw87xxx_i2c_remove(struct i2c_client *client) --{ -- struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -- -- aw87xxx_monitor_exit(&aw87xxx->monitor); -- -- /*rm attr node*/ -- sysfs_remove_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -- -- aw87xxx_fw_cfg_free(aw87xxx); -- -- mutex_lock(&g_aw87xxx_mutex_lock); -- g_aw87xxx_dev_cnt--; -- list_del(&aw87xxx->list); -- mutex_unlock(&g_aw87xxx_mutex_lock); -- -- devm_kfree(&client->dev, aw87xxx); -- aw87xxx = NULL; -- --// return 0; --} -- --static void aw87xxx_i2c_shutdown(struct i2c_client *client) --{ -- struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -- -- AW_DEV_LOGI(&client->dev, "enter"); -- -- /*soft and hw power off*/ -- aw87xxx_update_profile(aw87xxx, aw87xxx->prof_off_name); --} -- --static const struct acpi_device_id aw87xxx_acpi_match[] = { -- { "AWDZ8830", 0 }, -- { } --}; --MODULE_DEVICE_TABLE(acpi, aw87xxx_acpi_match); -- --// This is not necessary if the acpi match probes correctly. This is needed for userspace `new_device() functionality --static const struct i2c_device_id aw87xxx_i2c_id[] = { -- {AW87XXX_I2C_NAME, 0}, -- {}, --}; -- --static struct i2c_driver aw87xxx_i2c_driver = { -- .driver = { -- .owner = THIS_MODULE, -- .name = AW87XXX_I2C_NAME, -- .acpi_match_table = aw87xxx_acpi_match, -- }, -- .probe = aw87xxx_i2c_probe, -- .remove = aw87xxx_i2c_remove, -- .shutdown = aw87xxx_i2c_shutdown, -- .id_table = aw87xxx_i2c_id, --}; -- --module_i2c_driver(aw87xxx_i2c_driver) -- --MODULE_AUTHOR("<zhaozhongbo@awinic.com>"); --MODULE_DESCRIPTION("awinic aw87xxx pa driver"); --MODULE_LICENSE("GPL v2"); -+/* -+ * aw87xxx.c aw87xxx pa module -+ * -+ * Copyright (c) 2021 AWINIC Technology CO., LTD -+ * -+ * Author: Barry <zhaozhongbo@awinic.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ * -+ */ -+ -+#include <linux/i2c.h> -+#include <sound/pcm.h> -+#include <sound/pcm_params.h> -+#include <linux/gpio.h> -+#include <linux/of_gpio.h> -+#include <linux/gpio/consumer.h> -+#include <linux/interrupt.h> -+#include <linux/delay.h> -+#include <linux/module.h> -+#include <linux/kernel.h> -+#include <linux/device.h> -+#include <linux/irq.h> -+#include <linux/firmware.h> -+#include <linux/platform_device.h> -+#include <linux/slab.h> -+#include <linux/fs.h> -+#include <linux/proc_fs.h> -+#include <linux/uaccess.h> -+#include <linux/io.h> -+#include <linux/init.h> -+#include <linux/pci.h> -+#include <linux/dma-mapping.h> -+#include <linux/gameport.h> -+#include <linux/moduleparam.h> -+#include <linux/mutex.h> -+#include <linux/timer.h> -+#include <linux/workqueue.h> -+#include <linux/hrtimer.h> -+#include <linux/ktime.h> -+#include <linux/kthread.h> -+#include <uapi/sound/asound.h> -+#include <sound/control.h> -+#include <sound/soc.h> -+#include "aw87xxx.h" -+#include "aw87xxx_device.h" -+#include "aw87xxx_log.h" -+#include "aw87xxx_monitor.h" -+#include "aw87xxx_acf_bin.h" -+#include "aw87xxx_bin_parse.h" -+#include "aw87xxx_dsp.h" -+ -+/***************************************************************** -+* aw87xxx marco -+******************************************************************/ -+#define AW87XXX_I2C_NAME "aw87xxx_pa" -+#define AW87XXX_DRIVER_VERSION "v2.7.0" -+#define AW87XXX_FW_BIN_NAME "aw87xxx_acf.bin" -+#define AW87XXX_PROF_MUSIC "Music" -+/************************************************************************* -+ * aw87xxx variable -+ ************************************************************************/ -+static LIST_HEAD(g_aw87xxx_list); -+static DEFINE_MUTEX(g_aw87xxx_mutex_lock); -+unsigned int g_aw87xxx_dev_cnt = 0; -+ -+static const char *const aw87xxx_monitor_switch[] = {"Disable", "Enable"}; -+static const char *const aw87xxx_spin_switch[] = {"spin_0", "spin_90", -+ "spin_180", "spin_270"}; -+#ifdef AW_KERNEL_VER_OVER_4_19_1 -+static struct aw_componet_codec_ops aw_componet_codec_ops = { -+ .add_codec_controls = snd_soc_add_component_controls, -+ .unregister_codec = snd_soc_unregister_component, -+}; -+#else -+static struct aw_componet_codec_ops aw_componet_codec_ops = { -+ .add_codec_controls = snd_soc_add_codec_controls, -+ .unregister_codec = snd_soc_unregister_codec, -+}; -+#endif -+ -+ -+/************************************************************************ -+ * -+ * aw87xxx device update profile -+ * -+ ************************************************************************/ -+static int aw87xxx_power_down(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = 0; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ struct aw_data_container *data_container = NULL; -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!prof_info->status) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -+ if (prof_desc == NULL) -+ goto no_bin_pwr_off; -+ -+ if (!prof_desc->prof_st) -+ goto no_bin_pwr_off; -+ -+ -+ data_container = &prof_desc->data_container; -+ AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -+ profile, data_container->len); -+ -+ if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) { -+ AW_DEV_LOGI(aw87xxx->dev, "profile[%s] has already load ", profile); -+ } else { -+ if (aw_dev->ops.pwr_off_func) { -+ ret = aw_dev->ops.pwr_off_func(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -+ goto pwr_off_failed; -+ } -+ } else { -+ ret = aw87xxx_dev_default_pwr_off(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", profile); -+ goto pwr_off_failed; -+ } -+ } -+ } -+ -+ aw87xxx->current_profile = prof_desc->prof_name; -+ return 0; -+ -+pwr_off_failed: -+no_bin_pwr_off: -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ aw87xxx->current_profile = aw87xxx->prof_off_name; -+ return ret; -+} -+ -+static int aw87xxx_power_on(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -EINVAL; -+ struct aw_prof_desc *prof_desc = NULL; -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ struct aw_data_container *data_container = NULL; -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!prof_info->status) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile_cfg not load"); -+ return -EINVAL; -+ } -+ -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -+ return aw87xxx_power_down(aw87xxx, profile); -+ -+ prof_desc = aw87xxx_acf_get_prof_desc_form_name(aw87xxx->dev, &aw87xxx->acf_info, profile); -+ if (prof_desc == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found [%s] parameter", profile); -+ return -EINVAL; -+ } -+ -+ if (!prof_desc->prof_st) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found data container"); -+ return -EINVAL; -+ } -+ -+ data_container = &prof_desc->data_container; -+ AW_DEV_LOGD(aw87xxx->dev, "get profile[%s] data len [%d]", -+ profile, data_container->len); -+ -+ if (aw_dev->ops.pwr_on_func) { -+ ret = aw_dev->ops.pwr_on_func(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -+ profile); -+ return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -+ } -+ } else { -+ ret = aw87xxx_dev_default_pwr_on(aw_dev, data_container); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "load profile[%s] failed ", -+ profile); -+ return aw87xxx_power_down(aw87xxx, aw87xxx->prof_off_name); -+ } -+ } -+ -+ aw87xxx->current_profile = prof_desc->prof_name; -+ AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] succeed", profile); -+ -+ return 0; -+} -+ -+ -+ -+int aw87xxx_update_profile(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "load profile[%s] enter", profile); -+ mutex_lock(&aw87xxx->reg_lock); -+ aw87xxx_monitor_stop(&aw87xxx->monitor); -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) { -+ ret = aw87xxx_power_down(aw87xxx, profile); -+ } else { -+ ret = aw87xxx_power_on(aw87xxx, profile); -+ if (!ret) -+ aw87xxx_monitor_start(&aw87xxx->monitor); -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return ret; -+} -+ -+int aw87xxx_update_profile_esd(struct aw87xxx *aw87xxx, char *profile) -+{ -+ int ret = -1; -+ -+ if (0 == strncmp(profile, aw87xxx->prof_off_name, AW_PROFILE_STR_MAX)) -+ ret = aw87xxx_power_down(aw87xxx, profile); -+ else -+ ret = aw87xxx_power_on(aw87xxx, profile); -+ -+ return ret; -+} -+ -+char *aw87xxx_show_current_profile(int dev_index) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ if (aw87xxx->dev_index == dev_index) { -+ AW_DEV_LOGI(aw87xxx->dev, "current profile is [%s]", -+ aw87xxx->current_profile); -+ return aw87xxx->current_profile; -+ } -+ } -+ -+ AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -+ return NULL; -+} -+EXPORT_SYMBOL(aw87xxx_show_current_profile); -+ -+int aw87xxx_set_profile(int dev_index, char *profile) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ if (profile && aw87xxx->dev_index == dev_index) { -+ AW_DEV_LOGD(aw87xxx->dev, "set dev_index = %d, profile = %s", -+ dev_index, profile); -+ return aw87xxx_update_profile(aw87xxx, profile); -+ } -+ } -+ -+ AW_LOGE("not found struct aw87xxx, dev_index = [%d]", dev_index); -+ return -EINVAL; -+} -+EXPORT_SYMBOL(aw87xxx_set_profile); -+ -+int aw87xxx_set_profile_by_id(int dev_index, int profile_id) -+{ -+ char *profile = NULL; -+ -+ profile = aw87xxx_ctos_get_prof_name(profile_id); -+ if (profile == NULL) { -+ AW_LOGE("aw87xxx, dev_index[%d] profile[%d] not support!", -+ dev_index, profile_id); -+ return -EINVAL; -+ } -+ -+ AW_LOGI("aw87xxx, dev_index[%d] set profile[%s] by id[%d]", -+ dev_index, profile, profile_id); -+ return aw87xxx_set_profile(dev_index, profile); -+} -+EXPORT_SYMBOL(aw87xxx_set_profile_by_id); -+ -+/**************************************************************************** -+ * -+ * aw87xxx Kcontrols -+ * -+ ****************************************************************************/ -+static int aw87xxx_profile_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count = 0; -+ char *name = NULL; -+ char *profile_name = NULL; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ -+ /*make sure have prof */ -+ count = aw87xxx_acf_get_profile_count(aw87xxx->dev, &aw87xxx->acf_info); -+ if (count <= 0) { -+ uinfo->value.enumerated.items = 0; -+ AW_DEV_LOGE(aw87xxx->dev, "get count[%d] failed", count); -+ return 0; -+ } -+ -+ uinfo->value.enumerated.items = count; -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ name = uinfo->value.enumerated.name; -+ count = uinfo->value.enumerated.item; -+ profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, -+ &aw87xxx->acf_info, count); -+ if (profile_name == NULL) { -+ strscpy(uinfo->value.enumerated.name, "NULL", -+ strlen("NULL") + 1); -+ return 0; -+ } -+ -+ strscpy(name, profile_name, sizeof(uinfo->value.enumerated.name)); -+ -+ return 0; -+} -+ -+static int aw87xxx_profile_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int ret = -1; -+ char *profile_name = NULL; -+ int index = ucontrol->value.integer.value[0]; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct acf_bin_info *acf_info = NULL; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ acf_info = &aw87xxx->acf_info; -+ -+ profile_name = aw87xxx_acf_get_prof_name_form_index(aw87xxx->dev, acf_info, index); -+ if (!profile_name) { -+ AW_DEV_LOGE(aw87xxx->dev, "not found profile name,index=[%d]", -+ index); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "set profile [%s]", profile_name); -+ -+ ret = aw87xxx_update_profile(aw87xxx, profile_name); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "set dev_index[%d] profile failed, profile = %s", -+ aw87xxx->dev_index, profile_name); -+ return ret; -+ } -+ -+ return 0; -+} -+ -+static int aw87xxx_profile_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int index = 0; -+ char *profile; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ if (!aw87xxx->current_profile) { -+ AW_DEV_LOGE(aw87xxx->dev, "profile not init"); -+ return -EINVAL; -+ } -+ -+ profile = aw87xxx->current_profile; -+ AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", -+ aw87xxx->current_profile); -+ -+ -+ index = aw87xxx_acf_get_prof_index_form_name(aw87xxx->dev, -+ &aw87xxx->acf_info, aw87xxx->current_profile); -+ if (index < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "get profile index failed"); -+ return index; -+ } -+ -+ ucontrol->value.integer.value[0] = index; -+ -+ return 0; -+} -+ -+static int aw87xxx_vmax_get_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; -+ uinfo->count = 1; -+ uinfo->value.integer.min = INT_MIN; -+ uinfo->value.integer.max = AW_VMAX_MAX; -+ -+ return 0; -+} -+ -+static int aw87xxx_vmax_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ int ret = -1; -+ int vmax_val = 0; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ if (aw87xxx == NULL) { -+ AW_LOGE("get struct aw87xxx failed"); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_monitor_no_dsp_get_vmax(&aw87xxx->monitor, &vmax_val); -+ if (ret < 0) -+ return ret; -+ -+ ucontrol->value.integer.value[0] = vmax_val; -+ AW_DEV_LOGI(aw87xxx->dev, "get vmax = [0x%x]", vmax_val); -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count; -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ count = ARRAY_SIZE(aw87xxx_monitor_switch); -+ -+ uinfo->value.enumerated.items = count; -+ -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ strscpy(uinfo->value.enumerated.name, -+ aw87xxx_monitor_switch[uinfo->value.enumerated.item], -+ strlen(aw87xxx_monitor_switch[uinfo->value.enumerated.item]) + 1); -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ uint32_t ctrl_value = ucontrol->value.integer.value[0]; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct aw_monitor *aw_monitor = &aw87xxx->monitor; -+ int ret = -1; -+ -+ ret = aw87xxx_dev_monitor_switch_set(aw_monitor, ctrl_value); -+ if (ret) -+ return ret; -+ -+ return 0; -+} -+ -+static int aw87xxx_monitor_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ struct aw_monitor *aw_monitor = &aw87xxx->monitor; -+ -+ ucontrol->value.integer.value[0] = aw_monitor->monitor_hdr.monitor_switch; -+ -+ AW_DEV_LOGI(aw87xxx->dev, "monitor switch is %ld", ucontrol->value.integer.value[0]); -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_info(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_info *uinfo) -+{ -+ int count; -+ -+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED; -+ uinfo->count = 1; -+ count = ARRAY_SIZE(aw87xxx_spin_switch); -+ -+ uinfo->value.enumerated.items = count; -+ -+ if (uinfo->value.enumerated.item >= count) -+ uinfo->value.enumerated.item = count - 1; -+ -+ strscpy(uinfo->value.enumerated.name, -+ aw87xxx_spin_switch[uinfo->value.enumerated.item], -+ strlen(aw87xxx_spin_switch[uinfo->value.enumerated.item]) + 1); -+ -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_put(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ uint32_t ctrl_value = 0; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ ctrl_value = ucontrol->value.integer.value[0]; -+ -+ ret = aw87xxx_dsp_set_spin(ctrl_value); -+ if (ret) { -+ AW_DEV_LOGE(aw87xxx->dev, "write spin failed"); -+ return ret; -+ } -+ AW_DEV_LOGD(aw87xxx->dev, "write spin done ctrl_value=%d", ctrl_value); -+ return 0; -+} -+ -+static int aw87xxx_spin_switch_get(struct snd_kcontrol *kcontrol, -+ struct snd_ctl_elem_value *ucontrol) -+{ -+ struct aw87xxx *aw87xxx = (struct aw87xxx *)kcontrol->private_value; -+ -+ ucontrol->value.integer.value[0] = aw87xxx_dsp_get_spin(); -+ AW_DEV_LOGD(aw87xxx->dev, "current spin is %ld", ucontrol->value.integer.value[0]); -+ -+ return 0; -+} -+ -+ -+static int aw87xxx_kcontrol_dynamic_create(struct aw87xxx *aw87xxx, -+ void *codec) -+{ -+ struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -+ aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -+ char *kctl_name[AW87XXX_PRIVATE_KCONTROL_NUM]; -+ int kcontrol_num = AW87XXX_PRIVATE_KCONTROL_NUM; -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx->codec = soc_codec; -+ -+ aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -+ sizeof(struct snd_kcontrol_new) * kcontrol_num, -+ GFP_KERNEL); -+ if (aw87xxx_kcontrol == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[0] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_profile_switch_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[0].name = kctl_name[0]; -+ aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[0].info = aw87xxx_profile_switch_info; -+ aw87xxx_kcontrol[0].get = aw87xxx_profile_switch_get; -+ aw87xxx_kcontrol[0].put = aw87xxx_profile_switch_put; -+ aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -+ -+ kctl_name[1] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[1] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[1], AW_NAME_BUF_MAX, "aw87xxx_vmax_get_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[1].name = kctl_name[1]; -+ aw87xxx_kcontrol[1].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[1].access = SNDRV_CTL_ELEM_ACCESS_READ; -+ aw87xxx_kcontrol[1].info = aw87xxx_vmax_get_info; -+ aw87xxx_kcontrol[1].get = aw87xxx_vmax_get; -+ aw87xxx_kcontrol[1].private_value = (unsigned long)aw87xxx; -+ -+ kctl_name[2] = devm_kzalloc(aw87xxx->codec->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[2] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[2], AW_NAME_BUF_MAX, "aw87xxx_monitor_switch_%d", -+ aw87xxx->dev_index); -+ -+ aw87xxx_kcontrol[2].name = kctl_name[2]; -+ aw87xxx_kcontrol[2].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[2].info = aw87xxx_monitor_switch_info; -+ aw87xxx_kcontrol[2].get = aw87xxx_monitor_switch_get; -+ aw87xxx_kcontrol[2].put = aw87xxx_monitor_switch_put; -+ aw87xxx_kcontrol[2].private_value = (unsigned long)aw87xxx; -+ -+ ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -+ aw87xxx_kcontrol, kcontrol_num); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -+ ret); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "add codec controls[%s,%s,%s]", -+ aw87xxx_kcontrol[0].name, -+ aw87xxx_kcontrol[1].name, -+ aw87xxx_kcontrol[2].name); -+ -+ return 0; -+} -+ -+static int aw87xxx_public_kcontrol_create(struct aw87xxx *aw87xxx, -+ void *codec) -+{ -+ struct snd_kcontrol_new *aw87xxx_kcontrol = NULL; -+ aw_snd_soc_codec_t *soc_codec = (aw_snd_soc_codec_t *)codec; -+ char *kctl_name[AW87XXX_PUBLIC_KCONTROL_NUM]; -+ int kcontrol_num = AW87XXX_PUBLIC_KCONTROL_NUM; -+ int ret = -1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx->codec = soc_codec; -+ -+ aw87xxx_kcontrol = devm_kzalloc(aw87xxx->dev, -+ sizeof(struct snd_kcontrol_new) * kcontrol_num, -+ GFP_KERNEL); -+ if (aw87xxx_kcontrol == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "aw87xxx_kcontrol devm_kzalloc failed"); -+ return -ENOMEM; -+ } -+ -+ kctl_name[0] = devm_kzalloc(aw87xxx->dev, AW_NAME_BUF_MAX, -+ GFP_KERNEL); -+ if (kctl_name[0] == NULL) -+ return -ENOMEM; -+ -+ snprintf(kctl_name[0], AW_NAME_BUF_MAX, "aw87xxx_spin_switch"); -+ -+ aw87xxx_kcontrol[0].name = kctl_name[0]; -+ aw87xxx_kcontrol[0].iface = SNDRV_CTL_ELEM_IFACE_MIXER; -+ aw87xxx_kcontrol[0].info = aw87xxx_spin_switch_info; -+ aw87xxx_kcontrol[0].get = aw87xxx_spin_switch_get; -+ aw87xxx_kcontrol[0].put = aw87xxx_spin_switch_put; -+ aw87xxx_kcontrol[0].private_value = (unsigned long)aw87xxx; -+ -+ ret = aw_componet_codec_ops.add_codec_controls(aw87xxx->codec, -+ aw87xxx_kcontrol, kcontrol_num); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "add codec controls failed, ret = %d", -+ ret); -+ return ret; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "add public codec controls[%s]", -+ aw87xxx_kcontrol[0].name); -+ -+ return 0; -+} -+ -+/**************************************************************************** -+ * -+ *aw87xxx kcontrol create -+ * -+ ****************************************************************************/ -+int aw87xxx_add_codec_controls(void *codec) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = NULL; -+ int ret = -1; -+ -+ list_for_each(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ ret = aw87xxx_kcontrol_dynamic_create(aw87xxx, codec); -+ if (ret < 0) -+ return ret; -+ -+ if (aw87xxx->dev_index == 0) { -+ ret = aw87xxx_public_kcontrol_create(aw87xxx, codec); -+ if (ret < 0) -+ return ret; -+ } -+ } -+ -+ return 0; -+} -+EXPORT_SYMBOL(aw87xxx_add_codec_controls); -+ -+ -+/**************************************************************************** -+ * -+ * aw87xxx firmware cfg load -+ * -+ ***************************************************************************/ -+static void aw87xxx_fw_cfg_free(struct aw87xxx *aw87xxx) -+{ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ aw87xxx_acf_profile_free(aw87xxx->dev, &aw87xxx->acf_info); -+ aw87xxx_monitor_cfg_free(&aw87xxx->monitor); -+} -+ -+static int aw87xxx_init_default_prof(struct aw87xxx *aw87xxx) -+{ -+ char *profile = NULL; -+ -+ profile = aw87xxx_acf_get_prof_off_name(aw87xxx->dev, &aw87xxx->acf_info); -+ if (profile == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "get profile off name failed"); -+ return -EINVAL; -+ } -+ -+ snprintf(aw87xxx->prof_off_name, AW_PROFILE_STR_MAX, "%s", profile); -+ aw87xxx->current_profile = profile; -+ AW_DEV_LOGI(aw87xxx->dev, "init profile name [%s]", -+ aw87xxx->current_profile); -+ -+ return 0; -+} -+ -+static void aw87xxx_fw_load_retry(struct aw87xxx *aw87xxx) -+{ -+ struct acf_bin_info *acf_info = &aw87xxx->acf_info; -+ int ram_timer_val = 2000; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "failed to read [%s]", -+ aw87xxx->fw_name); -+ -+ if (acf_info->load_count < AW_LOAD_FW_RETRIES) { -+ AW_DEV_LOGD(aw87xxx->dev, -+ "restart hrtimer to load firmware"); -+ schedule_delayed_work(&aw87xxx->fw_load_work, -+ msecs_to_jiffies(ram_timer_val)); -+ } else { -+ acf_info->load_count = 0; -+ AW_DEV_LOGE(aw87xxx->dev, -+ "can not load firmware,please check name or file exists"); -+ return; -+ } -+ acf_info->load_count++; -+} -+ -+static void aw87xxx_fw_load(const struct firmware *fw, void *context) -+{ -+ int ret = -1; -+ struct aw87xxx *aw87xxx = context; -+ struct acf_bin_info *acf_info = &aw87xxx->acf_info; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (!fw) { -+ aw87xxx_fw_load_retry(aw87xxx); -+ return; -+ } -+ -+ AW_DEV_LOGD(aw87xxx->dev, "loaded %s - size: %ld", -+ aw87xxx->fw_name, (u_long)(fw ? fw->size : 0)); -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ acf_info->fw_data = vmalloc(fw->size); -+ if (!acf_info->fw_data) { -+ AW_DEV_LOGE(aw87xxx->dev, "fw_data kzalloc memory failed"); -+ goto exit_vmalloc_failed; -+ } -+ memset(acf_info->fw_data, 0, fw->size); -+ memcpy(acf_info->fw_data, fw->data, fw->size); -+ acf_info->fw_size = fw->size; -+ -+ ret = aw87xxx_acf_parse(aw87xxx->dev, &aw87xxx->acf_info); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "fw_data parse failed"); -+ goto exit_acf_parse_failed; -+ } -+ -+ ret = aw87xxx_init_default_prof(aw87xxx); -+ if (ret < 0) { -+ aw87xxx_fw_cfg_free(aw87xxx); -+ goto exit_acf_parse_failed; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "acf parse succeed"); -+ mutex_unlock(&aw87xxx->reg_lock); -+ release_firmware(fw); -+ // Updating profile to "Music" because the firmware is set to "off" during init -+ aw87xxx_update_profile(aw87xxx, AW87XXX_PROF_MUSIC); -+ -+ return; -+ -+exit_acf_parse_failed: -+exit_vmalloc_failed: -+ release_firmware(fw); -+ mutex_unlock(&aw87xxx->reg_lock); -+} -+ -+static void aw87xxx_fw_load_work_routine(struct work_struct *work) -+{ -+ struct aw87xxx *aw87xxx = container_of(work, -+ struct aw87xxx, fw_load_work.work); -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ -+ if (prof_info->status == AW_ACF_WAIT) { -+ request_firmware_nowait(THIS_MODULE, -+// FW_ACTION_HOTPLUG, -+ FW_ACTION_UEVENT, -+ aw87xxx->fw_name, -+ aw87xxx->dev, -+ GFP_KERNEL, aw87xxx, -+ aw87xxx_fw_load); -+ } -+} -+ -+static void aw87xxx_fw_load_init(struct aw87xxx *aw87xxx) -+{ -+#ifdef AW_CFG_UPDATE_DELAY -+ int cfg_timer_val = AW_CFG_UPDATE_DELAY_TIMER; -+#else -+ int cfg_timer_val = 0; -+#endif -+ AW_DEV_LOGI(aw87xxx->dev, "enter"); -+ snprintf(aw87xxx->fw_name, AW87XXX_FW_NAME_MAX, "%s", AW87XXX_FW_BIN_NAME); -+ aw87xxx_acf_init(&aw87xxx->aw_dev, &aw87xxx->acf_info, aw87xxx->dev_index); -+ -+ INIT_DELAYED_WORK(&aw87xxx->fw_load_work, aw87xxx_fw_load_work_routine); -+ schedule_delayed_work(&aw87xxx->fw_load_work, -+ msecs_to_jiffies(cfg_timer_val)); -+} -+ -+/**************************************************************************** -+ * -+ *aw87xxx attribute node -+ * -+ ****************************************************************************/ -+static ssize_t aw87xxx_attr_get_reg(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ int ret = 0; -+ unsigned int i = 0; -+ unsigned char reg_val = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_device *aw_dev = &aw87xxx->aw_dev; -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ for (i = 0; i < aw_dev->reg_max_addr; i++) { -+ if (!(aw_dev->reg_access[i] & AW_DEV_REG_RD_ACCESS)) -+ continue; -+ ret = aw87xxx_dev_i2c_read_byte(&aw87xxx->aw_dev, i, ®_val); -+ if (ret < 0) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "read reg [0x%x] failed\n", i); -+ AW_DEV_LOGE(aw87xxx->dev, "read reg [0x%x] failed", i); -+ } else { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "reg:0x%02X=0x%02X\n", i, reg_val); -+ AW_DEV_LOGD(aw87xxx->dev, "reg:0x%02X=0x%02X", -+ i, reg_val); -+ } -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_reg(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ unsigned int databuf[2] = { 0 }; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ if (sscanf(buf, "0x%x 0x%x", &databuf[0], &databuf[1]) == 2) { -+ if (databuf[0] >= aw87xxx->aw_dev.reg_max_addr) { -+ AW_DEV_LOGE(aw87xxx->dev, "set reg[0x%x] error,is out of reg_addr_max[0x%x]", -+ databuf[0], aw87xxx->aw_dev.reg_max_addr); -+ mutex_unlock(&aw87xxx->reg_lock); -+ return -EINVAL; -+ } -+ -+ ret = aw87xxx_dev_i2c_write_byte(&aw87xxx->aw_dev, -+ databuf[0], databuf[1]); -+ if (ret < 0) -+ AW_DEV_LOGE(aw87xxx->dev, "set [0x%x]=0x%x failed", -+ databuf[0], databuf[1]); -+ else -+ AW_DEV_LOGD(aw87xxx->dev, "set [0x%x]=0x%x succeed", -+ databuf[0], databuf[1]); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "i2c write cmd input error"); -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_get_profile(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ unsigned int i = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_prof_info *prof_info = &aw87xxx->acf_info.prof_info; -+ -+ if (!prof_info->status) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "profile_cfg not load\n"); -+ return len; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "current profile:[%s]", aw87xxx->current_profile); -+ -+ for (i = 0; i < prof_info->count; i++) { -+ if (!strncmp(aw87xxx->current_profile, prof_info->prof_name_list[i], -+ AW_PROFILE_STR_MAX)) -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ ">%s\n", prof_info->prof_name_list[i]); -+ else -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ " %s\n", prof_info->prof_name_list[i]); -+ } -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_profile(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ char profile[AW_PROFILE_STR_MAX] = {0}; -+ int ret = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ if (strlen(buf) > AW_PROFILE_STR_MAX) { -+ AW_DEV_LOGE(aw87xxx->dev, "input profile_str_len is out of max[%d]", -+ AW_PROFILE_STR_MAX); -+ return -EINVAL; -+ } -+ -+ if (sscanf(buf, "%s", profile) == 1) { -+ AW_DEV_LOGD(aw87xxx->dev, "set profile [%s]", profile); -+ ret = aw87xxx_update_profile(aw87xxx, profile); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "set profile[%s] failed", -+ profile); -+ return ret; -+ } -+ } -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_get_hwen(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ int hwen = aw87xxx->aw_dev.hwen_status; -+ -+ if (hwen >= AW_DEV_HWEN_INVALID) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: invalid\n"); -+ else if (hwen == AW_DEV_HWEN_ON) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: on\n"); -+ else if (hwen == AW_DEV_HWEN_OFF) -+ len += snprintf(buf + len, PAGE_SIZE - len, "hwen_status: off\n"); -+ -+ return len; -+} -+ -+static ssize_t aw87xxx_attr_set_hwen(struct device *dev, -+ struct device_attribute *attr, const char *buf, -+ size_t len) -+{ -+ int ret = -1; -+ unsigned int state; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ ret = kstrtouint(buf, 0, &state); -+ if (ret) { -+ AW_DEV_LOGE(aw87xxx->dev, "fail to channelge str to int"); -+ return ret; -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ if (state == AW_DEV_HWEN_OFF) -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); /*OFF*/ -+ else if (state == AW_DEV_HWEN_ON) -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); /*ON*/ -+ else -+ AW_DEV_LOGE(aw87xxx->dev, "input [%d] error, hwen_on=[%d],hwen_off=[%d]", -+ state, AW_DEV_HWEN_ON, AW_DEV_HWEN_OFF); -+ mutex_unlock(&aw87xxx->reg_lock); -+ return len; -+} -+ -+int aw87xxx_awrw_write(struct aw87xxx *aw87xxx, -+ const char *buf, size_t count) -+{ -+ int i = 0, ret = -1; -+ char *data_buf = NULL; -+ int buf_len = 0; -+ int temp_data = 0; -+ int data_str_size = 0; -+ char *reg_data; -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "enter"); -+ /* one addr or one data string Composition of Contains two bytes of symbol(0X)*/ -+ /* and two byte of hexadecimal data*/ -+ data_str_size = 2 + 2 * AWRW_DATA_BYTES; -+ -+ /* The buf includes the first address of the register to be written and all data */ -+ buf_len = AWRW_ADDR_BYTES + packet->reg_num * AWRW_DATA_BYTES; -+ AW_DEV_LOGI(aw87xxx->dev, "buf_len = %d,reg_num = %d", buf_len, packet->reg_num); -+ data_buf = vmalloc(buf_len); -+ if (data_buf == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "alloc memory failed"); -+ return -ENOMEM; -+ } -+ memset(data_buf, 0, buf_len); -+ -+ data_buf[0] = packet->reg_addr; -+ reg_data = data_buf + 1; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "reg_addr: 0x%02x", data_buf[0]); -+ -+ /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -+ for (i = 0; i < packet->reg_num; i++) { -+ ret = sscanf(buf + AWRW_HDR_LEN + 1 + i * (data_str_size + 1), -+ "0x%x", &temp_data); -+ if (ret != 1) { -+ AW_DEV_LOGE(aw87xxx->dev, "sscanf failed,ret=%d", ret); -+ vfree(data_buf); -+ data_buf = NULL; -+ return ret; -+ } -+ reg_data[i] = temp_data; -+ AW_DEV_LOGD(aw87xxx->dev, "[%d] : 0x%02x", i, reg_data[i]); -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ ret = i2c_master_send(aw87xxx->aw_dev.i2c, data_buf, buf_len); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "write failed"); -+ vfree(data_buf); -+ data_buf = NULL; -+ return -EFAULT; -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ vfree(data_buf); -+ data_buf = NULL; -+ -+ AW_DEV_LOGD(aw87xxx->dev, "down"); -+ return 0; -+} -+ -+static int aw87xxx_awrw_data_check(struct aw87xxx *aw87xxx, -+ int *data, size_t count) -+{ -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int req_data_len = 0; -+ int act_data_len = 0; -+ int data_str_size = 0; -+ -+ if ((data[AWRW_HDR_ADDR_BYTES] != AWRW_ADDR_BYTES) || -+ (data[AWRW_HDR_DATA_BYTES] != AWRW_DATA_BYTES)) { -+ AW_DEV_LOGE(aw87xxx->dev, "addr_bytes [%d] or data_bytes [%d] unsupport", -+ data[AWRW_HDR_ADDR_BYTES], data[AWRW_HDR_DATA_BYTES]); -+ return -EINVAL; -+ } -+ -+ /* one data string Composition of Contains two bytes of symbol(0x)*/ -+ /* and two byte of hexadecimal data*/ -+ data_str_size = 2 + 2 * AWRW_DATA_BYTES; -+ act_data_len = count - AWRW_HDR_LEN - 1; -+ -+ /* There is a comma(,) or space between each piece of data */ -+ if (data[AWRW_HDR_WR_FLAG] == AWRW_FLAG_WRITE) { -+ /*ag:0x00 0x01 0x01 0x01 0x01 0x00\x0a*/ -+ req_data_len = (data_str_size + 1) * packet->reg_num; -+ if (req_data_len > act_data_len) { -+ AW_DEV_LOGE(aw87xxx->dev, "data_len checkfailed,requeset data_len [%d],actaul data_len [%d]", -+ req_data_len, act_data_len); -+ return -EINVAL; -+ } -+ } -+ -+ return 0; -+} -+ -+/* flag addr_bytes data_bytes reg_num reg_addr*/ -+static int aw87xxx_awrw_parse_buf(struct aw87xxx *aw87xxx, -+ const char *buf, size_t count, int *wr_status) -+{ -+ int data[AWRW_HDR_MAX] = {0}; -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int ret = -1; -+ -+ if (sscanf(buf, "0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", -+ &data[AWRW_HDR_WR_FLAG], &data[AWRW_HDR_ADDR_BYTES], -+ &data[AWRW_HDR_DATA_BYTES], &data[AWRW_HDR_REG_NUM], -+ &data[AWRW_HDR_REG_ADDR]) == 5) { -+ -+ packet->reg_addr = data[AWRW_HDR_REG_ADDR]; -+ packet->reg_num = data[AWRW_HDR_REG_NUM]; -+ *wr_status = data[AWRW_HDR_WR_FLAG]; -+ ret = aw87xxx_awrw_data_check(aw87xxx, data, count); -+ if (ret < 0) -+ return ret; -+ -+ return 0; -+ } -+ -+ return -EINVAL; -+} -+ -+static ssize_t aw87xxx_attr_awrw_store(struct device *dev, -+ struct device_attribute *attr, const char *buf, size_t count) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int wr_status = 0; -+ int ret = -1; -+ -+ if (count < AWRW_HDR_LEN) { -+ AW_DEV_LOGE(aw87xxx->dev, "data count too smaller, please check write format"); -+ AW_DEV_LOGE(aw87xxx->dev, "string %s,count=%ld", -+ buf, (u_long)count); -+ return -EINVAL; -+ } -+ -+ AW_DEV_LOGI(aw87xxx->dev, "string:[%s],count=%ld", buf, (u_long)count); -+ ret = aw87xxx_awrw_parse_buf(aw87xxx, buf, count, &wr_status); -+ if (ret < 0) { -+ AW_DEV_LOGE(aw87xxx->dev, "can not parse string"); -+ return ret; -+ } -+ -+ if (wr_status == AWRW_FLAG_WRITE) { -+ ret = aw87xxx_awrw_write(aw87xxx, buf, count); -+ if (ret < 0) -+ return ret; -+ } else if (wr_status == AWRW_FLAG_READ) { -+ packet->status = AWRW_I2C_ST_READ; -+ AW_DEV_LOGI(aw87xxx->dev, "read_cmd:reg_addr[0x%02x], reg_num[%d]", -+ packet->reg_addr, packet->reg_num); -+ } else { -+ AW_DEV_LOGE(aw87xxx->dev, "please check str format, unsupport read_write_status: %d", -+ wr_status); -+ return -EINVAL; -+ } -+ -+ return count; -+} -+ -+static ssize_t aw87xxx_attr_awrw_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ struct aw_i2c_packet *packet = &aw87xxx->i2c_packet; -+ int data_len = 0; -+ size_t len = 0; -+ int ret = -1, i = 0; -+ char *reg_data = NULL; -+ -+ if (packet->status != AWRW_I2C_ST_READ) { -+ AW_DEV_LOGE(aw87xxx->dev, "please write read cmd first"); -+ return -EINVAL; -+ } -+ -+ data_len = AWRW_DATA_BYTES * packet->reg_num; -+ reg_data = (char *)vmalloc(data_len); -+ if (reg_data == NULL) { -+ AW_DEV_LOGE(aw87xxx->dev, "memory alloc failed"); -+ ret = -EINVAL; -+ goto exit; -+ } -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ ret = aw87xxx_dev_i2c_read_msg(&aw87xxx->aw_dev, packet->reg_addr, -+ (char *)reg_data, data_len); -+ if (ret < 0) { -+ ret = -EFAULT; -+ mutex_unlock(&aw87xxx->reg_lock); -+ goto exit; -+ } -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ AW_DEV_LOGI(aw87xxx->dev, "reg_addr 0x%02x, reg_num %d", -+ packet->reg_addr, packet->reg_num); -+ -+ for (i = 0; i < data_len; i++) { -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "0x%02x,", reg_data[i]); -+ AW_DEV_LOGI(aw87xxx->dev, "0x%02x", reg_data[i]); -+ } -+ -+ ret = len; -+ -+exit: -+ if (reg_data) { -+ vfree(reg_data); -+ reg_data = NULL; -+ } -+ packet->status = AWRW_I2C_ST_NONE; -+ return ret; -+} -+ -+static ssize_t aw87xxx_drv_ver_show(struct device *dev, -+ struct device_attribute *attr, char *buf) -+{ -+ ssize_t len = 0; -+ -+ len += snprintf(buf + len, PAGE_SIZE - len, -+ "driver_ver: %s \n", AW87XXX_DRIVER_VERSION); -+ -+ return len; -+} -+ -+static DEVICE_ATTR(reg, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_reg, aw87xxx_attr_set_reg); -+static DEVICE_ATTR(profile, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_profile, aw87xxx_attr_set_profile); -+static DEVICE_ATTR(hwen, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_get_hwen, aw87xxx_attr_set_hwen); -+static DEVICE_ATTR(awrw, S_IWUSR | S_IRUGO, -+ aw87xxx_attr_awrw_show, aw87xxx_attr_awrw_store); -+static DEVICE_ATTR(drv_ver, S_IRUGO, aw87xxx_drv_ver_show, NULL); -+ -+static struct attribute *aw87xxx_attributes[] = { -+ &dev_attr_reg.attr, -+ &dev_attr_profile.attr, -+ &dev_attr_hwen.attr, -+ &dev_attr_awrw.attr, -+ &dev_attr_drv_ver.attr, -+ NULL -+}; -+ -+static struct attribute_group aw87xxx_attribute_group = { -+ .attrs = aw87xxx_attributes -+}; -+ -+/**************************************************************************** -+ * -+ *aw87xxx device probe -+ * -+ ****************************************************************************/ -+static const struct acpi_gpio_params reset_gpio = { 0, 0, false }; -+static const struct acpi_gpio_mapping reset_acpi_gpios[] = { -+ { "reset-gpios", &reset_gpio, 1 }, -+ { } -+}; -+ -+static struct aw87xxx *aw87xxx_malloc_init(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = NULL; -+ -+ aw87xxx = devm_kzalloc(&client->dev, sizeof(struct aw87xxx), -+ GFP_KERNEL); -+ if (aw87xxx == NULL) { -+ AW_DEV_LOGE(&client->dev, "failed to devm_kzalloc aw87xxx"); -+ return NULL; -+ } -+ memset(aw87xxx, 0, sizeof(struct aw87xxx)); -+ -+ aw87xxx->dev = &client->dev; -+ aw87xxx->aw_dev.dev = &client->dev; -+ aw87xxx->aw_dev.i2c_bus = client->adapter->nr; -+ aw87xxx->aw_dev.i2c_addr = client->addr; -+ aw87xxx->aw_dev.i2c = client; -+ aw87xxx->aw_dev.hwen_status = false; -+ aw87xxx->aw_dev.reg_access = NULL; -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -+ aw87xxx->off_bin_status = AW87XXX_NO_OFF_BIN; -+ aw87xxx->codec = NULL; -+ aw87xxx->current_profile = aw87xxx->prof_off_name; -+ -+ mutex_init(&aw87xxx->reg_lock); -+ -+ AW_DEV_LOGI(&client->dev, "Driver struct alloc and mutex init done, devinfo: i2c_bus=%u, i2c_addr=%x", client->adapter->nr, client->addr); -+ return aw87xxx; -+} -+ -+static int aw87xxx_i2c_probe(struct i2c_client *client) -+{ -+ struct device_node *dev_node = client->dev.of_node; -+ struct aw87xxx *aw87xxx = NULL; -+ struct gpio_desc *gpiod = NULL; -+ int ret = -1; -+ -+ -+// To do, add this function -+//acpi_dev_add_driver_gpios() -+ -+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { -+ AW_DEV_LOGE(&client->dev, "check_functionality failed"); -+ ret = -ENODEV; -+ goto exit_check_functionality_failed; -+ } -+ -+ /* aw87xxx i2c_dev struct init */ -+ aw87xxx = aw87xxx_malloc_init(client); -+ if (aw87xxx == NULL) -+ goto exit_malloc_init_failed; -+ -+ i2c_set_clientdata(client, aw87xxx); -+ -+ aw87xxx_device_parse_port_id_dt(&aw87xxx->aw_dev); -+ aw87xxx_device_parse_topo_id_dt(&aw87xxx->aw_dev); -+ -+ /* aw87xxx Get ACPI GPIO */ -+/* -+ ret = devm_acpi_dev_add_driver_gpios(aw87xxx->dev, reset_acpi_gpios); -+ if(ret){ -+ AW_DEV_LOGE(aw87xxx->dev, "Unable to add GPIO mapping table"); -+ goto exit_device_init_failed; -+ } -+ -+ gpiod = gpiod_get_optional(aw87xxx->dev, "reset", GPIOD_OUT_LOW); -+*/ -+ -+ if (g_aw87xxx_dev_cnt == 0){ -+ gpiod = gpiod_get(aw87xxx->dev, NULL, GPIOD_OUT_LOW); -+ if (gpiod == NULL){ -+ AW_DEV_LOGE(aw87xxx->dev, "Gpiod returned NULL failing gracefully."); -+ goto exit_device_init_failed; -+ } -+ -+ if (IS_ERR(gpiod)){ -+ AW_DEV_LOGE(aw87xxx->dev, "Get gpiod failed."); -+ goto exit_device_init_failed; -+ } -+ -+ aw87xxx->aw_dev.rst_gpio = desc_to_gpio(gpiod); -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_OFF; -+ AW_DEV_LOGI(aw87xxx->dev, "reset gpio[%x] parse succeed", aw87xxx->aw_dev.rst_gpio); -+ -+ if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio)) { -+ ret = devm_gpio_request_one(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio, GPIOF_OUT_INIT_LOW, "aw87xxx_reset"); -+ if ((ret < 0) && (ret != -EBUSY)) { -+ AW_DEV_LOGE(aw87xxx->dev, "reset request failed, returned [%d]", ret); -+ goto exit_device_init_failed; -+ } -+ }else{ -+ /*Disabling RESET GPIO*/ -+ AW_DEV_LOGI(aw87xxx->dev, "no reset gpio provided, hardware reset unavailable"); -+ aw87xxx->aw_dev.rst_gpio = AW_NO_RESET_GPIO; -+ aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_INVALID; -+ } -+ -+ } -+ /*hw power on PA*/ -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ -+ /* aw87xxx devices private attributes init */ -+ ret = aw87xxx_dev_init(&aw87xxx->aw_dev); -+ if (ret < 0) -+ goto exit_device_init_failed; -+ -+ /*product register reset */ -+ aw87xxx_dev_soft_reset(&aw87xxx->aw_dev); -+ -+ /*hw power off */ -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ -+ /* create debug attrbute nodes */ -+ ret = sysfs_create_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -+ if (ret < 0) -+ AW_DEV_LOGE(aw87xxx->dev, "failed to create sysfs nodes, will not allowed to use"); -+ -+ /* cfg_load init */ -+ aw87xxx_fw_load_init(aw87xxx); -+ -+ /*monitor init*/ -+ aw87xxx_monitor_init(aw87xxx->dev, &aw87xxx->monitor, dev_node); -+ -+ /*add device to total list */ -+ mutex_lock(&g_aw87xxx_mutex_lock); -+ g_aw87xxx_dev_cnt++; -+ list_add(&aw87xxx->list, &g_aw87xxx_list); -+ aw87xxx->dev_index = g_aw87xxx_dev_cnt; -+ -+ mutex_unlock(&g_aw87xxx_mutex_lock); -+ AW_DEV_LOGI(aw87xxx->dev, "succeed, dev_index=[%d], g_aw87xxx_dev_cnt= [%d]", -+ aw87xxx->dev_index, g_aw87xxx_dev_cnt); -+ -+ return 0; -+ -+exit_device_init_failed: -+ AW_DEV_LOGE(aw87xxx->dev, "pa init failed"); -+ -+ devm_kfree(&client->dev, aw87xxx); -+ aw87xxx = NULL; -+exit_malloc_init_failed: -+exit_check_functionality_failed: -+ return ret; -+} -+ -+static void aw87xxx_i2c_remove(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -+ -+ aw87xxx_monitor_exit(&aw87xxx->monitor); -+ -+ /*rm attr node*/ -+ sysfs_remove_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -+ -+ aw87xxx_fw_cfg_free(aw87xxx); -+ -+ mutex_lock(&g_aw87xxx_mutex_lock); -+ g_aw87xxx_dev_cnt--; -+ list_del(&aw87xxx->list); -+ mutex_unlock(&g_aw87xxx_mutex_lock); -+ -+ devm_kfree(&client->dev, aw87xxx); -+ aw87xxx = NULL; -+ -+// return 0; -+} -+ -+static void aw87xxx_i2c_shutdown(struct i2c_client *client) -+{ -+ struct aw87xxx *aw87xxx = i2c_get_clientdata(client); -+ -+ AW_DEV_LOGI(&client->dev, "enter"); -+ -+ /*soft and hw power off*/ -+ aw87xxx_update_profile(aw87xxx, aw87xxx->prof_off_name); -+} -+ -+static const struct acpi_device_id aw87xxx_acpi_match[] = { -+ { "AWDZ8830", 0 }, -+ { } -+}; -+MODULE_DEVICE_TABLE(acpi, aw87xxx_acpi_match); -+ -+// This is not necessary if the acpi match probes correctly. This is needed for userspace `new_device() functionality -+static const struct i2c_device_id aw87xxx_i2c_id[] = { -+ {AW87XXX_I2C_NAME, 0}, -+ {}, -+}; -+ -+static struct i2c_driver aw87xxx_i2c_driver = { -+ .driver = { -+ .owner = THIS_MODULE, -+ .name = AW87XXX_I2C_NAME, -+ .acpi_match_table = aw87xxx_acpi_match, -+ }, -+ .probe = aw87xxx_i2c_probe, -+ .remove = aw87xxx_i2c_remove, -+ .shutdown = aw87xxx_i2c_shutdown, -+ .id_table = aw87xxx_i2c_id, -+}; -+ -+module_i2c_driver(aw87xxx_i2c_driver) -+ -+MODULE_AUTHOR("<zhaozhongbo@awinic.com>"); -+MODULE_DESCRIPTION("awinic aw87xxx pa driver"); -+MODULE_LICENSE("GPL v2"); -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx_device.c b/sound/soc/codecs/aw87xxx/aw87xxx_device.c -index 087770857..5874c598a 100644 ---- a/sound/soc/codecs/aw87xxx/aw87xxx_device.c -+++ b/sound/soc/codecs/aw87xxx/aw87xxx_device.c -@@ -102,8 +102,8 @@ int aw87xxx_dev_i2c_write_byte(struct aw_device *aw_dev, - while (cnt < AW_I2C_RETRIES) { - ret = i2c_smbus_write_byte_data(aw_dev->i2c, reg_addr, reg_data); - if (ret < 0) -- AW_DEV_LOGE(aw_dev->dev, "i2c_write cnt=%d error=%d", -- cnt, ret); -+ AW_DEV_LOGE(aw_dev->dev, "i2c_write cnt=%d error=%d i2c_bus=%u i2c_addr=%X chipid=%X", -+ cnt, ret, aw_dev->i2c_bus, aw_dev->i2c_addr, aw_dev->chipid); - else - break; - -@@ -123,8 +123,8 @@ int aw87xxx_dev_i2c_read_byte(struct aw_device *aw_dev, - while (cnt < AW_I2C_RETRIES) { - ret = i2c_smbus_read_byte_data(aw_dev->i2c, reg_addr); - if (ret < 0) { -- AW_DEV_LOGE(aw_dev->dev, "i2c_read cnt=%d error=%d", -- cnt, ret); -+ AW_DEV_LOGE(aw_dev->dev, "i2c_read cnt=%d error=%d i2c_bus=%u i2c_addr=%X chipid=%X", -+ cnt, ret, aw_dev->i2c_bus, aw_dev->i2c_addr, aw_dev->chipid); - } else { - *reg_data = ret; - break; --- -2.45.2 - - -From c929d4f9c7be7599522d39d207c77006d96dc70c Mon Sep 17 00:00:00 2001 -From: CVMagic <546352+CVMagic@users.noreply.github.com> -Date: Sun, 19 May 2024 21:37:37 +0200 -Subject: [PATCH 3/8] Updated AW87xxx driver to automatically enumerate a - second I2C chip if specified in ACPI - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/soc/codecs/aw87xxx/aw87xxx.c | 80 ++++++++++++++++++++++-------- - 1 file changed, 58 insertions(+), 22 deletions(-) - -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx.c b/sound/soc/codecs/aw87xxx/aw87xxx.c -index 7f44d9b9d..8b3e74a7b 100644 ---- a/sound/soc/codecs/aw87xxx/aw87xxx.c -+++ b/sound/soc/codecs/aw87xxx/aw87xxx.c -@@ -82,6 +82,22 @@ static struct aw_componet_codec_ops aw_componet_codec_ops = { - }; - #endif - -+enum smi_bus_type { -+ SMI_I2C, -+ SMI_SPI, -+ SMI_AUTO_DETECT, -+}; -+ -+struct smi_instance { -+ const char *type; -+ unsigned int flags; -+ int irq_idx; -+}; -+ -+struct smi_node { -+ enum smi_bus_type bus_type; -+ struct smi_instance instances[]; -+}; - - /************************************************************************ - * -@@ -1291,13 +1307,20 @@ static struct aw87xxx *aw87xxx_malloc_init(struct i2c_client *client) - static int aw87xxx_i2c_probe(struct i2c_client *client) - { - struct device_node *dev_node = client->dev.of_node; -+ const struct smi_node *node; -+ struct acpi_device *adev = ACPI_COMPANION(&client->dev); - struct aw87xxx *aw87xxx = NULL; - struct gpio_desc *gpiod = NULL; -+ struct i2c_board_info board_info = {}; -+ char i2c_name[32]; - int ret = -1; -+ int acpi_dev_count = 0; - -- --// To do, add this function --//acpi_dev_add_driver_gpios() -+ /* aw87xxx Get APCI I2C device count */ -+ if(g_aw87xxx_dev_cnt == 0){ -+ acpi_dev_count = i2c_acpi_client_count(adev); -+ AW_DEV_LOGI(&client->dev, "I2C_ACPI_CLIENT_COUNT returned [%d]", acpi_dev_count); -+ } - - if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { - AW_DEV_LOGE(&client->dev, "check_functionality failed"); -@@ -1316,18 +1339,15 @@ static int aw87xxx_i2c_probe(struct i2c_client *client) - aw87xxx_device_parse_topo_id_dt(&aw87xxx->aw_dev); - - /* aw87xxx Get ACPI GPIO */ --/* -- ret = devm_acpi_dev_add_driver_gpios(aw87xxx->dev, reset_acpi_gpios); -- if(ret){ -- AW_DEV_LOGE(aw87xxx->dev, "Unable to add GPIO mapping table"); -- goto exit_device_init_failed; -- } -- -- gpiod = gpiod_get_optional(aw87xxx->dev, "reset", GPIOD_OUT_LOW); --*/ - - if (g_aw87xxx_dev_cnt == 0){ -- gpiod = gpiod_get(aw87xxx->dev, NULL, GPIOD_OUT_LOW); -+ ret = devm_acpi_dev_add_driver_gpios(aw87xxx->dev, reset_acpi_gpios); -+ if(ret){ -+ AW_DEV_LOGE(aw87xxx->dev, "Unable to add GPIO mapping table"); -+ goto exit_device_init_failed; -+ } -+ -+ gpiod = devm_gpiod_get(aw87xxx->dev, "reset", GPIOD_OUT_LOW); - if (gpiod == NULL){ - AW_DEV_LOGE(aw87xxx->dev, "Gpiod returned NULL failing gracefully."); - goto exit_device_init_failed; -@@ -1342,13 +1362,7 @@ static int aw87xxx_i2c_probe(struct i2c_client *client) - aw87xxx->aw_dev.hwen_status = AW_DEV_HWEN_OFF; - AW_DEV_LOGI(aw87xxx->dev, "reset gpio[%x] parse succeed", aw87xxx->aw_dev.rst_gpio); - -- if (gpio_is_valid(aw87xxx->aw_dev.rst_gpio)) { -- ret = devm_gpio_request_one(aw87xxx->dev, aw87xxx->aw_dev.rst_gpio, GPIOF_OUT_INIT_LOW, "aw87xxx_reset"); -- if ((ret < 0) && (ret != -EBUSY)) { -- AW_DEV_LOGE(aw87xxx->dev, "reset request failed, returned [%d]", ret); -- goto exit_device_init_failed; -- } -- }else{ -+ if (!gpio_is_valid(aw87xxx->aw_dev.rst_gpio)) { - /*Disabling RESET GPIO*/ - AW_DEV_LOGI(aw87xxx->dev, "no reset gpio provided, hardware reset unavailable"); - aw87xxx->aw_dev.rst_gpio = AW_NO_RESET_GPIO; -@@ -1356,8 +1370,11 @@ static int aw87xxx_i2c_probe(struct i2c_client *client) - } - - } -+ - /*hw power on PA*/ -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ if(g_aw87xxx_dev_cnt == 0) { -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ } - - /* aw87xxx devices private attributes init */ - ret = aw87xxx_dev_init(&aw87xxx->aw_dev); -@@ -1368,7 +1385,9 @@ static int aw87xxx_i2c_probe(struct i2c_client *client) - aw87xxx_dev_soft_reset(&aw87xxx->aw_dev); - - /*hw power off */ -- aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ if(g_aw87xxx_dev_cnt == 0) { -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, false); -+ } - - /* create debug attrbute nodes */ - ret = sysfs_create_group(&aw87xxx->dev->kobj, &aw87xxx_attribute_group); -@@ -1391,6 +1410,23 @@ static int aw87xxx_i2c_probe(struct i2c_client *client) - AW_DEV_LOGI(aw87xxx->dev, "succeed, dev_index=[%d], g_aw87xxx_dev_cnt= [%d]", - aw87xxx->dev_index, g_aw87xxx_dev_cnt); - -+ AW_DEV_LOGI(aw87xxx->dev, "acpi_c=[%d] dev_c=[%d]", acpi_dev_count, g_aw87xxx_dev_cnt); -+ -+ /* Attempt to add other I2C AMPs */ -+ if ((acpi_dev_count > 1) && (g_aw87xxx_dev_cnt == 1)){ -+ /* power on the chip */ -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ -+ node = device_get_match_data(aw87xxx->dev); -+ memset(&board_info, 0, sizeof(board_info)); -+ strscpy(board_info.type, client->name, I2C_NAME_SIZE); -+ snprintf(i2c_name, sizeof(i2c_name), "%s.%d", client->name, 1); -+ board_info.dev_name = i2c_name; -+ -+ aw87xxx_i2c_probe(i2c_acpi_new_device_by_fwnode(acpi_fwnode_handle(adev), 1, &board_info)); -+ -+ } -+ - return 0; - - exit_device_init_failed: --- -2.45.2 - - -From e67153f0c9b2c66e66334c59136ecc244139e555 Mon Sep 17 00:00:00 2001 -From: CVMagic <546352+CVMagic@users.noreply.github.com> -Date: Wed, 22 May 2024 02:42:40 +0000 -Subject: [PATCH 4/8] Updated AW87xxx driver to implement Suspend and Resume. - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/soc/codecs/aw87xxx/aw87xxx.c | 39 ++++++++++++++++++++++++++++++ - 1 file changed, 39 insertions(+) - -diff --git a/sound/soc/codecs/aw87xxx/aw87xxx.c b/sound/soc/codecs/aw87xxx/aw87xxx.c -index 8b3e74a7b..134a9a750 100644 ---- a/sound/soc/codecs/aw87xxx/aw87xxx.c -+++ b/sound/soc/codecs/aw87xxx/aw87xxx.c -@@ -1471,6 +1471,44 @@ static void aw87xxx_i2c_shutdown(struct i2c_client *client) - aw87xxx_update_profile(aw87xxx, aw87xxx->prof_off_name); - } - -+ -+static int aw87xxx_runtime_suspend(struct device *dev) -+{ -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ AW_DEV_LOGI(aw87xxx->dev, "Suspending..."); -+ -+ // soft and hw power off -+ aw87xxx_update_profile(aw87xxx, aw87xxx->prof_off_name); -+ -+ return 0; -+} -+ -+static int aw87xxx_runtime_resume(struct device *dev) -+{ -+ struct list_head *pos = NULL; -+ struct aw87xxx *aw87xxx = dev_get_drvdata(dev); -+ -+ // Power on PA -+ if (aw87xxx->dev_index == 1) -+ aw87xxx_dev_hw_pwr_ctrl(&aw87xxx->aw_dev, true); -+ -+ // Set profile to Music -+ list_for_each_prev(pos, &g_aw87xxx_list) { -+ aw87xxx = list_entry(pos, struct aw87xxx, list); -+ AW_DEV_LOGI(aw87xxx->dev, "Resuming..."); -+ -+ mutex_lock(&aw87xxx->reg_lock); -+ aw87xxx_power_on(aw87xxx, AW87XXX_PROF_MUSIC); -+ mutex_unlock(&aw87xxx->reg_lock); -+ -+ } -+ -+ return 0; -+} -+ -+static SIMPLE_DEV_PM_OPS(aw87xxx_pm_ops, aw87xxx_runtime_suspend, aw87xxx_runtime_resume); -+ - static const struct acpi_device_id aw87xxx_acpi_match[] = { - { "AWDZ8830", 0 }, - { } -@@ -1488,6 +1526,7 @@ static struct i2c_driver aw87xxx_i2c_driver = { - .owner = THIS_MODULE, - .name = AW87XXX_I2C_NAME, - .acpi_match_table = aw87xxx_acpi_match, -+ .pm = &aw87xxx_pm_ops, - }, - .probe = aw87xxx_i2c_probe, - .remove = aw87xxx_i2c_remove, --- -2.45.2 - - -From c6eb7c48fd8bb0c281c43c6e2c89ec32ab6dc7c4 Mon Sep 17 00:00:00 2001 -From: bouhaa <boukehaarsma23@gmail.com> -Date: Fri, 22 Sep 2023 21:53:06 +0200 -Subject: [PATCH 5/8] Ayaneo geek headset patch - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/pci/hda/patch_realtek.c | 20 ++++++++++++++++++++ - 1 file changed, 20 insertions(+) - -diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c -index c0530d4aa..62ffe1448 100644 ---- a/sound/pci/hda/patch_realtek.c -+++ b/sound/pci/hda/patch_realtek.c -@@ -6555,6 +6555,20 @@ static void alc294_gx502_toggle_output(struct hda_codec *codec, - alc_write_coef_idx(codec, 0x10, 0x0a20); - } - -+static void alc269_fixup_headphone_volume(struct hda_codec *codec, -+ const struct hda_fixup *fix, int action) -+{ -+ /* Pin 0x21: Some devices share 0x14 for headphones and speakers. -+ * This will fix ensure these devices have volume controls. */ -+ if (!is_jack_detectable(codec, 0x21)) -+ return; -+ -+ if (action == HDA_FIXUP_ACT_PRE_PROBE) { -+ static const hda_nid_t conn1[] = { 0x02 }; -+ snd_hda_override_conn_list(codec, 0x14, ARRAY_SIZE(conn1), conn1); -+ } -+} -+ - static void alc294_fixup_gx502_hp(struct hda_codec *codec, - const struct hda_fixup *fix, int action) - { -@@ -7271,6 +7285,7 @@ enum { - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE, - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE_QUIET, - ALC269_FIXUP_HEADSET_MODE, -+ ALC269_FIXUP_HEADSET_AYA_GEEK, - ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC, - ALC269_FIXUP_ASPIRE_HEADSET_MIC, - ALC269_FIXUP_ASUS_X101_FUNC, -@@ -8769,6 +8784,10 @@ static const struct hda_fixup alc269_fixups[] = { - .chained = true, - .chain_id = ALC256_FIXUP_ASUS_HEADSET_MODE - }, -+ [ALC269_FIXUP_HEADSET_AYA_GEEK] = { -+ .type = HDA_FIXUP_FUNC, -+ .v.func = alc269_fixup_headphone_volume, -+ }, - [ALC299_FIXUP_PREDATOR_SPK] = { - .type = HDA_FIXUP_PINS, - .v.pins = (const struct hda_pintbl[]) { -@@ -10601,6 +10601,7 @@ - SND_PCI_QUIRK(0x2782, 0x0214, "VAIO VJFE-CL", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), - SND_PCI_QUIRK(0x2782, 0x0232, "CHUWI CoreBook XPro", ALC269VB_FIXUP_CHUWI_COREBOOK_XPRO), - SND_PCI_QUIRK(0x2782, 0x1707, "Vaio VJFE-ADL", ALC298_FIXUP_SPK_VOLUME), -+ SND_PCI_QUIRK(0x1f66, 0x0101, "GEEK", ALC269_FIXUP_HEADSET_AYA_GEEK), - SND_PCI_QUIRK(0x8086, 0x2074, "Intel NUC 8", ALC233_FIXUP_INTEL_NUC8_DMIC), - SND_PCI_QUIRK(0x8086, 0x2080, "Intel NUC 8 Rugged", ALC256_FIXUP_INTEL_NUC8_RUGGED), - SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", ALC256_FIXUP_INTEL_NUC10), --- -2.45.2 - - -From 2d9cf63b5f1b72a8dbdc226fda6e060b69b7d1c9 Mon Sep 17 00:00:00 2001 -From: bouhaa <boukehaarsma23@gmail.com> -Date: Fri, 22 Sep 2023 22:08:35 +0200 -Subject: [PATCH 6/8] ayaneo 2 headphone fix - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/pci/hda/patch_realtek.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c -index 62ffe1448..f4aaaf6ba 100644 ---- a/sound/pci/hda/patch_realtek.c -+++ b/sound/pci/hda/patch_realtek.c -@@ -7285,6 +7285,7 @@ enum { - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE, - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE_QUIET, - ALC269_FIXUP_HEADSET_MODE, -+ ALC269_FIXUP_HEADSET_AYA_2, - ALC269_FIXUP_HEADSET_AYA_GEEK, - ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC, - ALC269_FIXUP_ASPIRE_HEADSET_MIC, -@@ -8784,6 +8785,10 @@ static const struct hda_fixup alc269_fixups[] = { - .chained = true, - .chain_id = ALC256_FIXUP_ASUS_HEADSET_MODE - }, -+ [ALC269_FIXUP_HEADSET_AYA_2] = { -+ .type = HDA_FIXUP_FUNC, -+ .v.func = alc269_fixup_headphone_volume, -+ }, - [ALC269_FIXUP_HEADSET_AYA_GEEK] = { - .type = HDA_FIXUP_FUNC, - .v.func = alc269_fixup_headphone_volume, -@@ -10601,6 +10601,7 @@ - SND_PCI_QUIRK(0x2782, 0x0214, "VAIO VJFE-CL", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), - SND_PCI_QUIRK(0x2782, 0x0232, "CHUWI CoreBook XPro", ALC269VB_FIXUP_CHUWI_COREBOOK_XPRO), - SND_PCI_QUIRK(0x2782, 0x1707, "Vaio VJFE-ADL", ALC298_FIXUP_SPK_VOLUME), -+ SND_PCI_QUIRK(0x1f66, 0x0101, "AYANEO 2", ALC269_FIXUP_HEADSET_AYA_2), - SND_PCI_QUIRK(0x1f66, 0x0101, "GEEK", ALC269_FIXUP_HEADSET_AYA_GEEK), - SND_PCI_QUIRK(0x8086, 0x2074, "Intel NUC 8", ALC233_FIXUP_INTEL_NUC8_DMIC), - SND_PCI_QUIRK(0x8086, 0x2080, "Intel NUC 8 Rugged", ALC256_FIXUP_INTEL_NUC8_RUGGED), --- -2.45.2 - - -From e59906fda334a028c8b3997db4408995fdd61725 Mon Sep 17 00:00:00 2001 -From: fewtarius <fewtarius@steamfork.org> -Date: Thu, 11 Jul 2024 18:31:08 +0000 -Subject: [PATCH 7/8] Kernel 6.9.9, fix Air 1S audio - thanks in part to - @linh1987! - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/pci/hda/patch_realtek.c | 19 +++++++++++++++++++ - 1 file changed, 19 insertions(+) - -diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c -index f4aaaf6ba..f2be4b102 100644 ---- a/sound/pci/hda/patch_realtek.c -+++ b/sound/pci/hda/patch_realtek.c -@@ -7300,6 +7300,7 @@ enum { - ALC269VB_FIXUP_ASUS_ZENBOOK, - ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A, - ALC269VB_FIXUP_ASUS_MIC_NO_PRESENCE, -+ ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX, - ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED, - ALC269VB_FIXUP_ORDISSIMO_EVE2, - ALC283_FIXUP_CHROME_BOOK, -@@ -8012,6 +8013,22 @@ static const struct hda_fixup alc269_fixups[] = { - .chained = true, - .chain_id = ALC269_FIXUP_HEADSET_MIC - }, -+ [ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX] = { -+ .type = HDA_FIXUP_PINS, -+ .v.pins = (const struct hda_pintbl[]) { -+ { 0x12, 0x90a60130 }, -+ { 0x14, 0x90170110 }, -+ { 0x17, 0x40000000 }, -+ { 0x18, 0x03a19020 }, -+ { 0x19, 0x411111f0 }, -+ { 0x1a, 0x90170150 }, -+ { 0x1b, 0x411111f0 }, -+ { 0x1d, 0x40e69945 }, -+ { 0x1e, 0x411111f0 }, -+ { 0x21, 0x90170150 }, -+ { } -+ }, -+ }, - [ALC269_FIXUP_LIMIT_INT_MIC_BOOST_MUTE_LED] = { - .type = HDA_FIXUP_FUNC, - .v.func = alc269_fixup_limit_int_mic_boost, -@@ -10603,6 +10603,7 @@ - SND_PCI_QUIRK(0x2782, 0x1707, "Vaio VJFE-ADL", ALC298_FIXUP_SPK_VOLUME), - SND_PCI_QUIRK(0x1f66, 0x0101, "AYANEO 2", ALC269_FIXUP_HEADSET_AYA_2), - SND_PCI_QUIRK(0x1f66, 0x0101, "GEEK", ALC269_FIXUP_HEADSET_AYA_GEEK), -+ SND_PCI_QUIRK(0x1f66, 0x0103, "AYANEO AIR 1S", ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX), - SND_PCI_QUIRK(0x8086, 0x2074, "Intel NUC 8", ALC233_FIXUP_INTEL_NUC8_DMIC), - SND_PCI_QUIRK(0x8086, 0x2080, "Intel NUC 8 Rugged", ALC256_FIXUP_INTEL_NUC8_RUGGED), - SND_PCI_QUIRK(0x8086, 0x2081, "Intel NUC 10", ALC256_FIXUP_INTEL_NUC10), -@@ -10743,6 +10761,7 @@ static const struct hda_model_fixup alc269_fixup_models[] = { - {.id = ALC269VB_FIXUP_ASUS_ZENBOOK, .name = "asus-zenbook"}, - {.id = ALC269VB_FIXUP_ASUS_ZENBOOK_UX31A, .name = "asus-zenbook-ux31a"}, - {.id = ALC269VB_FIXUP_ORDISSIMO_EVE2, .name = "ordissimo"}, -+ {.id = ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX, .name = "ayaneo-speaker-pin-fix"}, - {.id = ALC282_FIXUP_ASUS_TX300, .name = "asus-tx300"}, - {.id = ALC283_FIXUP_INT_MIC, .name = "alc283-int-mic"}, - {.id = ALC290_FIXUP_MONO_SPEAKERS_HSJACK, .name = "mono-speakers"}, --- -2.45.2 - - -From c1ca32ecd4172c05ddc83a1927d73d3a23253353 Mon Sep 17 00:00:00 2001 -From: CVMagic <546352+CVMagic@users.noreply.github.com> -Date: Sat, 13 Jul 2024 12:18:58 -0400 -Subject: [PATCH 8/8] Use DMI matching for conflicting SSID 0x1f660101 between - Ayaneo and AYN - -Signed-off-by: Antheas Kapenekakis <git@antheas.dev> ---- - sound/pci/hda/patch_realtek.c | 38 ++++++++++++++++++++++++++++------- - 1 file changed, 31 insertions(+), 7 deletions(-) - -diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c -index f2be4b102..928202b1a 100644 ---- a/sound/pci/hda/patch_realtek.c -+++ b/sound/pci/hda/patch_realtek.c -@@ -20,6 +20,7 @@ - #include <linux/input.h> - #include <linux/leds.h> - #include <linux/ctype.h> -+#include <linux/dmi.h> - #include <sound/core.h> - #include <sound/jack.h> - #include <sound/hda_codec.h> -@@ -7285,8 +7286,8 @@ enum { - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE, - ALC269_FIXUP_DELL4_MIC_NO_PRESENCE_QUIET, - ALC269_FIXUP_HEADSET_MODE, -- ALC269_FIXUP_HEADSET_AYA_2, -- ALC269_FIXUP_HEADSET_AYA_GEEK, -+ ALC269_FIXUP_DMI_MATCH, -+ ALC269_FIXUP_AYA_HEADSET_VOLUME, - ALC269_FIXUP_HEADSET_MODE_NO_HP_MIC, - ALC269_FIXUP_ASPIRE_HEADSET_MIC, - ALC269_FIXUP_ASUS_X101_FUNC, -@@ -7555,6 +7555,30 @@ - ALC245_FIXUP_CLEVO_NOISY_MIC, - }; - -+/* A special fixup for AYN and AYANEO handhelds as both -+* have the same PCI SSID as well as the same codec, but -+* require different quirks, falling back to DMI matching. -+*/ -+static void alc269_fixup_match_via_dmi(struct hda_codec *codec, -+ const struct hda_fixup *fix, int action) -+{ -+ int alc269_fix_id; -+ const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); -+ -+ if (dmi_name_in_vendors("AYANEO") || dmi_name_in_vendors("AYADEVICE") || dmi_name_in_vendors("AYA DEVICE")) { -+ if (board_name && (strcmp(board_name, "AYANEO 2") || strcmp(board_name, "AYANEO 2S") || strcmp(board_name, "GEEK") || strcmp(board_name, "GEEK 1S"))) { -+ alc269_fix_id = ALC269_FIXUP_AYA_HEADSET_VOLUME; -+ } else { -+ return; -+ } -+ } else if (dmi_name_in_vendors("ayn") && strcmp(board_name, "Loki MiniPro")) { -+ alc269_fix_id = ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX; -+ } else { -+ return; -+ } -+ __snd_hda_apply_fixup(codec, alc269_fix_id, action, 0); -+} -+ - /* A special fixup for Lenovo C940 and Yoga Duet 7; - * both have the very same PCI SSID, and we need to apply different fixups - * depending on the codec ID -@@ -8802,11 +8827,11 @@ static const struct hda_fixup alc269_fixups[] = { - .chained = true, - .chain_id = ALC256_FIXUP_ASUS_HEADSET_MODE - }, -- [ALC269_FIXUP_HEADSET_AYA_2] = { -+ [ALC269_FIXUP_DMI_MATCH] = { - .type = HDA_FIXUP_FUNC, -- .v.func = alc269_fixup_headphone_volume, -+ .v.func = alc269_fixup_match_via_dmi, - }, -- [ALC269_FIXUP_HEADSET_AYA_GEEK] = { -+ [ALC269_FIXUP_AYA_HEADSET_VOLUME] = { - .type = HDA_FIXUP_FUNC, - .v.func = alc269_fixup_headphone_volume, - }, -@@ -10601,8 +10601,7 @@ - SND_PCI_QUIRK(0x2782, 0x0214, "VAIO VJFE-CL", ALC269_FIXUP_LIMIT_INT_MIC_BOOST), - SND_PCI_QUIRK(0x2782, 0x0232, "CHUWI CoreBook XPro", ALC269VB_FIXUP_CHUWI_COREBOOK_XPRO), - SND_PCI_QUIRK(0x2782, 0x1707, "Vaio VJFE-ADL", ALC298_FIXUP_SPK_VOLUME), -- SND_PCI_QUIRK(0x1f66, 0x0101, "AYANEO 2", ALC269_FIXUP_HEADSET_AYA_2), -- SND_PCI_QUIRK(0x1f66, 0x0101, "GEEK", ALC269_FIXUP_HEADSET_AYA_GEEK), -+ SND_PCI_QUIRK(0x1f66, 0x0101, "Multiple Vendors", ALC269_FIXUP_DMI_MATCH), - SND_PCI_QUIRK(0x1f66, 0x0103, "AYANEO AIR 1S", ALC269VB_FIXUP_AYANEO_SPKR_PIN_FIX), - SND_PCI_QUIRK(0x8086, 0x2074, "Intel NUC 8", ALC233_FIXUP_INTEL_NUC8_DMIC), - SND_PCI_QUIRK(0x8086, 0x2080, "Intel NUC 8 Rugged", ALC256_FIXUP_INTEL_NUC8_RUGGED), --- -2.45.2 - diff --git a/SOURCES/v2-ally-suspend-fix.patch b/SOURCES/v2-ally-suspend-fix.patch new file mode 100644 index 0000000..c37d49e --- /dev/null +++ b/SOURCES/v2-ally-suspend-fix.patch @@ -0,0 +1,913 @@ +From ff87284862db614a4067b2d7383ecb173e1454de Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Wed, 18 Sep 2024 23:53:53 +0200 +Subject: [PATCH v3 01/10] acpi/x86: s2idle: add support for Display Off and + Display On callbacks + +The Display Off and Display On firmware notifications are meant to signify +the system entering a state where the user is not actively interacting +with it (i.e., in Windows this state is called "Screen Off" and the +system enters it once it turns the screen off e.g., due to inactivity). + +Currently, these functions are called within the suspend sequence, which +causes issues when these notifications interact with e.g., a USB device +and makes them unable to be called as part of the screen turning off. + +This patch adds a set of callbacks to allow calling the Display On/Off +notifications outside of the suspend/resume path. + +Co-developed-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + include/linux/suspend.h | 5 +++++ + kernel/power/suspend.c | 12 ++++++++++++ + 2 files changed, 17 insertions(+) + +diff --git a/include/linux/suspend.h b/include/linux/suspend.h +index da6ebca3ff77..8f33249cc067 100644 +--- a/include/linux/suspend.h ++++ b/include/linux/suspend.h +@@ -132,6 +132,7 @@ struct platform_suspend_ops { + }; + + struct platform_s2idle_ops { ++ int (*display_off)(void); + int (*begin)(void); + int (*prepare)(void); + int (*prepare_late)(void); +@@ -140,6 +141,7 @@ struct platform_s2idle_ops { + void (*restore_early)(void); + void (*restore)(void); + void (*end)(void); ++ int (*display_on)(void); + }; + + #ifdef CONFIG_SUSPEND +@@ -160,6 +162,9 @@ extern unsigned int pm_suspend_global_flags; + #define PM_SUSPEND_FLAG_FW_RESUME BIT(1) + #define PM_SUSPEND_FLAG_NO_PLATFORM BIT(2) + ++int platform_suspend_display_off(void); ++int platform_suspend_display_on(void); ++ + static inline void pm_suspend_clear_flags(void) + { + pm_suspend_global_flags = 0; +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index 09f8397bae15..c527dc0ae5ae 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -254,6 +254,18 @@ static bool sleep_state_supported(suspend_state_t state) + (valid_state(state) && !cxl_mem_active()); + } + ++int platform_suspend_display_off(void) ++{ ++ return s2idle_ops && s2idle_ops->display_off ? s2idle_ops->display_off() : 0; ++} ++EXPORT_SYMBOL_GPL(platform_suspend_display_off); ++ ++int platform_suspend_display_on(void) ++{ ++ return s2idle_ops && s2idle_ops->display_on ? s2idle_ops->display_on() : 0; ++} ++EXPORT_SYMBOL_GPL(platform_suspend_display_on); ++ + static int platform_suspend_prepare(suspend_state_t state) + { + return state != PM_SUSPEND_TO_IDLE && suspend_ops->prepare ? +-- +2.46.2 + + +From 0f25cd27999b0fe6c0382208452422fd1866da1e Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Thu, 19 Sep 2024 00:02:32 +0200 +Subject: [PATCH v3 02/10] acpi/x86: s2idle: handle Display On/Off calls + outside of suspend sequence + +Currently, the Display On/Off calls are handled within the suspend +sequence, which is a deviation from Windows. This causes issues with +certain devices, where the notification interacts with a USB device +that expects the kernel to be fully awake. + +This patch calls the Display On/Off callbacks before entering the suspend +sequence, which fixes this issue. In addition, it opens the possibility +of modelling a state such as "Screen Off" that mirrors Windows, as the +callbacks will be accessible and validated to work outside of the +suspend sequence. + +Suggested-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + kernel/power/suspend.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index c527dc0ae5ae..610f8ecaeebd 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -589,6 +589,13 @@ static int enter_state(suspend_state_t state) + if (state == PM_SUSPEND_TO_IDLE) + s2idle_begin(); + ++ /* ++ * Linux does not have the concept of a "Screen Off" state, so call ++ * the platform functions for Display On/Off prior to the suspend ++ * sequence, mirroring Windows which calls them outside of it as well. ++ */ ++ platform_suspend_display_off(); ++ + if (sync_on_suspend_enabled) { + trace_suspend_resume(TPS("sync_filesystems"), 0, true); + ksys_sync_helper(); +@@ -616,6 +623,8 @@ static int enter_state(suspend_state_t state) + suspend_finish(); + Unlock: + mutex_unlock(&system_transition_mutex); ++ ++ platform_suspend_display_on(); + return error; + } + +-- +2.46.2 + + +From e0cad271a26ff16ea9456e0104ea10e1195f6d47 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Sun, 22 Sep 2024 11:47:29 +0200 +Subject: [PATCH v3 03/10] acpi/x86: s2idle: add quirk table for modern standby + delays + +Unfortunately, some modern standby systems, including the ROG Ally, rely +on a delay between modern standby transitions. Add a quirk table for +introducing delays between modern standby transitions, and quirk the +ROG Ally on "Display Off", which needs a bit of time to turn off its +controllers prior to suspending (i.e., entering DRIPS). + +Reported-by: Denis Benato <benato.denis96@gmail.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + include/linux/suspend.h | 5 +++++ + kernel/power/suspend.c | 41 +++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 46 insertions(+) + +diff --git a/include/linux/suspend.h b/include/linux/suspend.h +index 8f33249cc067..d7e2a4d8ab0c 100644 +--- a/include/linux/suspend.h ++++ b/include/linux/suspend.h +@@ -144,6 +144,11 @@ struct platform_s2idle_ops { + int (*display_on)(void); + }; + ++struct platform_s2idle_quirks { ++ int delay_display_off; ++ int delay_display_on; ++}; ++ + #ifdef CONFIG_SUSPEND + extern suspend_state_t pm_suspend_target_state; + extern suspend_state_t mem_sleep_current; +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index 610f8ecaeebd..af2abdd2f8c3 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -11,6 +11,7 @@ + + #include <linux/string.h> + #include <linux/delay.h> ++#include <linux/dmi.h> + #include <linux/errno.h> + #include <linux/init.h> + #include <linux/console.h> +@@ -61,6 +62,30 @@ static DECLARE_SWAIT_QUEUE_HEAD(s2idle_wait_head); + enum s2idle_states __read_mostly s2idle_state; + static DEFINE_RAW_SPINLOCK(s2idle_lock); + ++// The ROG Ally series disconnects its controllers on Display Off, without ++// holding a lock, introducing a race condition. Add a delay to allow the ++// controller to disconnect cleanly prior to suspend. ++static const struct platform_s2idle_quirks rog_ally_quirks = { ++ .delay_display_off = 500, ++}; ++ ++static const struct dmi_system_id platform_s2idle_quirks[] = { ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "RC71L"), ++ }, ++ .driver_data = (void *)&rog_ally_quirks ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_NAME, "RC72L"), ++ }, ++ .driver_data = (void *)&rog_ally_quirks ++ }, ++ {} ++}; ++ ++ + /** + * pm_suspend_default_s2idle - Check if suspend-to-idle is the default suspend. + * +@@ -589,12 +614,26 @@ static int enter_state(suspend_state_t state) + if (state == PM_SUSPEND_TO_IDLE) + s2idle_begin(); + ++ /* ++ * Windows transitions between Modern Standby states slowly, over multiple ++ * seconds. Certain manufacturers may rely on this, introducing race ++ * conditions. Until Linux can support modern standby, add the relevant ++ * delays between transitions here. ++ */ ++ const struct dmi_system_id *s2idle_sysid = dmi_first_match( ++ platform_s2idle_quirks ++ ); ++ const struct platform_s2idle_quirks *s2idle_quirks = s2idle_sysid ? ++ s2idle_sysid->driver_data : NULL; ++ + /* + * Linux does not have the concept of a "Screen Off" state, so call + * the platform functions for Display On/Off prior to the suspend + * sequence, mirroring Windows which calls them outside of it as well. + */ + platform_suspend_display_off(); ++ if (s2idle_quirks && s2idle_quirks->delay_display_off) ++ msleep(s2idle_quirks->delay_display_off); + + if (sync_on_suspend_enabled) { + trace_suspend_resume(TPS("sync_filesystems"), 0, true); +@@ -624,6 +663,8 @@ static int enter_state(suspend_state_t state) + Unlock: + mutex_unlock(&system_transition_mutex); + ++ if (s2idle_quirks && s2idle_quirks->delay_display_on) ++ msleep(s2idle_quirks->delay_display_on); + platform_suspend_display_on(); + return error; + } +-- +2.46.2 + + +From 230395bedb589220c3c126d7f33156edbb3dd1c7 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Thu, 19 Sep 2024 00:22:03 +0200 +Subject: [PATCH v3 04/10] acpi/x86: s2idle: call Display On/Off as part of + callbacks and rename + +Move the Display On/Off notifications into dedicated callbacks that gate +the ACPI mutex, so they can be called outside of the suspend path. +This fixes issues on certain devices that expect kernel drivers to be +fully active during the calls, and allows for the flexibility of calling +them as part of a more elaborate userspace suspend sequence (such as +with "Screen Off" in Windows Modern Standby). + +In addition, rename the notifications from "screen_" to "display_", as +there is no documentation referring to them as screen, either by +Intel or Microsoft. + +Co-developed-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + drivers/acpi/x86/s2idle.c | 89 +++++++++++++++++++++++++++------------ + 1 file changed, 62 insertions(+), 27 deletions(-) + +diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c +index dd0b40b9bbe8..a17e28b91326 100644 +--- a/drivers/acpi/x86/s2idle.c ++++ b/drivers/acpi/x86/s2idle.c +@@ -39,8 +39,8 @@ static const struct acpi_device_id lps0_device_ids[] = { + #define ACPI_LPS0_DSM_UUID "c4eb40a0-6cd2-11e2-bcfd-0800200c9a66" + + #define ACPI_LPS0_GET_DEVICE_CONSTRAINTS 1 +-#define ACPI_LPS0_SCREEN_OFF 3 +-#define ACPI_LPS0_SCREEN_ON 4 ++#define ACPI_LPS0_DISPLAY_OFF 3 ++#define ACPI_LPS0_DISPLAY_ON 4 + #define ACPI_LPS0_ENTRY 5 + #define ACPI_LPS0_EXIT 6 + #define ACPI_LPS0_MS_ENTRY 7 +@@ -50,8 +50,8 @@ static const struct acpi_device_id lps0_device_ids[] = { + #define ACPI_LPS0_DSM_UUID_AMD "e3f32452-febc-43ce-9039-932122d37721" + #define ACPI_LPS0_ENTRY_AMD 2 + #define ACPI_LPS0_EXIT_AMD 3 +-#define ACPI_LPS0_SCREEN_OFF_AMD 4 +-#define ACPI_LPS0_SCREEN_ON_AMD 5 ++#define ACPI_LPS0_DISPLAY_OFF_AMD 4 ++#define ACPI_LPS0_DISPLAY_ON_AMD 5 + + static acpi_handle lps0_device_handle; + static guid_t lps0_dsm_guid; +@@ -60,6 +60,7 @@ static int lps0_dsm_func_mask; + static guid_t lps0_dsm_guid_microsoft; + static int lps0_dsm_func_mask_microsoft; + static int lps0_dsm_state; ++static bool lsp0_dsm_in_display_off; + + /* Device constraint entry structure */ + struct lpi_device_info { +@@ -361,9 +362,9 @@ static const char *acpi_sleep_dsm_state_to_str(unsigned int state) + { + if (lps0_dsm_func_mask_microsoft || !acpi_s2idle_vendor_amd()) { + switch (state) { +- case ACPI_LPS0_SCREEN_OFF: ++ case ACPI_LPS0_DISPLAY_OFF: + return "screen off"; +- case ACPI_LPS0_SCREEN_ON: ++ case ACPI_LPS0_DISPLAY_ON: + return "screen on"; + case ACPI_LPS0_ENTRY: + return "lps0 entry"; +@@ -376,9 +377,9 @@ static const char *acpi_sleep_dsm_state_to_str(unsigned int state) + } + } else { + switch (state) { +- case ACPI_LPS0_SCREEN_ON_AMD: ++ case ACPI_LPS0_DISPLAY_ON_AMD: + return "screen on"; +- case ACPI_LPS0_SCREEN_OFF_AMD: ++ case ACPI_LPS0_DISPLAY_OFF_AMD: + return "screen off"; + case ACPI_LPS0_ENTRY_AMD: + return "lps0 entry"; +@@ -539,27 +540,69 @@ static struct acpi_scan_handler lps0_handler = { + .attach = lps0_device_attach, + }; + +-int acpi_s2idle_prepare_late(void) ++static int acpi_s2idle_display_off(void) + { +- struct acpi_s2idle_dev_ops *handler; +- + if (!lps0_device_handle || sleep_no_lps0) + return 0; + +- if (pm_debug_messages_on) +- lpi_check_constraints(); ++ if (unlikely(WARN_ON(lsp0_dsm_in_display_off))) ++ return -EINVAL; ++ ++ lsp0_dsm_in_display_off = true; ++ acpi_scan_lock_acquire(); + +- /* Screen off */ ++ /* Display off */ + if (lps0_dsm_func_mask > 0) + acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ? +- ACPI_LPS0_SCREEN_OFF_AMD : +- ACPI_LPS0_SCREEN_OFF, ++ ACPI_LPS0_DISPLAY_OFF_AMD : ++ ACPI_LPS0_DISPLAY_OFF, + lps0_dsm_func_mask, lps0_dsm_guid); + + if (lps0_dsm_func_mask_microsoft > 0) +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_OFF, ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_DISPLAY_OFF, + lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); + ++ acpi_scan_lock_release(); ++ ++ return 0; ++} ++ ++static int acpi_s2idle_display_on(void) ++{ ++ if (!lps0_device_handle || sleep_no_lps0) ++ return 0; ++ ++ if (unlikely(WARN_ON(!lsp0_dsm_in_display_off))) ++ return -EINVAL; ++ ++ lsp0_dsm_in_display_off = false; ++ acpi_scan_lock_acquire(); ++ ++ /* Display on */ ++ if (lps0_dsm_func_mask_microsoft > 0) ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_DISPLAY_ON, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ if (lps0_dsm_func_mask > 0) ++ acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ? ++ ACPI_LPS0_DISPLAY_ON_AMD : ++ ACPI_LPS0_DISPLAY_ON, ++ lps0_dsm_func_mask, lps0_dsm_guid); ++ ++ acpi_scan_lock_release(); ++ ++ return 0; ++} ++ ++int acpi_s2idle_prepare_late(void) ++{ ++ struct acpi_s2idle_dev_ops *handler; ++ ++ if (!lps0_device_handle || sleep_no_lps0) ++ return 0; ++ ++ if (pm_debug_messages_on) ++ lpi_check_constraints(); ++ + /* LPS0 entry */ + if (lps0_dsm_func_mask > 0 && acpi_s2idle_vendor_amd()) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD, +@@ -623,19 +666,10 @@ void acpi_s2idle_restore_early(void) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT, + lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); + } +- +- /* Screen on */ +- if (lps0_dsm_func_mask_microsoft > 0) +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_SCREEN_ON, +- lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); +- if (lps0_dsm_func_mask > 0) +- acpi_sleep_run_lps0_dsm(acpi_s2idle_vendor_amd() ? +- ACPI_LPS0_SCREEN_ON_AMD : +- ACPI_LPS0_SCREEN_ON, +- lps0_dsm_func_mask, lps0_dsm_guid); + } + + static const struct platform_s2idle_ops acpi_s2idle_ops_lps0 = { ++ .display_off = acpi_s2idle_display_off, + .begin = acpi_s2idle_begin, + .prepare = acpi_s2idle_prepare, + .prepare_late = acpi_s2idle_prepare_late, +@@ -644,6 +678,7 @@ static const struct platform_s2idle_ops acpi_s2idle_ops_lps0 = { + .restore_early = acpi_s2idle_restore_early, + .restore = acpi_s2idle_restore, + .end = acpi_s2idle_end, ++ .display_on = acpi_s2idle_display_on, + }; + + void __init acpi_s2idle_setup(void) +-- +2.46.2 + + +From 69cdca368e53713088771d2866adc48ac19cbf29 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Thu, 19 Sep 2024 00:29:59 +0200 +Subject: [PATCH v3 05/10] platform/x86: asus-wmi: remove Ally (1st gen) and + Ally X suspend quirk + +By moving the Display On/Off calls outside of the suspend sequence and +introducing a slight delay after Display Off, the ROG Ally controller +functions exactly as it does in Windows. + +Therefore, remove the quirk that fixed the controller only when the +mcu_powersave attribute was disabled, while adding a large amount of +delay to the suspend and wake process. + +Reviewed-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + drivers/platform/x86/asus-wmi.c | 54 --------------------------------- + 1 file changed, 54 deletions(-) + +diff --git a/drivers/platform/x86/asus-wmi.c b/drivers/platform/x86/asus-wmi.c +index 37636e5a38e3..2c9656e0afda 100644 +--- a/drivers/platform/x86/asus-wmi.c ++++ b/drivers/platform/x86/asus-wmi.c +@@ -137,11 +137,6 @@ + #define ASUS_MINI_LED_2024_STRONG 0x01 + #define ASUS_MINI_LED_2024_OFF 0x02 + +-/* Controls the power state of the USB0 hub on ROG Ally which input is on */ +-#define ASUS_USB0_PWR_EC0_CSEE "\\_SB.PCI0.SBRG.EC0.CSEE" +-/* 300ms so far seems to produce a reliable result on AC and battery */ +-#define ASUS_USB0_PWR_EC0_CSEE_WAIT 1500 +- + static const char * const ashs_ids[] = { "ATK4001", "ATK4002", NULL }; + + static int throttle_thermal_policy_write(struct asus_wmi *); +@@ -269,9 +264,6 @@ + u32 tablet_switch_dev_id; + bool tablet_switch_inverted; + +- /* The ROG Ally device requires the MCU USB device be disconnected before suspend */ +- bool ally_mcu_usb_switch; +- + enum fan_type fan_type; + enum fan_type gpu_fan_type; + enum fan_type mid_fan_type; +@@ -4708,8 +4700,6 @@ + asus->egpu_enable_available = asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_EGPU); + asus->dgpu_disable_available = asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_DGPU); + asus->kbd_rgb_state_available = asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_TUF_RGB_STATE); +- asus->ally_mcu_usb_switch = acpi_has_method(NULL, ASUS_USB0_PWR_EC0_CSEE) +- && dmi_check_system(asus_ally_mcu_quirk); + + if (asus_wmi_dev_is_present(asus, ASUS_WMI_DEVID_MINI_LED_MODE)) + asus->mini_led_dev_id = ASUS_WMI_DEVID_MINI_LED_MODE; +@@ -4892,34 +4868,6 @@ static int asus_hotk_resume(struct device *device) + return 0; + } + +-static int asus_hotk_resume_early(struct device *device) +-{ +- struct asus_wmi *asus = dev_get_drvdata(device); +- +- if (asus->ally_mcu_usb_switch) { +- /* sleep required to prevent USB0 being yanked then reappearing rapidly */ +- if (ACPI_FAILURE(acpi_execute_simple_method(NULL, ASUS_USB0_PWR_EC0_CSEE, 0xB8))) +- dev_err(device, "ROG Ally MCU failed to connect USB dev\n"); +- else +- msleep(ASUS_USB0_PWR_EC0_CSEE_WAIT); +- } +- return 0; +-} +- +-static int asus_hotk_prepare(struct device *device) +-{ +- struct asus_wmi *asus = dev_get_drvdata(device); +- +- if (asus->ally_mcu_usb_switch) { +- /* sleep required to ensure USB0 is disabled before sleep continues */ +- if (ACPI_FAILURE(acpi_execute_simple_method(NULL, ASUS_USB0_PWR_EC0_CSEE, 0xB7))) +- dev_err(device, "ROG Ally MCU failed to disconnect USB dev\n"); +- else +- msleep(ASUS_USB0_PWR_EC0_CSEE_WAIT); +- } +- return 0; +-} +- + static int asus_hotk_restore(struct device *device) + { + struct asus_wmi *asus = dev_get_drvdata(device); +@@ -4964,8 +4912,6 @@ static const struct dev_pm_ops asus_pm_ops = { + .thaw = asus_hotk_thaw, + .restore = asus_hotk_restore, + .resume = asus_hotk_resume, +- .resume_early = asus_hotk_resume_early, +- .prepare = asus_hotk_prepare, + }; + + /* Registration ***************************************************************/ +-- +2.46.2 + + +From 2d446e1e66be5ae07bb7c243a7c4383b49b1aa3e Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Wed, 25 Sep 2024 14:10:11 +0200 +Subject: [PATCH v3 06/10] acpi/x86: s2idle: add support for Sleep Entry and + Sleep Exit callbacks + +The Sleep Entry and Sleep Exit firmware notifications allow the platform +to enter Modern Standby. In this state, if supported, the platform turns +off auxiliary USB devices (e.g., the controllers of the Legion Go), +makes the power light of the device flash, and lowers the power envelope +to a minimum that still allows for software activity without affecting +battery life. + +Allow for entering this state prior to initiating the suspend sequence. +This fixes issues where the EC or the USB of the device need time to +power down before entering the suspend sequence, and allows for entering +this power state without suspending the device. + +Suggested-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + include/linux/suspend.h | 4 ++++ + kernel/power/suspend.c | 12 ++++++++++++ + 2 files changed, 16 insertions(+) + +diff --git a/include/linux/suspend.h b/include/linux/suspend.h +index d7e2a4d8ab0c..66c5b434334d 100644 +--- a/include/linux/suspend.h ++++ b/include/linux/suspend.h +@@ -133,6 +133,7 @@ struct platform_suspend_ops { + + struct platform_s2idle_ops { + int (*display_off)(void); ++ int (*sleep_entry)(void); + int (*begin)(void); + int (*prepare)(void); + int (*prepare_late)(void); +@@ -141,6 +142,7 @@ struct platform_s2idle_ops { + void (*restore_early)(void); + void (*restore)(void); + void (*end)(void); ++ int (*sleep_exit)(void); + int (*display_on)(void); + }; + +@@ -168,6 +170,8 @@ extern unsigned int pm_suspend_global_flags; + #define PM_SUSPEND_FLAG_NO_PLATFORM BIT(2) + + int platform_suspend_display_off(void); ++int platform_suspend_sleep_entry(void); ++int platform_suspend_sleep_exit(void); + int platform_suspend_display_on(void); + + static inline void pm_suspend_clear_flags(void) +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index af2abdd2f8c3..dab299e28195 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -285,6 +285,18 @@ int platform_suspend_display_off(void) + } + EXPORT_SYMBOL_GPL(platform_suspend_display_off); + ++int platform_suspend_sleep_entry(void) ++{ ++ return s2idle_ops && s2idle_ops->sleep_entry ? s2idle_ops->sleep_entry() : 0; ++} ++EXPORT_SYMBOL_GPL(platform_suspend_sleep_entry); ++ ++int platform_suspend_sleep_exit(void) ++{ ++ return s2idle_ops && s2idle_ops->sleep_exit ? s2idle_ops->sleep_exit() : 0; ++} ++EXPORT_SYMBOL_GPL(platform_suspend_sleep_exit); ++ + int platform_suspend_display_on(void) + { + return s2idle_ops && s2idle_ops->display_on ? s2idle_ops->display_on() : 0; +-- +2.46.2 + + +From ec33ea0c341d5b75a090910664c572d8d4793bbc Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Wed, 25 Sep 2024 14:19:00 +0200 +Subject: [PATCH v3 07/10] acpi/x86: s2idle: handle Sleep Entry/Exit calls + outside of suspend sequence + +As with Display On/Off, these calls should be made outside the suspend +sequence, to allow the EC and USB devices that are affected to complete +their power off sequence before the kernel suspends their power rails +and interrupts. + +Suggested-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + kernel/power/suspend.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index dab299e28195..9dcdd5273318 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -547,6 +547,13 @@ int suspend_devices_and_enter(suspend_state_t state) + if (state == PM_SUSPEND_TO_IDLE) + pm_set_suspend_no_platform(); + ++ /* ++ * Linux does not have the concept of a "Sleep" state. As with Display ++ * On/Off, call the platform functions for Sleep Entry/Exit prior to the ++ * suspend sequence. ++ */ ++ platform_suspend_sleep_entry(); ++ + error = platform_suspend_begin(state); + if (error) + goto Close; +@@ -577,6 +584,8 @@ int suspend_devices_and_enter(suspend_state_t state) + Close: + platform_resume_end(state); + pm_suspend_target_state = PM_SUSPEND_ON; ++ ++ platform_suspend_sleep_exit(); + return error; + + Recover_platform: +-- +2.46.2 + + +From 0825b095f26cbea829078f70d4c757ff9b2eab38 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Wed, 25 Sep 2024 14:29:42 +0200 +Subject: [PATCH v3 08/10] acpi/x86: s2idle: update quirk table for Sleep + Entry/Exit + +Add delays between the Sleep Entry and Sleep Exit calls, to avoid issues +in devices that rely on them that need time to power off. + +Especially for the ROG Ally, this should allow its EC to suspend gracefully, +avoiding issues where it is stuck in its suspend state. Since the delays +are additive, steal some of the delay from Display On/Off. + +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + include/linux/suspend.h | 2 ++ + kernel/power/suspend.c | 21 +++++++++++++++++++-- + 2 files changed, 21 insertions(+), 2 deletions(-) + +diff --git a/include/linux/suspend.h b/include/linux/suspend.h +index 66c5b434334d..5b4d4d9ef65a 100644 +--- a/include/linux/suspend.h ++++ b/include/linux/suspend.h +@@ -148,6 +148,8 @@ struct platform_s2idle_ops { + + struct platform_s2idle_quirks { + int delay_display_off; ++ int delay_sleep_entry; ++ int delay_sleep_exit; + int delay_display_on; + }; + +diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c +index 9dcdd5273318..1352c4066822 100644 +--- a/kernel/power/suspend.c ++++ b/kernel/power/suspend.c +@@ -65,8 +65,11 @@ static DEFINE_RAW_SPINLOCK(s2idle_lock); + // The ROG Ally series disconnects its controllers on Display Off, without + // holding a lock, introducing a race condition. Add a delay to allow the + // controller to disconnect cleanly prior to suspend. ++// In addition, the EC of the device rarely (1/20 attempts) may get stuck ++// after suspend in an invalid state, where it mirros Sleep behavior. + static const struct platform_s2idle_quirks rog_ally_quirks = { +- .delay_display_off = 500, ++ .delay_display_off = 200, ++ .delay_sleep_entry = 300, + }; + + static const struct dmi_system_id platform_s2idle_quirks[] = { +@@ -548,11 +551,23 @@ int suspend_devices_and_enter(suspend_state_t state) + pm_set_suspend_no_platform(); + + /* +- * Linux does not have the concept of a "Sleep" state. As with Display ++ * Windows transitions between Modern Standby states slowly, as with ++ * Display On/Off, query the appropriate delays here for Sleep Entry/Exit. ++ */ ++ const struct dmi_system_id *s2idle_sysid = dmi_first_match( ++ platform_s2idle_quirks ++ ); ++ const struct platform_s2idle_quirks *s2idle_quirks = s2idle_sysid ? ++ s2idle_sysid->driver_data : NULL; ++ ++ /* ++ * Linux does not have the concept of a "Sleep" state. As done with Display + * On/Off, call the platform functions for Sleep Entry/Exit prior to the + * suspend sequence. + */ + platform_suspend_sleep_entry(); ++ if (s2idle_quirks && s2idle_quirks->delay_sleep_entry) ++ msleep(s2idle_quirks->delay_sleep_entry); + + error = platform_suspend_begin(state); + if (error) +@@ -585,6 +600,8 @@ int suspend_devices_and_enter(suspend_state_t state) + platform_resume_end(state); + pm_suspend_target_state = PM_SUSPEND_ON; + ++ if (s2idle_quirks && s2idle_quirks->delay_sleep_exit) ++ msleep(s2idle_quirks->delay_sleep_exit); + platform_suspend_sleep_exit(); + return error; + +-- +2.46.2 + + +From 49cafd9d1cf20250e31f34a849c505d205968ef5 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <lkml@antheas.dev> +Date: Wed, 25 Sep 2024 14:41:03 +0200 +Subject: [PATCH v3 09/10] acpi/x86: s2idle: call Sleep Entry/Exit as part of + callbacks. + +Move the Sleep Entry/Exit notifications outside the suspend sequence, +with their own ACPI lock, as was done for Display On/Off. + +Suggested-by: Mario Limonciello <mario.limonciello@amd.com> +Signed-off-by: Antheas Kapenekakis <lkml@antheas.dev> +--- + drivers/acpi/x86/s2idle.c | 69 ++++++++++++++++++++++++++++++--------- + 1 file changed, 53 insertions(+), 16 deletions(-) + +diff --git a/drivers/acpi/x86/s2idle.c b/drivers/acpi/x86/s2idle.c +index a17e28b91326..6ff5e34c016e 100644 +--- a/drivers/acpi/x86/s2idle.c ++++ b/drivers/acpi/x86/s2idle.c +@@ -43,8 +43,8 @@ static const struct acpi_device_id lps0_device_ids[] = { + #define ACPI_LPS0_DISPLAY_ON 4 + #define ACPI_LPS0_ENTRY 5 + #define ACPI_LPS0_EXIT 6 +-#define ACPI_LPS0_MS_ENTRY 7 +-#define ACPI_LPS0_MS_EXIT 8 ++#define ACPI_LPS0_SLEEP_ENTRY 7 ++#define ACPI_LPS0_SLEEP_EXIT 8 + + /* AMD */ + #define ACPI_LPS0_DSM_UUID_AMD "e3f32452-febc-43ce-9039-932122d37721" +@@ -61,6 +61,7 @@ static guid_t lps0_dsm_guid_microsoft; + static int lps0_dsm_func_mask_microsoft; + static int lps0_dsm_state; + static bool lsp0_dsm_in_display_off; ++static bool lsp0_dsm_in_sleep; + + /* Device constraint entry structure */ + struct lpi_device_info { +@@ -370,10 +371,10 @@ static const char *acpi_sleep_dsm_state_to_str(unsigned int state) + return "lps0 entry"; + case ACPI_LPS0_EXIT: + return "lps0 exit"; +- case ACPI_LPS0_MS_ENTRY: +- return "lps0 ms entry"; +- case ACPI_LPS0_MS_EXIT: +- return "lps0 ms exit"; ++ case ACPI_LPS0_SLEEP_ENTRY: ++ return "lps0 sleep entry"; ++ case ACPI_LPS0_SLEEP_EXIT: ++ return "lps0 sleep exit"; + } + } else { + switch (state) { +@@ -567,6 +568,48 @@ static int acpi_s2idle_display_off(void) + return 0; + } + ++static int acpi_s2idle_sleep_entry(void) ++{ ++ if (!lps0_device_handle || sleep_no_lps0 || lps0_dsm_func_mask_microsoft <= 0) ++ return 0; ++ ++ if (WARN_ON(lsp0_dsm_in_sleep)) ++ return -EINVAL; ++ ++ lsp0_dsm_in_sleep = true; ++ acpi_scan_lock_acquire(); ++ ++ /* Modern Standby Sleep Entry */ ++ if (lps0_dsm_func_mask_microsoft > 0) ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SLEEP_ENTRY, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ ++ acpi_scan_lock_release(); ++ ++ return 0; ++} ++ ++static int acpi_s2idle_sleep_exit(void) ++{ ++ if (!lps0_device_handle || sleep_no_lps0 || lps0_dsm_func_mask_microsoft <= 0) ++ return 0; ++ ++ if (WARN_ON(!lsp0_dsm_in_sleep)) ++ return -EINVAL; ++ ++ lsp0_dsm_in_sleep = false; ++ acpi_scan_lock_acquire(); ++ ++ /* Modern Standby Sleep Exit */ ++ if (lps0_dsm_func_mask_microsoft > 0) ++ acpi_sleep_run_lps0_dsm(ACPI_LPS0_SLEEP_EXIT, ++ lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ ++ acpi_scan_lock_release(); ++ ++ return 0; ++} ++ + static int acpi_s2idle_display_on(void) + { + if (!lps0_device_handle || sleep_no_lps0) +@@ -608,13 +651,9 @@ int acpi_s2idle_prepare_late(void) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY_AMD, + lps0_dsm_func_mask, lps0_dsm_guid); + +- if (lps0_dsm_func_mask_microsoft > 0) { +- /* Modern Standby entry */ +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_ENTRY, +- lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); ++ if (lps0_dsm_func_mask_microsoft > 0) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY, + lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); +- } + + if (lps0_dsm_func_mask > 0 && !acpi_s2idle_vendor_amd()) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_ENTRY, +@@ -659,17 +698,14 @@ void acpi_s2idle_restore_early(void) + ACPI_LPS0_EXIT, + lps0_dsm_func_mask, lps0_dsm_guid); + +- if (lps0_dsm_func_mask_microsoft > 0) { ++ if (lps0_dsm_func_mask_microsoft > 0) + acpi_sleep_run_lps0_dsm(ACPI_LPS0_EXIT, + lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); +- /* Modern Standby exit */ +- acpi_sleep_run_lps0_dsm(ACPI_LPS0_MS_EXIT, +- lps0_dsm_func_mask_microsoft, lps0_dsm_guid_microsoft); +- } + } + + static const struct platform_s2idle_ops acpi_s2idle_ops_lps0 = { + .display_off = acpi_s2idle_display_off, ++ .sleep_entry = acpi_s2idle_sleep_entry, + .begin = acpi_s2idle_begin, + .prepare = acpi_s2idle_prepare, + .prepare_late = acpi_s2idle_prepare_late, +@@ -678,6 +714,7 @@ static const struct platform_s2idle_ops acpi_s2idle_ops_lps0 = { + .restore_early = acpi_s2idle_restore_early, + .restore = acpi_s2idle_restore, + .end = acpi_s2idle_end, ++ .sleep_exit = acpi_s2idle_sleep_exit, + .display_on = acpi_s2idle_display_on, + }; + +-- +2.46.2 diff --git a/SOURCES/v2-onexplayer.patch b/SOURCES/v2-onexplayer.patch new file mode 100644 index 0000000..f1a191e --- /dev/null +++ b/SOURCES/v2-onexplayer.patch @@ -0,0 +1,126 @@ +From 1ea6dd6a28c054be66cd361ccc33511e70c19c58 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <git@antheas.dev> +Date: Wed, 2 Oct 2024 22:17:26 +0200 +Subject: [PATCH v2 1/3] HID: Add quirk to ignore the touchscreen battery on + OneXPlayer X1 + +--- + drivers/hid/hid-ids.h | 1 + + drivers/hid/hid-input.c | 2 ++ + 2 files changed, 3 insertions(+) + +diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h +index 781c5aa29859..917595aafd5c 100644 +--- a/drivers/hid/hid-ids.h ++++ b/drivers/hid/hid-ids.h +@@ -1008,6 +1008,7 @@ + #define USB_VENDOR_ID_NOVATEK 0x0603 + #define USB_DEVICE_ID_NOVATEK_PCT 0x0600 + #define USB_DEVICE_ID_NOVATEK_MOUSE 0x1602 ++#define I2C_DEVICE_ID_ONEXPLAYER_X1 0xF001 + + #define USB_VENDOR_ID_NTI 0x0757 + #define USB_DEVICE_ID_USB_SUN 0x0a00 +diff --git a/drivers/hid/hid-input.c b/drivers/hid/hid-input.c +index c9094a4f281e..455e2fd4cec3 100644 +--- a/drivers/hid/hid-input.c ++++ b/drivers/hid/hid-input.c +@@ -417,6 +417,8 @@ static const struct hid_device_id hid_battery_quirks[] = { + HID_BATTERY_QUIRK_IGNORE }, + { HID_I2C_DEVICE(USB_VENDOR_ID_ELAN, I2C_DEVICE_ID_CHROMEBOOK_TROGDOR_POMPOM), + HID_BATTERY_QUIRK_AVOID_QUERY }, ++ { HID_I2C_DEVICE(USB_VENDOR_ID_NOVATEK, I2C_DEVICE_ID_ONEXPLAYER_X1), ++ HID_BATTERY_QUIRK_IGNORE }, + {} + }; + +-- +2.46.2 + + +From 0bb5d03d90997fde2d7756537039f7a4c5bd2898 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <git@antheas.dev> +Date: Wed, 2 Oct 2024 22:01:14 +0200 +Subject: [PATCH v2 2/3] drm/panel-orientation-quirks: add OneXPlayer X1 (AMD) + +--- + drivers/gpu/drm/drm_panel_orientation_quirks.c | 18 ++++++++++++++++++ + 1 file changed, 18 insertions(+) + +diff --git a/drivers/gpu/drm/drm_panel_orientation_quirks.c b/drivers/gpu/drm/drm_panel_orientation_quirks.c +index 0830cae9a4d0..03a640233e97 100644 +--- a/drivers/gpu/drm/drm_panel_orientation_quirks.c ++++ b/drivers/gpu/drm/drm_panel_orientation_quirks.c +@@ -473,6 +473,24 @@ + DMI_EXACT_MATCH(DMI_BOARD_NAME, "Default string"), + }, + .driver_data = (void *)&gpd_onemix2s, ++ }, { /* OneXPlayer X1 AMD */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ONE-NETBOOK"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ONEXPLAYER X1 A"), ++ }, ++ .driver_data = (void *)&lcd1600x2560_leftside_up, ++ }, { /* OneXPlayer X1 Intel */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ONE-NETBOOK"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ONEXPLAYER X1 i"), ++ }, ++ .driver_data = (void *)&lcd1600x2560_leftside_up, ++ }, { /* OneXPlayer X1 mini (AMD) */ ++ .matches = { ++ DMI_EXACT_MATCH(DMI_SYS_VENDOR, "ONE-NETBOOK"), ++ DMI_EXACT_MATCH(DMI_PRODUCT_NAME, "ONEXPLAYER X1 mini"), ++ }, ++ .driver_data = (void *)&lcd1600x2560_leftside_up, + }, + {} + }; +-- +2.46.2 + + +From 8d4503da18e170537fec84e2b0adfb130df42d38 Mon Sep 17 00:00:00 2001 +From: Antheas Kapenekakis <git@antheas.dev> +Date: Mon, 7 Oct 2024 20:38:32 +0200 +Subject: [PATCH v2 3/3] add more OXP F1 and X1 variants + +--- + drivers/hwmon/oxp-sensors.c | 21 +++++++++++++++++++++ + 1 file changed, 21 insertions(+) + +diff --git a/drivers/hwmon/oxp-sensors.c b/drivers/hwmon/oxp-sensors.c +index b6d06370469d..5733d767da00 100644 +--- a/drivers/hwmon/oxp-sensors.c ++++ b/drivers/hwmon/oxp-sensors.c +@@ -188,6 +188,27 @@ static const struct dmi_system_id dmi_table[] = { + }, + .driver_data = (void *)oxp_fly, + }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_MATCH(DMI_BOARD_NAME, "ONEXPLAYER F1 "), ++ }, ++ .driver_data = (void *)oxp_fly, ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_EXACT_MATCH(DMI_BOARD_NAME, "ONEXPLAYER F1L"), ++ }, ++ .driver_data = (void *)oxp_fly, ++ }, ++ { ++ .matches = { ++ DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), ++ DMI_MATCH(DMI_BOARD_NAME, "ONEXPLAYER F1L "), ++ }, ++ .driver_data = (void *)oxp_fly, ++ }, + { + .matches = { + DMI_MATCH(DMI_BOARD_VENDOR, "ONE-NETBOOK"), +-- +2.46.2 + |