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authorJan200101 <sentrycraft123@gmail.com>2022-11-15 07:24:35 +0100
committerJan200101 <sentrycraft123@gmail.com>2022-11-15 07:24:35 +0100
commit8a2d5881827646cc90a49a3b9f9b97794c2151f0 (patch)
tree922840b1e154962a039e5185e4c75ef12c53e21b /SOURCES/patch-6.0-redhat.patch
parent3bec65f530f8bfbe01ce15b6ad347cf27c65bc14 (diff)
downloadkernel-fsync-8a2d5881827646cc90a49a3b9f9b97794c2151f0.tar.gz
kernel-fsync-8a2d5881827646cc90a49a3b9f9b97794c2151f0.zip
kernel 6.0.8
Diffstat (limited to 'SOURCES/patch-6.0-redhat.patch')
-rw-r--r--SOURCES/patch-6.0-redhat.patch652
1 files changed, 585 insertions, 67 deletions
diff --git a/SOURCES/patch-6.0-redhat.patch b/SOURCES/patch-6.0-redhat.patch
index d780947..fef59ec 100644
--- a/SOURCES/patch-6.0-redhat.patch
+++ b/SOURCES/patch-6.0-redhat.patch
@@ -4,32 +4,37 @@
arch/s390/include/asm/ipl.h | 1 +
arch/s390/kernel/ipl.c | 5 +
arch/s390/kernel/setup.c | 4 +
- arch/x86/kernel/setup.c | 22 ++--
- drivers/acpi/apei/hest.c | 8 ++
- drivers/acpi/irq.c | 17 ++-
- drivers/acpi/scan.c | 9 ++
- drivers/ata/libahci.c | 18 +++
- drivers/char/ipmi/ipmi_dmi.c | 15 +++
- drivers/char/ipmi/ipmi_msghandler.c | 16 ++-
+ arch/x86/kernel/setup.c | 22 +-
+ drivers/acpi/apei/hest.c | 8 +
+ drivers/acpi/irq.c | 17 +-
+ drivers/acpi/scan.c | 9 +
+ drivers/ata/libahci.c | 18 ++
+ drivers/char/ipmi/ipmi_dmi.c | 15 ++
+ drivers/char/ipmi/ipmi_msghandler.c | 16 +-
drivers/firmware/efi/Makefile | 1 +
- drivers/firmware/efi/efi.c | 124 +++++++++++++++------
- drivers/firmware/efi/secureboot.c | 38 +++++++
- drivers/firmware/sysfb.c | 18 ++-
- drivers/gpu/drm/tiny/simpledrm.c | 65 +++++++++--
- drivers/gpu/drm/vc4/vc4_hdmi.c | 39 ++++++-
+ drivers/firmware/efi/efi.c | 124 ++++++---
+ drivers/firmware/efi/secureboot.c | 38 +++
+ drivers/firmware/sysfb.c | 18 +-
+ drivers/gpu/drm/tiny/simpledrm.c | 65 ++++-
+ drivers/gpu/drm/vc4/vc4_hdmi.c | 21 +-
drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +
- drivers/hid/hid-rmi.c | 64 -----------
- drivers/hwtracing/coresight/coresight-etm4x-core.c | 19 ++++
- drivers/input/rmi4/rmi_driver.c | 124 ++++++++++++---------
- drivers/iommu/iommu.c | 22 ++++
- drivers/nvme/host/core.c | 22 +++-
- drivers/nvme/host/multipath.c | 19 ++--
+ drivers/hid/hid-rmi.c | 64 -----
+ drivers/hwtracing/coresight/coresight-etm4x-core.c | 19 ++
+ drivers/input/rmi4/rmi_driver.c | 124 +++++----
+ drivers/iommu/iommu.c | 22 ++
+ drivers/nvme/host/core.c | 22 +-
+ drivers/nvme/host/multipath.c | 19 +-
drivers/nvme/host/nvme.h | 4 +
- drivers/pci/quirks.c | 24 ++++
- drivers/usb/core/hub.c | 7 ++
- include/linux/efi.h | 22 ++--
+ drivers/pci/pci-driver.c | 11 +
+ drivers/pci/pci.c | 28 +-
+ drivers/pci/pci.h | 14 +-
+ drivers/pci/pcie/ptm.c | 300 ++++++++++++---------
+ drivers/pci/quirks.c | 24 ++
+ drivers/usb/core/hub.c | 7 +
+ include/linux/efi.h | 22 +-
include/linux/lsm_hook_defs.h | 2 +
include/linux/lsm_hooks.h | 6 +
+ include/linux/pci.h | 3 +
include/linux/rmi.h | 1 +
include/linux/security.h | 5 +
init/Kconfig | 2 +-
@@ -38,14 +43,14 @@
scripts/pahole-flags.sh | 3 +
scripts/tags.sh | 2 +
security/integrity/platform_certs/load_uefi.c | 6 +-
- security/lockdown/Kconfig | 13 +++
+ security/lockdown/Kconfig | 13 +
security/lockdown/lockdown.c | 1 +
security/security.c | 6 +
tools/testing/selftests/net/fib_nexthops.sh | 5 +
- 44 files changed, 609 insertions(+), 199 deletions(-)
+ 49 files changed, 780 insertions(+), 366 deletions(-)
diff --git a/Makefile b/Makefile
-index c2144a4bb2ef..4e8ae58e2ec1 100644
+index bcb76d4fdbc1..504aa3071925 100644
--- a/Makefile
+++ b/Makefile
@@ -18,6 +18,10 @@ $(if $(filter __%, $(MAKECMDGOALS)), \
@@ -375,7 +380,7 @@ index 8d151e332584..bd29fe4ddbf3 100644
obj-$(CONFIG_EFI_RCI2_TABLE) += rci2-table.o
obj-$(CONFIG_EFI_EMBEDDED_FIRMWARE) += embedded-firmware.o
diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
-index aa6d109fac08..a606fcc42649 100644
+index a06decee51e0..039897a56c5c 100644
--- a/drivers/firmware/efi/efi.c
+++ b/drivers/firmware/efi/efi.c
@@ -31,6 +31,7 @@
@@ -702,7 +707,7 @@ index 5422363690e7..a5b500811892 100644
}
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
-index 780a19a75c3f..281f01e8cbca 100644
+index 874c6bd787c5..4e5bba0822a5 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
@@ -2712,9 +2712,16 @@ static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
@@ -744,51 +749,29 @@ index 780a19a75c3f..281f01e8cbca 100644
return 0;
}
-@@ -2869,6 +2882,7 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
- struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
- unsigned long __maybe_unused flags;
- u32 __maybe_unused value;
-+ unsigned long rate;
- int ret;
-
- /*
-@@ -2884,6 +2898,25 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
+@@ -2877,11 +2890,11 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
+ * its frequency while the power domain is active so that it
+ * keeps its rate.
+ */
+- ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ);
++ ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ);
if (ret)
return ret;
+- ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
+ ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock);
-+ if (ret)
-+ return ret;
-+
-+ /*
-+ * Whenever the RaspberryPi boots without an HDMI monitor
-+ * plugged in, the firmware won't have initialized the HSM clock
-+ * rate and it will be reported as 0.
-+ *
-+ * If we try to access a register of the controller in such a
-+ * case, it will lead to a silent CPU stall. Let's make sure we
-+ * prevent such a case.
-+ */
-+ rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
-+ if (!rate) {
-+ ret = -EINVAL;
-+ goto err_disable_clk;
-+ }
-+
- if (vc4_hdmi->variant->reset)
- vc4_hdmi->variant->reset(vc4_hdmi);
-
-@@ -2905,6 +2938,10 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
- #endif
-
- return 0;
-+
-+err_disable_clk:
-+ clk_disable_unprepare(vc4_hdmi->hsm_clock);
-+ return ret;
- }
+ if (ret)
+ return ret;
- static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
+@@ -2894,7 +2907,7 @@ static int vc4_hdmi_runtime_resume(struct device *dev)
+ * case, it will lead to a silent CPU stall. Let's make sure we
+ * prevent such a case.
+ */
+- rate = clk_get_rate(vc4_hdmi->hsm_clock);
++ rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock);
+ if (!rate) {
+ ret = -EINVAL;
+ goto err_disable_clk;
diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.h b/drivers/gpu/drm/vc4/vc4_hdmi.h
index c3ed2b07df23..47f141ec8c40 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.h
@@ -1320,6 +1303,516 @@ index a0bf9560cf67..2a226be9b32a 100644
static inline void nvme_kick_requeue_lists(struct nvme_ctrl *ctrl)
{
}
+diff --git a/drivers/pci/pci-driver.c b/drivers/pci/pci-driver.c
+index 49238ddd39ee..5d8c37c3e15a 100644
+--- a/drivers/pci/pci-driver.c
++++ b/drivers/pci/pci-driver.c
+@@ -774,6 +774,12 @@ static int pci_pm_suspend(struct device *dev)
+
+ pci_dev->skip_bus_pm = false;
+
++ /*
++ * Disabling PTM allows some systems, e.g., Intel mobile chips
++ * since Coffee Lake, to enter a lower-power PM state.
++ */
++ pci_suspend_ptm(pci_dev);
++
+ if (pci_has_legacy_pm_support(pci_dev))
+ return pci_legacy_suspend(dev, PMSG_SUSPEND);
+
+@@ -987,6 +993,8 @@ static int pci_pm_resume(struct device *dev)
+ if (pci_dev->state_saved)
+ pci_restore_standard_config(pci_dev);
+
++ pci_resume_ptm(pci_dev);
++
+ if (pci_has_legacy_pm_support(pci_dev))
+ return pci_legacy_resume(dev);
+
+@@ -1274,6 +1282,8 @@ static int pci_pm_runtime_suspend(struct device *dev)
+ pci_power_t prev = pci_dev->current_state;
+ int error;
+
++ pci_suspend_ptm(pci_dev);
++
+ /*
+ * If pci_dev->driver is not set (unbound), we leave the device in D0,
+ * but it may go to D3cold when the bridge above it runtime suspends.
+@@ -1335,6 +1345,7 @@ static int pci_pm_runtime_resume(struct device *dev)
+ * D3cold when the bridge above it runtime suspended.
+ */
+ pci_pm_default_resume_early(pci_dev);
++ pci_resume_ptm(pci_dev);
+
+ if (!pci_dev->driver)
+ return 0;
+diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
+index 95bc329e74c0..107afa0a5b03 100644
+--- a/drivers/pci/pci.c
++++ b/drivers/pci/pci.c
+@@ -2706,24 +2706,12 @@ int pci_prepare_to_sleep(struct pci_dev *dev)
+ if (target_state == PCI_POWER_ERROR)
+ return -EIO;
+
+- /*
+- * There are systems (for example, Intel mobile chips since Coffee
+- * Lake) where the power drawn while suspended can be significantly
+- * reduced by disabling PTM on PCIe root ports as this allows the
+- * port to enter a lower-power PM state and the SoC to reach a
+- * lower-power idle state as a whole.
+- */
+- if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+- pci_disable_ptm(dev);
+-
+ pci_enable_wake(dev, target_state, wakeup);
+
+ error = pci_set_power_state(dev, target_state);
+
+- if (error) {
++ if (error)
+ pci_enable_wake(dev, target_state, false);
+- pci_restore_ptm_state(dev);
+- }
+
+ return error;
+ }
+@@ -2764,24 +2752,12 @@ int pci_finish_runtime_suspend(struct pci_dev *dev)
+ if (target_state == PCI_POWER_ERROR)
+ return -EIO;
+
+- /*
+- * There are systems (for example, Intel mobile chips since Coffee
+- * Lake) where the power drawn while suspended can be significantly
+- * reduced by disabling PTM on PCIe root ports as this allows the
+- * port to enter a lower-power PM state and the SoC to reach a
+- * lower-power idle state as a whole.
+- */
+- if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
+- pci_disable_ptm(dev);
+-
+ __pci_enable_wake(dev, target_state, pci_dev_run_wake(dev));
+
+ error = pci_set_power_state(dev, target_state);
+
+- if (error) {
++ if (error)
+ pci_enable_wake(dev, target_state, false);
+- pci_restore_ptm_state(dev);
+- }
+
+ return error;
+ }
+diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
+index 785f31086313..5cca2e58cce8 100644
+--- a/drivers/pci/pci.h
++++ b/drivers/pci/pci.h
+@@ -505,13 +505,17 @@ static inline int pci_iov_bus_range(struct pci_bus *bus)
+ #endif /* CONFIG_PCI_IOV */
+
+ #ifdef CONFIG_PCIE_PTM
++void pci_ptm_init(struct pci_dev *dev);
+ void pci_save_ptm_state(struct pci_dev *dev);
+ void pci_restore_ptm_state(struct pci_dev *dev);
+-void pci_disable_ptm(struct pci_dev *dev);
++void pci_suspend_ptm(struct pci_dev *dev);
++void pci_resume_ptm(struct pci_dev *dev);
+ #else
++static inline void pci_ptm_init(struct pci_dev *dev) { }
+ static inline void pci_save_ptm_state(struct pci_dev *dev) { }
+ static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
+-static inline void pci_disable_ptm(struct pci_dev *dev) { }
++static inline void pci_suspend_ptm(struct pci_dev *dev) { }
++static inline void pci_resume_ptm(struct pci_dev *dev) { }
+ #endif
+
+ unsigned long pci_cardbus_resource_alignment(struct resource *);
+@@ -575,12 +579,6 @@ static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
+ static inline void pcie_ecrc_get_policy(char *str) { }
+ #endif
+
+-#ifdef CONFIG_PCIE_PTM
+-void pci_ptm_init(struct pci_dev *dev);
+-#else
+-static inline void pci_ptm_init(struct pci_dev *dev) { }
+-#endif
+-
+ struct pci_dev_reset_methods {
+ u16 vendor;
+ u16 device;
+diff --git a/drivers/pci/pcie/ptm.c b/drivers/pci/pcie/ptm.c
+index 368a254e3124..b4e5f553467c 100644
+--- a/drivers/pci/pcie/ptm.c
++++ b/drivers/pci/pcie/ptm.c
+@@ -9,30 +9,38 @@
+ #include <linux/pci.h>
+ #include "../pci.h"
+
+-static void pci_ptm_info(struct pci_dev *dev)
++/*
++ * If the next upstream device supports PTM, return it; otherwise return
++ * NULL. PTM Messages are local, so both link partners must support it.
++ */
++static struct pci_dev *pci_upstream_ptm(struct pci_dev *dev)
+ {
+- char clock_desc[8];
++ struct pci_dev *ups = pci_upstream_bridge(dev);
+
+- switch (dev->ptm_granularity) {
+- case 0:
+- snprintf(clock_desc, sizeof(clock_desc), "unknown");
+- break;
+- case 255:
+- snprintf(clock_desc, sizeof(clock_desc), ">254ns");
+- break;
+- default:
+- snprintf(clock_desc, sizeof(clock_desc), "%uns",
+- dev->ptm_granularity);
+- break;
+- }
+- pci_info(dev, "PTM enabled%s, %s granularity\n",
+- dev->ptm_root ? " (root)" : "", clock_desc);
++ /*
++ * Switch Downstream Ports are not permitted to have a PTM
++ * capability; their PTM behavior is controlled by the Upstream
++ * Port (PCIe r5.0, sec 7.9.16), so if the upstream bridge is a
++ * Switch Downstream Port, look up one more level.
++ */
++ if (ups && pci_pcie_type(ups) == PCI_EXP_TYPE_DOWNSTREAM)
++ ups = pci_upstream_bridge(ups);
++
++ if (ups && ups->ptm_cap)
++ return ups;
++
++ return NULL;
+ }
+
+-void pci_disable_ptm(struct pci_dev *dev)
++/*
++ * Find the PTM Capability (if present) and extract the information we need
++ * to use it.
++ */
++void pci_ptm_init(struct pci_dev *dev)
+ {
+- int ptm;
+- u16 ctrl;
++ u16 ptm;
++ u32 cap;
++ struct pci_dev *ups;
+
+ if (!pci_is_pcie(dev))
+ return;
+@@ -41,21 +49,47 @@ void pci_disable_ptm(struct pci_dev *dev)
+ if (!ptm)
+ return;
+
+- pci_read_config_word(dev, ptm + PCI_PTM_CTRL, &ctrl);
+- ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
+- pci_write_config_word(dev, ptm + PCI_PTM_CTRL, ctrl);
++ dev->ptm_cap = ptm;
++ pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u32));
++
++ pci_read_config_dword(dev, ptm + PCI_PTM_CAP, &cap);
++ dev->ptm_granularity = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
++
++ /*
++ * Per the spec recommendation (PCIe r6.0, sec 7.9.15.3), select the
++ * furthest upstream Time Source as the PTM Root. For Endpoints,
++ * "the Effective Granularity is the maximum Local Clock Granularity
++ * reported by the PTM Root and all intervening PTM Time Sources."
++ */
++ ups = pci_upstream_ptm(dev);
++ if (ups) {
++ if (ups->ptm_granularity == 0)
++ dev->ptm_granularity = 0;
++ else if (ups->ptm_granularity > dev->ptm_granularity)
++ dev->ptm_granularity = ups->ptm_granularity;
++ } else if (cap & PCI_PTM_CAP_ROOT) {
++ dev->ptm_root = 1;
++ } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
++
++ /*
++ * Per sec 7.9.15.3, this should be the Local Clock
++ * Granularity of the associated Time Source. But it
++ * doesn't say how to find that Time Source.
++ */
++ dev->ptm_granularity = 0;
++ }
++
++ if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT ||
++ pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM)
++ pci_enable_ptm(dev, NULL);
+ }
+
+ void pci_save_ptm_state(struct pci_dev *dev)
+ {
+- int ptm;
++ u16 ptm = dev->ptm_cap;
+ struct pci_cap_saved_state *save_state;
+- u16 *cap;
++ u32 *cap;
+
+- if (!pci_is_pcie(dev))
+- return;
+-
+- ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
+ if (!ptm)
+ return;
+
+@@ -63,146 +97,152 @@ void pci_save_ptm_state(struct pci_dev *dev)
+ if (!save_state)
+ return;
+
+- cap = (u16 *)&save_state->cap.data[0];
+- pci_read_config_word(dev, ptm + PCI_PTM_CTRL, cap);
++ cap = (u32 *)&save_state->cap.data[0];
++ pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, cap);
+ }
+
+ void pci_restore_ptm_state(struct pci_dev *dev)
+ {
++ u16 ptm = dev->ptm_cap;
+ struct pci_cap_saved_state *save_state;
+- int ptm;
+- u16 *cap;
++ u32 *cap;
+
+- if (!pci_is_pcie(dev))
++ if (!ptm)
+ return;
+
+ save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_PTM);
+- ptm = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
+- if (!save_state || !ptm)
++ if (!save_state)
+ return;
+
+- cap = (u16 *)&save_state->cap.data[0];
+- pci_write_config_word(dev, ptm + PCI_PTM_CTRL, *cap);
++ cap = (u32 *)&save_state->cap.data[0];
++ pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, *cap);
+ }
+
+-void pci_ptm_init(struct pci_dev *dev)
++/* Enable PTM in the Control register if possible */
++static int __pci_enable_ptm(struct pci_dev *dev)
+ {
+- int pos;
+- u32 cap, ctrl;
+- u8 local_clock;
++ u16 ptm = dev->ptm_cap;
+ struct pci_dev *ups;
++ u32 ctrl;
+
+- if (!pci_is_pcie(dev))
+- return;
+-
+- /*
+- * Enable PTM only on interior devices (root ports, switch ports,
+- * etc.) on the assumption that it causes no link traffic until an
+- * endpoint enables it.
+- */
+- if ((pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT ||
+- pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END))
+- return;
++ if (!ptm)
++ return -EINVAL;
+
+ /*
+- * Switch Downstream Ports are not permitted to have a PTM
+- * capability; their PTM behavior is controlled by the Upstream
+- * Port (PCIe r5.0, sec 7.9.16).
++ * A device uses local PTM Messages to request time information
++ * from a PTM Root that's farther upstream. Every device along the
++ * path must support PTM and have it enabled so it can handle the
++ * messages. Therefore, if this device is not a PTM Root, the
++ * upstream link partner must have PTM enabled before we can enable
++ * PTM.
+ */
+- ups = pci_upstream_bridge(dev);
+- if (pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM &&
+- ups && ups->ptm_enabled) {
+- dev->ptm_granularity = ups->ptm_granularity;
+- dev->ptm_enabled = 1;
+- return;
++ if (!dev->ptm_root) {
++ ups = pci_upstream_ptm(dev);
++ if (!ups || !ups->ptm_enabled)
++ return -EINVAL;
+ }
+
+- pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
+- if (!pos)
+- return;
+-
+- pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_PTM, sizeof(u16));
+-
+- pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
+- local_clock = (cap & PCI_PTM_GRANULARITY_MASK) >> 8;
+-
+- /*
+- * There's no point in enabling PTM unless it's enabled in the
+- * upstream device or this device can be a PTM Root itself. Per
+- * the spec recommendation (PCIe r3.1, sec 7.32.3), select the
+- * furthest upstream Time Source as the PTM Root.
+- */
+- if (ups && ups->ptm_enabled) {
+- ctrl = PCI_PTM_CTRL_ENABLE;
+- if (ups->ptm_granularity == 0)
+- dev->ptm_granularity = 0;
+- else if (ups->ptm_granularity > local_clock)
+- dev->ptm_granularity = ups->ptm_granularity;
+- } else {
+- if (cap & PCI_PTM_CAP_ROOT) {
+- ctrl = PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT;
+- dev->ptm_root = 1;
+- dev->ptm_granularity = local_clock;
+- } else
+- return;
+- }
++ pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
+
++ ctrl |= PCI_PTM_CTRL_ENABLE;
++ ctrl &= ~PCI_PTM_GRANULARITY_MASK;
+ ctrl |= dev->ptm_granularity << 8;
+- pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
+- dev->ptm_enabled = 1;
++ if (dev->ptm_root)
++ ctrl |= PCI_PTM_CTRL_ROOT;
+
+- pci_ptm_info(dev);
++ pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl);
++ return 0;
+ }
+
++/**
++ * pci_enable_ptm() - Enable Precision Time Measurement
++ * @dev: PCI device
++ * @granularity: pointer to return granularity
++ *
++ * Enable Precision Time Measurement for @dev. If successful and
++ * @granularity is non-NULL, return the Effective Granularity.
++ *
++ * Return: zero if successful, or -EINVAL if @dev lacks a PTM Capability or
++ * is not a PTM Root and lacks an upstream path of PTM-enabled devices.
++ */
+ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
+ {
+- int pos;
+- u32 cap, ctrl;
+- struct pci_dev *ups;
+-
+- if (!pci_is_pcie(dev))
+- return -EINVAL;
+-
+- pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_PTM);
+- if (!pos)
+- return -EINVAL;
+-
+- pci_read_config_dword(dev, pos + PCI_PTM_CAP, &cap);
+- if (!(cap & PCI_PTM_CAP_REQ))
+- return -EINVAL;
+-
+- /*
+- * For a PCIe Endpoint, PTM is only useful if the endpoint can
+- * issue PTM requests to upstream devices that have PTM enabled.
+- *
+- * For Root Complex Integrated Endpoints, there is no upstream
+- * device, so there must be some implementation-specific way to
+- * associate the endpoint with a time source.
+- */
+- if (pci_pcie_type(dev) == PCI_EXP_TYPE_ENDPOINT) {
+- ups = pci_upstream_bridge(dev);
+- if (!ups || !ups->ptm_enabled)
+- return -EINVAL;
++ int rc;
++ char clock_desc[8];
+
+- dev->ptm_granularity = ups->ptm_granularity;
+- } else if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) {
+- dev->ptm_granularity = 0;
+- } else
+- return -EINVAL;
++ rc = __pci_enable_ptm(dev);
++ if (rc)
++ return rc;
+
+- ctrl = PCI_PTM_CTRL_ENABLE;
+- ctrl |= dev->ptm_granularity << 8;
+- pci_write_config_dword(dev, pos + PCI_PTM_CTRL, ctrl);
+ dev->ptm_enabled = 1;
+
+- pci_ptm_info(dev);
+-
+ if (granularity)
+ *granularity = dev->ptm_granularity;
++
++ switch (dev->ptm_granularity) {
++ case 0:
++ snprintf(clock_desc, sizeof(clock_desc), "unknown");
++ break;
++ case 255:
++ snprintf(clock_desc, sizeof(clock_desc), ">254ns");
++ break;
++ default:
++ snprintf(clock_desc, sizeof(clock_desc), "%uns",
++ dev->ptm_granularity);
++ break;
++ }
++ pci_info(dev, "PTM enabled%s, %s granularity\n",
++ dev->ptm_root ? " (root)" : "", clock_desc);
++
+ return 0;
+ }
+ EXPORT_SYMBOL(pci_enable_ptm);
+
++static void __pci_disable_ptm(struct pci_dev *dev)
++{
++ u16 ptm = dev->ptm_cap;
++ u32 ctrl;
++
++ if (!ptm)
++ return;
++
++ pci_read_config_dword(dev, ptm + PCI_PTM_CTRL, &ctrl);
++ ctrl &= ~(PCI_PTM_CTRL_ENABLE | PCI_PTM_CTRL_ROOT);
++ pci_write_config_dword(dev, ptm + PCI_PTM_CTRL, ctrl);
++}
++
++/**
++ * pci_disable_ptm() - Disable Precision Time Measurement
++ * @dev: PCI device
++ *
++ * Disable Precision Time Measurement for @dev.
++ */
++void pci_disable_ptm(struct pci_dev *dev)
++{
++ if (dev->ptm_enabled) {
++ __pci_disable_ptm(dev);
++ dev->ptm_enabled = 0;
++ }
++}
++EXPORT_SYMBOL(pci_disable_ptm);
++
++/*
++ * Disable PTM, but preserve dev->ptm_enabled so we silently re-enable it on
++ * resume if necessary.
++ */
++void pci_suspend_ptm(struct pci_dev *dev)
++{
++ if (dev->ptm_enabled)
++ __pci_disable_ptm(dev);
++}
++
++/* If PTM was enabled before suspend, re-enable it when resuming */
++void pci_resume_ptm(struct pci_dev *dev)
++{
++ if (dev->ptm_enabled)
++ __pci_enable_ptm(dev);
++}
++
+ bool pcie_ptm_enabled(struct pci_dev *dev)
+ {
+ if (!dev)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 4944798e75b5..079a29ef1bf2 100644
--- a/drivers/pci/quirks.c
@@ -1374,7 +1867,7 @@ index bbab424b0d55..ed86042fb57b 100644
* disconnected while waiting for the lock to succeed. */
usb_lock_device(hdev);
diff --git a/include/linux/efi.h b/include/linux/efi.h
-index 4459794b65db..79735fc77198 100644
+index f87b2f5db9f8..0b156c2a4ab3 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -43,6 +43,8 @@
@@ -1471,6 +1964,31 @@ index 3aa6030302f5..23b63de268a3 100644
* Security hooks for perf events
*
* @perf_event_open:
+diff --git a/include/linux/pci.h b/include/linux/pci.h
+index 060af91bafcd..cb5f796e3319 100644
+--- a/include/linux/pci.h
++++ b/include/linux/pci.h
+@@ -475,6 +475,7 @@ struct pci_dev {
+ unsigned int broken_cmd_compl:1; /* No compl for some cmds */
+ #endif
+ #ifdef CONFIG_PCIE_PTM
++ u16 ptm_cap; /* PTM Capability */
+ unsigned int ptm_root:1;
+ unsigned int ptm_enabled:1;
+ u8 ptm_granularity;
+@@ -1677,10 +1678,12 @@ bool pci_ats_disabled(void);
+
+ #ifdef CONFIG_PCIE_PTM
+ int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
++void pci_disable_ptm(struct pci_dev *dev);
+ bool pcie_ptm_enabled(struct pci_dev *dev);
+ #else
+ static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
+ { return -EINVAL; }
++static inline void pci_disable_ptm(struct pci_dev *dev) { }
+ static inline bool pcie_ptm_enabled(struct pci_dev *dev)
+ { return false; }
+ #endif
diff --git a/include/linux/rmi.h b/include/linux/rmi.h
index ab7eea01ab42..fff7c5f737fc 100644
--- a/include/linux/rmi.h