kernel 6.6.5

1 files changed, 160 insertions, 80 deletions

diff --git a/SOURCES/0001-amd-hdr.patch b/SOURCES/0001-amd-hdr.patch
index 7e0717f..6c0deff 100644
--- a/SOURCES/0001-amd-hdr.patch
+++ b/SOURCES/0001-amd-hdr.patch
@@ -1,17 +1,18 @@
-From 414938db7a335d0ba6579abf402cfaafdc98bae7 Mon Sep 17 00:00:00 2001
-From: Peter Jung <admin@ptr1337.dev>
-Date: Wed, 29 Nov 2023 19:55:12 +0100
-Subject: [PATCH 1/7] amd-hdr
+From a890fe8f821eab96408c2263320e1106d5263f10 Mon Sep 17 00:00:00 2001
+From: Thomas Crider <gloriouseggroll@gmail.com>
+Date: Wed, 6 Dec 2023 17:09:52 -0500
+Subject: [PATCH] hdr
 
-Signed-off-by: Peter Jung <admin@ptr1337.dev>
 ---
  drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h      |  71 ++
- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  34 +-
+ drivers/gpu/drm/amd/display/Kconfig           |   7 +
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c |  35 +-
  .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 100 +++
- .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 805 ++++++++++++++++--
+ .../amd/display/amdgpu_dm/amdgpu_dm_color.c   | 812 ++++++++++++++++--
  .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c    |  72 ++
- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 224 ++++-
- .../amd/display/dc/dcn10/dcn10_cm_common.c    |  95 ++-
+ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c   | 234 ++++-
+ .../amd/display/dc/dcn10/dcn10_cm_common.c    |  95 +-
+ .../amd/display/dc/dcn10/dcn10_hw_sequencer.c |  14 +-
  .../drm/amd/display/dc/dcn30/dcn30_hwseq.c    |  37 +
  .../drm/amd/display/dc/dcn30/dcn30_hwseq.h    |   3 +
  .../drm/amd/display/dc/dcn301/dcn301_init.c   |   2 +-
@@ -24,10 +25,10 @@ Signed-off-by: Peter Jung <admin@ptr1337.dev>
  include/drm/drm_plane.h                       |   7 +
  include/drm/drm_property.h                    |   6 +
  include/uapi/drm/drm_mode.h                   |   8 +
- 19 files changed, 1441 insertions(+), 90 deletions(-)
+ 21 files changed, 1473 insertions(+), 97 deletions(-)
 
 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
-index 32fe05c810c6f..84bf501b02f4c 100644
+index 32fe05c81..84bf501b0 100644
 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
 +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
 @@ -343,6 +343,77 @@ struct amdgpu_mode_info {
@@ -108,15 +109,39 @@ index 32fe05c810c6f..84bf501b02f4c 100644
  };
  
  #define AMDGPU_MAX_BL_LEVEL 0xFF
+diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig
+index 901d1961b..49523fa82 100644
+--- a/drivers/gpu/drm/amd/display/Kconfig
++++ b/drivers/gpu/drm/amd/display/Kconfig
+@@ -51,4 +51,11 @@ config DRM_AMD_SECURE_DISPLAY
+ 	  This option enables the calculation of crc of specific region via
+ 	  debugfs. Cooperate with specific DMCU FW.
+ 
++config DRM_AMD_COLOR_STEAMDECK
++	bool "Enable color calibration features for Steam Deck"
++	depends on DRM_AMD_DC
++	help
++	  Choose this option if you want to use AMDGPU features for broader
++	  color management support on Steam Deck.
++
+ endmenu
 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-index deedcd9978459..572c71a54df42 100644
+index deedcd997..ccd99545b 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
-@@ -4022,6 +4022,11 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
+@@ -2963,6 +2963,7 @@ static int dm_resume(void *handle)
+ 			dc_stream_release(dm_new_crtc_state->stream);
+ 			dm_new_crtc_state->stream = NULL;
+ 		}
++		dm_new_crtc_state->base.color_mgmt_changed = true;
+ 	}
+ 
+ 	for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
+@@ -4022,6 +4023,11 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
  		return r;
  	}
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +	if (amdgpu_dm_create_color_properties(adev))
 +		return -ENOMEM;
 +#endif
@@ -124,7 +149,7 @@ index deedcd9978459..572c71a54df42 100644
  	r = amdgpu_dm_audio_init(adev);
  	if (r) {
  		dc_release_state(state->context);
-@@ -5094,7 +5099,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
+@@ -5094,7 +5100,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev,
  	 * Always set input transfer function, since plane state is refreshed
  	 * every time.
  	 */
@@ -135,7 +160,7 @@ index deedcd9978459..572c71a54df42 100644
  	if (ret)
  		return ret;
  
-@@ -8117,6 +8124,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+@@ -8117,6 +8125,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
  			bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction;
  			bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func;
  			bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix;
@@ -146,7 +171,7 @@ index deedcd9978459..572c71a54df42 100644
  		}
  
  		amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state,
-@@ -8328,6 +8339,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
+@@ -8328,6 +8340,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
  				&acrtc_state->stream->csc_color_matrix;
  			bundle->stream_update.out_transfer_func =
  				acrtc_state->stream->out_transfer_func;
@@ -157,7 +182,7 @@ index deedcd9978459..572c71a54df42 100644
  		}
  
  		acrtc_state->stream->abm_level = acrtc_state->abm_level;
-@@ -9516,6 +9531,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
+@@ -9516,6 +9532,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm,
  	 * when a modeset is needed, to ensure it gets reprogrammed.
  	 */
  	if (dm_new_crtc_state->base.color_mgmt_changed ||
@@ -165,7 +190,7 @@ index deedcd9978459..572c71a54df42 100644
  	    drm_atomic_crtc_needs_modeset(new_crtc_state)) {
  		ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state);
  		if (ret)
-@@ -9583,6 +9599,10 @@ static bool should_reset_plane(struct drm_atomic_state *state,
+@@ -9583,6 +9600,10 @@ static bool should_reset_plane(struct drm_atomic_state *state,
  	 */
  	for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) {
  		struct amdgpu_framebuffer *old_afb, *new_afb;
@@ -176,7 +201,7 @@ index deedcd9978459..572c71a54df42 100644
  
  		if (other->type == DRM_PLANE_TYPE_CURSOR)
  			continue;
-@@ -9619,6 +9639,18 @@ static bool should_reset_plane(struct drm_atomic_state *state,
+@@ -9619,6 +9640,18 @@ static bool should_reset_plane(struct drm_atomic_state *state,
  		    old_other_state->color_encoding != new_other_state->color_encoding)
  			return true;
  
@@ -196,7 +221,7 @@ index deedcd9978459..572c71a54df42 100644
  		if (!old_other_state->fb || !new_other_state->fb)
  			continue;
 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
-index 9e4cc5eeda767..24c87f425afbb 100644
+index 9e4cc5eed..24c87f425 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
 @@ -33,6 +33,8 @@
@@ -339,7 +364,7 @@ index 9e4cc5eeda767..24c87f425afbb 100644
  
  void amdgpu_dm_update_connector_after_detect(
 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
-index a4cb23d059bd6..0442eeaa97637 100644
+index a4cb23d05..10fef576c 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c
 @@ -72,6 +72,7 @@
@@ -354,7 +379,7 @@ index a4cb23d059bd6..0442eeaa97637 100644
  	setup_x_points_distribution();
  }
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +/* Pre-defined Transfer Functions (TF)
 + *
 + * AMD driver supports pre-defined mathematical functions for transferring
@@ -462,54 +487,54 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +
 +	prop = drm_property_create(adev_to_drm(adev),
 +				   DRM_MODE_PROP_BLOB,
-+				   "AMD_PLANE_DEGAMMA_LUT", 0);
++				   "VALVE1_PLANE_DEGAMMA_LUT", 0);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_degamma_lut_property = prop;
 +
 +	prop = drm_property_create_range(adev_to_drm(adev),
 +					 DRM_MODE_PROP_IMMUTABLE,
-+					 "AMD_PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX);
++					 "VALVE1_PLANE_DEGAMMA_LUT_SIZE", 0, UINT_MAX);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_degamma_lut_size_property = prop;
 +
 +	prop = amdgpu_create_tf_property(adev_to_drm(adev),
-+					 "AMD_PLANE_DEGAMMA_TF",
++					 "VALVE1_PLANE_DEGAMMA_TF",
 +					 amdgpu_eotf);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_degamma_tf_property = prop;
 +
 +	prop = drm_property_create_range(adev_to_drm(adev),
-+					 0, "AMD_PLANE_HDR_MULT", 0, U64_MAX);
++					 0, "VALVE1_PLANE_HDR_MULT", 0, U64_MAX);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_hdr_mult_property = prop;
 +
 +	prop = drm_property_create(adev_to_drm(adev),
 +				   DRM_MODE_PROP_BLOB,
-+				   "AMD_PLANE_CTM", 0);
++				   "VALVE1_PLANE_CTM", 0);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_ctm_property = prop;
 +
 +	prop = drm_property_create(adev_to_drm(adev),
 +				   DRM_MODE_PROP_BLOB,
-+				   "AMD_PLANE_SHAPER_LUT", 0);
++				   "VALVE1_PLANE_SHAPER_LUT", 0);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_shaper_lut_property = prop;
 +
 +	prop = drm_property_create_range(adev_to_drm(adev),
 +					 DRM_MODE_PROP_IMMUTABLE,
-+					 "AMD_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX);
++					 "VALVE1_PLANE_SHAPER_LUT_SIZE", 0, UINT_MAX);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_shaper_lut_size_property = prop;
 +
 +	prop = amdgpu_create_tf_property(adev_to_drm(adev),
-+					 "AMD_PLANE_SHAPER_TF",
++					 "VALVE1_PLANE_SHAPER_TF",
 +					 amdgpu_inv_eotf);
 +	if (!prop)
 +		return -ENOMEM;
@@ -517,41 +542,41 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +
 +	prop = drm_property_create(adev_to_drm(adev),
 +				   DRM_MODE_PROP_BLOB,
-+				   "AMD_PLANE_LUT3D", 0);
++				   "VALVE1_PLANE_LUT3D", 0);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_lut3d_property = prop;
 +
 +	prop = drm_property_create_range(adev_to_drm(adev),
 +					 DRM_MODE_PROP_IMMUTABLE,
-+					 "AMD_PLANE_LUT3D_SIZE", 0, UINT_MAX);
++					 "VALVE1_PLANE_LUT3D_SIZE", 0, UINT_MAX);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_lut3d_size_property = prop;
 +
 +	prop = drm_property_create(adev_to_drm(adev),
 +				   DRM_MODE_PROP_BLOB,
-+				   "AMD_PLANE_BLEND_LUT", 0);
++				   "VALVE1_PLANE_BLEND_LUT", 0);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_blend_lut_property = prop;
 +
 +	prop = drm_property_create_range(adev_to_drm(adev),
 +					 DRM_MODE_PROP_IMMUTABLE,
-+					 "AMD_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX);
++					 "VALVE1_PLANE_BLEND_LUT_SIZE", 0, UINT_MAX);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_blend_lut_size_property = prop;
 +
 +	prop = amdgpu_create_tf_property(adev_to_drm(adev),
-+					 "AMD_PLANE_BLEND_TF",
++					 "VALVE1_PLANE_BLEND_TF",
 +					 amdgpu_eotf);
 +	if (!prop)
 +		return -ENOMEM;
 +	adev->mode_info.plane_blend_tf_property = prop;
 +
 +	prop = amdgpu_create_tf_property(adev_to_drm(adev),
-+					 "AMD_CRTC_REGAMMA_TF",
++					 "VALVE1_CRTC_REGAMMA_TF",
 +					 amdgpu_inv_eotf);
 +	if (!prop)
 +		return -ENOMEM;
@@ -583,8 +608,7 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +		matrix[i] = dc_fixpt_from_s3132(ctm->matrix[i - (i / 4)]);
 +	}
 +}
- 
--		matrix[i].value = val;
++
 +/**
 + * __drm_ctm2_to_dc_matrix - converts a DRM CTM2 to a DC CSC float matrix
 + * @ctm: DRM color transformation matrix
@@ -596,7 +620,8 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +				   struct fixed31_32 *matrix)
 +{
 +	int i;
-+
+ 
+-		matrix[i].value = val;
 +	/*
 +	 * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating
 +	 * with homogeneous coordinates, augment the matrix with 0's.
@@ -729,15 +754,15 @@ index a4cb23d059bd6..0442eeaa97637 100644
 -	gamma->num_entries = lut_size;
 +		gamma->type = GAMMA_CUSTOM;
 +		gamma->num_entries = lut_size;
- 
--	__drm_lut_to_dc_gamma(lut, gamma, false);
++
 +		__drm_lut_to_dc_gamma(lut, gamma, false);
 +	}
  
+-	__drm_lut_to_dc_gamma(lut, gamma, false);
++	res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL);
+ 
 -	res = mod_color_calculate_degamma_params(NULL, func, gamma, true);
 -	dc_gamma_release(&gamma);
-+	res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL);
-+
 +	if (gamma)
 +		dc_gamma_release(&gamma);
  
@@ -1064,7 +1089,7 @@ index a4cb23d059bd6..0442eeaa97637 100644
  		/*
  		 * For legacy gamma support we need the regamma input
  		 * in linear space. Assume that the input is sRGB.
-@@ -577,14 +1053,213 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
+@@ -577,14 +1053,220 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc,
  		dc_plane_state->in_transfer_func->tf = tf;
  
  		if (tf != TRANSFER_FUNCTION_SRGB &&
@@ -1145,8 +1170,15 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +	int ret;
 +
 +	/* We have nothing to do here, return */
++	/*
++	 * JoshA: WE HAVE TO DO THIS EVERY TIME.
++	 * It's on a new dc_plane_state allocation, none of this data is here!
++	 * !!!!!!!!
++	 * This was always true before we duped properties due to LUCK and the
++	 * properties matching.
 +	if (!plane_state->color_mgmt_changed)
 +		return 0;
++	*/
 +
 +	dc_plane_state->hdr_mult = dc_fixpt_from_s3132(dm_plane_state->hdr_mult);
 +
@@ -1285,7 +1317,7 @@ index a4cb23d059bd6..0442eeaa97637 100644
 +						    dc_plane_state, color_caps);
 +}
 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
-index 97b7a0b8a1c26..a05c210754d44 100644
+index 97b7a0b8a..f1707c774 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
 @@ -260,6 +260,7 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc)
@@ -1300,7 +1332,7 @@ index 97b7a0b8a1c26..a05c210754d44 100644
  }
  #endif
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +/**
 + * drm_crtc_additional_color_mgmt - enable additional color properties
 + * @crtc: DRM CRTC
@@ -1371,7 +1403,7 @@ index 97b7a0b8a1c26..a05c210754d44 100644
  #if defined(CONFIG_DEBUG_FS)
  	.late_register = amdgpu_dm_crtc_late_register,
  #endif
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +	.atomic_set_property = amdgpu_dm_atomic_crtc_set_property,
 +	.atomic_get_property = amdgpu_dm_atomic_crtc_get_property,
 +#endif
@@ -1382,14 +1414,14 @@ index 97b7a0b8a1c26..a05c210754d44 100644
  
  	drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +	dm_crtc_additional_color_mgmt(&acrtc->base);
 +#endif
  	return 0;
  
  fail:
 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
-index cc74dd69acf2b..17719e15cbe58 100644
+index cc74dd69a..2ed20e6e4 100644
 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
 +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
 @@ -1333,8 +1333,14 @@ static void dm_drm_plane_reset(struct drm_plane *plane)
@@ -1409,20 +1441,30 @@ index cc74dd69acf2b..17719e15cbe58 100644
  }
  
  static struct drm_plane_state *
-@@ -1354,6 +1360,22 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
+@@ -1354,6 +1360,32 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane)
  		dc_plane_state_retain(dm_plane_state->dc_state);
  	}
  
-+	if (dm_plane_state->degamma_lut)
-+		drm_property_blob_get(dm_plane_state->degamma_lut);
-+	if (dm_plane_state->ctm)
-+		drm_property_blob_get(dm_plane_state->ctm);
-+	if (dm_plane_state->shaper_lut)
-+		drm_property_blob_get(dm_plane_state->shaper_lut);
-+	if (dm_plane_state->lut3d)
-+		drm_property_blob_get(dm_plane_state->lut3d);
-+	if (dm_plane_state->blend_lut)
-+		drm_property_blob_get(dm_plane_state->blend_lut);
++	if (old_dm_plane_state->degamma_lut) {
++		drm_property_blob_get(old_dm_plane_state->degamma_lut);
++		dm_plane_state->degamma_lut = old_dm_plane_state->degamma_lut;
++	}
++	if (old_dm_plane_state->ctm) {
++		drm_property_blob_get(old_dm_plane_state->ctm);
++		dm_plane_state->ctm = old_dm_plane_state->ctm;
++	}
++	if (old_dm_plane_state->shaper_lut) {
++		drm_property_blob_get(old_dm_plane_state->shaper_lut);
++		dm_plane_state->shaper_lut = old_dm_plane_state->shaper_lut;
++	}
++	if (old_dm_plane_state->lut3d) {
++		drm_property_blob_get(old_dm_plane_state->lut3d);
++		dm_plane_state->lut3d = old_dm_plane_state->lut3d;
++	}
++	if (old_dm_plane_state->blend_lut) {
++		drm_property_blob_get(old_dm_plane_state->blend_lut);
++		dm_plane_state->blend_lut = old_dm_plane_state->blend_lut;
++	}
 +
 +	dm_plane_state->degamma_tf = old_dm_plane_state->degamma_tf;
 +	dm_plane_state->hdr_mult = old_dm_plane_state->hdr_mult;
@@ -1432,7 +1474,7 @@ index cc74dd69acf2b..17719e15cbe58 100644
  	return &dm_plane_state->base;
  }
  
-@@ -1421,12 +1443,203 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane,
+@@ -1421,12 +1453,203 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane,
  {
  	struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
  
@@ -1453,7 +1495,7 @@ index cc74dd69acf2b..17719e15cbe58 100644
  	drm_atomic_helper_plane_destroy_state(plane, state);
  }
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +static void
 +dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm,
 +					     struct drm_plane *plane)
@@ -1636,29 +1678,29 @@ index cc74dd69acf2b..17719e15cbe58 100644
  static const struct drm_plane_funcs dm_plane_funcs = {
  	.update_plane	= drm_atomic_helper_update_plane,
  	.disable_plane	= drm_atomic_helper_disable_plane,
-@@ -1435,6 +1648,10 @@ static const struct drm_plane_funcs dm_plane_funcs = {
+@@ -1435,6 +1658,10 @@ static const struct drm_plane_funcs dm_plane_funcs = {
  	.atomic_duplicate_state = dm_drm_plane_duplicate_state,
  	.atomic_destroy_state = dm_drm_plane_destroy_state,
  	.format_mod_supported = dm_plane_format_mod_supported,
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +	.atomic_set_property = dm_atomic_plane_set_property,
 +	.atomic_get_property = dm_atomic_plane_get_property,
 +#endif
  };
  
  int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
-@@ -1514,6 +1731,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
+@@ -1514,6 +1741,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
  
  	drm_plane_helper_add(plane, &dm_plane_helper_funcs);
  
-+#ifdef AMD_PRIVATE_COLOR
++#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK
 +	dm_atomic_plane_attach_color_mgmt_properties(dm, plane);
 +#endif
  	/* Create (reset) the plane state */
  	if (plane->funcs->reset)
  		plane->funcs->reset(plane);
 diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
-index 3538973bd0c6c..04b2e04b68f33 100644
+index 3538973bd..04b2e04b6 100644
 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
 +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
 @@ -349,20 +349,37 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx,
@@ -1775,8 +1817,46 @@ index 3538973bd0c6c..04b2e04b68f33 100644
  			j++;
  		}
  	}
+diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+index 79befa17b..4daf8621b 100644
+--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
++++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+@@ -2486,17 +2486,17 @@ void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx)
+ 	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
+ 
+ 
+-	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
++	if (pipe_ctx->plane_state &&
++	    pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
+ 		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
+ 		for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
+ 			adjust.temperature_matrix[i] =
+-				pipe_ctx->stream->gamut_remap_matrix.matrix[i];
+-	} else if (pipe_ctx->plane_state &&
+-		   pipe_ctx->plane_state->gamut_remap_matrix.enable_remap == true) {
++				pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
++	} else if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
+ 		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
+ 		for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
+ 			adjust.temperature_matrix[i] =
+-				pipe_ctx->plane_state->gamut_remap_matrix.matrix[i];
++				pipe_ctx->stream->gamut_remap_matrix.matrix[i];
+ 	}
+ 
+ 	pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
+@@ -2942,8 +2942,8 @@ void dcn10_program_pipe(
+ 	hws->funcs.set_hdr_multiplier(pipe_ctx);
+ 
+ 	if (pipe_ctx->plane_state->update_flags.bits.full_update ||
+-			pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
+-			pipe_ctx->plane_state->update_flags.bits.gamma_change)
++	    pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
++	    pipe_ctx->plane_state->update_flags.bits.gamma_change)
+ 		hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
+ 
+ 	/* dcn10_translate_regamma_to_hw_format takes 750us to finish
 diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
-index 255713ec29bb0..fce9b33c0f881 100644
+index 255713ec2..fce9b33c0 100644
 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
 +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
 @@ -186,6 +186,43 @@ bool dcn30_set_input_transfer_func(struct dc *dc,
@@ -1824,7 +1904,7 @@ index 255713ec29bb0..fce9b33c0f881 100644
  				struct pipe_ctx *pipe_ctx,
  				const struct dc_stream_state *stream)
 diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
-index ce19c54097f8b..e557e2b986187 100644
+index ce19c5409..e557e2b98 100644
 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
 +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.h
 @@ -58,6 +58,9 @@ bool dcn30_set_blend_lut(struct pipe_ctx *pipe_ctx,
@@ -1838,7 +1918,7 @@ index ce19c54097f8b..e557e2b986187 100644
  				struct pipe_ctx *pipe_ctx,
  				const struct dc_stream_state *stream);
 diff --git a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
-index 61205cdbe2d5a..fdbe3d42cd7b6 100644
+index 61205cdbe..fdbe3d42c 100644
 --- a/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
 +++ b/drivers/gpu/drm/amd/display/dc/dcn301/dcn301_init.c
 @@ -33,7 +33,7 @@
@@ -1851,7 +1931,7 @@ index 61205cdbe2d5a..fdbe3d42cd7b6 100644
  	.power_down_on_boot = dcn10_power_down_on_boot,
  	.apply_ctx_to_hw = dce110_apply_ctx_to_hw,
 diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h
-index d4cf7ead1d877..84da1dd34efd1 100644
+index d4cf7ead1..84da1dd34 100644
 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h
 +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h
 @@ -69,6 +69,18 @@ static const struct fixed31_32 dc_fixpt_epsilon = { 1LL };
@@ -1874,7 +1954,7 @@ index d4cf7ead1d877..84da1dd34efd1 100644
   * @brief
   * Initialization routines
 diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c
-index dc01c43f61930..d72c22dcf6855 100644
+index dc01c43f6..d72c22dcf 100644
 --- a/drivers/gpu/drm/arm/malidp_crtc.c
 +++ b/drivers/gpu/drm/arm/malidp_crtc.c
 @@ -221,7 +221,7 @@ static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
@@ -1887,7 +1967,7 @@ index dc01c43f61930..d72c22dcf6855 100644
  	ctm = (struct drm_color_ctm *)state->ctm->data;
  	for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
 diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
-index c277b198fa3fa..c3df45f901456 100644
+index c277b198f..c3df45f90 100644
 --- a/drivers/gpu/drm/drm_atomic.c
 +++ b/drivers/gpu/drm/drm_atomic.c
 @@ -733,6 +733,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p,
@@ -1899,7 +1979,7 @@ index c277b198fa3fa..c3df45f901456 100644
  	if (plane->funcs->atomic_print_state)
  		plane->funcs->atomic_print_state(p, state);
 diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c
-index 784e63d70a421..25bb0859fda74 100644
+index 784e63d70..25bb0859f 100644
 --- a/drivers/gpu/drm/drm_atomic_state_helper.c
 +++ b/drivers/gpu/drm/drm_atomic_state_helper.c
 @@ -338,6 +338,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane,
@@ -1911,7 +1991,7 @@ index 784e63d70a421..25bb0859fda74 100644
  EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state);
  
 diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c
-index dfec479830e49..f72ef6493340a 100644
+index dfec47983..f72ef6493 100644
 --- a/drivers/gpu/drm/drm_property.c
 +++ b/drivers/gpu/drm/drm_property.c
 @@ -751,6 +751,55 @@ bool drm_property_replace_blob(struct drm_property_blob **blob,
@@ -1971,7 +2051,7 @@ index dfec479830e49..f72ef6493340a 100644
  			   void *data, struct drm_file *file_priv)
  {
 diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h
-index 912f1e4156853..08d7a7f0188fe 100644
+index 912f1e415..08d7a7f01 100644
 --- a/include/drm/drm_mode_object.h
 +++ b/include/drm/drm_mode_object.h
 @@ -60,7 +60,7 @@ struct drm_mode_object {
@@ -1984,7 +2064,7 @@ index 912f1e4156853..08d7a7f0188fe 100644
   * struct drm_object_properties - property tracking for &drm_mode_object
   */
 diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h
-index 79d62856defbf..4f87803b3ea12 100644
+index 79d62856d..4f87803b3 100644
 --- a/include/drm/drm_plane.h
 +++ b/include/drm/drm_plane.h
 @@ -237,6 +237,13 @@ struct drm_plane_state {
@@ -2002,7 +2082,7 @@ index 79d62856defbf..4f87803b3ea12 100644
  
  static inline struct drm_rect
 diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h
-index 65bc9710a4702..082f29156b3e3 100644
+index 65bc9710a..082f29156 100644
 --- a/include/drm/drm_property.h
 +++ b/include/drm/drm_property.h
 @@ -279,6 +279,12 @@ struct drm_property_blob *drm_property_create_blob(struct drm_device *dev,
@@ -2019,7 +2099,7 @@ index 65bc9710a4702..082f29156b3e3 100644
  				     struct drm_property_blob **replace,
  				     size_t length,
 diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
-index ea1b639bcb288..cea5653e4020b 100644
+index ea1b639bc..cea5653e4 100644
 --- a/include/uapi/drm/drm_mode.h
 +++ b/include/uapi/drm/drm_mode.h
 @@ -846,6 +846,14 @@ struct drm_color_ctm {