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-rw-r--r--SOURCES/0001-kms-nv50-Move-8BPC-limit-for-MST-into-nv50_mstc_get_.patch65
1 files changed, 65 insertions, 0 deletions
diff --git a/SOURCES/0001-kms-nv50-Move-8BPC-limit-for-MST-into-nv50_mstc_get_.patch b/SOURCES/0001-kms-nv50-Move-8BPC-limit-for-MST-into-nv50_mstc_get_.patch
new file mode 100644
index 0000000..0a6a4cf
--- /dev/null
+++ b/SOURCES/0001-kms-nv50-Move-8BPC-limit-for-MST-into-nv50_mstc_get_.patch
@@ -0,0 +1,65 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Lyude Paul <lyude@redhat.com>
+Date: Mon, 11 May 2020 18:41:26 -0400
+Subject: [PATCH] kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()
+
+This just limits the BPC for MST connectors to a maximum of 8 from
+nv50_mstc_get_modes(), instead of doing so during
+nv50_msto_atomic_check(). This doesn't introduce any functional changes
+yet (other then userspace now lying about the max bpc, but we can't
+support that yet anyway so meh). But, we'll need this in a moment so
+that we can share mode validation between SST and MST which will fix
+some real world issues.
+
+Signed-off-by: Lyude Paul <lyude@redhat.com>
+Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
+---
+ drivers/gpu/drm/nouveau/dispnv50/disp.c | 25 ++++++++++++++-----------
+ 1 file changed, 14 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
+index 1db4f20b8697..e92e7bf49780 100644
+--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
++++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
+@@ -908,15 +908,9 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
+ if (!state->duplicated) {
+ const int clock = crtc_state->adjusted_mode.clock;
+
+- /*
+- * XXX: Since we don't use HDR in userspace quite yet, limit
+- * the bpc to 8 to save bandwidth on the topology. In the
+- * future, we'll want to properly fix this by dynamically
+- * selecting the highest possible bpc that would fit in the
+- * topology
+- */
+- asyh->or.bpc = min(connector->display_info.bpc, 8U);
+- asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3, false);
++ asyh->or.bpc = connector->display_info.bpc;
++ asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
++ false);
+ }
+
+ slots = drm_dp_atomic_find_vcpi_slots(state, &mstm->mgr, mstc->port,
+@@ -1076,8 +1070,17 @@ nv50_mstc_get_modes(struct drm_connector *connector)
+ if (mstc->edid)
+ ret = drm_add_edid_modes(&mstc->connector, mstc->edid);
+
+- if (!mstc->connector.display_info.bpc)
+- mstc->connector.display_info.bpc = 8;
++ /*
++ * XXX: Since we don't use HDR in userspace quite yet, limit the bpc
++ * to 8 to save bandwidth on the topology. In the future, we'll want
++ * to properly fix this by dynamically selecting the highest possible
++ * bpc that would fit in the topology
++ */
++ if (connector->display_info.bpc)
++ connector->display_info.bpc =
++ clamp(connector->display_info.bpc, 6U, 8U);
++ else
++ connector->display_info.bpc = 8;
+
+ if (mstc->native)
+ drm_mode_destroy(mstc->connector.dev, mstc->native);
+--
+2.26.2
+