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`std.Io.tty.Config.detect` may be an expensive check (e.g. involving
syscalls), and doing it every time we need to print isn't really
necessary; under normal usage, we can compute the value once and cache
it for the whole program's execution. Since anyone outputting to stderr
may reasonably want this information (in fact they are very likely to),
it makes sense to cache it and return it from `lockStderrWriter`. Call
sites who do not need it will experience no significant overhead, and
can just ignore the TTY config with a `const w, _` destructure.
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* fix: add `i86` cpu in `update_cpu_features`
* feat: add `x86_16` debug `cpu_context`
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As with Solaris (dba1bf935390ddb0184a4dc72245454de6c06fd2), we have no way to
actually audit contributions for these OSs. IBM also makes it even harder than
Oracle to actually obtain these OSs.
closes #23695
closes #23694
closes #3655
closes #23693
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* Remove the generic model; we already have generic_la32 and generic_la64 and
pick appropriately based on bitness.
* Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's
actually pretty misleading and useless; it doesn't represent any real CPU and
has less features than generic_la64.
* Add la64v1_0 and la64v1_1 models.
* Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to
the baseline feature set.
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evex512 for avx512f
Intel has abandoned AVX10.N/128,256; AVX10.N is now always 512-bit.
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/lib/std/Target/amdgcn.zig:1656:5: error: evaluation exceeded 1000 backwards branches
for (&result, 0..) |*elem, i| {
^~~
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Closes #21818.
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`OpCapability` and `OpExtension` now can also be emitted from inline assembly
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This will mainly be used when targeting our wasm2c implementation which has no
problem with zero-length bulk memory operations, as a non-standard extension.
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See: https://github.com/WebAssembly/tool-conventions/pull/235
This is not *quite* using the same features as the spec'd lime1 model because
LLVM 19 doesn't have the level of feature granularity that we need for that.
This will be fixed once we upgrade to LLVM 20.
Part of #21818.
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Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
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To my knowledge there isn't an implementation of `sse4.2` that doesn't have `crc32`.
The Clang driver also sets `crc32` to be implicitly enabled when an explicit `-crc32`
wasn't provided. This matches that behaviour.
We need this behaviour to compile libraries like `rocksdb` which currently guard against
`crc32` intrinsics by checking for `sse4.2`.
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* Cleanup the argument handling logic to allow for optional arguments.
* Add a filter for which `llvm_target` to process.
* Switch to using a threadpool, needed for skipping llvm targets cleanly
and better distributes the work.
* Remove a seemingly useless piece of logic. I re-ran the script and it gave identical outputs.
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This was an inconsistency left over from c825b567b26c475e058e074e5d22af006854fab6.
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Like d1d95294fd657f771657ea671a6984b860347fb0, this is more Apple nonsense where
they abused the arch component of the triple to encode what's really an ABI.
Handling this correctly in Zig's target triple model would take quite a bit of
work. Fortunately, the last Armv7-based Apple Watch was released in 2017 and
these targets are now considered legacy. By the time Zig hits 1.0, they will be
a distant memory. So just remove them.
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`test`: Rewrite the target triple list for `llvm_targets`.
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At bare minimum, the compiler expects std.Target.<arch>.cpu.generic to work for
any given architecture when generating the builtin module. So rather than try to
hack that into working when the affected modules are omitted, just actually keep
them.
This affected lanai and xcore.
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cortex-m85 already has 8msecext, which is not the same as trustzone. The former
is for the M profile, while the latter is for the A profile.
Revert of a small part of #18498.
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misuse.
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* Add `ProcessorAlias` support.
* Bump output buffer size.
* Include `i` extension in RISC-V baselines.
* Update evaluation branch quota for RISC-V.
* Retain some CPU features that LLVM removed.
* Flatten more 'meta-features' used for CPU models.
* Remove some superfluous dependencies.
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The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.
This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
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From https://ziglang.org/documentation/master/#Names:
> If `x` is callable, and `x`'s return type is `type`, then `x` should
> be `TitleCase`.
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Before this commit, the name `v9.5a` was being used for two different features, and one was overwriting the other in the `all_features` array.
`arrowlake_s` is an alias for `arrowlake-s`
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closes #20261
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release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
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`{}` for decls
`{p}` for enum fields
`{p_}` for struct fields and in contexts following a `.`
Elsewhere, `{p}` was used since it's equivalent to the old behavior.
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Based on the Arm Cortex-M Processor Comparison Table v3.0
<https://developer.arm.com/documentation/102787/0300/?lang=en>
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Justification: exec, execv etc are unix concepts and portable version
should be called differently.
Do no touch non-Zig code. Adjust error names as well, if associated.
Closes #5853.
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* some manual fixes to generated CPU features code. in the future it
would be nice to make the script do those automatically. I suspect
the sm_90a thing is a bug in LLVM.
* add liteos to various target OS switches. I know nothing about this
OS; someone will need to work specifically on support for this OS
when the time comes to support it properly in zig.
* while waiting for the compiler, I went ahead and made more
conservative choices about when to use `inline` in std/Target.zig
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release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8
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Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
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json.parse* (#15705)
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