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Age	Commit message (Collapse)	Author
2022-09-09	stage2 ARM: amend implementation of various AIR instructions	joachimschmidt557
	- unwrap_errunion_err for registers - unwrap_errunion_payload for registers - ptr_slice_len_ptr for all MCValues - ptr_slice_ptr_ptr for all MCValues
2022-07-13	AstGen: fix loop control flow applying to wrong loop	Andrew Kelley
	In the case of 'continue' or 'break' inside the 'else' block of a 'while' or 'for' loop. Closes #12109
2022-06-25	stage2 ARM: implement basic intCast and error union wrapping	joachimschmidt557

2022-03-24	AstGen: emit break_inline from inline while loop	Andrew Kelley

2022-03-19	stage2: add debug info for payload captures	Veikka Tuominen

2022-03-09	Sema: implement pointer to tuple to pointer to array coercion	Andrew Kelley
	This involved an LLVM backend fix for the aggregate_init instruction.
2022-03-08	stage2 ARM: implement ret_load	joachimschmidt557

2022-03-05	stage2 AArch64: add more slice support	joachimschmidt557
	* airSlice * airArrayToSlice * and initial support for airSlicePtr and co
2022-02-28	x64: pass more behavior tests	Jakub Konka

2022-02-27	stage2 ARM: implement slice and array_to_slice	joachimschmidt557

2022-02-22	Skip unsupported while behavior tests	Jakub Konka

2022-02-22	Port more behavior tests	Jakub Konka

2022-01-17	Sema: implement else capture value	Andrew Kelley
	The ZIR instructions `switch_capture_else` and `switch_capture_ref` are removed because they are not needed. Instead, the prong index is set to max int for the special prong. Else prong with error sets is not handled yet. Adds a new behavior test because there was not a prior on to cover only the capture value of else on a switch.
2021-12-27	AstGen: fix loop result locations	Andrew Kelley
	The main problem was that the loop body was treated as an expression that was one of the peer result values of a loop, when in reality the loop body is noreturn and only the `break` operands are the result values of loops. This was solved by introducing an override that prevents rvalue() from emitting a store to result location instruction for loop bodies. An orthogonal change also included in this commit is switching `elem_val` index expressions to using `coerced_ty` and doing the coercion to `usize` inside `Sema`, resulting in smaller ZIR (since the cast becomes implied). I also changed the break operand expression to use `reachableExpr`, introducing a new compile error for double break. This makes a few more behavior tests pass for `while` and `for` loops.
2021-11-27	stage2: implement `@typeName`	Andrew Kelley
	* stage1: change the `@typeName` of `@TypeOf(undefined)`, `@TypeOf(null)`, and `@TypeOf(.foo)` to match stage2. * move passing behavior tests to the passing-for-stage2 section.
2021-10-14	stage2: LLVM backend: implement `wrap_optional` AIR	Andrew Kelley
	and move over some passing tests
2021-10-02	AstGen: fix `while` and `for` with unreachable bodies	Andrew Kelley
	Companion commit to 61a53a587558ff1fe1b0ec98bb424022885edccf. This commit also moves over a bunch of behavior test cases to the passing-for-stage2 section.
2021-06-21	fix code broken from previous commit	Jacob G-W

2021-05-08	Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgen	Andrew Kelley
	Conflicts: * doc/langref.html.in * lib/std/enums.zig * lib/std/fmt.zig * lib/std/hash/auto_hash.zig * lib/std/math.zig * lib/std/mem.zig * lib/std/meta.zig * test/behavior/alignof.zig * test/behavior/bitcast.zig * test/behavior/bugs/1421.zig * test/behavior/cast.zig * test/behavior/ptrcast.zig * test/behavior/type_info.zig * test/behavior/vector.zig Master branch added `try` to a bunch of testing function calls, and some lines also had changed how to refer to the native architecture and other `@import("builtin")` stuff.
2021-04-29	move behavior tests from test/stage1/ to test/	Andrew Kelley
	And fix test cases to make them pass. This is in preparation for starting to pass behavior tests with self-hosted.