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2025-10-03x86_64: fix bool vector init register clobberJacob Young
Closes #25439
2025-09-24remove behavior test that depended on std.zig.c_translationAndrew Kelley
behavior tests may not depend on this namespace.
2025-09-20allow some test cases to regressAndrew Kelley
tracked by #24061 - these should be re-enabled once that is solved.
2025-09-20disable failing stage2_aarch64 behavior testsAndrew Kelley
2025-09-20aarch64: enable fixed behaviorJacob Young
2025-09-20compiler: require comptime vector indexesAndrew Kelley
2025-09-10x86_64: fix strictness edge cases in `+|`Jacob Young
Closes #25145
2025-09-07wasm backend: disable failing behavior testsAndrew Kelley
2025-09-04Reenable vector tests for armeb/thumbebLuna Schwalbe
https://github.com/ziglang/zig/issues/22060 has been fixed by upstream.
2025-08-30test: re-enable a bunch of vector behavior tests on hexagonAlex Rønne Petersen
2025-07-22aarch64: add new from scratch self-hosted backendJacob Young
2025-07-01test: Disable vector division operators on RISC-V with vector supportAlex Rønne Petersen
https://github.com/ziglang/zig/issues/24301
2025-06-19x86_64: increase passing test coverage on windowsJacob Young
Now that codegen has no references to linker state this is much easier. Closes #24153
2025-06-16rename spirv backend nameAli Cheraghi
`stage2_spirv64` -> `stage2_spirv`
2025-06-12Allow more operators on bool vectors (#24131)Daniel Kongsgaard
* Sema: allow binary operations and boolean not on vectors of bool * langref: Clarify use of operators on vectors (`and` and `or` not allowed) closes #24093
2025-06-11test: Enable some working vector testsDanielkonge
Closes #12827.
2025-06-05std.Target: Introduce Cpu convenience functions for feature tests.Alex Rønne Petersen
Before: * std.Target.arm.featureSetHas(target.cpu.features, .has_v7) * std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov }) * std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory }) After: * target.cpu.has(.arm, .has_v7) * target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov }) * target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-02x86_64: implement integer `@divFloor` and `@mod`Jacob Young
Closes #24039
2025-06-01Legalize: implement scalarization of overflow intrinsicsJacob Young
2025-06-01Legalize: implement scalarization of `@shuffle`Jacob Young
2025-05-31Legalize: implement scalarization of binary operationsJacob Young
2025-05-28x86_64: implement strict float `@reduce(.Max)`Jacob Young
2025-05-28x86_64: implement integer `@reduce(.Add)`Jacob Young
2025-05-17x86_64: implement `vector_store_elem`Jacob Young
2025-05-17x86_64: rewrite `@splat`Jacob Young
2025-05-17x86_64: rewrite vector `-|`Jacob Young
2025-05-17x86_64: rewrite vector `+|`Jacob Young
2025-04-28test: Disable `vector reduce operation` for sparc.Alex Rønne Petersen
https://github.com/ziglang/zig/issues/23719
2025-04-04Revert "test: Partially disable `vector float operators` on mips."Alex Rønne Petersen
This reverts commit 19a91084c2a29175bad47d41cd11935904ede0b9. Closes #21051.
2025-03-16Sema: rewrite comptime arithmeticmlugg
This commit reworks how Sema handles arithmetic on comptime-known values, fixing many bugs in the process. The general pattern is that arithmetic on comptime-known values is now handled by the new namespace `Sema.arith`. Functions handling comptime arithmetic no longer live on `Value`; this is because some of them can emit compile errors, so some *can't* go on `Value`. Only semantic analysis should really be doing arithmetic on `Value`s anyway, so it makes sense for it to integrate more tightly with `Sema`. This commit also implements more coherent rules surrounding how `undefined` interacts with comptime and mixed-comptime-runtime arithmetic. The rules are as follows. * If an operation cannot trigger Illegal Behavior, and any operand is `undefined`, the result is `undefined`. This includes operations like `0 *| undef`, where the LHS logically *could* be used to determine a defined result. This is partly to simplify the language, but mostly to permit codegen backends to represent `undefined` values as completely invalid states. * If an operation *can* trigger Illegal Behvaior, and any operand is `undefined`, then Illegal Behavior results. This occurs even if the operand in question isn't the one that "decides" illegal behavior; for instance, `undef / 1` is undefined. This is for the same reasons as described above. * An operation which would trigger Illegal Behavior, when evaluated at comptime, instead triggers a compile error. Additionally, if one operand is comptime-known undef, such that the other (runtime-known) operand isn't needed to determine that Illegal Behavior would occur, the compile error is triggered. * The only situation in which an operation with one comptime-known operand has a comptime-known result is if that operand is undefined, in which case the result is either undefined or a compile error per the above rules. This could potentially be loosened in future (for instance, `0 * rt` could be comptime-known 0 with a runtime assertion that `rt` is not undefined), but at least for now, defining it more conservatively simplifies the language and allows us to easily change this in future if desired. This commit fixes many bugs regarding the handling of `undefined`, particularly in vectors. Along with a collection of smaller tests, two very large test cases are added to check arithmetic on `undefined`. The operations which have been rewritten in this PR are: * `+`, `+%`, `+|`, `@addWithOverflow` * `-`, `-%`, `-|`, `@subWithOverflow` * `*`, `*%`, `*|`, `@mulWithOverflow` * `/`, `@divFloor`, `@divTrunc`, `@divExact` * `%`, `@rem`, `@mod` Other arithmetic operations are currently unchanged. Resolves: #22743 Resolves: #22745 Resolves: #22748 Resolves: #22749 Resolves: #22914
2025-02-24test: skip failing tests with spirv-vulkanAli Cheraghi
2025-02-06x86_64: rewrite most of the remaining float opsJacob Young
2025-01-16x86_64: pass more behavior testsJacob Young
2025-01-16x86_64: implement switch jump tablesJacob Young
2025-01-16x86_64: implement clz and notJacob Young
2025-01-06test: Disable vector behavior tests affected by #22060 for thumbeb too.Alex Rønne Petersen
2024-12-13test: Disable some vector behavior tests on armeb.Alex Rønne Petersen
https://github.com/ziglang/zig/issues/22060
2024-11-04test: Disable some vector behavior tests on aarch64_be.Alex Rønne Petersen
See: https://github.com/ziglang/zig/issues/21893
2024-11-03std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().Alex Rønne Petersen
The old isARM() function was a portability trap. With the name it had, it seemed like the obviously correct function to use, but it didn't include Thumb. In the vast majority of cases where someone wants to ask "is the target Arm?", Thumb *should* be included. There are exactly 3 cases in the codebase where we do actually need to exclude Thumb, although one of those is in Aro and mirrors a check in Clang that is itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-09-19test: Re-enable `store vector with memset` for LLVM.Alex Rønne Petersen
Closes #16177.
2024-09-12test: Re-enable a bunch of behavior tests with LLVM.Alex Rønne Petersen
Closes #10627. Closes #12013. Closes #18034.
2024-09-11Merge pull request #21269 from alexrp/soft-floatAndrew Kelley
Fix soft float support, split musl triples by float ABI, and enable CI
2024-09-10test: Disable `store vector with memset` on soft float arm.Alex Rønne Petersen
https://github.com/ziglang/zig/issues/16177
2024-09-07test: Re-enable `vector reduce operation` for most LLVM targets.Alex Rønne Petersen
mips64 failure is tracked in #21091. Closes #7138.
2024-09-07test: Re-enable `vector shift operators` for all LLVM targets.Alex Rønne Petersen
Closes #4951.
2024-09-05test: Disable `store vector with memset` on powerpc64.Alex Rønne Petersen
This will be re-enabled with LLVM 19.
2024-08-28std: update `std.builtin.Type` fields to follow naming conventionsmlugg
The compiler actually doesn't need any functional changes for this: Sema does reification based on the tag indices of `std.builtin.Type` already! So, no zig1.wasm update is necessary. This change is necessary to disallow name clashes between fields and decls on a type, which is a prerequisite of #9938.
2024-08-18test: Disable `vector reduce operation` on mips64.Alex Rønne Petersen
https://github.com/ziglang/zig/issues/21091
2024-08-12test: Partially disable `vector float operators` on mips.Alex Rønne Petersen
https://github.com/ziglang/zig/issues/21051
2024-07-28std.Target.Cpu.Arch: Remove the `aarch64_32` tag.Alex Rønne Petersen
This is a misfeature that we inherited from LLVM: * https://reviews.llvm.org/D61259 * https://reviews.llvm.org/D61939 (`aarch64_32` and `arm64_32` are equivalent.) I truly have no idea why this triple passed review in LLVM. It is, to date, the *only* tag in the architecture component that is not, in fact, an architecture. In reality, it is just an ILP32 ABI for AArch64 (*not* AArch32). The triples that use `aarch64_32` look like `aarch64_32-apple-watchos`. Yes, that triple is exactly what you think; it has no ABI component. They really, seriously did this. Since only Apple could come up with silliness like this, it should come as no surprise that no one else uses `aarch64_32`. Later on, a GNU ILP32 ABI for AArch64 was developed, and support was added to LLVM: * https://reviews.llvm.org/D94143 * https://reviews.llvm.org/D104931 Here, sanity seems to have prevailed, and a triple using this ABI looks like `aarch64-linux-gnu_ilp32` as you would expect. As can be seen from the diffs in this commit, there was plenty of confusion throughout the Zig codebase about what exactly `aarch64_32` was. So let's just remove it. In its place, we'll use `aarch64-watchos-ilp32`, `aarch64-linux-gnuilp32`, and so on. We'll then translate these appropriately when talking to LLVM. Hence, this commit adds the `ilp32` ABI tag (we already have `gnuilp32`).
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-28 14:42:12 +0000