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path: root/test/behavior/cast.zig
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2025-10-02Coff2: create a new linker from scratchJacob Young
2025-09-10x86_64: delete usages of avx2 `vpack?s??`Jacob Young
This instruction actually has fairly useless semantics, and even the cases that were semantically correct could save 1 cycle of latency by using a different sequnce involving the avx version instead. Closes #25174
2025-09-07wasm backend: disable failing behavior testsAndrew Kelley
2025-08-13llvm: unions which are equivalent to enums are not by-refmlugg
The LLVM backend lowers unions where all fields are zero-bit as equivalent to their backing enum, and expects them to have the same by-ref-ness in at least one place in the backend, probably more. Resolves: #23577
2025-08-09test: skip tests that were not meant to pass for spirvAli Cheraghi
2025-07-25aarch64: more progressJacob Young
- factor out `loadReg` - support all general system control registers in inline asm - fix asserts after iterating field offsets - fix typo in `slice_elem_val` - fix translation of argument locations
2025-07-22aarch64: add new from scratch self-hosted backendJacob Young
2025-06-28riscv64: skip failing testsBingwu Zhang
2025-06-19x86_64: increase passing test coverage on windowsJacob Young
Now that codegen has no references to linker state this is much easier. Closes #24153
2025-06-17Merge pull request #24188 from mlugg/intfromfloat-safetyMatthew Lugg
Absorb std.math.big.rational logic into std.math.big.int; fix `@intFromFloat` safety check
2025-06-16rename spirv backend nameAli Cheraghi
`stage2_spirv64` -> `stage2_spirv`
2025-06-15compiler: fix `@intFromFloat` safety checkmlugg
This safety check was completely broken; it triggered unchecked illegal behavior *in order to implement the safety check*. You definitely can't do that! Instead, we must explicitly check the boundaries. This is a tiny bit fiddly, because we need to make sure we do floating-point rounding in the correct direction, and also handle the fact that the operation truncates so the boundary works differently for min vs max. Instead of implementing this safety check in Sema, there are now dedicated AIR instructions for safety-checked intfromfloat (two instructions; which one is used depends on the float mode). Currently, no backend directly implements them; instead, a `Legalize.Feature` is added which expands the safety check, and this feature is enabled for all backends we currently test, including the LLVM backend. The `u0` case is still handled in Sema, because Sema needs to check for that anyway due to the comptime-known result. The old safety check here was also completely broken and has therefore been rewritten. In that case, we just check for 'abs(input) < 1.0'. I've added a bunch of test coverage for the boundary cases of `@intFromFloat`, both for successes (in `test/behavior/cast.zig`) and failures (in `test/cases/safety/`). Resolves: #24161
2025-06-03Legalize: handle packed semanticsJacob Young
Closes #22915
2025-05-31Legalize: implement scalarization of binary operationsJacob Young
2025-05-28x86_64: implement integer `@reduce(.Add)`Jacob Young
2025-04-11Merge pull request #23061 from pavelverigo/stage2-wasm-miscAndrew Kelley
stage2-wasm: multiple fixes
2025-04-11test: Disable a bunch of vector behavior tests for hexagon.Alex Rønne Petersen
Most of the failures are: * https://github.com/llvm/llvm-project/issues/118879 * https://github.com/llvm/llvm-project/issues/134659 But some are also miscompilations leading to wrong results. I'm not going to investigate the latter further until all the backend crashes have been resolved.
2025-03-24stage2-wasm: enable already working testsPavel Verigo
2025-02-24test: skip failing tests with spirv-vulkanAli Cheraghi
2025-02-12x86_64: implement conversions between float and int vectorsJacob Young
2025-02-05Sema: fix PTR of slice of sentinel-terminated arraymlugg
Resolves: #20901
2025-01-16x86_64: pass more behavior testsJacob Young
2025-01-16x86_64: implement switch jump tablesJacob Young
2025-01-16all: update to `std.builtin.Type.Pointer.Size` field renamesmlugg
This was done by regex substitution with `sed`. I then manually went over the entire diff and fixed any incorrect changes. This diff also changes a lot of `callconv(.C)` to `callconv(.c)`, since my regex happened to also trigger here. I opted to leave these changes in, since they *are* a correct migration, even if they're not the one I was trying to do!
2024-11-20Fix peer type resolution with allowzero pointersxdBronch
2024-11-03std.Target: Replace isARM() with isArmOrThumb() and rename it to isArm().Alex Rønne Petersen
The old isARM() function was a portability trap. With the name it had, it seemed like the obviously correct function to use, but it didn't include Thumb. In the vast majority of cases where someone wants to ask "is the target Arm?", Thumb *should* be included. There are exactly 3 cases in the codebase where we do actually need to exclude Thumb, although one of those is in Aro and mirrors a check in Clang that is itself likely a bug. These rare cases can just add an extra isThumb() check.
2024-10-31compiler: remove anonymous struct types, unify all tuplesmlugg
This commit reworks how anonymous struct literals and tuples work. Previously, an untyped anonymous struct literal (e.g. `const x = .{ .a = 123 }`) was given an "anonymous struct type", which is a special kind of struct which coerces using structural equivalence. This mechanism was a holdover from before we used RLS / result types as the primary mechanism of type inference. This commit changes the language so that the type assigned here is a "normal" struct type. It uses a form of equivalence based on the AST node and the type's structure, much like a reified (`@Type`) type. Additionally, tuples have been simplified. The distinction between "simple" and "complex" tuple types is eliminated. All tuples, even those explicitly declared using `struct { ... }` syntax, use structural equivalence, and do not undergo staged type resolution. Tuples are very restricted: they cannot have non-`auto` layouts, cannot have aligned fields, and cannot have default values with the exception of `comptime` fields. Tuples currently do not have optimized layout, but this can be changed in the future. This change simplifies the language, and fixes some problematic coercions through pointers which led to unintuitive behavior. Resolves: #16865
2024-10-22tests: re-enable tests that now pass on aarch64-windowskcbanner
2024-09-12riscv: implement `optional_payload_ptr_set`David Rubin
2024-08-28std: update `std.builtin.Type` fields to follow naming conventionsmlugg
The compiler actually doesn't need any functional changes for this: Sema does reification based on the tag indices of `std.builtin.Type` already! So, no zig1.wasm update is necessary. This change is necessary to disallow name clashes between fields and decls on a type, which is a prerequisite of #9938.
2024-07-26riscv: update tests and fix reuse bugDavid Rubin
2024-07-26riscv: airAsm rewriteDavid Rubin
with this rewrite we can call functions inside of inline assembly, enabling us to use the default start.zig logic all that's left is to implement lr/sc loops for atomically manipulating 1 and 2 byte values, after which we can use the segfault handler logic.
2024-07-26riscv: enable passing testsDavid Rubin
2024-07-26riscv: implement `@floatFromInt`David Rubin
2024-07-26riscv: remove redundant assert in `genBinOp`David Rubin
2024-07-26riscv: implement more operatorsDavid Rubin
we can run `std.debug.print` now, with both run-time strings and integers!
2024-06-13test: disable-enable riscv testsDavid Rubin
2024-06-13riscv: disable failing testDavid Rubin
2024-06-13riscv: rewrite "binOp"David Rubin
Reorganize how the binOp and genBinOp functions work. I've spent quite a while here reading exactly through the spec and so many tests are enabled because of several critical issues the old design had. There are some regressions that will take a long time to figure out individually so I will ignore them for now, and pray they get fixed by themselves. When we're closer to 100% passing is when I will start diving into them one-by-one.
2024-06-13riscv: implement optional logicDavid Rubin
2024-06-13riscv: integer + float `@abs`David Rubin
2024-06-13riscv: implement more arithmetic instructionsDavid Rubin
2024-06-13riscv: zero registers when using register-wide operationsDavid Rubin
what was happening is that instructions like `lb` were only affecting the lower bytes of the register and leaving the top dirty. this would lead to situtations were `cmp_eq` for example was using `xor`, which was failing because of the left-over stuff in the top of the register. with this commit, we now zero out or truncate depending on the context, to ensure instructions like xor will provide proper results.
2024-06-13riscv: fix register clobber in certain edge casesDavid Rubin
2024-06-13riscv: `std.fmt.format` runningDavid Rubin
- implements `airSlice`, `airBitAnd`, `airBitOr`, `airShr`. - got a basic design going for the `airErrorName` but for some reason it simply returns empty bytes. will investigate further. - only generating `.got.zig` entries when not compiling an object or shared library - reduced the total amount of ops a mnemonic can have to 3, simplifying the logic
2024-06-13riscv: arbitrary sized arraysDavid Rubin
2024-06-13riscv: switch progress + by-ref return progressDavid Rubin
2024-06-10spirv: disable tests that fail on poclRobin Voetter
Besides the Intel OpenCL CPU runtime, we can now run the behavior tests using the Portable Computing Language. This implementation is open-source, so it will be easier for us to patch in updated versions of spirv-llvm-translator that have bug fixes etc.
2024-05-11riscv: finally fix bug + `airAggregateInit`David Rubin
i just hadn't realized that I placed the `riscv_start` branch in the non-simplified starts
2024-05-11riscv: by-value structs + `@min`David Rubin