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2025-11-04Fixing SPIR-V header generator magic + Adding Zig compiler version to SPIR-V ↵kbz_8
OpSource (#25435) * fixing Zig generator magic in SPIR-V header; adding zig compiler version to SPIR-V OpSource * Update src/codegen/spirv/Module.zig Co-authored-by: rpkak <67059904+rpkak@users.noreply.github.com> --------- Co-authored-by: rpkak <67059904+rpkak@users.noreply.github.com>
2025-10-28spirv: fix airWorkGroupSize to use workgroup_size builtinCooksey99
2025-10-27feat: init x86_16 arch via CBEGasInfinity
2025-08-29std.Io: delete GenericReaderAndrew Kelley
and delete deprecated alias std.io
2025-08-18spirv: do not decorate nav alignmentAli Cheraghi
they seem to be always `null` even when accessed through extern key so we have no way to tell whether they have natural alignment or not to decorate. And the reason we don't always decorate them is because some environments might be too dumb and crash for this.
2025-08-12Sema: replace all remaining aggregate interns related to `@typeInfo`Justus Klausecker
2025-08-11std.ArrayList: make unmanaged the defaultAndrew Kelley
2025-08-09spirv: remove prune_unused ISelAli Cheraghi
2025-08-04spirv: define and use extended instruction set opcodesAli Cheraghi
2025-08-03Watch: do not fail when file is removedAli Cheraghi
before this we would get a crash
2025-08-02spirv: refactorAli Cheraghi
2025-07-14spirv: snake-case the specAli Cheraghi
2025-07-07std.fmt: fully remove format string from format methodsAndrew Kelley
Introduces `std.fmt.alt` which is a helper for calling alternate format methods besides one named "format".
2025-07-07compiler: update a bunch of format stringsAndrew Kelley
2025-06-23remove `spirv` cpu archAli Cheraghi
2025-06-19Target: pass and use locals by pointer instead of by valueJacob Young
This struct is larger than 256 bytes and code that copies it consistently shows up in profiles of the compiler.
2025-06-12compiler: slightly untangle LLVM from the linkersmlugg
The main goal of this commit is to make it easier to decouple codegen from the linkers by being able to do LLVM codegen without going through the `link.File`; however, this ended up being a nice refactor anyway. Previously, every linker stored an optional `llvm.Object`, which was populated when using LLVM for the ZCU *and* linking an output binary; and `Zcu` also stored an optional `llvm.Object`, which was used only when we needed LLVM for the ZCU (e.g. for `-femit-llvm-bc`) but were not emitting a binary. This situation was incredibly silly. It meant there were N+1 places the LLVM object might be instead of just 1, and it meant that every linker had to start a bunch of methods by checking for an LLVM object, and just dispatching to the corresponding method on *it* instead if it was not `null`. Instead, we now always store the LLVM object on the `Zcu` -- which makes sense, because it corresponds to the object emitted by, well, the Zig Compilation Unit! The linkers now mostly don't make reference to LLVM. `Compilation` makes sure to emit the LLVM object if necessary before calling `flush`, so it is ready for the linker. Also, all of the `link.File` methods which act on the ZCU -- like `updateNav` -- now check for the LLVM object in `link.zig` instead of in every single individual linker implementation. Notably, the change to LLVM emit improves this rather ludicrous call chain in the `-fllvm -flld` case: * Compilation.flush * link.File.flush * link.Elf.flush * link.Elf.linkWithLLD * link.Elf.flushModule * link.emitLlvmObject * Compilation.emitLlvmObject * llvm.Object.emit Replacing it with this one: * Compilation.flush * llvm.Object.emit ...although we do currently still end up in `link.Elf.linkWithLLD` to do the actual linking. The logic for invoking LLD should probably also be unified at least somewhat; I haven't done that in this commit.
2025-06-05std.Target: Introduce Cpu convenience functions for feature tests.Alex Rønne Petersen
Before: * std.Target.arm.featureSetHas(target.cpu.features, .has_v7) * std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov }) * std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory }) After: * target.cpu.has(.arm, .has_v7) * target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov }) * target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-05-21spirv: error when execution mode is set more than onceAli Cheraghi
2025-05-21spirv: super basic composite int supportAli Cheraghi
2025-05-21spirv: write error value in an storage bufferAli Cheraghi
2025-05-21spirv: unroll all vector operationsAli Cheraghi
2025-03-19spirv: Assemble OpTypeRuntimeArray.dan
2025-03-18spirv: require int8/int16 capabilitiesAli Cheraghi
2025-03-18spirv: packed struct init + field val accessAli Cheraghi
2025-03-17spirv/target: arbitrary_precision_integers feature supportAli Cheraghi
2025-03-17spirv: lower more types in assemblerAli Cheraghi
2025-03-17target: split `addresses` and `physical_storage_buffer` featuresAli Cheraghi
2025-03-05Remove uses of deprecated callconv aliasesLinus Groh
2025-02-24spirv: get rid of function_types cacheRobin Voetter
This deep hash map doesn't work
2025-02-24spirv: replace some unreachables with compile errorsAli Cheraghi
2025-02-18spirv: extend supported `c` constraint valuesAli Cheraghi
2025-02-18spirv: ziggify and remove unknown spirv featuresAli Cheraghi
`OpCapability` and `OpExtension` now can also be emitted from inline assembly
2025-02-18spirv: respect cpu featuresAli Cheraghi
2025-02-18spirv: cache more types & merge constructX functionsAli Cheraghi
2025-01-16all: update to `std.builtin.Type.Pointer.Size` field renamesmlugg
This was done by regex substitution with `sed`. I then manually went over the entire diff and fixed any incorrect changes. This diff also changes a lot of `callconv(.C)` to `callconv(.c)`, since my regex happened to also trigger here. I opted to leave these changes in, since they *are* a correct migration, even if they're not the one I was trying to do!
2024-11-08spirv: assembler hacky constant placeholdersRobin Voetter
2024-11-08spirv: track global OpVariables properly in assemblerRobin Voetter
Also cleans up the assembler a bit in general.
2024-11-01spirv: Uniform/PushConstant variablesAli Cheraghi
- Rename GPU address spaces to match with SPIR-V spec. - Emit `Block` Decoration for Uniform/PushConstant variables. - Don't emit `OpTypeForwardPointer` for non-opencl targets. (there's still a false-positive about recursive structs) Signed-off-by: Ali Cheraghi <alichraghi@proton.me>
2024-09-12Replace deprecated default initializations with decl literalsLinus Groh
2024-08-28std: update `std.builtin.Type` fields to follow naming conventionsmlugg
The compiler actually doesn't need any functional changes for this: Sema does reification based on the tag indices of `std.builtin.Type` already! So, no zig1.wasm update is necessary. This change is necessary to disallow name clashes between fields and decls on a type, which is a prerequisite of #9938.
2024-06-16spirv: add support for workItemId, workGroupId, workGroupSizeRobin Voetter
2024-06-10spirv: new vectorization helperRobin Voetter
The old vectorization helper (WipElementWise) was clunky and a bit annoying to use, and it wasn't really flexible enough. This introduces a new vectorization helper, which uses Temporary and Operation types to deduce a Vectorization to perform the operation in a reasonably efficient manner. It removes the outer loop required by WipElementWise so that implementations of AIR instructions are cleaner. This helps with sanity when we start to introduce support for composite integers. airShift, convertToDirect, convertToIndirect, and normalize are initially implemented using this new method.
2024-04-06spirv: yeet cacheRobin Voetter
2024-04-06spirv: remove cache usage from assemblerRobin Voetter
2024-04-06spirv: remove cache usage for typesRobin Voetter
2024-04-06spirv: remove cache usage for constantsRobin Voetter
2024-04-06spirv: id range helperRobin Voetter
This allows us to more sanely allocate a continuous range of result-ids, and avoids a bunch of nasty casting code in a few places. Its currently not used very often, but will be useful in the future.
2024-04-06spirv: implement `@mulWithOverflow`Ali Chraghi
2024-04-06spirv: OpExtInstImport in assemblerAli Chraghi