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path: root/src/codegen/spirv/Module.zig
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2025-11-04Fixing SPIR-V header generator magic + Adding Zig compiler version to SPIR-V ↵kbz_8
OpSource (#25435) * fixing Zig generator magic in SPIR-V header; adding zig compiler version to SPIR-V OpSource * Update src/codegen/spirv/Module.zig Co-authored-by: rpkak <67059904+rpkak@users.noreply.github.com> --------- Co-authored-by: rpkak <67059904+rpkak@users.noreply.github.com>
2025-10-27feat: init x86_16 arch via CBEGasInfinity
2025-08-11std.ArrayList: make unmanaged the defaultAndrew Kelley
2025-08-09spirv: remove prune_unused ISelAli Cheraghi
2025-08-04spirv: define and use extended instruction set opcodesAli Cheraghi
2025-08-03Watch: do not fail when file is removedAli Cheraghi
before this we would get a crash
2025-08-02spirv: refactorAli Cheraghi
2025-07-14spirv: snake-case the specAli Cheraghi
2025-06-23remove `spirv` cpu archAli Cheraghi
2025-06-19Target: pass and use locals by pointer instead of by valueJacob Young
This struct is larger than 256 bytes and code that copies it consistently shows up in profiles of the compiler.
2025-06-05std.Target: Introduce Cpu convenience functions for feature tests.Alex Rønne Petersen
Before: * std.Target.arm.featureSetHas(target.cpu.features, .has_v7) * std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov }) * std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory }) After: * target.cpu.has(.arm, .has_v7) * target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov }) * target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-05-21spirv: error when execution mode is set more than onceAli Cheraghi
2025-05-21spirv: super basic composite int supportAli Cheraghi
2025-05-21spirv: write error value in an storage bufferAli Cheraghi
2025-05-21spirv: unroll all vector operationsAli Cheraghi
2025-03-18spirv: require int8/int16 capabilitiesAli Cheraghi
2025-03-18spirv: packed struct init + field val accessAli Cheraghi
2025-03-17spirv/target: arbitrary_precision_integers feature supportAli Cheraghi
2025-03-17target: split `addresses` and `physical_storage_buffer` featuresAli Cheraghi
2025-02-24spirv: get rid of function_types cacheRobin Voetter
This deep hash map doesn't work
2025-02-24spirv: replace some unreachables with compile errorsAli Cheraghi
2025-02-18spirv: ziggify and remove unknown spirv featuresAli Cheraghi
`OpCapability` and `OpExtension` now can also be emitted from inline assembly
2025-02-18spirv: respect cpu featuresAli Cheraghi
2025-02-18spirv: cache more types & merge constructX functionsAli Cheraghi
2024-11-01spirv: Uniform/PushConstant variablesAli Cheraghi
- Rename GPU address spaces to match with SPIR-V spec. - Emit `Block` Decoration for Uniform/PushConstant variables. - Don't emit `OpTypeForwardPointer` for non-opencl targets. (there's still a false-positive about recursive structs) Signed-off-by: Ali Cheraghi <alichraghi@proton.me>
2024-09-12Replace deprecated default initializations with decl literalsLinus Groh
2024-06-16spirv: add support for workItemId, workGroupId, workGroupSizeRobin Voetter
2024-06-10spirv: new vectorization helperRobin Voetter
The old vectorization helper (WipElementWise) was clunky and a bit annoying to use, and it wasn't really flexible enough. This introduces a new vectorization helper, which uses Temporary and Operation types to deduce a Vectorization to perform the operation in a reasonably efficient manner. It removes the outer loop required by WipElementWise so that implementations of AIR instructions are cleaner. This helps with sanity when we start to introduce support for composite integers. airShift, convertToDirect, convertToIndirect, and normalize are initially implemented using this new method.
2024-04-06spirv: yeet cacheRobin Voetter
2024-04-06spirv: remove cache usage for typesRobin Voetter
2024-04-06spirv: remove cache usage for constantsRobin Voetter
2024-04-06spirv: id range helperRobin Voetter
This allows us to more sanely allocate a continuous range of result-ids, and avoids a bunch of nasty casting code in a few places. Its currently not used very often, but will be useful in the future.
2024-04-06spirv: OpExtInstImport in assemblerAli Chraghi
2024-04-06spirv: implement `@divFloor`, `@floor` and `@mod`Ali Chraghi
2024-03-18spirv: make generic globals invocation-localRobin Voetter
2024-03-18spirv: make IdResult an enumRobin Voetter
2024-02-15spirv: add capability to compile with x86_64 backendAli Chraghi
2024-02-15spirv: use extended instructions whenever possibleAli Chraghi
2024-02-09spirv: make rusticl the primary testing implementationAli Chraghi
2024-02-05spirv: emit vectors whenever we canAli Chraghi
2024-02-05spirv: basic shader supportAli Chraghi
2023-11-24spirv: fix memory leak in SpvModuleRobin Voetter
2023-10-23Revert "Revert "Merge pull request #17657 from Snektron/spirv-recursive-ptrs""Robin Voetter
This reverts commit 9f0359d78f9facc38418e32b0e8c1bf6f99f0d26 in an attempt to make the tests pass again. The CI failure from that merge should be unrelated to this commit.
2023-10-22Revert "Merge pull request #17657 from Snektron/spirv-recursive-ptrs"Andrew Kelley
This reverts commit b822e841cda0adabe3fec260ff51c18508f7ee32, reversing changes made to 0c99ba1eab63865592bb084feb271cd4e4b0357e. This caused a CI failure when it landed in master branch.
2023-10-21spirv: self-referential pointers via new fwd_ptr_typeRobin Voetter
Its a little ugly but it works.
2023-10-15spirv: work around OpSource parsing issue in llvm-spirvRobin Voetter
The Khronos SPIRV-LLVM translator does not parse OpSource correctly. This was causing tests to fail and other mysterious issues. These are resolved by only generating a single OpSource instruction for now, which does not have the source file locations also. See https://github.com/KhronosGroup/SPIRV-LLVM-Translator/issues/2188
2023-10-15spirv: use CacheString for source_file_names instead of []const u8Robin Voetter
2023-10-15spirv: get rid of SpvModule arenaRobin Voetter
2023-09-23spirv: air dbg_var_val and dbg_var_ptrRobin Voetter
2023-09-23spirv: generate module initializerRobin Voetter
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-28 14:48:54 +0000