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2021-07-20stage2: codegen.zig updated to new AIR memory layoutAndrew Kelley
2021-07-20codegen: add FnResult type which is a Result that removes externally_managedJacob G-W
2021-07-20stage2: compile error fixes for AIR memory layout branchAndrew Kelley
Now the branch is compiling again, provided that one uses `-Dskip-non-native`, but many code paths are disabled. The code paths can now be re-enabled one at a time and updated to conform to the new AIR memory layout.
2021-07-20stage2: Air and Liveness are passed ephemerallyAndrew Kelley
to the link infrastructure, instead of being stored with Module.Fn. This moves towards a strategy to make more efficient use of memory by not storing Air or Liveness data in the Fn struct, but computing it on demand, immediately sending it to the backend, and then immediately freeing it. Backends which want to defer codegen until flush() such as SPIR-V must move the Air/Liveness data upon `updateFunc` being called and keep track of that data in the backend implementation itself.
2021-07-20stage2: first pass over Module.zig for AIR memory layoutAndrew Kelley
2021-07-20stage2: first pass over codegen.zig for AIR memory layoutAndrew Kelley
2021-07-20stage2: update liveness analysis to new AIR memory layoutAndrew Kelley
It's pretty compact, with each AIR instruction only taking up 4 bits, plus a sparse table for special instructions such as conditional branch, switch branch, and function calls with more than 2 arguments.
2021-07-20stage2: rework AIR memory layoutAndrew Kelley
This commit changes the AIR file and the documentation of the memory layout. The actual work of modifying the surrounding code (in Sema and codegen) is not yet done.
2021-07-20macho: add stub relocs when adding extern fnJakub Konka
in self-hosted.
2021-07-18zld: migrate symbol mgmt to incremental backendJakub Konka
2021-07-11stage2 plan9: add aarch64 supportJacob G-W
2021-07-08plan9 cleanupsAndrew Kelley
* rename files to adhere to conventions * remove unnecessary function / optionality * fix merge conflict * better panic message * remove unnecessary TODO comment * proper namespacing of declarations * clean up documentation comments * no copyright header needed for a brand new zig file that is not copied from anywhere
2021-07-08plan9 linker: remove unused stuffJacob G-W
2021-07-08stage2: include enough inline asm support for more plan9 syscallsJacob G-W
Also make the exit more correct by exiting 0 rather than random stuff on the stack.
2021-07-08plan9 linker: use a global offset tableJacob G-W
this simplifies stuff and makes us not have to use relocations
2021-07-08plan9 linker: do relocationsJacob G-W
2021-07-08plan9 linker: make runnable binariesJacob G-W
We can now run binaries! (they segfault, but still run!)
2021-07-07stage2: fix if expressions on error unionsAndrew Kelley
AstGen had the then-else logic backwards for if expressions on error unions. This commit fixes it. Turns out AstGen only really needs `is_non_null` and `is_non_err`, and does not need the `is_null` or `is_err` variants. So I removed the `is_null{,_ptr}` and `is_err{,_ptr}` ZIR instructions (-4) and added `is_non_err`, `is_non_err_ptr` ZIR instructions (+2) for a total of (-2) ZIR instructions, giving us a tiny bit more headroom within the 256 tag limit. This required swapping the order of then/else blocks in a handful of cases, but ultimately means the ZIR will be in the same as source order, which is convenient when debugging. AIR code on the other hand, gains the `is_non_err` and `is_non_err_ptr` instructions. Sema: fix logic in zirErrUnionCode and zirErrUnionCodePtr returning the wrong result type.
2021-07-07stage2: get tests passingAndrew Kelley
* implement enough of ret_err_value to pass wasm tests * only do the proper `@panic` implementation for the backends which support it, which is currently only the C backend. The other backends will see `@breakpoint(); unreachable;` same as before. - I plan to do AIR memory layout reworking as a prerequisite to fixing other backends, because that will help me put all the constants up front, which will allow the codegen to lower to memory without jumps. * `@panic` is implemented using anon decls for the message. Makes it easier on the backends. Might want to look into re-using decls for this in the future. * implement DWARF .debug_info for pointer-like optionals.
2021-06-21cleanups related to unused paramsAndrew Kelley
2021-06-21fix code broken from previous commitJacob G-W
2021-06-21std, src, doc, test: remove unused variablesJacob G-W
2021-06-21stage2 Sema: implement @intToPtr (#9144)g-w1
Co-authored-by: Veikka Tuominen <git@vexu.eu>
2021-06-21stage2: simplify codegen for errorToInt and intToErrorJacob G-W
We can just use bitcast instead of error_to_int, int_to_error since errorToInt and intToError do not actually do anything, just change types. This allows us to remove 2 air ops that were the exact same as bitcast
2021-06-09stage2 codegen: Remove hacks for discontinued SPU II backendjoachimschmidt557
2021-06-03Breaking hash map changes for 0.8.0Martin Wickham
- hash/eql functions moved into a Context object - *Context functions pass an explicit context - *Adapted functions pass specialized keys and contexts - new getPtr() function returns a pointer to value - remove functions renamed to fetchRemove - new remove functions return bool - removeAssertDiscard deleted, use assert(remove(...)) instead - Keys and values are stored in separate arrays - Entry is now {*K, *V}, the new KV is {K, V} - BufSet/BufMap functions renamed to match other set/map types - fixed iterating-while-modifying bug in src/link/C.zig
2021-05-22stage2: Move BlockData out of ir.Inst.Blockjoachimschmidt557
2021-05-22stage2: rename ir.zig to air.zigAndrew Kelley
We've settled on the nomenclature for the artifacts the compiler pipeline produces: 1. Tokens 2. AST (Abstract Syntax Tree) 3. ZIR (Zig Intermediate Representation) 4. AIR (Analyzed Intermediate Representation) 5. Machine Code Renaming `ir` identifiers to `air` will come with the inevitable air-memory-layout branch that I plan to start after the 0.8.0 release.
2021-05-17Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
Conflicts: * src/codegen/spirv.zig * src/link/SpirV.zig We're going to want to improve the stage2 test harness to print the source file name when a compile error occurs otherwise std lib contributors are going to see some confusing CI failures when they cause stage2 AstGen compile errors.
2021-05-17stage2 ARM: correct spilling in genArmMul as welljoachimschmidt557
2021-05-15Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
Conflicts: * build.zig * src/Compilation.zig * src/codegen/spirv/spec.zig * src/link/SpirV.zig * test/stage2/darwin.zig - this one might be problematic; start.zig looks for `main` in the root source file, not `_main`. Not sure why there is an underscore there in master branch.
2021-05-15stage2: remove SPU Mark II backendAndrew Kelley
As it stands, the backend is incomplete, and there is no active contributor, making it dead weight. However, anyone is free to resurrect this backend at any time.
2021-05-15codegen: implement const value rendering for ints <= 64 bitsAndrew Kelley
2021-05-14stage2 register manager: clean up API and add more unit testsjoachimschmidt557
2021-05-12Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
Conflicts: * lib/std/os/linux.zig * lib/std/os/windows/bits.zig * src/Module.zig * src/Sema.zig * test/stage2/test.zig Mainly I wanted Jakub's new macOS code for respecting stack size, since we now depend on it for debug builds able to pass one of the test cases for recursive comptime function calls with `@setEvalBranchQuota`. The conflicts were all trivial.
2021-05-09stage2 ARM: Overhaul of genArmBinOpjoachimschmidt557
2021-05-09Merge pull request #8474 from gracefuu/grace/encode-instructionAndrew Kelley
stage2 x86_64: encoding helpers, fix bugs
2021-05-01stage2: dbg_stmt ZIR instructions have line/colAndrew Kelley
instead of node indexes. * AstGen: dbg_stmt instructions now have line and column indexes, relative to the parent declaration. This allows codegen to emit debug info without having the source bytes, tokens, or AST nodes loaded in memory. * ZIR: each decl has the absolute line number. This allows computing line numbers from offsets without consulting source code bytes. Memory management: creating a function definition does not prematurely set the Decl arena. Instead the function is allocated with the general purpose allocator. Codegen no longer looks at source code bytes for any reason. They can remain unloaded from disk.
2021-04-28stage2: implement semantic analysis for functions and global varsAndrew Kelley
* AstGen: add missing `break_inline` for comptime blocks. * Module: call getTree() in byteOffset(). This generates the AST when using cached ZIR and compile errors need to be reported. * Scope.File: distinguish between successful ZIR generation and AIR generation (when Decls in scope have been scanned). - `semaFile` correctly avoids doing work twice. * Implement first pass at `lookupInNamespace`. It has various TODOs left, such as `usingnamespace`, and setting up Decl dependencies.
2021-04-28stage2: semaDecl properly analyzes the decl blockAndrew Kelley
Also flattened out Decl TypedValue fields into ty, val, has_tv and add relevant fields to Decl for alignment and link section.
2021-04-28Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
In particular I wanted to take advantage of the new hex float parsing code.
2021-04-25stage2 register manager: Use an array instead of a hashmap for trackingjoachimschmidt557
allocated registers
2021-04-24Merge remote-tracking branch 'origin/master' into stage2-whole-file-astgenAndrew Kelley
In particular I wanted the change that makes `suspend;` illegal in the parser.
2021-04-20stage2: fix compile error in codegenjacob gw
2021-04-19AstGen: implement inline asm outputAndrew Kelley
2021-04-17stage2 codegen: Fix silent bug in reuseOperandjoachimschmidt557
2021-04-16stage2 x86_64: fix incorrect comment in genX8664BinMathgracefu
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16stage2 x86_64: force 64 bit mode when loading address of GOTgracefu
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16stage2 x86_64: fix codegen ensureCapacity bug for function callsgracefu
Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>
2021-04-16stage2 x86_64: bugfix abi_size == 64 should be abi_size == 8gracefu