| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2022-09-13 | stage2: remove pointless discards from source code | Andrew Kelley | |
| Good riddance! | |||
| 2022-09-09 | stage2 ARM: implement basic array_elem_val | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: implement ptr_elem_val | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: support larger function stacks | joachimschmidt557 | |
| This is done by introducing a new Mir pseudo-instruction | |||
| 2022-09-09 | stage2 ARM: implement struct_field_val for registers | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: fix multiple uses of reuseOperand | joachimschmidt557 | |
| - add missing checks whether destination fits into the operand - remove reuseOperand invocations from airIsNullPtr and similar functions as we need to load the operands into temporary locations | |||
| 2022-09-09 | stage2 ARM: amend implementation of various AIR instructions | joachimschmidt557 | |
| - unwrap_errunion_err for registers - unwrap_errunion_payload for registers - ptr_slice_len_ptr for all MCValues - ptr_slice_ptr_ptr for all MCValues | |||
| 2022-09-09 | stage2 ARM: implement field_parent_ptr | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: remove remaining uses of binOp{Register,Immediate} | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: extract remaining operations out of binOp | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: extract mul, div, and mod out of binOp | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: extract add+sub from binOp | joachimschmidt557 | |
| This commit also lays the groundwork for further extractions from binOp. | |||
| 2022-09-09 | stage2 ARM: move cmp to new allocReg mechanism; remove from binOp | joachimschmidt557 | |
| 2022-09-09 | stage2 ARM: introduce allocRegs | joachimschmidt557 | |
| This new register allocation mechanism which is designed to be more generic and flexible will replace binOp. | |||
| 2022-09-09 | stage2 ARM: improve Mir representation of mov and cmp | joachimschmidt557 | |
| 2022-08-30 | coff: cleanup relocations; remove COFF support from other backends | Jakub Konka | |
| Given that COFF will want to support PIC from ground-up, there is no point in leaving outdated code for COFF in other backends such as arm or aarch64. Instead, when we are ready to look into those, we can start figuring out what to add and where. | |||
| 2022-08-30 | coff: reorganize the linker | Jakub Konka | |
| 2022-08-15 | Merge pull request #12416 from Vexu/stage2-safety | Veikka Tuominen | |
| Stage2 error set safety improvements | |||
| 2022-08-13 | stage2 ARM: add inline memcpy to genSetStack | joachimschmidt557 | |
| 2022-08-13 | stage2 ARM: Fix tracking of function return values | joachimschmidt557 | |
| 2022-08-13 | stage2 ARM: pass stack arguments in opposite order | joachimschmidt557 | |
| Earlier arguments have a smaller address (i.e. towards the bottom of the stack) | |||
| 2022-08-12 | stage2: generate a switch for `@errSetCast` safety | Veikka Tuominen | |
| 2022-08-05 | stage2: add runtime safety for invalid enum values | Veikka Tuominen | |
| 2022-08-01 | Removed param_names from Fn inside Module.zig | antlilja | |
| Removed the copy of param_names inside of Fn and changed to implementation of getParamName to fetch to parameter name from the ZIR. The signature of getParamName was also changed to take an additional *Module argument. | |||
| 2022-07-28 | stage2 ARM: more support for switch statements | joachimschmidt557 | |
| 2022-07-23 | stage2: implement `@setFloatMode` | Veikka Tuominen | |
| 2022-07-12 | stage2 ARM: add integer modulo with constant power-of-two rhs | joachimschmidt557 | |
| 2022-07-12 | stage2 ARM: implement division by constant int power-of-two divisors | joachimschmidt557 | |
| 2022-06-30 | stage2: lower float negation explicitly | Andrew Kelley | |
| Rather than lowering float negation as `0.0 - x`. * Add AIR instruction for float negation. * Add compiler-rt functions for f128, f80 negation closes #11853 | |||
| 2022-06-25 | stage2 ARM: implement basic intCast and error union wrapping | joachimschmidt557 | |
| 2022-06-11 | stage2: make `error{}` the same size as `anyerror` | Veikka Tuominen | |
| Having `error{}` be a zero bit type causes issues when it interracts with empty inferred error sets which are the same size as `anyerror`. | |||
| 2022-06-06 | Merge pull request #11783 from ziglang/stage2-try | Andrew Kelley | |
| introduce a "try" ZIR and AIR instruction | |||
| 2022-06-06 | dwarf: fix incorrect type reloc for unions | Jakub Konka | |
| Split type relocs into two kinds: local and global. Global relocs use a global type resolver and calculate offset to the existing definition of a type abbreviation. Local relocs use offset in the abbrev section of the containing atom plus addend to generate a local relocation. | |||
| 2022-06-06 | stage2 ARM: implement `try` AIR instruction | joachimschmidt557 | |
| 2022-06-05 | stage2: implement the new "try" ZIR/AIR instruction | Andrew Kelley | |
| Implements semantic analysis for the new try/try_inline ZIR instruction. Adds the new try/try_ptr AIR instructions and implements them for the LLVM backend. Fixes not calling rvalue() for tryExpr in AstGen. This is part of an effort to implement #11772. | |||
| 2022-06-04 | stage2 ARM: introduce support for basic switch expressions | joachimschmidt557 | |
| 2022-06-02 | stage2 ARM: rework cmp in preparation for switch | joachimschmidt557 | |
| 2022-05-27 | math: make `cast` return optional instead of an error | Ali Chraghi | |
| 2022-05-24 | stage2: fixes for error unions, optionals, errors | Andrew Kelley | |
| * `?E` where E is an error set with only one field now lowers the same as `bool`. * Fix implementation of errUnionErrOffset and errUnionPayloadOffset to properly compute the offset of each field. Also name them the same as the corresponding LLVM functions and have the same function signature, to avoid confusion. This fixes a bug where wasm was passing the error union type instead of the payload type. * Fix C backend handling of optionals with zero-bit payload types. * C backend: separate out airOptionalPayload and airOptionalPayloadPtr which reduces branching and cleans up control flow. * Make Type.isNoReturn return true for error sets with no fields. * Make `?error{}` have only one possible value (null). | |||
| 2022-05-24 | stage2 ARM: update to new union layout | joachimschmidt557 | |
| 2022-05-22 | stage2 ARM: fix recursive fibonacci | joachimschmidt557 | |
| Some handling of register_c_flag/register_v_flag was incorrect. | |||
| 2022-05-21 | stage2 ARM: Introduce MCValue.cpsr_flags | joachimschmidt557 | |
| MCValue.cpsr_flags replaces MCValue.compare_flags_{signed,unsigned}. This simplifies a lot of stuff and enables an MCValue to represent only the overflow bits in the CPU (previously, it was only possible to represent a register + the overflow bits). | |||
| 2022-05-19 | regalloc: make register class bitmask non-optional | Jakub Konka | |
| 2022-05-19 | regalloc: allow for optional selector mask when allocating | Jakub Konka | |
| 2022-05-17 | stage2: fix pointer arithmetic result type | Andrew Kelley | |
| This makes it so the result of doing pointer arithmetic creates a new pointer type that has adjusted alignment. | |||
| 2022-05-16 | stage2: disable error return tracing on unsupported targets | Veikka Tuominen | |
| 2022-05-16 | stage2: implement error return traces | Veikka Tuominen | |
| 2022-05-16 | arm: sub_with_overflow should always track V flag | Jakub Konka | |
| 2022-05-07 | arm: lock dest register in shl_overflow so that we do not spill it | Jakub Konka | |
| Nerf two tests - they will require further investigation, but arm now passes all tests with the safety PR. | |||
| 2022-05-07 | arm: fix CF flags spilling and implement genSetStack for reg with overflow flags | Jakub Konka | |
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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