aboutsummaryrefslogtreecommitdiff
path: root/src/arch/aarch64/CodeGen.zig
AgeCommit message (Collapse)Author
2022-09-13stage2: remove pointless discards from source codeAndrew Kelley
Good riddance!
2022-09-10aarch64: update codegen to using a global index rather than local indexJakub Konka
2022-08-30coff: cleanup relocations; remove COFF support from other backendsJakub Konka
Given that COFF will want to support PIC from ground-up, there is no point in leaving outdated code for COFF in other backends such as arm or aarch64. Instead, when we are ready to look into those, we can start figuring out what to add and where.
2022-08-30coff: reorganize the linkerJakub Konka
2022-08-12stage2: generate a switch for `@errSetCast` safetyVeikka Tuominen
2022-08-06Merge pull request #12337 from Vexu/stage2-safetyAndrew Kelley
Stage2: implement remaining runtime safety checks
2022-08-05stage2: add runtime safety for invalid enum valuesVeikka Tuominen
2022-08-05stage2 AArch64: improve correctness of register aliasesjoachimschmidt557
Also implements ptr_elem_ptr
2022-08-05stage2 AArch64: implement basic integer rem/modjoachimschmidt557
2022-08-05stage2 AArch64: implement basic integer divisionjoachimschmidt557
2022-08-05stage2 AArch64: memcpy support in store and more complete intcastjoachimschmidt557
2022-08-05stage2 AArch64: support returning values by referencejoachimschmidt557
also adds some more support for slices passed as stack arguments
2022-08-05stage2 AArch64: all arguments passed via stack from now onjoachimschmidt557
Only in the Undefined calling convention, not in other calling conventions
2022-08-05stage2 AArch64: introduce MCValue.stack_argument_offsetjoachimschmidt557
This new MCValue union member shares the same semantics as the MCValue type of the same name in the ARM backend.
2022-08-05stage2 AArch64: Fix struct_field_val for register_with_overflowjoachimschmidt557
Now mirrors the behavior of the native ARM backend
2022-07-23stage2: implement `@setFloatMode`Veikka Tuominen
2022-07-22macho: improve logs for dyld infoJakub Konka
2022-07-22macho: rework symbol handling to match zld/ELFJakub Konka
Now, each object file will store a mutable table of symbols that it defines. Upon symbol resolution between object files, the symbol will be updated with a globally allocated section ordinal and address in virtual memory. If the object defines a globally available symbol, its location only (comprising of the symbol index and object index) will be stored in the globals map for easy access when relocating, etc. This approach cleans up the symbol management significantly, and matches the status quo used in zld/ELF. Additionally, this makes scoping symbol stabs easier too as they are now naturally contained within each object file.
2022-06-30stage2: lower float negation explicitlyAndrew Kelley
Rather than lowering float negation as `0.0 - x`. * Add AIR instruction for float negation. * Add compiler-rt functions for f128, f80 negation closes #11853
2022-06-29aarch64: add airRetLoad for register mcvJakub Konka
2022-06-24link:clarification & enable MachO getGlobalSymbolLuuk de Gram
This adds clarification to the getGlobalSymbol doc comments, as well as renames the `addExternFn` function for MachO to `getGlobalSymbol`. This function will now be called from 'src/link.zig' as well. Finally, this also enables compiling zig's libc using LLVM even though the `fno-LLVM` flag is given.
2022-06-11stage2: make `error{}` the same size as `anyerror`Veikka Tuominen
Having `error{}` be a zero bit type causes issues when it interracts with empty inferred error sets which are the same size as `anyerror`.
2022-06-07stage2 AArch64: introduce MCValue.condition_flagsjoachimschmidt557
Follows 9747303d16dfca61316a292d1e05ac901191e3a3 for AArch64
2022-06-06stage2 AArch64: implement `try` AIR instructionjoachimschmidt557
2022-06-05stage2: implement the new "try" ZIR/AIR instructionAndrew Kelley
Implements semantic analysis for the new try/try_inline ZIR instruction. Adds the new try/try_ptr AIR instructions and implements them for the LLVM backend. Fixes not calling rvalue() for tryExpr in AstGen. This is part of an effort to implement #11772.
2022-05-27math: make `cast` return optional instead of an errorAli Chraghi
2022-05-27stage2 AArch64: complete genTypedValuejoachimschmidt557
2022-05-25aarch64: check lo/cc flag for unsigned sub_with_overflowJakub Konka
With this change, we are now correctly lowering `sub_with_overflow` for signed and unsigned integers of register-sized integers (32- or 64-bit precisely). We also match LLVM's behavior and so, the condition flags we now set are: * unsigned: - `add_with_overflow`: `hs`/`cs` (carry set) - `sub_with_overflow`: `lo`/`cc` (carry clear) * signed: - `add_with_overflow`/`sub_with_overflow`: `vs` (overflow)
2022-05-24stage2: fixes for error unions, optionals, errorsAndrew Kelley
* `?E` where E is an error set with only one field now lowers the same as `bool`. * Fix implementation of errUnionErrOffset and errUnionPayloadOffset to properly compute the offset of each field. Also name them the same as the corresponding LLVM functions and have the same function signature, to avoid confusion. This fixes a bug where wasm was passing the error union type instead of the payload type. * Fix C backend handling of optionals with zero-bit payload types. * C backend: separate out airOptionalPayload and airOptionalPayloadPtr which reduces branching and cleans up control flow. * Make Type.isNoReturn return true for error sets with no fields. * Make `?error{}` have only one possible value (null).
2022-05-24aarch64: update for new error union layoutJakub Konka
2022-05-19regalloc: make register class bitmask non-optionalJakub Konka
2022-05-19regalloc: allow for optional selector mask when allocatingJakub Konka
2022-05-17stage2: fix pointer arithmetic result typeAndrew Kelley
This makes it so the result of doing pointer arithmetic creates a new pointer type that has adjusted alignment.
2022-05-16stage2: disable error return tracing on unsupported targetsVeikka Tuominen
2022-05-16stage2: implement error return tracesVeikka Tuominen
2022-05-16aarch64: sub_with_overflow should always track V flagJakub Konka
2022-05-07regalloc: refactor locking multiple registers at onceJakub Konka
2022-05-07regalloc: rename freeze/unfreeze to lock/unlock registersJakub Konka
2022-05-07regalloc: ensure we only freeze/unfreeze at the outermost scopeJakub Konka
This prevents a nasty type of bugs where we accidentally unfreeze a register that was frozen purposely in the outer scope, risking accidental realloc of a taken register. Fix CF flags spilling on aarch64 backend.
2022-05-05aarch64: ensure we set correct operand size at codegen stageJakub Konka
2022-05-05aarch64: fix mul_with_overflow for ints <= 32bitsJakub Konka
2022-05-05aarch64: implement mul_with_overflow for ints in range 33-64 bits inclJakub Konka
2022-05-05aarch64: implement mul_with_overflow for <= 32bit intsJakub Konka
Add emitters for `smull`, `umull` and `tst (immediate)` instructions.
2022-05-05stage2 AArch64: implement shl_with_overflowjoachimschmidt557
2022-05-05stage2 AArch64: implement {add,sub}_with_overflow for all ints < 64joachimschmidt557
2022-05-05stage2 AArch64: initial implementation of {add,sub}_with_overflowjoachimschmidt557
2022-05-02stage2: improve inline asm stage1 compatibilityAndrew Kelley
* outputs can have names and be referenced with template replacements the same as inputs. * fix print_air.zig not decoding correctly. * LLVM backend: use a table for template names for simplicity
2022-04-27add new builtin function `@tan`Andrew Kelley
The reason for having `@tan` is that we already have `@sin` and `@cos` because some targets have machine code instructions for them, but in the case that the implementation needs to go into compiler-rt, sin, cos, and tan all share a common dependency which includes a table of data. To avoid duplicating this table of data, we promote tan to become a builtin alongside sin and cos. ZIR: The tag enum is at capacity so this commit moves `field_call_bind_named` to be `extended`. I measured this as one of the least used tags in the zig codebase. Fix libc math suffix for `f32` being wrong in both stage1 and stage2. stage1: add missing libc prefix for float functions.
2022-04-20stage2: use indexes for Decl objectsAndrew Kelley
Rather than allocating Decl objects with an Allocator, we instead allocate them with a SegmentedList. This provides four advantages: * Stable memory so that one thread can access a Decl object while another thread allocates additional Decl objects from this list. * It allows us to use u32 indexes to reference Decl objects rather than pointers, saving memory in Type, Value, and dependency sets. * Using integers to reference Decl objects rather than pointers makes serialization trivial. * It provides a unique integer to be used for anonymous symbol names, avoiding multi-threaded contention on an atomic counter.
2022-04-19stage2 AArch64: fix shl, shr, shl_exact, shr_exactjoachimschmidt557
Introduces the necessary truncation after shift