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path: root/src/Module.zig
AgeCommit message (Expand)Author
2021-03-23stage2: remove all async related codeIsaac Freund
2021-03-22fix calculation in ensureCapacityDimenus
2021-03-22astgen: implement array typesIsaac Freund
2021-03-21Sema: implement arithmeticAndrew Kelley
2021-03-22astgen: implement bool_and/bool_orIsaac Freund
2021-03-21zir: add negate/negate_wrap, implement astgenIsaac Freund
2021-03-20stage2: fix memory management of ZIR codeAndrew Kelley
2021-03-20astgen: implement inline assemblyAndrew Kelley
2021-03-20astgen: implement function callsAndrew Kelley
2021-03-19astgen: support blocksAndrew Kelley
2021-03-19stage2: first pass at repairing ZIR printingAndrew Kelley
2021-03-19Sema: allocate inst_map with arena where appropriateAndrew Kelley
2021-03-19stage2: fix some math oopsies and typosAndrew Kelley
2021-03-19stage2: fix export source locations not being relative to DeclAndrew Kelley
2021-03-19llvm backend: use new srclocjacob gw
2021-03-19zir-memory-layout: astgen: fill in identifierjacob gw
2021-03-18stage2: the code is compiling againAndrew Kelley
2021-03-18stage2: get Module and Sema compiling againAndrew Kelley
2021-03-17stage2: Module and Sema are compiling againAndrew Kelley
2021-03-17stage2: work through some compile errors in Module and SemaAndrew Kelley
2021-03-16stage2: rename zir_sema.zig to Sema.zigAndrew Kelley
2021-03-16stage2: *WIP*: rework ZIR memory layout; overhaul source locationsAndrew Kelley
2021-03-06stage2: implement var argsVeikka Tuominen
2021-03-06stage2: astgen asyncVeikka Tuominen
2021-03-03stage2: remove error number from error set mapjacob gw
2021-02-28stage2: remove value field from errorjacob gw
2021-02-25improve stage2 to allow catch at comptime:g-w1
2021-02-24zig fmt src/Andrew Kelley
2021-02-19stage2: fix not setting up ZIR arg instruction correctlyAndrew Kelley
2021-02-19stage2: remove incorrect newlines from log statementsAndrew Kelley
2021-02-19stage2: AST: clean up parse errorsAndrew Kelley
2021-02-18stage2: astgen: fix most of the remaining compile errorsAndrew Kelley
2021-02-17stage2: fix a couple more compilation errorsAndrew Kelley
2021-02-17stage2: fix some of the compilation errors in this branchAndrew Kelley
2021-02-17astgen: finish updating expressions to new mem layoutAndrew Kelley
2021-02-12stage2: more progress towards Module/astgen building with new mem layoutAndrew Kelley
2021-02-11Merge remote-tracking branch 'origin/master' into ast-memory-layoutAndrew Kelley
2021-02-11stage2: start reworking Module/astgen for memory layout changesAndrew Kelley
2021-02-10stage2: switch from inline fn to callconv(.Inline)Tadeo Kondrak
2021-02-09require specifier for arrayish typesJonathan Marler
2021-02-01Merge pull request #7827 from Snektron/spirv-setupAndrew Kelley
2021-02-01stage2 cbe: implement switchbrVeikka Tuominen
2021-01-31stage2: delete astgen for switch expressionsAndrew Kelley
2021-01-31astgen: rework labeled blocksAndrew Kelley
2021-01-31sema: after block gets peer type resolved, insert type coercionsAndrew Kelley
2021-01-31stage2: rework astgen result locationsAndrew Kelley
2021-01-19SPIR-V: Linking and codegen setupRobin Voetter
2021-01-19Merge pull request #7818 from kubkon/macho-more-cleanupJakub Konka
2021-01-19astgen: eliminate rlWrapPtr and all its callsitesAndrew Kelley
2021-01-18stage2: rework ZIR/TZIR for optionals and error unionsAndrew Kelley
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