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There seems to be an LLVM bug with this feature. Since it's new, let's
collect more information before adding it.
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* some manual fixes to generated CPU features code. in the future it
would be nice to make the script do those automatically. I suspect
the sm_90a thing is a bug in LLVM.
* add liteos to various target OS switches. I know nothing about this
OS; someone will need to work specifically on support for this OS
when the time comes to support it properly in zig.
* while waiting for the compiler, I went ahead and made more
conservative choices about when to use `inline` in std/Target.zig
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release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8
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Signed-off-by: Eric Joldasov <bratishkaerik@getgoogleoff.me>
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The majority of these are in comments, some in doc comments which might
affect the generated documentation, and a few in parameter names -
nothing that should be breaking, however.
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This adds a general target for SPIR-V compilation. Previously there was not
any target machine defined for SPIR-V.
TODO is to reword the features for this target. We don't really need the full
list of capabilities in the features, we should only put a few features here
which we can actually use during code generation.
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PR #13101 recently renamed the "i386" architecture to "x86", and it
seems the specific CPU model got swept up in that. "x86" is an umbrella
term that describes a family of CPUs, and the "i386" is the oldest
supported model under that umbrella.
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Notable changes:
`_i386`, `_i486`, and `_i686` are renamed to `i386`, `i486`,
and `i686` respectively. `std.zig.fmtId` is enhanced to support
formatting `i386` as `@"i386"`.
Some CPU features which are actually CPU models have been
properly flattened, such as `apple_a12`, `apple_a13`, `apple_a7`,
`cortex_a78c`, `exynos_m4`, `neoverse_e1`, `neoverse_n1`,
`neoverse_n2`, `neoverse_v1`.
Some CPU features have been added and some have been removed, following
LLVM's lead.
CSky CPU features support is added.
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The idea is to depend on this language feature as little as possible
with the hopes that it can be adjusted to be less of an anti-pattern.
This also helps self-hosted, which does not yet implement
`usingnamespace`, get closer to being able to build compiler-rt.
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Lakemont has no x86, no MMX, no SSE and no way of handling any fp-math. In theory LLVM is able to implicitly use the soft-float emulation library calls to legalize any such operation but, given Zig's use of many non-standard features, sometimes we hit a weak spot in the X86 codegen backend.
Consider this as a work-around for this LLVM problem, fixing the problem in LLVM is not so high in my todo list as the target is pretty niche and Intel axed it in '19.
(Commit message by @LemonBoy)
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This replaces callconv(.Inline) with the more idiomatic inline keyword.
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Modeled after GCC's description.
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- original PR #7949 (incorrectly) patched a generated-file and changes
have subsequently been lost/overwritten
- fix #7947 in a different way: drop `ppc32` because `ppc` already exists
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This completes the process. All target CPU features are now
auto-generated by the tools/update_cpu_features.zig script, which
contains all the overrides.
Invoking this tool against LLVM 12rc2 now produces an empty git diff.
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and use it to clean up aarch64 target CPU features
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With this change, added & modified cpus & features participate in the
same pruning system, and sorting takes into account the zig name, not
the pre-modified llvm name.
The modified target files in this commit are due to the improved
sorting and pruning.
The script now fully supports extra cpus & features.
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The tools/update_cpu_features script is coming along, and generates
correct information for all these targets. The remaining targets are:
* arm
* aarch64
* amdgpu
* riscv
I will commit them once the issues with the updater tool are resolved.
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Conflicts:
* src/clang.zig
* src/llvm.zig
- this file got moved to src/llvm/bindings.zig in master branch so I
had to put the new LLVM arch/os enum tags into it.
* lib/std/target.zig, src/stage1/target.cpp
- haiku had an inconsistency with its default target ABI, gnu vs
eabi. In this commit we make it gnu in both places to match the
latest changes by @hoanga.
* src/translate_c.zig
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- llvm does not accept `ppc32` as a CPU type
closes #7947
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Rather than directly pasting the output from the
target-details-generator tool, we have to look at the diff line by line
and decide how to incorporate the changes.
The baseline abstraction is something that Zig provides.
The changes to x86 appear to be incorrect. After LLVM commit
3ad09fd03c51823aeb0bcbd7898aada33e9228d6 the CPU features are stored in
a different data layout in their tables, and so we need to update the
target details extraction tool to match.
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llvm commit b2851aea80e5a8f0cfd6c3c5a56a6b00fb28c6b6
zig-llvm-target-details-generator commit
4299674ecabeb668b0d84285cd1b41a652a391b1
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LLVM calls generic sparc32 CPUs "v8" and generic sparc64 CPUs "v9".
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add SPDX license identifier
copyright ownership is zig contributors
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This is to prevent "expected token 'Symbol', found 'IntLiteral'" errors
when building zig files.
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This matches GCC's and Clang's default behavior for these targets.
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v6m is thumb-mode and the baseline should probably be an 'a' variant.
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