| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2025-10-27 | feat: init x86_16 arch via CBE | GasInfinity | |
| 2025-10-23 | std.Target: add tags and info for alpha, hppa, microblaze, sh | Alex Rønne Petersen | |
| 2025-10-23 | std.Target: add arceb and xtensaeb Cpu.Arch tags | Alex Rønne Petersen | |
| 2025-08-25 | start adding big endian RISC-V support | Alex Rønne Petersen | |
| The big endian RISC-V effort is mostly driven by MIPS (the company) which is pivoting to RISC-V, and presumably needs a big endian variant to fill the niche that big endian MIPS (the ISA) did. GCC already supports these targets, but LLVM support will only appear in 22; this commit just adds the necessary target knowledge and checks on our end. | |||
| 2025-07-16 | add lr register to mips | Andrew Kelley | |
| 2025-07-16 | fix sparc ccr regs | Andrew Kelley | |
| 2025-07-16 | fix mips clobbers | Andrew Kelley | |
| 2025-07-16 | add clobbers for more architectures | Andrew Kelley | |
| 2025-07-16 | remove condition codes | Andrew Kelley | |
| LLVM always assumes these are on. Zig backends do not observe them. If Zig backends want to start using them, they can be introduced, one arch at a time, with proper documentation. | |||
| 2025-07-16 | alexrp suggestions | Andrew Kelley | |
| 2025-07-16 | inline assembly: use types | Andrew Kelley | |
| until now these were stringly typed. it's kinda obvious when you think about it. | |||
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index : zig | |
| General-purpose programming language and toolchain for maintaining robust, optimal, and reusable software. https://ziglang.org |
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