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Closes #21818.
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Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
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The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.
This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
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From https://ziglang.org/documentation/master/#Names:
> If `x` is callable, and `x`'s return type is `type`, then `x` should
> be `TitleCase`.
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- RISCV unaligned-scalar-mem was added in LLVM 18.1.6
- Fixes arm v9_5a confusion
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release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
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