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Closes #21818.
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Most of this commit is whitespace changes, moving to use RLS
for assigning the `CpuModel`
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Like d1d95294fd657f771657ea671a6984b860347fb0, this is more Apple nonsense where
they abused the arch component of the triple to encode what's really an ABI.
Handling this correctly in Zig's target triple model would take quite a bit of
work. Fortunately, the last Armv7-based Apple Watch was released in 2017 and
these targets are now considered legacy. By the time Zig hits 1.0, they will be
a distant memory. So just remove them.
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* DefaultExts parsing for aarch64.
* cortex-m85 trustzone correction for arm.
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The compiler actually doesn't need any functional changes for this: Sema
does reification based on the tag indices of `std.builtin.Type` already!
So, no zig1.wasm update is necessary.
This change is necessary to disallow name clashes between fields and
decls on a type, which is a prerequisite of #9938.
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From https://ziglang.org/documentation/master/#Names:
> If `x` is callable, and `x`'s return type is `type`, then `x` should
> be `TitleCase`.
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- RISCV unaligned-scalar-mem was added in LLVM 18.1.6
- Fixes arm v9_5a confusion
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* some manual fixes to generated CPU features code. In the future it
would be nice to make the script do those automatically.
* add to various target OS switches. Some of the values I was unsure of
and added TODO panics, for example in the case of spirv CPU arch.
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release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42
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release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8
(same as the previous run)
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