diff options
Diffstat (limited to 'src/codegen/llvm.zig')
| -rw-r--r-- | src/codegen/llvm.zig | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 91bbea8b4a..41c817303c 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -1301,7 +1301,7 @@ pub const Object = struct { .large => .Large, }; - const float_abi: llvm.TargetMachine.FloatABI = if (comp.root_mod.resolved_target.result.floatAbi() == .hard) + const float_abi: llvm.TargetMachine.FloatABI = if (comp.root_mod.resolved_target.result.abi.float() == .hard) .Hard else .Soft; @@ -2939,7 +2939,7 @@ pub const Object = struct { function_index.setLinkage(.internal, &o.builder); function_index.setUnnamedAddr(.unnamed_addr, &o.builder); } else { - if (target.isWasm()) { + if (target.cpu.arch.isWasm()) { try attributes.addFnAttr(.{ .string = .{ .kind = try o.builder.string("wasm-import-name"), .value = try o.builder.string(nav.name.toSlice(ip)), @@ -3156,7 +3156,7 @@ pub const Object = struct { .value = try o.builder.string(std.mem.span(s)), } }, &o.builder); } - if (target.floatAbi() == .soft) { + if (target.abi.float() == .soft) { // `use-soft-float` means "use software routines for floating point computations". In // other words, it configures how LLVM lowers basic float instructions like `fcmp`, // `fadd`, etc. The float calling convention is configured on `TargetMachine` and is @@ -4830,7 +4830,7 @@ pub const NavGen = struct { const global_index = o.nav_map.get(nav_index).?; const decl_name = decl_name: { - if (zcu.getTarget().isWasm() and ty.zigTypeTag(zcu) == .@"fn") { + if (zcu.getTarget().cpu.arch.isWasm() and ty.zigTypeTag(zcu) == .@"fn") { if (lib_name.toSlice(ip)) |lib_name_slice| { if (!std.mem.eql(u8, lib_name_slice, "c")) { break :decl_name try o.builder.strtabStringFmt("{}|{s}", .{ nav.name.fmt(ip), lib_name_slice }); @@ -6567,7 +6567,7 @@ pub const FuncGen = struct { // Workaround for: // * https://github.com/llvm/llvm-project/blob/56905dab7da50bccfcceaeb496b206ff476127e1/llvm/lib/MC/WasmObjectWriter.cpp#L560 // * https://github.com/llvm/llvm-project/blob/56905dab7da50bccfcceaeb496b206ff476127e1/llvm/test/MC/WebAssembly/blockaddress.ll - if (zcu.comp.getTarget().isWasm()) break :jmp_table null; + if (zcu.comp.getTarget().cpu.arch.isWasm()) break :jmp_table null; // On a 64-bit target, 1024 pointers in our jump table is about 8K of pointers. This seems just // about acceptable - it won't fill L1d cache on most CPUs. @@ -10024,7 +10024,7 @@ pub const FuncGen = struct { // of the length. This means we need to emit a check where we skip the memset when the length // is 0 as we allow for undefined pointers in 0-sized slices. // This logic can be removed once https://github.com/ziglang/zig/issues/16360 is done. - const intrinsic_len0_traps = o.target.isWasm() and + const intrinsic_len0_traps = o.target.cpu.arch.isWasm() and ptr_ty.isSlice(zcu) and std.Target.wasm.featureSetHas(o.target.cpu.features, .bulk_memory); @@ -10181,7 +10181,7 @@ pub const FuncGen = struct { // For this reason we must add a check for 0-sized slices as its pointer field can be undefined. // We only have to do this for slices as arrays will have a valid pointer. // This logic can be removed once https://github.com/ziglang/zig/issues/16360 is done. - if (o.target.isWasm() and + if (o.target.cpu.arch.isWasm() and std.Target.wasm.featureSetHas(o.target.cpu.features, .bulk_memory) and dest_ptr_ty.isSlice(zcu)) { @@ -12696,7 +12696,7 @@ fn backendSupportsF16(target: std.Target) bool { .armeb, .thumb, .thumbeb, - => target.floatAbi() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8), + => target.abi.float() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8), .aarch64, .aarch64_be, => std.Target.aarch64.featureSetHas(target.cpu.features, .fp_armv8), @@ -12723,7 +12723,7 @@ fn backendSupportsF128(target: std.Target) bool { .armeb, .thumb, .thumbeb, - => target.floatAbi() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8), + => target.abi.float() == .soft or std.Target.arm.featureSetHas(target.cpu.features, .fp_armv8), .aarch64, .aarch64_be, => std.Target.aarch64.featureSetHas(target.cpu.features, .fp_armv8), |