diff options
Diffstat (limited to 'src/arch/arm/bits.zig')
| -rw-r--r-- | src/arch/arm/bits.zig | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/src/arch/arm/bits.zig b/src/arch/arm/bits.zig index 1de40a7059..6c33f3e82a 100644 --- a/src/arch/arm/bits.zig +++ b/src/arch/arm/bits.zig @@ -159,7 +159,7 @@ pub const Register = enum(u5) { /// Returns the unique 4-bit ID of this register which is used in /// the machine code pub fn id(self: Register) u4 { - return @truncate(u4, @intFromEnum(self)); + return @as(u4, @truncate(@intFromEnum(self))); } pub fn dwarfLocOp(self: Register) u8 { @@ -399,8 +399,8 @@ pub const Instruction = union(enum) { pub fn toU8(self: Shift) u8 { return switch (self) { - .register => |v| @bitCast(u8, v), - .immediate => |v| @bitCast(u8, v), + .register => |v| @as(u8, @bitCast(v)), + .immediate => |v| @as(u8, @bitCast(v)), }; } @@ -425,8 +425,8 @@ pub const Instruction = union(enum) { pub fn toU12(self: Operand) u12 { return switch (self) { - .register => |v| @bitCast(u12, v), - .immediate => |v| @bitCast(u12, v), + .register => |v| @as(u12, @bitCast(v)), + .immediate => |v| @as(u12, @bitCast(v)), }; } @@ -463,8 +463,8 @@ pub const Instruction = union(enum) { if (x & mask == x) { break Operand{ .immediate = .{ - .imm = @intCast(u8, std.math.rotl(u32, x, 2 * i)), - .rotate = @intCast(u4, i), + .imm = @as(u8, @intCast(std.math.rotl(u32, x, 2 * i))), + .rotate = @as(u4, @intCast(i)), }, }; } @@ -522,7 +522,7 @@ pub const Instruction = union(enum) { pub fn toU12(self: Offset) u12 { return switch (self) { - .register => |v| @bitCast(u12, v), + .register => |v| @as(u12, @bitCast(v)), .immediate => |v| v, }; } @@ -604,20 +604,20 @@ pub const Instruction = union(enum) { pub fn toU32(self: Instruction) u32 { return switch (self) { - .data_processing => |v| @bitCast(u32, v), - .multiply => |v| @bitCast(u32, v), - .multiply_long => |v| @bitCast(u32, v), - .signed_multiply_halfwords => |v| @bitCast(u32, v), - .integer_saturating_arithmetic => |v| @bitCast(u32, v), - .bit_field_extract => |v| @bitCast(u32, v), - .single_data_transfer => |v| @bitCast(u32, v), - .extra_load_store => |v| @bitCast(u32, v), - .block_data_transfer => |v| @bitCast(u32, v), - .branch => |v| @bitCast(u32, v), - .branch_exchange => |v| @bitCast(u32, v), - .supervisor_call => |v| @bitCast(u32, v), + .data_processing => |v| @as(u32, @bitCast(v)), + .multiply => |v| @as(u32, @bitCast(v)), + .multiply_long => |v| @as(u32, @bitCast(v)), + .signed_multiply_halfwords => |v| @as(u32, @bitCast(v)), + .integer_saturating_arithmetic => |v| @as(u32, @bitCast(v)), + .bit_field_extract => |v| @as(u32, @bitCast(v)), + .single_data_transfer => |v| @as(u32, @bitCast(v)), + .extra_load_store => |v| @as(u32, @bitCast(v)), + .block_data_transfer => |v| @as(u32, @bitCast(v)), + .branch => |v| @as(u32, @bitCast(v)), + .branch_exchange => |v| @as(u32, @bitCast(v)), + .supervisor_call => |v| @as(u32, @bitCast(v)), .undefined_instruction => |v| v.imm32, - .breakpoint => |v| @intCast(u32, v.imm4) | (@intCast(u32, v.fixed_1) << 4) | (@intCast(u32, v.imm12) << 8) | (@intCast(u32, v.fixed_2_and_cond) << 20), + .breakpoint => |v| @as(u32, @intCast(v.imm4)) | (@as(u32, @intCast(v.fixed_1)) << 4) | (@as(u32, @intCast(v.imm12)) << 8) | (@as(u32, @intCast(v.fixed_2_and_cond)) << 20), }; } @@ -656,9 +656,9 @@ pub const Instruction = union(enum) { .i = 1, .opcode = if (top) 0b1010 else 0b1000, .s = 0, - .rn = @truncate(u4, imm >> 12), + .rn = @as(u4, @truncate(imm >> 12)), .rd = rd.id(), - .op2 = @truncate(u12, imm), + .op2 = @as(u12, @truncate(imm)), }, }; } @@ -760,7 +760,7 @@ pub const Instruction = union(enum) { .rn = rn.id(), .lsb = lsb, .rd = rd.id(), - .widthm1 = @intCast(u5, width - 1), + .widthm1 = @as(u5, @intCast(width - 1)), .unsigned = unsigned, .cond = @intFromEnum(cond), }, @@ -810,11 +810,11 @@ pub const Instruction = union(enum) { offset: ExtraLoadStoreOffset, ) Instruction { const imm4l: u4 = switch (offset) { - .immediate => |imm| @truncate(u4, imm), + .immediate => |imm| @as(u4, @truncate(imm)), .register => |reg| reg, }; const imm4h: u4 = switch (offset) { - .immediate => |imm| @truncate(u4, imm >> 4), + .immediate => |imm| @as(u4, @truncate(imm >> 4)), .register => 0b0000, }; @@ -853,7 +853,7 @@ pub const Instruction = union(enum) { ) Instruction { return Instruction{ .block_data_transfer = .{ - .register_list = @bitCast(u16, reg_list), + .register_list = @as(u16, @bitCast(reg_list)), .rn = rn.id(), .load_store = load_store, .write_back = @intFromBool(write_back), @@ -870,7 +870,7 @@ pub const Instruction = union(enum) { .branch = .{ .cond = @intFromEnum(cond), .link = link, - .offset = @bitCast(u24, @intCast(i24, offset >> 2)), + .offset = @as(u24, @bitCast(@as(i24, @intCast(offset >> 2)))), }, }; } @@ -904,8 +904,8 @@ pub const Instruction = union(enum) { fn breakpoint(imm: u16) Instruction { return Instruction{ .breakpoint = .{ - .imm12 = @truncate(u12, imm >> 4), - .imm4 = @truncate(u4, imm), + .imm12 = @as(u12, @truncate(imm >> 4)), + .imm4 = @as(u4, @truncate(imm)), }, }; } @@ -1319,7 +1319,7 @@ pub const Instruction = union(enum) { const reg = @as(Register, arg); register_list |= @as(u16, 1) << reg.id(); } - return ldm(cond, .sp, true, @bitCast(RegisterList, register_list)); + return ldm(cond, .sp, true, @as(RegisterList, @bitCast(register_list))); } } @@ -1343,7 +1343,7 @@ pub const Instruction = union(enum) { const reg = @as(Register, arg); register_list |= @as(u16, 1) << reg.id(); } - return stmdb(cond, .sp, true, @bitCast(RegisterList, register_list)); + return stmdb(cond, .sp, true, @as(RegisterList, @bitCast(register_list))); } } |