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-rw-r--r--lib/std/os/bits/linux.zig2
-rw-r--r--lib/std/os/linux.zig1
-rw-r--r--lib/std/os/linux/thumb.zig168
-rw-r--r--lib/std/os/linux/tls.zig6
-rw-r--r--lib/std/os/test.zig2
-rw-r--r--lib/std/special/c.zig2
-rw-r--r--lib/std/special/compiler_rt/clzsi2.zig27
-rw-r--r--lib/std/special/compiler_rt/clzsi2_test.zig2
-rw-r--r--lib/std/start.zig2
-rw-r--r--lib/std/zig/system.zig9
10 files changed, 208 insertions, 13 deletions
diff --git a/lib/std/os/bits/linux.zig b/lib/std/os/bits/linux.zig
index b877976072..556eb20ab2 100644
--- a/lib/std/os/bits/linux.zig
+++ b/lib/std/os/bits/linux.zig
@@ -18,7 +18,7 @@ pub usingnamespace switch (arch) {
.i386 => @import("linux/i386.zig"),
.x86_64 => @import("linux/x86_64.zig"),
.aarch64 => @import("linux/arm64.zig"),
- .arm => @import("linux/arm-eabi.zig"),
+ .arm, .thumb => @import("linux/arm-eabi.zig"),
.riscv64 => @import("linux/riscv64.zig"),
.sparcv9 => @import("linux/sparc64.zig"),
.mips, .mipsel => @import("linux/mips.zig"),
diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig
index 5e5fde2b97..65cbc87e36 100644
--- a/lib/std/os/linux.zig
+++ b/lib/std/os/linux.zig
@@ -24,6 +24,7 @@ pub usingnamespace switch (native_arch) {
.x86_64 => @import("linux/x86_64.zig"),
.aarch64 => @import("linux/arm64.zig"),
.arm => @import("linux/arm-eabi.zig"),
+ .thumb => @import("linux/thumb.zig"),
.riscv64 => @import("linux/riscv64.zig"),
.sparcv9 => @import("linux/sparc64.zig"),
.mips, .mipsel => @import("linux/mips.zig"),
diff --git a/lib/std/os/linux/thumb.zig b/lib/std/os/linux/thumb.zig
new file mode 100644
index 0000000000..5db9d2cbf4
--- /dev/null
+++ b/lib/std/os/linux/thumb.zig
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: MIT
+// Copyright (c) 2015-2021 Zig Contributors
+// This file is part of [zig](https://ziglang.org/), which is MIT licensed.
+// The MIT license requires this copyright notice to be included in all copies
+// and substantial portions of the software.
+usingnamespace @import("../bits.zig");
+
+// The syscall interface is identical to the ARM one but we're facing an extra
+// challenge: r7, the register where the syscall number is stored, may be
+// reserved for the frame pointer.
+// Save and restore r7 around the syscall without touching the stack pointer not
+// to break the frame chain.
+
+pub fn syscall0(number: SYS) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r1}" (buf)
+ : "memory"
+ );
+}
+
+pub fn syscall1(number: SYS, arg1: usize) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r1}" (buf),
+ [arg1] "{r0}" (arg1)
+ : "memory"
+ );
+}
+
+pub fn syscall2(number: SYS, arg1: usize, arg2: usize) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r2}" (buf),
+ [arg1] "{r0}" (arg1),
+ [arg2] "{r1}" (arg2)
+ : "memory"
+ );
+}
+
+pub fn syscall3(number: SYS, arg1: usize, arg2: usize, arg3: usize) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r3}" (buf),
+ [arg1] "{r0}" (arg1),
+ [arg2] "{r1}" (arg2),
+ [arg3] "{r2}" (arg3)
+ : "memory"
+ );
+}
+
+pub fn syscall4(number: SYS, arg1: usize, arg2: usize, arg3: usize, arg4: usize) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r4}" (buf),
+ [arg1] "{r0}" (arg1),
+ [arg2] "{r1}" (arg2),
+ [arg3] "{r2}" (arg3),
+ [arg4] "{r3}" (arg4)
+ : "memory"
+ );
+}
+
+pub fn syscall5(number: SYS, arg1: usize, arg2: usize, arg3: usize, arg4: usize, arg5: usize) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r5}" (buf),
+ [arg1] "{r0}" (arg1),
+ [arg2] "{r1}" (arg2),
+ [arg3] "{r2}" (arg3),
+ [arg4] "{r3}" (arg4),
+ [arg5] "{r4}" (arg5)
+ : "memory"
+ );
+}
+
+pub fn syscall6(
+ number: SYS,
+ arg1: usize,
+ arg2: usize,
+ arg3: usize,
+ arg4: usize,
+ arg5: usize,
+ arg6: usize,
+) usize {
+ @setRuntimeSafety(false);
+
+ var buf: [2]usize = .{ @enumToInt(number), undefined };
+ return asm volatile (
+ \\ str r7, [%[tmp], #4]
+ \\ ldr r7, [%[tmp]]
+ \\ svc #0
+ \\ ldr r7, [%[tmp], #4]
+ : [ret] "={r0}" (-> usize)
+ : [tmp] "{r6}" (buf),
+ [arg1] "{r0}" (arg1),
+ [arg2] "{r1}" (arg2),
+ [arg3] "{r2}" (arg3),
+ [arg4] "{r3}" (arg4),
+ [arg5] "{r4}" (arg5),
+ [arg6] "{r5}" (arg6)
+ : "memory"
+ );
+}
+
+/// This matches the libc clone function.
+pub extern fn clone(func: fn (arg: usize) callconv(.C) u8, stack: usize, flags: u32, arg: usize, ptid: *i32, tls: usize, ctid: *i32) usize;
+
+pub fn restore() callconv(.Naked) void {
+ return asm volatile (
+ \\ mov r7, %[number]
+ \\ svc #0
+ :
+ : [number] "I" (@enumToInt(SYS.sigreturn))
+ );
+}
+
+pub fn restore_rt() callconv(.Naked) void {
+ return asm volatile (
+ \\ mov r7, %[number]
+ \\ svc #0
+ :
+ : [number] "I" (@enumToInt(SYS.rt_sigreturn))
+ : "memory"
+ );
+}
diff --git a/lib/std/os/linux/tls.zig b/lib/std/os/linux/tls.zig
index 38a307ac2f..4d5dba3112 100644
--- a/lib/std/os/linux/tls.zig
+++ b/lib/std/os/linux/tls.zig
@@ -53,7 +53,7 @@ const TLSVariant = enum {
};
const tls_variant = switch (native_arch) {
- .arm, .armeb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => TLSVariant.VariantI,
+ .arm, .armeb, .thumb, .aarch64, .aarch64_be, .riscv32, .riscv64, .mips, .mipsel, .powerpc, .powerpc64, .powerpc64le => TLSVariant.VariantI,
.x86_64, .i386, .sparcv9 => TLSVariant.VariantII,
else => @compileError("undefined tls_variant for this architecture"),
};
@@ -62,7 +62,7 @@ const tls_variant = switch (native_arch) {
const tls_tcb_size = switch (native_arch) {
// ARM EABI mandates enough space for two pointers: the first one points to
// the DTV while the second one is unspecified but reserved
- .arm, .armeb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
+ .arm, .armeb, .thumb, .aarch64, .aarch64_be => 2 * @sizeOf(usize),
// One pointer-sized word that points either to the DTV or the TCB itself
else => @sizeOf(usize),
};
@@ -150,7 +150,7 @@ pub fn setThreadPointer(addr: usize) void {
: [addr] "r" (addr)
);
},
- .arm => {
+ .arm, .thumb => {
const rc = std.os.linux.syscall1(.set_tls, addr);
assert(rc == 0);
},
diff --git a/lib/std/os/test.zig b/lib/std/os/test.zig
index bae03ba6aa..bcb2fa339a 100644
--- a/lib/std/os/test.zig
+++ b/lib/std/os/test.zig
@@ -43,6 +43,8 @@ test "chdir smoke test" {
// Next, change current working directory to one level above
const parent = fs.path.dirname(old_cwd) orelse unreachable; // old_cwd should be absolute
try os.chdir(parent);
+ // Restore cwd because process may have other tests that do not tolerate chdir.
+ defer os.chdir(old_cwd) catch unreachable;
var new_cwd_buf: [fs.MAX_PATH_BYTES]u8 = undefined;
const new_cwd = try os.getcwd(new_cwd_buf[0..]);
expect(mem.eql(u8, parent, new_cwd));
diff --git a/lib/std/special/c.zig b/lib/std/special/c.zig
index 6515a790b3..8a9093f3ea 100644
--- a/lib/std/special/c.zig
+++ b/lib/std/special/c.zig
@@ -388,7 +388,7 @@ fn clone() callconv(.Naked) void {
\\ svc #0
);
},
- .arm => {
+ .arm, .thumb => {
// __clone(func, stack, flags, arg, ptid, tls, ctid)
// r0, r1, r2, r3, +0, +4, +8
diff --git a/lib/std/special/compiler_rt/clzsi2.zig b/lib/std/special/compiler_rt/clzsi2.zig
index c10786b462..d7464d5ea9 100644
--- a/lib/std/special/compiler_rt/clzsi2.zig
+++ b/lib/std/special/compiler_rt/clzsi2.zig
@@ -26,6 +26,8 @@ fn __clzsi2_generic(a: i32) callconv(.C) i32 {
}
fn __clzsi2_thumb1() callconv(.Naked) void {
+ @setRuntimeSafety(false);
+
// Similar to the generic version with the last two rounds replaced by a LUT
asm volatile (
\\ movs r1, #32
@@ -58,6 +60,8 @@ fn __clzsi2_thumb1() callconv(.Naked) void {
}
fn __clzsi2_arm32() callconv(.Naked) void {
+ @setRuntimeSafety(false);
+
asm volatile (
\\ // Assumption: n != 0
\\ // r0: n
@@ -104,13 +108,22 @@ fn __clzsi2_arm32() callconv(.Naked) void {
unreachable;
}
-pub const __clzsi2 = switch (std.Target.current.cpu.arch) {
- .arm, .armeb => if (std.Target.arm.featureSetHas(std.Target.current.cpu.features, .noarm))
- __clzsi2_thumb1
- else
- __clzsi2_arm32,
- .thumb, .thumbeb => __clzsi2_thumb1,
- else => __clzsi2_generic,
+pub const __clzsi2 = impl: {
+ switch (std.Target.current.cpu.arch) {
+ .arm, .armeb, .thumb, .thumbeb => {
+ const use_thumb1 =
+ (std.Target.current.cpu.arch.isThumb() or
+ std.Target.arm.featureSetHas(std.Target.current.cpu.features, .noarm)) and
+ !std.Target.arm.featureSetHas(std.Target.current.cpu.features, .thumb2);
+
+ if (use_thumb1) break :impl __clzsi2_thumb1
+ // From here on we're either targeting Thumb2 or ARM.
+ else if (!std.Target.current.cpu.arch.isThumb()) break :impl __clzsi2_arm32
+ // Use the generic implementation otherwise.
+ else break :impl __clzsi2_generic;
+ },
+ else => break :impl __clzsi2_generic,
+ }
};
test "test clzsi2" {
diff --git a/lib/std/special/compiler_rt/clzsi2_test.zig b/lib/std/special/compiler_rt/clzsi2_test.zig
index 2b860afd22..c74a1c3ec2 100644
--- a/lib/std/special/compiler_rt/clzsi2_test.zig
+++ b/lib/std/special/compiler_rt/clzsi2_test.zig
@@ -7,6 +7,8 @@ const clzsi2 = @import("clzsi2.zig");
const testing = @import("std").testing;
fn test__clzsi2(a: u32, expected: i32) void {
+ // XXX At high optimization levels this test may be horribly miscompiled if
+ // one of the naked implementations is selected.
var nakedClzsi2 = clzsi2.__clzsi2;
var actualClzsi2 = @ptrCast(fn (a: i32) callconv(.C) i32, nakedClzsi2);
var x = @bitCast(i32, a);
diff --git a/lib/std/start.zig b/lib/std/start.zig
index 998dba6074..fa9d5a92b6 100644
--- a/lib/std/start.zig
+++ b/lib/std/start.zig
@@ -182,7 +182,7 @@ fn _start() callconv(.Naked) noreturn {
: [argc] "={esp}" (-> [*]usize)
);
},
- .aarch64, .aarch64_be, .arm, .armeb => {
+ .aarch64, .aarch64_be, .arm, .armeb, .thumb => {
argc_argv_ptr = asm volatile (
\\ mov fp, #0
\\ mov lr, #0
diff --git a/lib/std/zig/system.zig b/lib/std/zig/system.zig
index 04b3d75cb4..5792e7f115 100644
--- a/lib/std/zig/system.zig
+++ b/lib/std/zig/system.zig
@@ -350,6 +350,15 @@ pub const NativeTargetInfo = struct {
}
}
},
+ .arm, .armeb => {
+ // XXX What do we do if the target has the noarm feature?
+ // What do we do if the user specifies +thumb_mode?
+ },
+ .thumb, .thumbeb => {
+ result.target.cpu.features.addFeature(
+ @enumToInt(std.Target.arm.Feature.thumb_mode),
+ );
+ },
else => {},
}
cross_target.updateCpuFeatures(&result.target.cpu.features);
generated by cgit v1.2.3 (git 2.39.1) at 2025-12-27 22:04:07 +0000