diff options
Diffstat (limited to 'lib/std')
28 files changed, 896 insertions, 173 deletions
diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig index a4f0ef269f..08fc85871b 100644 --- a/lib/std/builtin.zig +++ b/lib/std/builtin.zig @@ -460,6 +460,8 @@ pub const Version = struct { /// therefore must be kept in sync with the compiler implementation. pub const CallOptions = struct { modifier: Modifier = .auto, + + /// Only valid when `Modifier` is `Modifier.async_kw`. stack: ?[]align(std.Target.stack_align) u8 = null, pub const Modifier = enum { diff --git a/lib/std/fmt.zig b/lib/std/fmt.zig index 3729b7dc87..38371b3aea 100644 --- a/lib/std/fmt.zig +++ b/lib/std/fmt.zig @@ -1728,8 +1728,14 @@ test "positional/alignment/width/precision" { } test "vector" { - // https://github.com/ziglang/zig/issues/3317 - if (builtin.arch == .mipsel) return error.SkipZigTest; + if (builtin.arch == .mipsel) { + // https://github.com/ziglang/zig/issues/3317 + return error.SkipZigTest; + } + if (builtin.arch == .riscv64) { + // https://github.com/ziglang/zig/issues/4486 + return error.SkipZigTest; + } const vbool: @Vector(4, bool) = [_]bool{ true, false, true, false }; const vi64: @Vector(4, i64) = [_]i64{ -2, -1, 0, 1 }; diff --git a/lib/std/fmt/parse_float.zig b/lib/std/fmt/parse_float.zig index c62d614a6f..0268ca96cc 100644 --- a/lib/std/fmt/parse_float.zig +++ b/lib/std/fmt/parse_float.zig @@ -382,10 +382,6 @@ pub fn parseFloat(comptime T: type, s: []const u8) !T { } test "fmt.parseFloat" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } const testing = std.testing; const expect = testing.expect; const expectEqual = testing.expectEqual; diff --git a/lib/std/io/test.zig b/lib/std/io/test.zig index 1ab0f82313..bc194046f6 100644 --- a/lib/std/io/test.zig +++ b/lib/std/io/test.zig @@ -544,10 +544,6 @@ fn testSerializerDeserializer(comptime endian: builtin.Endian, comptime packing: } test "Serializer/Deserializer generic" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } try testSerializerDeserializer(builtin.Endian.Big, .Byte); try testSerializerDeserializer(builtin.Endian.Little, .Byte); try testSerializerDeserializer(builtin.Endian.Big, .Bit); diff --git a/lib/std/math/fabs.zig b/lib/std/math/fabs.zig index 2635962fcc..a659e35ca2 100644 --- a/lib/std/math/fabs.zig +++ b/lib/std/math/fabs.zig @@ -95,10 +95,6 @@ test "math.fabs64.special" { } test "math.fabs128.special" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } expect(math.isPositiveInf(fabs(math.inf(f128)))); expect(math.isPositiveInf(fabs(-math.inf(f128)))); expect(math.isNan(fabs(math.nan(f128)))); diff --git a/lib/std/math/isinf.zig b/lib/std/math/isinf.zig index c51747fd12..6eacab52ad 100644 --- a/lib/std/math/isinf.zig +++ b/lib/std/math/isinf.zig @@ -74,10 +74,6 @@ pub fn isNegativeInf(x: var) bool { } test "math.isInf" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } expect(!isInf(@as(f16, 0.0))); expect(!isInf(@as(f16, -0.0))); expect(!isInf(@as(f32, 0.0))); @@ -97,10 +93,6 @@ test "math.isInf" { } test "math.isPositiveInf" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } expect(!isPositiveInf(@as(f16, 0.0))); expect(!isPositiveInf(@as(f16, -0.0))); expect(!isPositiveInf(@as(f32, 0.0))); @@ -120,10 +112,6 @@ test "math.isPositiveInf" { } test "math.isNegativeInf" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } expect(!isNegativeInf(@as(f16, 0.0))); expect(!isNegativeInf(@as(f16, -0.0))); expect(!isNegativeInf(@as(f32, 0.0))); diff --git a/lib/std/math/isnan.zig b/lib/std/math/isnan.zig index 2879c44502..ac865f0d0c 100644 --- a/lib/std/math/isnan.zig +++ b/lib/std/math/isnan.zig @@ -16,10 +16,6 @@ pub fn isSignalNan(x: var) bool { } test "math.isNan" { - if (std.Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } expect(isNan(math.nan(f16))); expect(isNan(math.nan(f32))); expect(isNan(math.nan(f64))); diff --git a/lib/std/special/compiler_rt/addXf3_test.zig b/lib/std/special/compiler_rt/addXf3_test.zig index d7e175045c..af991b37e9 100644 --- a/lib/std/special/compiler_rt/addXf3_test.zig +++ b/lib/std/special/compiler_rt/addXf3_test.zig @@ -31,10 +31,6 @@ fn test__addtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) void { } test "addtf3" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__addtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0); // NaN + any = NaN @@ -75,10 +71,6 @@ fn test__subtf3(a: f128, b: f128, expected_hi: u64, expected_lo: u64) void { } test "subtf3" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } // qNaN - any = qNaN test__subtf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0); diff --git a/lib/std/special/compiler_rt/fixtfdi_test.zig b/lib/std/special/compiler_rt/fixtfdi_test.zig index cb4b94c5cd..6baa9011c3 100644 --- a/lib/std/special/compiler_rt/fixtfdi_test.zig +++ b/lib/std/special/compiler_rt/fixtfdi_test.zig @@ -11,10 +11,6 @@ fn test__fixtfdi(a: f128, expected: i64) void { } test "fixtfdi" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } //warn("\n", .{}); test__fixtfdi(-math.f128_max, math.minInt(i64)); diff --git a/lib/std/special/compiler_rt/fixtfsi_test.zig b/lib/std/special/compiler_rt/fixtfsi_test.zig index 96bb151e80..c7294fe250 100644 --- a/lib/std/special/compiler_rt/fixtfsi_test.zig +++ b/lib/std/special/compiler_rt/fixtfsi_test.zig @@ -11,10 +11,6 @@ fn test__fixtfsi(a: f128, expected: i32) void { } test "fixtfsi" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } //warn("\n", .{}); test__fixtfsi(-math.f128_max, math.minInt(i32)); diff --git a/lib/std/special/compiler_rt/fixtfti_test.zig b/lib/std/special/compiler_rt/fixtfti_test.zig index 73cc0596e7..6b8218e2f6 100644 --- a/lib/std/special/compiler_rt/fixtfti_test.zig +++ b/lib/std/special/compiler_rt/fixtfti_test.zig @@ -11,10 +11,6 @@ fn test__fixtfti(a: f128, expected: i128) void { } test "fixtfti" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } //warn("\n", .{}); test__fixtfti(-math.f128_max, math.minInt(i128)); diff --git a/lib/std/special/compiler_rt/fixunstfdi_test.zig b/lib/std/special/compiler_rt/fixunstfdi_test.zig index 02cef2f700..0d47641c09 100644 --- a/lib/std/special/compiler_rt/fixunstfdi_test.zig +++ b/lib/std/special/compiler_rt/fixunstfdi_test.zig @@ -7,10 +7,6 @@ fn test__fixunstfdi(a: f128, expected: u64) void { } test "fixunstfdi" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__fixunstfdi(0.0, 0); test__fixunstfdi(0.5, 0); diff --git a/lib/std/special/compiler_rt/fixunstfsi_test.zig b/lib/std/special/compiler_rt/fixunstfsi_test.zig index 734efff4de..286567629a 100644 --- a/lib/std/special/compiler_rt/fixunstfsi_test.zig +++ b/lib/std/special/compiler_rt/fixunstfsi_test.zig @@ -9,10 +9,6 @@ fn test__fixunstfsi(a: f128, expected: u32) void { const inf128 = @bitCast(f128, @as(u128, 0x7fff0000000000000000000000000000)); test "fixunstfsi" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__fixunstfsi(inf128, 0xffffffff); test__fixunstfsi(0, 0x0); test__fixunstfsi(0x1.23456789abcdefp+5, 0x24); diff --git a/lib/std/special/compiler_rt/fixunstfti_test.zig b/lib/std/special/compiler_rt/fixunstfti_test.zig index 649fcdf1e3..62a9bbfecf 100644 --- a/lib/std/special/compiler_rt/fixunstfti_test.zig +++ b/lib/std/special/compiler_rt/fixunstfti_test.zig @@ -9,10 +9,6 @@ fn test__fixunstfti(a: f128, expected: u128) void { const inf128 = @bitCast(f128, @as(u128, 0x7fff0000000000000000000000000000)); test "fixunstfti" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__fixunstfti(inf128, 0xffffffffffffffffffffffffffffffff); test__fixunstfti(0.0, 0); diff --git a/lib/std/special/compiler_rt/floattitf_test.zig b/lib/std/special/compiler_rt/floattitf_test.zig index 4601b90107..53e3e48bdb 100644 --- a/lib/std/special/compiler_rt/floattitf_test.zig +++ b/lib/std/special/compiler_rt/floattitf_test.zig @@ -7,10 +7,6 @@ fn test__floattitf(a: i128, expected: f128) void { } test "floattitf" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__floattitf(0, 0.0); test__floattitf(1, 1.0); diff --git a/lib/std/special/compiler_rt/floatuntitf_test.zig b/lib/std/special/compiler_rt/floatuntitf_test.zig index 34c7407c98..09f3eabb3e 100644 --- a/lib/std/special/compiler_rt/floatuntitf_test.zig +++ b/lib/std/special/compiler_rt/floatuntitf_test.zig @@ -7,10 +7,6 @@ fn test__floatuntitf(a: u128, expected: f128) void { } test "floatuntitf" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } test__floatuntitf(0, 0.0); test__floatuntitf(1, 1.0); diff --git a/lib/std/special/compiler_rt/mulXf3_test.zig b/lib/std/special/compiler_rt/mulXf3_test.zig index 45baa62a17..57dc385321 100644 --- a/lib/std/special/compiler_rt/mulXf3_test.zig +++ b/lib/std/special/compiler_rt/mulXf3_test.zig @@ -44,10 +44,6 @@ fn makeNaN128(rand: u64) f128 { return float_result; } test "multf3" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } // qNaN * any = qNaN test__multf3(qnan128, 0x1.23456789abcdefp+5, 0x7fff800000000000, 0x0); diff --git a/lib/std/special/compiler_rt/truncXfYf2_test.zig b/lib/std/special/compiler_rt/truncXfYf2_test.zig index bd05c8652c..baec2a4450 100644 --- a/lib/std/special/compiler_rt/truncXfYf2_test.zig +++ b/lib/std/special/compiler_rt/truncXfYf2_test.zig @@ -151,10 +151,6 @@ fn test__trunctfsf2(a: f128, expected: u32) void { } test "trunctfsf2" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } // qnan test__trunctfsf2(@bitCast(f128, @as(u128, 0x7fff800000000000 << 64)), 0x7fc00000); // nan @@ -190,10 +186,6 @@ fn test__trunctfdf2(a: f128, expected: u64) void { } test "trunctfdf2" { - if (@import("std").Target.current.os.tag == .windows) { - // TODO https://github.com/ziglang/zig/issues/508 - return error.SkipZigTest; - } // qnan test__trunctfdf2(@bitCast(f128, @as(u128, 0x7fff800000000000 << 64)), 0x7ff8000000000000); // nan diff --git a/lib/std/target.zig b/lib/std/target.zig index 53c5731179..74c5362a00 100644 --- a/lib/std/target.zig +++ b/lib/std/target.zig @@ -321,8 +321,6 @@ pub const Target = struct { code16, eabi, eabihf, - elfv1, - elfv2, android, musl, musleabi, @@ -458,7 +456,7 @@ pub const Target = struct { pub const Set = struct { ints: [usize_count]usize, - pub const needed_bit_count = 154; + pub const needed_bit_count = 155; pub const byte_count = (needed_bit_count + 7) / 8; pub const usize_count = (byte_count + (@sizeOf(usize) - 1)) / @sizeOf(usize); pub const Index = std.math.Log2Int(std.meta.IntType(false, usize_count * @bitSizeOf(usize))); @@ -605,6 +603,7 @@ pub const Target = struct { wasm64, renderscript32, renderscript64, + ve, pub fn isARM(arch: Arch) bool { return switch (arch) { @@ -819,6 +818,7 @@ pub const Target = struct { .bpfeb, .sparcv9, .s390x, + .ve, => return 64, } } @@ -1261,6 +1261,7 @@ pub const Target = struct { .lanai, .renderscript32, .renderscript64, + .ve, => return result, }, diff --git a/lib/std/target/aarch64.zig b/lib/std/target/aarch64.zig index 40d3ea96ba..5c49d4acfc 100644 --- a/lib/std/target/aarch64.zig +++ b/lib/std/target/aarch64.zig @@ -3,12 +3,18 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { + a65, a76, aes, aggressive_fma, alternate_sextload_cvt_f32_pattern, altnzcv, am, + apple_a10, + apple_a11, + apple_a12, + apple_a13, + apple_a7, arith_bcc_fusion, arith_cbz_fusion, balance_fp_ops, @@ -29,10 +35,10 @@ pub const Feature = enum { crc, crypto, custom_cheap_as_move, - cyclone, disable_latency_sched_heuristic, dit, dotprod, + ete, exynos_cheap_as_move, exynosm4, fmi, @@ -54,12 +60,15 @@ pub const Feature = enum { mpam, mte, neon, + neoversee1, + neoversen1, no_neg_immediates, nv, pa, pan, pan_rwv, perfmon, + pmu, predictable_select_expensive, predres, rand, @@ -110,11 +119,14 @@ pub const Feature = enum { sve2_bitperm, sve2_sha3, sve2_sm4, + tagged_globals, tlb_rmi, + tme, tpidr_el1, tpidr_el2, tpidr_el3, tracev8_4, + trbe, uaops, use_aa, use_postra_scheduler, @@ -140,6 +152,21 @@ pub const all_features = blk: { const len = @typeInfo(Feature).Enum.fields.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; + result[@enumToInt(Feature.a65)] = .{ + .llvm_name = "a65", + .description = "Cortex-A65 ARM processors", + .dependencies = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .neon, + .ras, + .rcpc, + .ssbs, + .v8_2a, + }), + }; result[@enumToInt(Feature.a76)] = .{ .llvm_name = "a76", .description = "Cortex-A76 ARM processors", @@ -179,6 +206,110 @@ pub const all_features = blk: { .description = "Enable v8.4-A Activity Monitors extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.apple_a10)] = .{ + .llvm_name = "apple-a10", + .description = "Apple A10", + .dependencies = featureSet(&[_]Feature{ + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .crc, + .crypto, + .disable_latency_sched_heuristic, + .fp_armv8, + .fuse_aes, + .fuse_crypto_eor, + .lor, + .neon, + .pan, + .perfmon, + .rdm, + .vh, + .zcm, + .zcz, + }), + }; + result[@enumToInt(Feature.apple_a11)] = .{ + .llvm_name = "apple-a11", + .description = "Apple A11", + .dependencies = featureSet(&[_]Feature{ + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .crypto, + .disable_latency_sched_heuristic, + .fp_armv8, + .fullfp16, + .fuse_aes, + .fuse_crypto_eor, + .neon, + .perfmon, + .v8_2a, + .zcm, + .zcz, + }), + }; + result[@enumToInt(Feature.apple_a12)] = .{ + .llvm_name = "apple-a12", + .description = "Apple A12", + .dependencies = featureSet(&[_]Feature{ + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .crypto, + .disable_latency_sched_heuristic, + .fp_armv8, + .fullfp16, + .fuse_aes, + .fuse_crypto_eor, + .neon, + .perfmon, + .v8_3a, + .zcm, + .zcz, + }), + }; + result[@enumToInt(Feature.apple_a13)] = .{ + .llvm_name = "apple-a13", + .description = "Apple A13", + .dependencies = featureSet(&[_]Feature{ + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .crypto, + .disable_latency_sched_heuristic, + .fp_armv8, + .fp16fml, + .fullfp16, + .fuse_aes, + .fuse_crypto_eor, + .neon, + .perfmon, + .sha3, + .v8_4a, + .zcm, + .zcz, + }), + }; + result[@enumToInt(Feature.apple_a7)] = .{ + .llvm_name = "apple-a7", + .description = "Apple A7 (the CPU formerly known as Cyclone)", + .dependencies = featureSet(&[_]Feature{ + .alternate_sextload_cvt_f32_pattern, + .arith_bcc_fusion, + .arith_cbz_fusion, + .crypto, + .disable_latency_sched_heuristic, + .fp_armv8, + .fuse_aes, + .fuse_crypto_eor, + .neon, + .perfmon, + .zcm, + .zcz, + .zcz_fp_workaround, + }), + }; result[@enumToInt(Feature.arith_bcc_fusion)] = .{ .llvm_name = "arith-bcc-fusion", .description = "CPU fuses arithmetic+bcc operations", @@ -285,24 +416,6 @@ pub const all_features = blk: { .description = "Use custom handling of cheap instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.cyclone)] = .{ - .llvm_name = "cyclone", - .description = "Cyclone", - .dependencies = featureSet(&[_]Feature{ - .alternate_sextload_cvt_f32_pattern, - .arith_bcc_fusion, - .arith_cbz_fusion, - .crypto, - .disable_latency_sched_heuristic, - .fuse_aes, - .fuse_crypto_eor, - .perfmon, - .v8a, - .zcm, - .zcz, - .zcz_fp_workaround, - }), - }; result[@enumToInt(Feature.disable_latency_sched_heuristic)] = .{ .llvm_name = "disable-latency-sched-heuristic", .description = "Disable latency scheduling heuristic", @@ -318,6 +431,13 @@ pub const all_features = blk: { .description = "Enable dot product support", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.ete)] = .{ + .llvm_name = "ete", + .description = "Enable Embedded Trace Extension", + .dependencies = featureSet(&[_]Feature{ + .trbe, + }), + }; result[@enumToInt(Feature.exynos_cheap_as_move)] = .{ .llvm_name = "exynos-cheap-as-move", .description = "Use Exynos specific handling of cheap instructions", @@ -451,6 +571,35 @@ pub const all_features = blk: { .fp_armv8, }), }; + result[@enumToInt(Feature.neoversee1)] = .{ + .llvm_name = "neoversee1", + .description = "Neoverse E1 ARM processors", + .dependencies = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .neon, + .rcpc, + .ssbs, + .v8_2a, + }), + }; + result[@enumToInt(Feature.neoversen1)] = .{ + .llvm_name = "neoversen1", + .description = "Neoverse N1 ARM processors", + .dependencies = featureSet(&[_]Feature{ + .crypto, + .dotprod, + .fp_armv8, + .fullfp16, + .neon, + .rcpc, + .spe, + .ssbs, + .v8_2a, + }), + }; result[@enumToInt(Feature.no_neg_immediates)] = .{ .llvm_name = "no-neg-immediates", .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", @@ -483,6 +632,11 @@ pub const all_features = blk: { .description = "Enable ARMv8 PMUv3 Performance Monitors extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.pmu)] = .{ + .llvm_name = "pmu", + .description = "Enable v8.4-A PMU extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.predictable_select_expensive)] = .{ .llvm_name = "predictable-select-expensive", .description = "Prefer likely predicted branches over selects", @@ -757,11 +911,21 @@ pub const all_features = blk: { .sve2, }), }; + result[@enumToInt(Feature.tagged_globals)] = .{ + .llvm_name = "tagged-globals", + .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.tlb_rmi)] = .{ .llvm_name = "tlb-rmi", .description = "Enable v8.4-A TLB Range and Maintenance Instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.tme)] = .{ + .llvm_name = "tme", + .description = "Enable Transactional Memory Extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.tpidr_el1)] = .{ .llvm_name = "tpidr-el1", .description = "Permit use of TPIDR_EL1 for the TLS base", @@ -782,6 +946,11 @@ pub const all_features = blk: { .description = "Enable v8.4-A Trace extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.trbe)] = .{ + .llvm_name = "trbe", + .description = "Enable Trace Buffer Extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.uaops)] = .{ .llvm_name = "uaops", .description = "Enable v8.2 UAO PState", @@ -856,6 +1025,7 @@ pub const all_features = blk: { .fmi, .mpam, .nv, + .pmu, .rasv8_4, .rcpc_immo, .sel2, @@ -921,11 +1091,74 @@ pub const all_features = blk: { }; pub const cpu = struct { + pub const apple_a10 = CpuModel{ + .name = "apple_a10", + .llvm_name = "apple-a10", + .features = featureSet(&[_]Feature{ + .apple_a10, + }), + }; + pub const apple_a11 = CpuModel{ + .name = "apple_a11", + .llvm_name = "apple-a11", + .features = featureSet(&[_]Feature{ + .apple_a11, + }), + }; + pub const apple_a12 = CpuModel{ + .name = "apple_a12", + .llvm_name = "apple-a12", + .features = featureSet(&[_]Feature{ + .apple_a12, + }), + }; + pub const apple_a13 = CpuModel{ + .name = "apple_a13", + .llvm_name = "apple-a13", + .features = featureSet(&[_]Feature{ + .apple_a13, + }), + }; + pub const apple_a7 = CpuModel{ + .name = "apple_a7", + .llvm_name = "apple-a7", + .features = featureSet(&[_]Feature{ + .apple_a7, + }), + }; + pub const apple_a8 = CpuModel{ + .name = "apple_a8", + .llvm_name = "apple-a8", + .features = featureSet(&[_]Feature{ + .apple_a7, + }), + }; + pub const apple_a9 = CpuModel{ + .name = "apple_a9", + .llvm_name = "apple-a9", + .features = featureSet(&[_]Feature{ + .apple_a7, + }), + }; pub const apple_latest = CpuModel{ .name = "apple_latest", .llvm_name = "apple-latest", .features = featureSet(&[_]Feature{ - .cyclone, + .apple_a13, + }), + }; + pub const apple_s4 = CpuModel{ + .name = "apple_s4", + .llvm_name = "apple-s4", + .features = featureSet(&[_]Feature{ + .apple_a12, + }), + }; + pub const apple_s5 = CpuModel{ + .name = "apple_s5", + .llvm_name = "apple-s5", + .features = featureSet(&[_]Feature{ + .apple_a12, }), }; pub const cortex_a35 = CpuModel{ @@ -982,6 +1215,20 @@ pub const cpu = struct { .v8a, }), }; + pub const cortex_a65 = CpuModel{ + .name = "cortex_a65", + .llvm_name = "cortex-a65", + .features = featureSet(&[_]Feature{ + .a65, + }), + }; + pub const cortex_a65ae = CpuModel{ + .name = "cortex_a65ae", + .llvm_name = "cortex-a65ae", + .features = featureSet(&[_]Feature{ + .a65, + }), + }; pub const cortex_a72 = CpuModel{ .name = "cortex_a72", .llvm_name = "cortex-a72", @@ -1035,12 +1282,12 @@ pub const cpu = struct { .name = "cyclone", .llvm_name = "cyclone", .features = featureSet(&[_]Feature{ - .cyclone, + .apple_a7, }), }; pub const exynos_m1 = CpuModel{ .name = "exynos_m1", - .llvm_name = "exynos-m1", + .llvm_name = null, .features = featureSet(&[_]Feature{ .crc, .crypto, @@ -1058,7 +1305,7 @@ pub const cpu = struct { }; pub const exynos_m2 = CpuModel{ .name = "exynos_m2", - .llvm_name = "exynos-m2", + .llvm_name = null, .features = featureSet(&[_]Feature{ .crc, .crypto, @@ -1128,6 +1375,7 @@ pub const cpu = struct { .name = "generic", .llvm_name = "generic", .features = featureSet(&[_]Feature{ + .ete, .fuse_aes, .perfmon, .use_postra_scheduler, @@ -1149,6 +1397,20 @@ pub const cpu = struct { .v8a, }), }; + pub const neoverse_e1 = CpuModel{ + .name = "neoverse_e1", + .llvm_name = "neoverse-e1", + .features = featureSet(&[_]Feature{ + .neoversee1, + }), + }; + pub const neoverse_n1 = CpuModel{ + .name = "neoverse_n1", + .llvm_name = "neoverse-n1", + .features = featureSet(&[_]Feature{ + .neoversen1, + }), + }; pub const saphira = CpuModel{ .name = "saphira", .llvm_name = "saphira", @@ -1248,11 +1510,22 @@ pub const cpu = struct { /// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1 /// compiler has inefficient memory and CPU usage, affecting build times. pub const all_cpus = &[_]*const CpuModel{ + &cpu.apple_a10, + &cpu.apple_a11, + &cpu.apple_a12, + &cpu.apple_a13, + &cpu.apple_a7, + &cpu.apple_a8, + &cpu.apple_a9, &cpu.apple_latest, + &cpu.apple_s4, + &cpu.apple_s5, &cpu.cortex_a35, &cpu.cortex_a53, &cpu.cortex_a55, &cpu.cortex_a57, + &cpu.cortex_a65, + &cpu.cortex_a65ae, &cpu.cortex_a72, &cpu.cortex_a73, &cpu.cortex_a75, @@ -1267,6 +1540,8 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.falkor, &cpu.generic, &cpu.kryo, + &cpu.neoverse_e1, + &cpu.neoverse_n1, &cpu.saphira, &cpu.thunderx, &cpu.thunderx2t99, diff --git a/lib/std/target/amdgpu.zig b/lib/std/target/amdgpu.zig index e524dc12a2..962e3073cf 100644 --- a/lib/std/target/amdgpu.zig +++ b/lib/std/target/amdgpu.zig @@ -63,6 +63,7 @@ pub const Feature = enum { max_private_element_size_16, max_private_element_size_4, max_private_element_size_8, + mfma_inline_literal_bug, mimg_r128, movrel, no_data_dep_hazard, @@ -491,6 +492,11 @@ pub const all_features = blk: { .description = "Maximum private access size may be 8", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.mfma_inline_literal_bug)] = .{ + .llvm_name = "mfma-inline-literal-bug", + .description = "MFMA cannot use inline literal as SrcC", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.mimg_r128)] = .{ .llvm_name = "mimg-r128", .description = "Support 128-bit texture resources", @@ -1103,6 +1109,7 @@ pub const cpu = struct { .half_rate_64_ops, .ldsbankcount32, .mai_insts, + .mfma_inline_literal_bug, .pk_fmac_f16_inst, .sram_ecc, }), diff --git a/lib/std/target/arm.zig b/lib/std/target/arm.zig index acb8318bde..23a45851ec 100644 --- a/lib/std/target/arm.zig +++ b/lib/std/target/arm.zig @@ -69,6 +69,9 @@ pub const Feature = enum { muxed_units, mve, mve_fp, + mve1beat, + mve2beat, + mve4beat, nacl_trap, neon, neon_fpmovs, @@ -95,6 +98,7 @@ pub const Feature = enum { slow_odd_reg, slow_vdup32, slow_vgetlni32, + slowfpvfmx, slowfpvmlx, soft_float, splat_vfp_neon, @@ -103,7 +107,6 @@ pub const Feature = enum { thumb2, thumb_mode, trustzone, - use_aa, use_misched, v2, v2a, @@ -139,8 +142,6 @@ pub const Feature = enum { v8_4a, v8_5a, vfp2, - vfp2d16, - vfp2d16sp, vfp2sp, vfp3, vfp3d16, @@ -290,9 +291,9 @@ pub const all_features = blk: { .slow_fp_brcc, .slow_vdup32, .slow_vgetlni32, + .slowfpvfmx, .slowfpvmlx, .splat_vfp_neon, - .use_aa, .wide_stride_vfp, .zcz, }), @@ -599,6 +600,21 @@ pub const all_features = blk: { .mve, }), }; + result[@enumToInt(Feature.mve1beat)] = .{ + .llvm_name = "mve1beat", + .description = "Model MVE instructions as a 1 beat per tick architecture", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.mve2beat)] = .{ + .llvm_name = "mve2beat", + .description = "Model MVE instructions as a 2 beats per tick architecture", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.mve4beat)] = .{ + .llvm_name = "mve4beat", + .description = "Model MVE instructions as a 4 beats per tick architecture", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.nacl_trap)] = .{ .llvm_name = "nacl-trap", .description = "NaCl trap", @@ -733,6 +749,11 @@ pub const all_features = blk: { .description = "Has slow VGETLNi32 - prefer VMOV", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.slowfpvfmx)] = .{ + .llvm_name = "slowfpvfmx", + .description = "Disable VFP / NEON FMA instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.slowfpvmlx)] = .{ .llvm_name = "slowfpvmlx", .description = "Disable VFP / NEON MAC instructions", @@ -775,11 +796,6 @@ pub const all_features = blk: { .description = "Enable support for TrustZone security extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.use_aa)] = .{ - .llvm_name = "use-aa", - .description = "Use alias analysis during codegen", - .dependencies = featureSet(&[_]Feature{}), - }; result[@enumToInt(Feature.use_misched)] = .{ .llvm_name = "use-misched", .description = "Use the MachineScheduler", @@ -1151,30 +1167,15 @@ pub const all_features = blk: { .llvm_name = "vfp2", .description = "Enable VFP2 instructions", .dependencies = featureSet(&[_]Feature{ - .vfp2d16, - .vfp2sp, - }), - }; - result[@enumToInt(Feature.vfp2d16)] = .{ - .llvm_name = "vfp2d16", - .description = "Enable VFP2 instructions", - .dependencies = featureSet(&[_]Feature{ .fp64, - .vfp2d16sp, - }), - }; - result[@enumToInt(Feature.vfp2d16sp)] = .{ - .llvm_name = "vfp2d16sp", - .description = "Enable VFP2 instructions with no double precision", - .dependencies = featureSet(&[_]Feature{ - .fpregs, + .vfp2sp, }), }; result[@enumToInt(Feature.vfp2sp)] = .{ .llvm_name = "vfp2sp", .description = "Enable VFP2 instructions with no double precision", .dependencies = featureSet(&[_]Feature{ - .vfp2d16sp, + .fpregs, }), }; result[@enumToInt(Feature.vfp3)] = .{ @@ -1587,6 +1588,7 @@ pub const cpu = struct { .mp, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .trustzone, .vfp4, @@ -1637,6 +1639,7 @@ pub const cpu = struct { .mp, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .trustzone, .vfp4, @@ -1713,6 +1716,7 @@ pub const cpu = struct { .nonpipelined_vfp, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .trustzone, .vmlx_forwarding, @@ -1775,7 +1779,6 @@ pub const cpu = struct { .loop_align, .m3, .no_branch_predictor, - .use_aa, .use_misched, }), }; @@ -1788,8 +1791,8 @@ pub const cpu = struct { .fp_armv8d16sp, .loop_align, .no_branch_predictor, + .slowfpvfmx, .slowfpvmlx, - .use_aa, .use_misched, }), }; @@ -1802,8 +1805,8 @@ pub const cpu = struct { .fp_armv8d16sp, .loop_align, .no_branch_predictor, + .slowfpvfmx, .slowfpvmlx, - .use_aa, .use_misched, }), }; @@ -1814,8 +1817,8 @@ pub const cpu = struct { .v7em, .loop_align, .no_branch_predictor, + .slowfpvfmx, .slowfpvmlx, - .use_aa, .use_misched, .vfp4d16sp, }), @@ -1847,6 +1850,7 @@ pub const cpu = struct { .r4, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .vfp3d16, }), @@ -1860,6 +1864,7 @@ pub const cpu = struct { .hwdiv_arm, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .vfp3d16, }), @@ -1870,7 +1875,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .v8r, .fpao, - .use_aa, .use_misched, }), }; @@ -1885,6 +1889,7 @@ pub const cpu = struct { .mp, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .vfp3d16, }), @@ -1900,6 +1905,7 @@ pub const cpu = struct { .mp, .ret_addr_stack, .slow_fp_brcc, + .slowfpvfmx, .slowfpvmlx, .vfp3d16, }), @@ -1918,6 +1924,7 @@ pub const cpu = struct { .mp, .neonfp, .ret_addr_stack, + .slowfpvfmx, .slowfpvmlx, .swift, .use_misched, @@ -1934,7 +1941,7 @@ pub const cpu = struct { }; pub const exynos_m1 = CpuModel{ .name = "exynos_m1", - .llvm_name = "exynos-m1", + .llvm_name = null, .features = featureSet(&[_]Feature{ .v8a, .exynos, @@ -1942,7 +1949,7 @@ pub const cpu = struct { }; pub const exynos_m2 = CpuModel{ .name = "exynos_m2", - .llvm_name = "exynos-m2", + .llvm_name = null, .features = featureSet(&[_]Feature{ .v8a, .exynos, @@ -2031,6 +2038,18 @@ pub const cpu = struct { .v6k, }), }; + pub const neoverse_n1 = CpuModel{ + .name = "neoverse_n1", + .llvm_name = "neoverse-n1", + .features = featureSet(&[_]Feature{ + .v8_2a, + .crc, + .crypto, + .dotprod, + .hwdiv, + .hwdiv_arm, + }), + }; pub const sc000 = CpuModel{ .name = "sc000", .llvm_name = "sc000", @@ -2045,7 +2064,6 @@ pub const cpu = struct { .v7m, .m3, .no_branch_predictor, - .use_aa, .use_misched, }), }; @@ -2096,6 +2114,7 @@ pub const cpu = struct { .slow_odd_reg, .slow_vdup32, .slow_vgetlni32, + .slowfpvfmx, .slowfpvmlx, .swift, .use_misched, @@ -2191,6 +2210,7 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.kryo, &cpu.mpcore, &cpu.mpcorenovfp, + &cpu.neoverse_n1, &cpu.sc000, &cpu.sc300, &cpu.strongarm, diff --git a/lib/std/target/mips.zig b/lib/std/target/mips.zig index 6ea7f665f0..21211ae20e 100644 --- a/lib/std/target/mips.zig +++ b/lib/std/target/mips.zig @@ -5,6 +5,7 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { abs2008, cnmips, + cnmipsp, crc, dsp, dspr2, @@ -52,6 +53,7 @@ pub const Feature = enum { use_tcc_in_div, vfpu, virt, + xgot, }; pub usingnamespace CpuFeature.feature_set_fns(Feature); @@ -72,6 +74,13 @@ pub const all_features = blk: { .mips64r2, }), }; + result[@enumToInt(Feature.cnmipsp)] = .{ + .llvm_name = "cnmipsp", + .description = "Octeon+ cnMIPS Support", + .dependencies = featureSet(&[_]Feature{ + .cnmips, + }), + }; result[@enumToInt(Feature.crc)] = .{ .llvm_name = "crc", .description = "Mips R6 CRC ASE", @@ -364,6 +373,11 @@ pub const all_features = blk: { .description = "Mips Virtualization ASE", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.xgot)] = .{ + .llvm_name = "xgot", + .description = "Assume 32-bit GOT", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; @@ -373,6 +387,13 @@ pub const all_features = blk: { }; pub const cpu = struct { + pub const generic = CpuModel{ + .name = "generic", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .mips32, + }), + }; pub const mips1 = CpuModel{ .name = "mips1", .llvm_name = "mips1", @@ -486,6 +507,15 @@ pub const cpu = struct { .mips64r2, }), }; + pub const @"octeon+" = CpuModel{ + .name = "octeon+", + .llvm_name = "octeon+", + .features = featureSet(&[_]Feature{ + .cnmips, + .cnmipsp, + .mips64r2, + }), + }; pub const p5600 = CpuModel{ .name = "p5600", .llvm_name = "p5600", @@ -499,6 +529,7 @@ pub const cpu = struct { /// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1 /// compiler has inefficient memory and CPU usage, affecting build times. pub const all_cpus = &[_]*const CpuModel{ + &cpu.generic, &cpu.mips1, &cpu.mips2, &cpu.mips3, @@ -515,5 +546,6 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.mips64r5, &cpu.mips64r6, &cpu.octeon, + &cpu.@"octeon+", &cpu.p5600, }; diff --git a/lib/std/target/powerpc.zig b/lib/std/target/powerpc.zig index ae3371e066..c06b82f02a 100644 --- a/lib/std/target/powerpc.zig +++ b/lib/std/target/powerpc.zig @@ -5,6 +5,7 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"64bit", @"64bitregs", + allow_unaligned_fp_access, altivec, booke, bpermd, @@ -72,6 +73,11 @@ pub const all_features = blk: { .description = "Enable 64-bit registers usage for ppc32 [beta]", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.allow_unaligned_fp_access)] = .{ + .llvm_name = "allow-unaligned-fp-access", + .description = "CPU does not trap on unaligned FP access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.altivec)] = .{ .llvm_name = "altivec", .description = "Enable Altivec instructions", @@ -561,6 +567,7 @@ pub const cpu = struct { .booke, .icbt, .isel, + .spe, }), }; pub const e500mc = CpuModel{ @@ -585,6 +592,45 @@ pub const cpu = struct { .stfiwx, }), }; + pub const future = CpuModel{ + .name = "future", + .llvm_name = "future", + .features = featureSet(&[_]Feature{ + .@"64bit", + .allow_unaligned_fp_access, + .altivec, + .bpermd, + .cmpb, + .crypto, + .direct_move, + .extdiv, + .fcpsgn, + .fpcvt, + .fprnd, + .fre, + .fres, + .frsqrte, + .frsqrtes, + .fsqrt, + .htm, + .icbt, + .isa_v30_instructions, + .isel, + .ldbrx, + .lfiwax, + .mfocrf, + .partword_atomics, + .popcntd, + .power8_altivec, + .power8_vector, + .power9_altivec, + .power9_vector, + .recipprec, + .stfiwx, + .two_const_nr, + .vsx, + }), + }; pub const g3 = CpuModel{ .name = "g3", .llvm_name = "g3", @@ -663,6 +709,7 @@ pub const cpu = struct { .llvm_name = "ppc64le", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -794,6 +841,7 @@ pub const cpu = struct { .llvm_name = "pwr7", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -822,6 +870,7 @@ pub const cpu = struct { .llvm_name = "pwr8", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -857,6 +906,7 @@ pub const cpu = struct { .llvm_name = "pwr9", .features = featureSet(&[_]Feature{ .@"64bit", + .allow_unaligned_fp_access, .altivec, .bpermd, .cmpb, @@ -918,6 +968,7 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.e500, &cpu.e500mc, &cpu.e5500, + &cpu.future, &cpu.g3, &cpu.g4, &cpu.@"g4+", diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig index a799c29df6..ff8921eaf2 100644 --- a/lib/std/target/riscv.zig +++ b/lib/std/target/riscv.zig @@ -11,6 +11,38 @@ pub const Feature = enum { f, m, relax, + reserve_x1, + reserve_x10, + reserve_x11, + reserve_x12, + reserve_x13, + reserve_x14, + reserve_x15, + reserve_x16, + reserve_x17, + reserve_x18, + reserve_x19, + reserve_x2, + reserve_x20, + reserve_x21, + reserve_x22, + reserve_x23, + reserve_x24, + reserve_x25, + reserve_x26, + reserve_x27, + reserve_x28, + reserve_x29, + reserve_x3, + reserve_x30, + reserve_x31, + reserve_x4, + reserve_x5, + reserve_x6, + reserve_x7, + reserve_x8, + reserve_x9, + rvc_hints, }; pub usingnamespace CpuFeature.feature_set_fns(Feature); @@ -61,6 +93,166 @@ pub const all_features = blk: { .description = "Enable Linker relaxation.", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.reserve_x1)] = .{ + .llvm_name = "reserve-x1", + .description = "Reserve X1", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x10)] = .{ + .llvm_name = "reserve-x10", + .description = "Reserve X10", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x11)] = .{ + .llvm_name = "reserve-x11", + .description = "Reserve X11", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x12)] = .{ + .llvm_name = "reserve-x12", + .description = "Reserve X12", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x13)] = .{ + .llvm_name = "reserve-x13", + .description = "Reserve X13", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x14)] = .{ + .llvm_name = "reserve-x14", + .description = "Reserve X14", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x15)] = .{ + .llvm_name = "reserve-x15", + .description = "Reserve X15", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x16)] = .{ + .llvm_name = "reserve-x16", + .description = "Reserve X16", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x17)] = .{ + .llvm_name = "reserve-x17", + .description = "Reserve X17", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x18)] = .{ + .llvm_name = "reserve-x18", + .description = "Reserve X18", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x19)] = .{ + .llvm_name = "reserve-x19", + .description = "Reserve X19", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x2)] = .{ + .llvm_name = "reserve-x2", + .description = "Reserve X2", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x20)] = .{ + .llvm_name = "reserve-x20", + .description = "Reserve X20", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x21)] = .{ + .llvm_name = "reserve-x21", + .description = "Reserve X21", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x22)] = .{ + .llvm_name = "reserve-x22", + .description = "Reserve X22", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x23)] = .{ + .llvm_name = "reserve-x23", + .description = "Reserve X23", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x24)] = .{ + .llvm_name = "reserve-x24", + .description = "Reserve X24", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x25)] = .{ + .llvm_name = "reserve-x25", + .description = "Reserve X25", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x26)] = .{ + .llvm_name = "reserve-x26", + .description = "Reserve X26", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x27)] = .{ + .llvm_name = "reserve-x27", + .description = "Reserve X27", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x28)] = .{ + .llvm_name = "reserve-x28", + .description = "Reserve X28", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x29)] = .{ + .llvm_name = "reserve-x29", + .description = "Reserve X29", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x3)] = .{ + .llvm_name = "reserve-x3", + .description = "Reserve X3", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x30)] = .{ + .llvm_name = "reserve-x30", + .description = "Reserve X30", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x31)] = .{ + .llvm_name = "reserve-x31", + .description = "Reserve X31", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x4)] = .{ + .llvm_name = "reserve-x4", + .description = "Reserve X4", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x5)] = .{ + .llvm_name = "reserve-x5", + .description = "Reserve X5", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x6)] = .{ + .llvm_name = "reserve-x6", + .description = "Reserve X6", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x7)] = .{ + .llvm_name = "reserve-x7", + .description = "Reserve X7", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x8)] = .{ + .llvm_name = "reserve-x8", + .description = "Reserve X8", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.reserve_x9)] = .{ + .llvm_name = "reserve-x9", + .description = "Reserve X9", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.rvc_hints)] = .{ + .llvm_name = "rvc-hints", + .description = "Enable RVC Hint Instructions.", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (result) |*elem, i| { elem.index = i; @@ -72,7 +264,7 @@ pub const all_features = blk: { pub const cpu = struct { pub const baseline_rv32 = CpuModel{ .name = "baseline_rv32", - .llvm_name = "generic-rv32", + .llvm_name = null, .features = featureSet(&[_]Feature{ .a, .c, @@ -84,7 +276,7 @@ pub const cpu = struct { pub const baseline_rv64 = CpuModel{ .name = "baseline_rv64", - .llvm_name = "generic-rv64", + .llvm_name = null, .features = featureSet(&[_]Feature{ .@"64bit", .a, @@ -97,15 +289,17 @@ pub const cpu = struct { pub const generic_rv32 = CpuModel{ .name = "generic_rv32", - .llvm_name = "generic-rv32", - .features = featureSet(&[_]Feature{}), + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .rvc_hints, + }), }; - pub const generic_rv64 = CpuModel{ .name = "generic_rv64", - .llvm_name = "generic-rv64", + .llvm_name = null, .features = featureSet(&[_]Feature{ .@"64bit", + .rvc_hints, }), }; }; diff --git a/lib/std/target/systemz.zig b/lib/std/target/systemz.zig index 798ecf5630..453ce8887f 100644 --- a/lib/std/target/systemz.zig +++ b/lib/std/target/systemz.zig @@ -451,6 +451,47 @@ pub const cpu = struct { .vector_packed_decimal, }), }; + pub const z15 = CpuModel{ + .name = "z15", + .llvm_name = "z15", + .features = featureSet(&[_]Feature{ + .deflate_conversion, + .dfp_packed_conversion, + .dfp_zoned_conversion, + .distinct_ops, + .enhanced_dat_2, + .enhanced_sort, + .execution_hint, + .fast_serialization, + .fp_extension, + .guarded_storage, + .high_word, + .insert_reference_bits_multiple, + .interlocked_access1, + .load_and_trap, + .load_and_zero_rightmost_byte, + .load_store_on_cond, + .load_store_on_cond_2, + .message_security_assist_extension3, + .message_security_assist_extension4, + .message_security_assist_extension5, + .message_security_assist_extension7, + .message_security_assist_extension8, + .message_security_assist_extension9, + .miscellaneous_extensions, + .miscellaneous_extensions_2, + .miscellaneous_extensions_3, + .population_count, + .processor_assist, + .reset_reference_bits_multiple, + .transactional_execution, + .vector, + .vector_enhancements_1, + .vector_enhancements_2, + .vector_packed_decimal, + .vector_packed_decimal_enhancement, + }), + }; pub const z196 = CpuModel{ .name = "z196", .llvm_name = "z196", @@ -506,6 +547,7 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.z10, &cpu.z13, &cpu.z14, + &cpu.z15, &cpu.z196, &cpu.zEC12, }; diff --git a/lib/std/target/x86.zig b/lib/std/target/x86.zig index 1e2ac409bd..5eccd61c7e 100644 --- a/lib/std/target/x86.zig +++ b/lib/std/target/x86.zig @@ -46,7 +46,6 @@ pub const Feature = enum { fast_gather, fast_hops, fast_lzcnt, - fast_partial_ymm_or_zmm_write, fast_scalar_fsqrt, fast_scalar_shift_masks, fast_shld_rotate, @@ -79,7 +78,9 @@ pub const Feature = enum { pconfig, pku, popcnt, + prefer_128_bit, prefer_256_bit, + prefer_mask_registers, prefetchwt1, prfchw, ptwrite, @@ -114,8 +115,11 @@ pub const Feature = enum { sse4a, ssse3, tbm, + use_aa, + use_glm_div_sqrt_costs, vaes, vpclmulqdq, + vzeroupper, waitpkg, wbnoinvd, x87, @@ -386,20 +390,13 @@ pub const all_features = blk: { result[@enumToInt(Feature.fast_hops)] = .{ .llvm_name = "fast-hops", .description = "Prefer horizontal vector math instructions (haddp, phsub, etc.) over normal vector instructions with shuffles", - .dependencies = featureSet(&[_]Feature{ - .sse3, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.fast_lzcnt)] = .{ .llvm_name = "fast-lzcnt", .description = "LZCNT instructions are as fast as most simple integer ops", .dependencies = featureSet(&[_]Feature{}), }; - result[@enumToInt(Feature.fast_partial_ymm_or_zmm_write)] = .{ - .llvm_name = "fast-partial-ymm-or-zmm-write", - .description = "Partial writes to YMM/ZMM registers are fast", - .dependencies = featureSet(&[_]Feature{}), - }; result[@enumToInt(Feature.fast_scalar_fsqrt)] = .{ .llvm_name = "fast-scalar-fsqrt", .description = "Scalar SQRT is fast (disable Newton-Raphson)", @@ -529,7 +526,7 @@ pub const all_features = blk: { }; result[@enumToInt(Feature.mpx)] = .{ .llvm_name = "mpx", - .description = "Support MPX instructions", + .description = "Deprecated. Support MPX instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@enumToInt(Feature.mwaitx)] = .{ @@ -569,11 +566,21 @@ pub const all_features = blk: { .description = "Support POPCNT instruction", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.prefer_128_bit)] = .{ + .llvm_name = "prefer-128-bit", + .description = "Prefer 128-bit AVX instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.prefer_256_bit)] = .{ .llvm_name = "prefer-256-bit", .description = "Prefer 256-bit AVX instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.prefer_mask_registers)] = .{ + .llvm_name = "prefer-mask-registers", + .description = "Prefer AVX512 mask registers over PTEST/MOVMSK", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.prefetchwt1)] = .{ .llvm_name = "prefetchwt1", .description = "Prefetch with Intent to Write and T1 Hint", @@ -763,6 +770,16 @@ pub const all_features = blk: { .description = "Enable TBM instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@enumToInt(Feature.use_aa)] = .{ + .llvm_name = "use-aa", + .description = "Use alias analysis during codegen", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@enumToInt(Feature.use_glm_div_sqrt_costs)] = .{ + .llvm_name = "use-glm-div-sqrt-costs", + .description = "Use Goldmont specific floating point div/sqrt costs", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.vaes)] = .{ .llvm_name = "vaes", .description = "Promote selected AES instructions to AVX512/AVX registers", @@ -779,6 +796,11 @@ pub const all_features = blk: { .pclmul, }), }; + result[@enumToInt(Feature.vzeroupper)] = .{ + .llvm_name = "vzeroupper", + .description = "Should insert vzeroupper instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@enumToInt(Feature.waitpkg)] = .{ .llvm_name = "waitpkg", .description = "Wait and pause enhancements", @@ -847,6 +869,7 @@ pub const cpu = struct { .sahf, .slow_shld, .sse4a, + .vzeroupper, .x87, }), }; @@ -860,6 +883,7 @@ pub const cpu = struct { .nopl, .slow_shld, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -875,6 +899,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -892,6 +917,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -907,6 +933,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -920,6 +947,7 @@ pub const cpu = struct { .nopl, .slow_shld, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -935,6 +963,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -952,6 +981,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -970,6 +1000,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -994,6 +1025,7 @@ pub const cpu = struct { .slow_two_mem_ops, .slow_unaligned_mem_16, .ssse3, + .vzeroupper, .x87, }), }; @@ -1014,6 +1046,7 @@ pub const cpu = struct { .sahf, .slow_shld, .sse4a, + .vzeroupper, .x87, }), }; @@ -1039,6 +1072,7 @@ pub const cpu = struct { .prfchw, .sahf, .slow_shld, + .vzeroupper, .x87, .xop, .xsave, @@ -1071,6 +1105,7 @@ pub const cpu = struct { .sahf, .slow_shld, .tbm, + .vzeroupper, .x87, .xop, .xsave, @@ -1104,6 +1139,7 @@ pub const cpu = struct { .sahf, .slow_shld, .tbm, + .vzeroupper, .x87, .xop, .xsave, @@ -1141,6 +1177,7 @@ pub const cpu = struct { .sahf, .slow_shld, .tbm, + .vzeroupper, .x87, .xop, .xsave, @@ -1168,6 +1205,7 @@ pub const cpu = struct { .slow_two_mem_ops, .slow_unaligned_mem_16, .ssse3, + .vzeroupper, .x87, }), }; @@ -1210,6 +1248,7 @@ pub const cpu = struct { .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1236,6 +1275,7 @@ pub const cpu = struct { .slow_shld, .sse4a, .ssse3, + .vzeroupper, .x87, }), }; @@ -1255,7 +1295,6 @@ pub const cpu = struct { .fast_bextr, .fast_hops, .fast_lzcnt, - .fast_partial_ymm_or_zmm_write, .fast_scalar_shift_masks, .fast_vector_shift_masks, .fxsr, @@ -1281,6 +1320,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3dnow", .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1294,6 +1334,7 @@ pub const cpu = struct { .mmx, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -1336,11 +1377,11 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdrnd, .rdseed, @@ -1349,6 +1390,7 @@ pub const cpu = struct { .sha, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1396,17 +1438,18 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdrnd, .rdseed, .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1455,17 +1498,18 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdrnd, .rdseed, .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1500,6 +1544,7 @@ pub const cpu = struct { .slow_3ops_lea, .slow_unaligned_mem_32, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1541,6 +1586,7 @@ pub const cpu = struct { .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1561,6 +1607,7 @@ pub const cpu = struct { .sahf, .slow_unaligned_mem_16, .ssse3, + .vzeroupper, .x87, }), }; @@ -1579,6 +1626,7 @@ pub const cpu = struct { .popcnt, .sahf, .sse4_2, + .vzeroupper, .x87, }), }; @@ -1606,6 +1654,7 @@ pub const cpu = struct { .slow_3ops_lea, .slow_unaligned_mem_32, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1617,6 +1666,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1627,6 +1677,7 @@ pub const cpu = struct { .@"3dnowa", .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1645,7 +1696,6 @@ pub const cpu = struct { .fxsr, .mmx, .movbe, - .mpx, .nopl, .pclmul, .popcnt, @@ -1659,6 +1709,8 @@ pub const cpu = struct { .slow_two_mem_ops, .sse4_2, .ssse3, + .use_glm_div_sqrt_costs, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1680,7 +1732,6 @@ pub const cpu = struct { .fxsr, .mmx, .movbe, - .mpx, .nopl, .pclmul, .popcnt, @@ -1697,6 +1748,8 @@ pub const cpu = struct { .slow_two_mem_ops, .sse4_2, .ssse3, + .use_glm_div_sqrt_costs, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1740,6 +1793,7 @@ pub const cpu = struct { .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1750,6 +1804,7 @@ pub const cpu = struct { .llvm_name = "i386", .features = featureSet(&[_]Feature{ .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1758,6 +1813,7 @@ pub const cpu = struct { .llvm_name = "i486", .features = featureSet(&[_]Feature{ .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1767,6 +1823,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1777,6 +1834,7 @@ pub const cpu = struct { .cmov, .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1825,11 +1883,11 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdpid, .rdrnd, @@ -1841,6 +1899,7 @@ pub const cpu = struct { .sse4_2, .vaes, .vpclmulqdq, + .vzeroupper, .x87, .xsave, .xsavec, @@ -1893,12 +1952,12 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pconfig, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdpid, .rdrnd, @@ -1910,6 +1969,7 @@ pub const cpu = struct { .sse4_2, .vaes, .vpclmulqdq, + .vzeroupper, .wbnoinvd, .x87, .xsave, @@ -1945,6 +2005,7 @@ pub const cpu = struct { .slow_3ops_lea, .slow_unaligned_mem_32, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -1957,6 +2018,7 @@ pub const cpu = struct { .cx8, .mmx, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1967,6 +2029,7 @@ pub const cpu = struct { .@"3dnow", .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1977,6 +2040,7 @@ pub const cpu = struct { .@"3dnow", .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -1994,6 +2058,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -2012,6 +2077,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -2033,7 +2099,6 @@ pub const cpu = struct { .cx8, .f16c, .fast_gather, - .fast_partial_ymm_or_zmm_write, .fma, .fsgsbase, .fxsr, @@ -2044,6 +2109,7 @@ pub const cpu = struct { .nopl, .pclmul, .popcnt, + .prefer_mask_registers, .prefetchwt1, .prfchw, .rdrnd, @@ -2077,7 +2143,6 @@ pub const cpu = struct { .cx8, .f16c, .fast_gather, - .fast_partial_ymm_or_zmm_write, .fma, .fsgsbase, .fxsr, @@ -2088,6 +2153,7 @@ pub const cpu = struct { .nopl, .pclmul, .popcnt, + .prefer_mask_registers, .prefetchwt1, .prfchw, .rdrnd, @@ -2105,7 +2171,9 @@ pub const cpu = struct { pub const lakemont = CpuModel{ .name = "lakemont", .llvm_name = "lakemont", - .features = featureSet(&[_]Feature{}), + .features = featureSet(&[_]Feature{ + .vzeroupper, + }), }; pub const nehalem = CpuModel{ .name = "nehalem", @@ -2122,6 +2190,7 @@ pub const cpu = struct { .popcnt, .sahf, .sse4_2, + .vzeroupper, .x87, }), }; @@ -2138,6 +2207,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -2155,6 +2225,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -2173,6 +2244,7 @@ pub const cpu = struct { .slow_shld, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -2191,6 +2263,7 @@ pub const cpu = struct { .sahf, .slow_unaligned_mem_16, .sse4_1, + .vzeroupper, .x87, }), }; @@ -2200,6 +2273,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .cx8, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2214,6 +2288,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -2224,6 +2299,7 @@ pub const cpu = struct { .cx8, .mmx, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2237,6 +2313,7 @@ pub const cpu = struct { .mmx, .nopl, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2251,6 +2328,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -2265,6 +2343,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse, + .vzeroupper, .x87, }), }; @@ -2279,6 +2358,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -2293,6 +2373,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse2, + .vzeroupper, .x87, }), }; @@ -2304,6 +2385,7 @@ pub const cpu = struct { .cx8, .nopl, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2318,6 +2400,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -2345,6 +2428,7 @@ pub const cpu = struct { .slow_3ops_lea, .slow_unaligned_mem_32, .sse4_2, + .vzeroupper, .x87, .xsave, .xsaveopt, @@ -2375,6 +2459,7 @@ pub const cpu = struct { .slow_two_mem_ops, .sse4_2, .ssse3, + .vzeroupper, .x87, }), }; @@ -2417,17 +2502,18 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdrnd, .rdseed, .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -2468,7 +2554,6 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .popcnt, @@ -2479,6 +2564,7 @@ pub const cpu = struct { .sgx, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -2525,17 +2611,18 @@ pub const cpu = struct { .merge_to_threeway_branch, .mmx, .movbe, - .mpx, .nopl, .pclmul, .pku, .popcnt, + .prefer_256_bit, .prfchw, .rdrnd, .rdseed, .sahf, .slow_3ops_lea, .sse4_2, + .vzeroupper, .x87, .xsave, .xsavec, @@ -2568,7 +2655,81 @@ pub const cpu = struct { .slow_two_mem_ops, .sse4_2, .ssse3, + .vzeroupper, + .x87, + }), + }; + pub const tigerlake = CpuModel{ + .name = "tigerlake", + .llvm_name = "tigerlake", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .aes, + .avx, + .avx2, + .avx512bitalg, + .avx512bw, + .avx512cd, + .avx512dq, + .avx512f, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vl, + .avx512vnni, + .avx512vp2intersect, + .avx512vpopcntdq, + .bmi, + .bmi2, + .clflushopt, + .clwb, + .cmov, + .cx16, + .cx8, + .ermsb, + .f16c, + .fast_gather, + .fast_scalar_fsqrt, + .fast_shld_rotate, + .fast_variable_shuffle, + .fast_vector_fsqrt, + .fma, + .fsgsbase, + .fxsr, + .gfni, + .idivq_to_divl, + .invpcid, + .lzcnt, + .macrofusion, + .merge_to_threeway_branch, + .mmx, + .movbe, + .movdir64b, + .movdiri, + .nopl, + .pclmul, + .pku, + .popcnt, + .prefer_256_bit, + .prfchw, + .rdpid, + .rdrnd, + .rdseed, + .sahf, + .sgx, + .sha, + .shstk, + .slow_3ops_lea, + .sse4_2, + .vaes, + .vpclmulqdq, + .vzeroupper, .x87, + .xsave, + .xsavec, + .xsaveopt, + .xsaves, }), }; pub const tremont = CpuModel{ @@ -2589,7 +2750,6 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, - .mpx, .nopl, .pclmul, .popcnt, @@ -2606,6 +2766,8 @@ pub const cpu = struct { .slow_two_mem_ops, .sse4_2, .ssse3, + .use_glm_div_sqrt_costs, + .vzeroupper, .waitpkg, .x87, .xsave, @@ -2630,6 +2792,7 @@ pub const cpu = struct { .popcnt, .sahf, .sse4_2, + .vzeroupper, .x87, }), }; @@ -2639,6 +2802,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .mmx, .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2648,6 +2812,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"3dnow", .slow_unaligned_mem_16, + .vzeroupper, .x87, }), }; @@ -2665,6 +2830,7 @@ pub const cpu = struct { .slow_3ops_lea, .slow_incdec, .sse2, + .vzeroupper, .x87, }), }; @@ -2679,6 +2845,7 @@ pub const cpu = struct { .nopl, .slow_unaligned_mem_16, .sse3, + .vzeroupper, .x87, }), }; @@ -2719,6 +2886,7 @@ pub const cpu = struct { .sha, .slow_shld, .sse4a, + .vzeroupper, .x87, .xsave, .xsavec, @@ -2765,6 +2933,7 @@ pub const cpu = struct { .sha, .slow_shld, .sse4a, + .vzeroupper, .wbnoinvd, .x87, .xsave, @@ -2849,6 +3018,7 @@ pub const all_cpus = &[_]*const CpuModel{ &cpu.skylake, &cpu.skylake_avx512, &cpu.slm, + &cpu.tigerlake, &cpu.tremont, &cpu.westmere, &cpu.winchip_c6, diff --git a/lib/std/zig/ast.zig b/lib/std/zig/ast.zig index bc4f6350d6..1aa440fbc7 100644 --- a/lib/std/zig/ast.zig +++ b/lib/std/zig/ast.zig @@ -15,6 +15,9 @@ pub const Tree = struct { root_node: *Node.Root, arena_allocator: std.heap.ArenaAllocator, errors: ErrorList, + + /// translate-c uses this to avoid having to emit correct newlines + /// TODO get rid of this hack generated: bool = false, pub const TokenList = SegmentedList(Token, 64); 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