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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-28 01:00:12 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-30 06:36:41 +0200 |
| commit | 978555eea47a4d401e21735a01c806bbcf8a5199 (patch) | |
| tree | c17f8dc85a9d18cb41d73361ff49996cf063f0e7 /tools/update_cpu_features.zig | |
| parent | 2c0cc81e745ddcea072bce6895a3ba31523d73f8 (diff) | |
| download | zig-978555eea47a4d401e21735a01c806bbcf8a5199.tar.gz zig-978555eea47a4d401e21735a01c806bbcf8a5199.zip | |
std.Target.x86: purge avx10.n-256, rename avx10.n_512 to avx10.n, require evex512 for avx512f
Intel has abandoned AVX10.N/128,256; AVX10.N is now always 512-bit.
Diffstat (limited to 'tools/update_cpu_features.zig')
| -rw-r--r-- | tools/update_cpu_features.zig | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 09c665cfa3..b6e0d6495e 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -1229,6 +1229,27 @@ const targets = [_]ArchTarget{ .llvm_name = "64bit-mode", .omit = true, }, + // Remove these when LLVM removes AVX10.N-256 support. + .{ + .llvm_name = "avx10.1-256", + .flatten = true, + }, + .{ + .llvm_name = "avx10.2-256", + .flatten = true, + }, + .{ + .llvm_name = "avx10.1-512", + .zig_name = "avx10_1", + }, + .{ + .llvm_name = "avx10.2-512", + .zig_name = "avx10_2", + }, + .{ + .llvm_name = "avx512f", + .extra_deps = &.{"evex512"}, + }, .{ .llvm_name = "alderlake", .extra_deps = &.{ "smap", "smep" }, |