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| author | Timon Kruiper <timonkruiper@gmail.com> | 2020-04-01 20:42:43 +0200 |
|---|---|---|
| committer | Timon Kruiper <timonkruiper@gmail.com> | 2020-04-01 20:50:13 +0200 |
| commit | d33766e6c7289b79256b2e50d0dc2344729ff710 (patch) | |
| tree | 24da3981755618f82cfec5da88ebe5df791a708b /src/ir.cpp | |
| parent | ae6965a4e73cd5aad04e1c6831f48e7f0ecafc04 (diff) | |
| download | zig-d33766e6c7289b79256b2e50d0dc2344729ff710.tar.gz zig-d33766e6c7289b79256b2e50d0dc2344729ff710.zip | |
Make sure that ZigTypeVector and ZigTypeArray have the same memory layout
Throughout the stage1 code it is assumed that these have the same layout,
but that was not the case. This caused an issue on 32-bit hardware.
Diffstat (limited to 'src/ir.cpp')
| -rw-r--r-- | src/ir.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/ir.cpp b/src/ir.cpp index 215dac5946..41c4a3b58c 100644 --- a/src/ir.cpp +++ b/src/ir.cpp @@ -15953,7 +15953,7 @@ static IrInstGen *ir_analyze_bin_op_cmp_numeric(IrAnalyze *ira, IrInst *source_i if (op1->value->type->id == ZigTypeIdVector && op2->value->type->id == ZigTypeIdVector) { if (op1->value->type->data.vector.len != op2->value->type->data.vector.len) { ir_add_error(ira, source_instr, - buf_sprintf("vector length mismatch: %" PRIu32 " and %" PRIu32, + buf_sprintf("vector length mismatch: %" PRIu64 " and %" PRIu64, op1->value->type->data.vector.len, op2->value->type->data.vector.len)); return ira->codegen->invalid_inst_gen; } |