diff options
| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-02-22 12:23:53 +0100 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-02-24 06:07:05 +0100 |
| commit | 76558f8c6b8361ab520ea77e4b4cd2bfc8f688ad (patch) | |
| tree | d8731c7449e024527fd44a442e35477cd7d68aee /src/codegen | |
| parent | 68bd82d0cc9b0cd07cde509c1c89a438b6d297c9 (diff) | |
| download | zig-76558f8c6b8361ab520ea77e4b4cd2bfc8f688ad.tar.gz zig-76558f8c6b8361ab520ea77e4b4cd2bfc8f688ad.zip | |
llvm: Fix C ABI integer promotion for loongarch64.
It appears to just be a 1:1 copy of riscv64, including the super weird sign
extension quirk for u32.
Contributes to #21671.
Diffstat (limited to 'src/codegen')
| -rw-r--r-- | src/codegen/llvm.zig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index a6dbb08a42..fe68721665 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -12578,7 +12578,7 @@ fn ccAbiPromoteInt( else => null, }, else => switch (target.cpu.arch) { - .riscv64 => switch (int_info.bits) { + .loongarch64, .riscv64 => switch (int_info.bits) { 0...16 => int_info.signedness, 32 => .signed, // LLVM always signextends 32 bit ints, unsure if bug. 17...31, 33...63 => int_info.signedness, |