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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-06-30 07:01:35 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-07-01 18:16:40 +0200 |
| commit | 07114e6bc69106fb77beb879a8a2f78a4ba4b256 (patch) | |
| tree | a3d4833ac74c53c13520e5508140f68ed7ee8b4f /src/codegen | |
| parent | aa7b32d78189a66bb1fb62fd9735be5d15651d5b (diff) | |
| download | zig-07114e6bc69106fb77beb879a8a2f78a4ba4b256.tar.gz zig-07114e6bc69106fb77beb879a8a2f78a4ba4b256.zip | |
llvm: Disable the machine outliner pass on RISC-V
Diffstat (limited to 'src/codegen')
| -rw-r--r-- | src/codegen/llvm.zig | 3 | ||||
| -rw-r--r-- | src/codegen/llvm/bindings.zig | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index a48fb68352..a5e6d35fd6 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -1068,6 +1068,9 @@ pub const Object = struct { .full => .FullPreLink, }, .allow_fast_isel = true, + // LLVM's RISC-V backend for some reason enables the machine outliner by default even + // though it's clearly not ready and produces multiple miscompilations in our std tests. + .allow_machine_outliner = !comp.root_mod.resolved_target.result.cpu.arch.isRISCV(), .asm_filename = null, .bin_filename = options.bin_path, .llvm_ir_filename = options.post_ir_path, diff --git a/src/codegen/llvm/bindings.zig b/src/codegen/llvm/bindings.zig index 44ca599fdc..5d2d4c2a99 100644 --- a/src/codegen/llvm/bindings.zig +++ b/src/codegen/llvm/bindings.zig @@ -92,6 +92,7 @@ pub const TargetMachine = opaque { sancov: bool, lto: LtoPhase, allow_fast_isel: bool, + allow_machine_outliner: bool, asm_filename: ?[*:0]const u8, bin_filename: ?[*:0]const u8, llvm_ir_filename: ?[*:0]const u8, |