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authorAli Cheraghi <alichraghi@proton.me>2025-05-07 20:25:06 +0330
committerAli Cheraghi <alichraghi@proton.me>2025-05-21 13:01:20 +0330
commitdacd70fbe41d959bb7b48b5bad8612e74231524b (patch)
tree6370ef5fa121ecb9aa44cf64d3b6a11530c3d008 /src/codegen/spirv/Module.zig
parent0901328f12e7ea3d05dc1d5b4a588e595c4bc0bc (diff)
downloadzig-dacd70fbe41d959bb7b48b5bad8612e74231524b.tar.gz
zig-dacd70fbe41d959bb7b48b5bad8612e74231524b.zip
spirv: super basic composite int support
Diffstat (limited to 'src/codegen/spirv/Module.zig')
-rw-r--r--src/codegen/spirv/Module.zig7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/codegen/spirv/Module.zig b/src/codegen/spirv/Module.zig
index 16c32c26d5..920215bee1 100644
--- a/src/codegen/spirv/Module.zig
+++ b/src/codegen/spirv/Module.zig
@@ -369,8 +369,11 @@ pub fn finalize(self: *Module, a: Allocator) ![]Word {
// Emit memory model
const addressing_model: spec.AddressingModel = blk: {
if (self.hasFeature(.shader)) {
- assert(self.target.cpu.arch == .spirv64);
- if (self.hasFeature(.physical_storage_buffer)) break :blk .PhysicalStorageBuffer64;
+ if (self.hasFeature(.physical_storage_buffer)) {
+ assert(self.target.cpu.arch == .spirv64);
+ break :blk .PhysicalStorageBuffer64;
+ }
+ assert(self.target.cpu.arch == .spirv);
break :blk .Logical;
}