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authorAlex Rønne Petersen <alex@alexrp.com>2025-02-18 05:25:36 +0100
committerAlex Rønne Petersen <alex@alexrp.com>2025-06-05 06:12:00 +0200
commit9d534790ebc869ec933e932abe4be8b9e3593bbc (patch)
tree70652dde381fd0c0d536d8e7665e725e0924bb51 /src/codegen/spirv/Module.zig
parent14873f9a3434a0d753ca8438f389a7931956cf26 (diff)
downloadzig-9d534790ebc869ec933e932abe4be8b9e3593bbc.tar.gz
zig-9d534790ebc869ec933e932abe4be8b9e3593bbc.zip
std.Target: Introduce Cpu convenience functions for feature tests.
Before: * std.Target.arm.featureSetHas(target.cpu.features, .has_v7) * std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov }) * std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory }) After: * target.cpu.has(.arm, .has_v7) * target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov }) * target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
Diffstat (limited to 'src/codegen/spirv/Module.zig')
-rw-r--r--src/codegen/spirv/Module.zig14
1 files changed, 7 insertions, 7 deletions
diff --git a/src/codegen/spirv/Module.zig b/src/codegen/spirv/Module.zig
index 691749bf1d..20bf1b3670 100644
--- a/src/codegen/spirv/Module.zig
+++ b/src/codegen/spirv/Module.zig
@@ -190,12 +190,12 @@ entry_points: std.AutoArrayHashMapUnmanaged(IdRef, EntryPoint) = .empty,
pub fn init(gpa: Allocator, target: std.Target) Module {
const version_minor: u8 = blk: {
// Prefer higher versions
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_6)) break :blk 6;
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_5)) break :blk 5;
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_4)) break :blk 4;
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_3)) break :blk 3;
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_2)) break :blk 2;
- if (std.Target.spirv.featureSetHas(target.cpu.features, .v1_1)) break :blk 1;
+ if (target.cpu.has(.spirv, .v1_6)) break :blk 6;
+ if (target.cpu.has(.spirv, .v1_5)) break :blk 5;
+ if (target.cpu.has(.spirv, .v1_4)) break :blk 4;
+ if (target.cpu.has(.spirv, .v1_3)) break :blk 3;
+ if (target.cpu.has(.spirv, .v1_2)) break :blk 2;
+ if (target.cpu.has(.spirv, .v1_1)) break :blk 1;
break :blk 0;
};
@@ -268,7 +268,7 @@ pub fn idBound(self: Module) Word {
}
pub fn hasFeature(self: *Module, feature: std.Target.spirv.Feature) bool {
- return std.Target.spirv.featureSetHas(self.target.cpu.features, feature);
+ return self.target.cpu.has(.spirv, feature);
}
fn addEntryPointDeps(