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| author | Alex Rønne Petersen <alex@alexrp.com> | 2024-10-06 13:35:56 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-06 13:35:56 +0200 |
| commit | be5378b03805fa95b3cf36b6727d2c364c155e64 (patch) | |
| tree | e6571591425e1cf8e373a9663010de536b644148 /src/codegen/llvm.zig | |
| parent | 008bb1f1201a4b4987bf00de9daf46185aa9292d (diff) | |
| parent | 45644b7e152e851b9f9f51095e3ce1ca7fcc8a56 (diff) | |
| download | zig-be5378b03805fa95b3cf36b6727d2c364c155e64.tar.gz zig-be5378b03805fa95b3cf36b6727d2c364c155e64.zip | |
Merge pull request #21587 from alexrp/hexagon-porting
Some initial `hexagon-linux` port work
Diffstat (limited to 'src/codegen/llvm.zig')
| -rw-r--r-- | src/codegen/llvm.zig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 1190975238..1201c41486 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -12444,6 +12444,7 @@ fn backendSupportsF80(target: std.Target) bool { /// if it produces miscompilations. fn backendSupportsF16(target: std.Target) bool { return switch (target.cpu.arch) { + .hexagon, .powerpc, .powerpcle, .powerpc64, |