llvm: Implement sub-architecture translation in targetTriple().

1 files changed, 74 insertions, 4 deletions

diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 2cd1af783e..5ada6dbcd4 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -37,10 +37,20 @@ const compilerRtIntAbbrev = target_util.compilerRtIntAbbrev;
 
 const Error = error{ OutOfMemory, CodegenFail };
 
+fn subArchName(features: std.Target.Cpu.Feature.Set, arch: anytype, mappings: anytype) ?[]const u8 {
+    inline for (mappings) |mapping| {
+        if (arch.featureSetHas(features, mapping[0])) return mapping[1];
+    }
+
+    return null;
+}
+
 pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
     var llvm_triple = std.ArrayList(u8).init(allocator);
     defer llvm_triple.deinit();
 
+    const features = target.cpu.features;
+
     const llvm_arch = switch (target.cpu.arch) {
         .arm => "arm",
         .armeb => "armeb",
@@ -55,10 +65,11 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .loongarch32 => "loongarch32",
         .loongarch64 => "loongarch64",
         .m68k => "m68k",
-        .mips => "mips",
-        .mipsel => "mipsel",
-        .mips64 => "mips64",
-        .mips64el => "mips64el",
+        // MIPS sub-architectures are a bit irregular, so we handle them manually here.
+        .mips => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6" else "mips",
+        .mipsel => if (std.Target.mips.featureSetHas(features, .mips32r6)) "mipsisa32r6el" else "mipsel",
+        .mips64 => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6" else "mips64",
+        .mips64el => if (std.Target.mips.featureSetHas(features, .mips64r6)) "mipsisa64r6el" else "mips64el",
         .msp430 => "msp430",
         .powerpc => "powerpc",
         .powerpcle => "powerpcle",
@@ -90,8 +101,67 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .spu_2,
         => unreachable, // Gated by hasLlvmSupport().
     };
+
     try llvm_triple.appendSlice(llvm_arch);
 
+    const llvm_sub_arch: ?[]const u8 = switch (target.cpu.arch) {
+        .arm, .armeb, .thumb, .thumbeb => subArchName(features, std.Target.arm, .{
+            .{ .v4t, "v4t" },
+            .{ .v5t, "v5t" },
+            .{ .v5te, "v5te" },
+            .{ .v5tej, "v5tej" },
+            .{ .v6, "v6" },
+            .{ .v6k, "v6k" },
+            .{ .v6kz, "v6kz" },
+            .{ .v6m, "v6m" },
+            .{ .v6t2, "v6t2" },
+            // v7k and v7s imply v7a so they have to be tested first.
+            .{ .v7k, "v7k" },
+            .{ .v7s, "v7s" },
+            .{ .v7a, "v7a" },
+            .{ .v7em, "v7em" },
+            .{ .v7m, "v7m" },
+            .{ .v7r, "v7r" },
+            .{ .v7ve, "v7ve" },
+            .{ .v8a, "v8a" },
+            .{ .v8_1a, "v8.1a" },
+            .{ .v8_2a, "v8.2a" },
+            .{ .v8_3a, "v8.3a" },
+            .{ .v8_4a, "v8.4a" },
+            .{ .v8_5a, "v8.5a" },
+            .{ .v8_6a, "v8.6a" },
+            .{ .v8_7a, "v8.7a" },
+            .{ .v8_8a, "v8.8a" },
+            .{ .v8_9a, "v8.9a" },
+            .{ .v8m, "v8m.base" },
+            .{ .v8m_main, "v8m.main" },
+            .{ .v8_1m_main, "v8.1m.main" },
+            .{ .v8r, "v8r" },
+            .{ .v9a, "v9a" },
+            .{ .v9_1a, "v9.1a" },
+            .{ .v9_2a, "v9.2a" },
+            .{ .v9_3a, "v9.3a" },
+            .{ .v9_4a, "v9.4a" },
+            .{ .v9_5a, "v9.5a" },
+        }),
+        .powerpc => subArchName(features, std.Target.powerpc, .{
+            .{ .spe, "spe" },
+        }),
+        .spirv => subArchName(features, std.Target.spirv, .{
+            .{ .v1_5, "1.5" },
+        }),
+        .spirv32, .spirv64 => subArchName(features, std.Target.spirv, .{
+            .{ .v1_5, "1.5" },
+            .{ .v1_4, "1.4" },
+            .{ .v1_3, "1.3" },
+            .{ .v1_2, "1.2" },
+            .{ .v1_1, "1.1" },
+        }),
+        else => null,
+    };
+
+    if (llvm_sub_arch) |sub| try llvm_triple.appendSlice(sub);
+
     // Unlike CPU backends, GPU backends actually care about the vendor tag.
     try llvm_triple.appendSlice(switch (target.cpu.arch) {
         .amdgcn => if (target.os.tag == .mesa3d) "-mesa-" else "-amd-",