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| author | Andrew Kelley <andrew@ziglang.org> | 2023-05-03 16:07:36 -0700 |
|---|---|---|
| committer | Andrew Kelley <andrew@ziglang.org> | 2023-06-10 20:40:03 -0700 |
| commit | 4cd8a40b3b34d4e68853088dd637a9da9b6a8891 (patch) | |
| tree | 8fbf70325352d59010ddbeca2cde7ca8538b0703 /src/codegen/llvm.zig | |
| parent | aa1bb5517d57ae7540ce2c7a4315b2f242d1470c (diff) | |
| download | zig-4cd8a40b3b34d4e68853088dd637a9da9b6a8891.tar.gz zig-4cd8a40b3b34d4e68853088dd637a9da9b6a8891.zip | |
stage2: move float types to InternPool
Diffstat (limited to 'src/codegen/llvm.zig')
| -rw-r--r-- | src/codegen/llvm.zig | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 5bc06e4bfc..ce78b06f2e 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -10932,7 +10932,7 @@ const ParamTypeIterator = struct { .riscv32, .riscv64 => { it.zig_index += 1; it.llvm_index += 1; - if (ty.tag() == .f16) { + if (ty.ip_index == .f16_type) { return .as_u16; } switch (riscv_c_abi.classifyType(ty, mod)) { @@ -11264,10 +11264,10 @@ fn backendSupportsF128(target: std.Target) bool { /// LLVM does not support all relevant intrinsics for all targets, so we /// may need to manually generate a libc call fn intrinsicsAllowed(scalar_ty: Type, target: std.Target) bool { - return switch (scalar_ty.tag()) { - .f16 => backendSupportsF16(target), - .f80 => (target.c_type_bit_size(.longdouble) == 80) and backendSupportsF80(target), - .f128 => (target.c_type_bit_size(.longdouble) == 128) and backendSupportsF128(target), + return switch (scalar_ty.ip_index) { + .f16_type => backendSupportsF16(target), + .f80_type => (target.c_type_bit_size(.longdouble) == 80) and backendSupportsF80(target), + .f128_type => (target.c_type_bit_size(.longdouble) == 128) and backendSupportsF128(target), else => true, }; } |