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authorJakub Konka <kubkon@jakubkonka.com>2020-11-08 14:49:31 +0100
committerJakub Konka <kubkon@jakubkonka.com>2020-11-11 14:34:53 +0100
commit4ef6864a155cbb23edb5e5aaa5aa34fdd0e53b39 (patch)
treef7983ff2f79c02f5f0c665ad8e6ea186e7a5a698 /src/codegen.zig
parentd601b0f4eb025c753ca9f139480578511122afad (diff)
downloadzig-4ef6864a155cbb23edb5e5aaa5aa34fdd0e53b39.tar.gz
zig-4ef6864a155cbb23edb5e5aaa5aa34fdd0e53b39.zip
Add move wide with zero (movz) instruction
Diffstat (limited to 'src/codegen.zig')
-rw-r--r--src/codegen.zig8
1 files changed, 7 insertions, 1 deletions
diff --git a/src/codegen.zig b/src/codegen.zig
index 47d33570d5..d946c913a9 100644
--- a/src/codegen.zig
+++ b/src/codegen.zig
@@ -2504,7 +2504,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
else => unreachable, // unexpected register size
}
},
- .immediate => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
+ .immediate => |x| {
+ if (x <= math.maxInt(u16)) {
+ mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.movz(reg, @intCast(u16, x), 0).toU32());
+ } else {
+ return self.fail(src, "TODO genSetReg with 32,48,64bit immediates", .{});
+ }
+ },
.register => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
else => return self.fail(src, "TODO implement genSetReg for aarch64 {}", .{mcv}),
},