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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-24 21:23:45 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-25 16:15:17 +0200 |
| commit | 5d019abe4ec70373db7a75c2a8a3e2d76939817c (patch) | |
| tree | 4ca5e04afceab7cc8e363d7adfe0436f54a3e82a /src/Compilation.zig | |
| parent | 12686d9b7df8fe4c2663cd8e2136991dc3cf661c (diff) | |
| download | zig-5d019abe4ec70373db7a75c2a8a3e2d76939817c.tar.gz zig-5d019abe4ec70373db7a75c2a8a3e2d76939817c.zip | |
start adding big endian RISC-V support
The big endian RISC-V effort is mostly driven by MIPS (the company) which is
pivoting to RISC-V, and presumably needs a big endian variant to fill the niche
that big endian MIPS (the ISA) did.
GCC already supports these targets, but LLVM support will only appear in 22;
this commit just adds the necessary target knowledge and checks on our end.
Diffstat (limited to 'src/Compilation.zig')
| -rw-r--r-- | src/Compilation.zig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/Compilation.zig b/src/Compilation.zig index db15eee954..933774afc7 100644 --- a/src/Compilation.zig +++ b/src/Compilation.zig @@ -7051,7 +7051,7 @@ pub fn addCCArgs( // compiler frontend does. Therefore we must hard-code the -m flags for // all CPU features here. switch (target.cpu.arch) { - .riscv32, .riscv64 => { + .riscv32, .riscv32be, .riscv64, .riscv64be => { const RvArchFeat = struct { char: u8, feat: std.Target.riscv.Feature }; const letters = [_]RvArchFeat{ .{ .char = 'm', .feat = .m }, |