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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-04 20:47:13 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-08-30 06:36:41 +0200 |
| commit | af78c5567682535ff763dddc785f851dc41bbd04 (patch) | |
| tree | 1670cda91c50f82fdc00a9708fb2d7510eb316ee /lib | |
| parent | 367be3777c7dcdd8ca19de0b2a8e2dc4b91486e0 (diff) | |
| download | zig-af78c5567682535ff763dddc785f851dc41bbd04.tar.gz zig-af78c5567682535ff763dddc785f851dc41bbd04.zip | |
std: skip some failing tests on hexagon
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/std/math.zig | 2 | ||||
| -rw-r--r-- | lib/std/math/isnan.zig | 1 | ||||
| -rw-r--r-- | lib/std/math/log10.zig | 1 |
3 files changed, 4 insertions, 0 deletions
diff --git a/lib/std/math.zig b/lib/std/math.zig index 9fd97df855..c1b489a41d 100644 --- a/lib/std/math.zig +++ b/lib/std/math.zig @@ -636,6 +636,7 @@ test shl { try testing.expect(shl(i8, -1, -100) == -1); try testing.expect(shl(i8, -1, 100) == 0); + if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; try testing.expect(@reduce(.And, shl(@Vector(2, i8), .{ -1, 1 }, -100) == @Vector(2, i8){ -1, 0 })); try testing.expect(@reduce(.And, shl(@Vector(2, i8), .{ -1, 1 }, 100) == @Vector(2, i8){ 0, 0 })); } @@ -684,6 +685,7 @@ test shr { try testing.expect(shr(i8, -1, -100) == 0); try testing.expect(shr(i8, -1, 100) == -1); + if (builtin.cpu.arch == .hexagon and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; try testing.expect(@reduce(.And, shr(@Vector(2, i8), .{ -1, 1 }, -100) == @Vector(2, i8){ 0, 0 })); try testing.expect(@reduce(.And, shr(@Vector(2, i8), .{ -1, 1 }, 100) == @Vector(2, i8){ -1, 0 })); } diff --git a/lib/std/math/isnan.zig b/lib/std/math/isnan.zig index 36e0d25f4d..7cd8c2e734 100644 --- a/lib/std/math/isnan.zig +++ b/lib/std/math/isnan.zig @@ -34,6 +34,7 @@ test isSignalNan { // See https://github.com/ziglang/zig/issues/14366 if (!builtin.cpu.arch.isArm() and !builtin.cpu.arch.isAARCH64() and + builtin.cpu.arch != .hexagon and !builtin.cpu.arch.isMIPS32() and !builtin.cpu.arch.isPowerPC() and builtin.zig_backend != .stage2_c) diff --git a/lib/std/math/log10.zig b/lib/std/math/log10.zig index 9ac5c6da24..e55ac46849 100644 --- a/lib/std/math/log10.zig +++ b/lib/std/math/log10.zig @@ -135,6 +135,7 @@ test log10_int { if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch.isWasm()) return error.SkipZigTest; // TODO + if (builtin.zig_backend == .stage2_llvm and comptime builtin.target.cpu.arch == .hexagon) return error.SkipZigTest; inline for ( .{ u8, u16, u32, u64, u128, u256, u512 }, |