remove `spirv` cpu arch

6 files changed, 8 insertions, 64 deletions

diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index bc7b79a9c3..457b93e0cf 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -486,7 +486,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .kalimba,
         .lanai,
         .wasm32,
-        .spirv,
         .spirv32,
         .loongarch32,
         .xtensa,
@@ -554,7 +553,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle => copy.cpu.arch = .powerpc64le,
         .riscv32 => copy.cpu.arch = .riscv64,
         .sparc => copy.cpu.arch = .sparc64,
-        .spirv => copy.cpu.arch = .spirv64,
         .spirv32 => copy.cpu.arch = .spirv64,
         .thumb => copy.cpu.arch = .aarch64,
         .thumbeb => copy.cpu.arch = .aarch64_be,
@@ -609,7 +607,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .spirv => "spirv",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
diff --git a/lib/compiler_rt/common.zig b/lib/compiler_rt/common.zig
index 978e701130..f5423019f1 100644
--- a/lib/compiler_rt/common.zig
+++ b/lib/compiler_rt/common.zig
@@ -120,7 +120,6 @@ pub fn F16T(comptime OtherType: type) type {
         .nvptx64,
         .riscv32,
         .riscv64,
-        .spirv,
         .spirv32,
         .spirv64,
         => f16,
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index b31f6c2de9..18d37e6bf6 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1066,7 +1066,7 @@ pub const ObjectFormat = enum {
             .uefi, .windows => .coff,
             .zos => .goff,
             else => switch (arch) {
-                .spirv, .spirv32, .spirv64 => .spirv,
+                .spirv32, .spirv64 => .spirv,
                 .wasm32, .wasm64 => .wasm,
                 else => .elf,
             },
@@ -1106,7 +1106,6 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
 
         .nvptx,
         .nvptx64,
-        .spirv,
         .spirv32,
         .spirv64,
         .wasm32,
@@ -1155,7 +1154,6 @@ pub fn toCoffMachine(target: *const Target) std.coff.MachineType {
         .s390x,
         .sparc,
         .sparc64,
-        .spirv,
         .spirv32,
         .spirv64,
         .ve,
@@ -1368,7 +1366,6 @@ pub const Cpu = struct {
         s390x,
         sparc,
         sparc64,
-        spirv,
         spirv32,
         spirv64,
         ve,
@@ -1454,7 +1451,7 @@ pub const Cpu = struct {
                 .riscv32, .riscv64 => .riscv,
                 .s390x => .s390x,
                 .sparc, .sparc64 => .sparc,
-                .spirv, .spirv32, .spirv64 => .spirv,
+                .spirv32, .spirv64 => .spirv,
                 .ve => .ve,
                 .wasm32, .wasm64 => .wasm,
                 .x86, .x86_64 => .x86,
@@ -1558,7 +1555,7 @@ pub const Cpu = struct {
 
         pub inline fn isSpirV(arch: Arch) bool {
             return switch (arch) {
-                .spirv, .spirv32, .spirv64 => true,
+                .spirv32, .spirv64 => true,
                 else => false,
             };
         }
@@ -1614,7 +1611,6 @@ pub const Cpu = struct {
                 .thumb,
                 .ve,
                 // GPU bitness is opaque. For now, assume little endian.
-                .spirv,
                 .spirv32,
                 .spirv64,
                 .loongarch32,
@@ -1843,7 +1839,7 @@ pub const Cpu = struct {
                 .spirv_kernel,
                 .spirv_fragment,
                 .spirv_vertex,
-                => &.{ .spirv, .spirv32, .spirv64 },
+                => &.{ .spirv32, .spirv64 },
             };
         }
     };
@@ -2638,7 +2634,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
         .sparc64,
         .s390x,
         .ve,
-        .spirv,
         .spirv64,
         .loongarch64,
         => 64,
@@ -3157,7 +3152,6 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
             .riscv32,
             .riscv64,
             .sparc64,
-            .spirv,
             .spirv32,
             .spirv64,
             .x86_64,
@@ -3250,7 +3244,6 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
             .riscv32,
             .riscv64,
             .sparc64,
-            .spirv,
             .spirv32,
             .spirv64,
             .x86_64,
@@ -3319,7 +3312,6 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
         .loongarch32,
         .loongarch64,
         .m68k,
-        .spirv,
         .spirv32,
         .spirv64,
         .ve,
@@ -3389,7 +3381,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .xtensa => .{ .xtensa_call0 = .{} },
         .amdgcn => .{ .amdgcn_device = .{} },
         .nvptx, .nvptx64 => .nvptx_device,
-        .spirv, .spirv32, .spirv64 => .spirv_device,
+        .spirv32, .spirv64 => .spirv_device,
     };
 }
 
diff --git a/lib/std/Target/spirv.zig b/lib/std/Target/spirv.zig
index 229d77a6d6..28fda54e9d 100644
--- a/lib/std/Target/spirv.zig
+++ b/lib/std/Target/spirv.zig
@@ -5,16 +5,11 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
-    addresses,
     arbitrary_precision_integers,
     float16,
     float64,
     generic_pointer,
     int64,
-    kernel,
-    matrix,
-    physical_storage_buffer,
-    shader,
     storage_push_constant16,
     v1_0,
     v1_1,
@@ -37,13 +32,6 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).@"enum".fields.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
-    result[@intFromEnum(Feature.addresses)] = .{
-        .llvm_name = null,
-        .description = "Enable Addresses capability",
-        .dependencies = featureSet(&[_]Feature{
-            .v1_0,
-        }),
-    };
     result[@intFromEnum(Feature.arbitrary_precision_integers)] = .{
         .llvm_name = null,
         .description = "Enable SPV_INTEL_arbitrary_precision_integers extension and the ArbitraryPrecisionIntegersINTEL capability",
@@ -69,7 +57,7 @@ pub const all_features = blk: {
         .llvm_name = null,
         .description = "Enable GenericPointer capability",
         .dependencies = featureSet(&[_]Feature{
-            .addresses,
+            .v1_0,
         }),
     };
     result[@intFromEnum(Feature.int64)] = .{
@@ -79,34 +67,6 @@ pub const all_features = blk: {
             .v1_0,
         }),
     };
-    result[@intFromEnum(Feature.kernel)] = .{
-        .llvm_name = null,
-        .description = "Enable Kernel capability",
-        .dependencies = featureSet(&[_]Feature{
-            .v1_0,
-        }),
-    };
-    result[@intFromEnum(Feature.matrix)] = .{
-        .llvm_name = null,
-        .description = "Enable Matrix capability",
-        .dependencies = featureSet(&[_]Feature{
-            .v1_0,
-        }),
-    };
-    result[@intFromEnum(Feature.physical_storage_buffer)] = .{
-        .llvm_name = null,
-        .description = "Enable SPV_KHR_variable_pointers extension and the (VariablePointers, VariablePointersStorageBuffer) capabilities",
-        .dependencies = featureSet(&[_]Feature{
-            .v1_0,
-        }),
-    };
-    result[@intFromEnum(Feature.shader)] = .{
-        .llvm_name = null,
-        .description = "Enable Shader capability",
-        .dependencies = featureSet(&[_]Feature{
-            .matrix,
-        }),
-    };
     result[@intFromEnum(Feature.storage_push_constant16)] = .{
         .llvm_name = null,
         .description = "Enable SPV_KHR_16bit_storage extension and the StoragePushConstant16 capability",
@@ -172,7 +132,7 @@ pub const all_features = blk: {
         .llvm_name = null,
         .description = "Enable Vector16 capability",
         .dependencies = featureSet(&[_]Feature{
-            .kernel,
+            .v1_0,
         }),
     };
     const ti = @typeInfo(Feature);
@@ -193,8 +153,6 @@ pub const cpu = struct {
         .name = "opencl_v2",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
-            .generic_pointer,
-            .kernel,
             .v1_2,
         }),
     };
@@ -202,7 +160,6 @@ pub const cpu = struct {
         .name = "vulkan_v1_2",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
-            .shader,
             .v1_5,
         }),
     };
diff --git a/lib/std/builtin.zig b/lib/std/builtin.zig
index d262a70293..9df042f86f 100644
--- a/lib/std/builtin.zig
+++ b/lib/std/builtin.zig
@@ -189,7 +189,7 @@ pub const CallingConvention = union(enum(u8)) {
     pub const kernel: CallingConvention = switch (builtin.target.cpu.arch) {
         .amdgcn => .amdgcn_kernel,
         .nvptx, .nvptx64 => .nvptx_kernel,
-        .spirv, .spirv32, .spirv64 => .spirv_kernel,
+        .spirv32, .spirv64 => .spirv_kernel,
         else => unreachable,
     };
 
diff --git a/lib/std/debug/Dwarf/abi.zig b/lib/std/debug/Dwarf/abi.zig
index e880b12863..b8b644e026 100644
--- a/lib/std/debug/Dwarf/abi.zig
+++ b/lib/std/debug/Dwarf/abi.zig
@@ -14,7 +14,6 @@ pub fn supportsUnwinding(target: *const std.Target) bool {
         .amdgcn,
         .nvptx,
         .nvptx64,
-        .spirv,
         .spirv32,
         .spirv64,
         => false,