std.debug: add CPU context and DWARF mappings for lanai

2 files changed, 58 insertions, 0 deletions

diff --git a/lib/std/debug/Dwarf.zig b/lib/std/debug/Dwarf.zig
index 044232b996..fd0683d156 100644
--- a/lib/std/debug/Dwarf.zig
+++ b/lib/std/debug/Dwarf.zig
@@ -1432,6 +1432,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
         .aarch64, .aarch64_be => 32,
         .arm, .armeb, .thumb, .thumbeb => 15,
         .hexagon => 76,
+        .lanai => 2,
         .loongarch32, .loongarch64 => 64,
         .mips, .mipsel, .mips64, .mips64el => 66,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 67,
@@ -1450,6 +1451,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
         .aarch64, .aarch64_be => 29,
         .arm, .armeb, .thumb, .thumbeb => 11,
         .hexagon => 30,
+        .lanai => 5,
         .loongarch32, .loongarch64 => 22,
         .mips, .mipsel, .mips64, .mips64el => 30,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
@@ -1468,6 +1470,7 @@ pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
         .aarch64, .aarch64_be => 31,
         .arm, .armeb, .thumb, .thumbeb => 13,
         .hexagon => 29,
+        .lanai => 4,
         .loongarch32, .loongarch64 => 3,
         .mips, .mipsel, .mips64, .mips64el => 29,
         .powerpc, .powerpcle, .powerpc64, .powerpc64le => 1,
diff --git a/lib/std/debug/cpu_context.zig b/lib/std/debug/cpu_context.zig
index f989c01e88..b3c348df90 100644
--- a/lib/std/debug/cpu_context.zig
+++ b/lib/std/debug/cpu_context.zig
@@ -7,6 +7,7 @@ else switch (native_arch) {
     .aarch64, .aarch64_be => Aarch64,
     .arm, .armeb, .thumb, .thumbeb => Arm,
     .hexagon => Hexagon,
+    .lanai => Lanai,
     .loongarch32, .loongarch64 => LoongArch,
     .mips, .mipsel, .mips64, .mips64el => Mips,
     .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc,
@@ -501,6 +502,60 @@ const Hexagon = extern struct {
 };
 
 /// This is an `extern struct` so that inline assembly in `current` can use field offsets.
+const Lanai = extern struct {
+    r: [32]u32,
+
+    pub inline fn current() Lanai {
+        var ctx: Lanai = undefined;
+        asm volatile (
+            \\ st %%r0, 0[r9]
+            \\ st %%r1, 4[r9]
+            \\ st %%r2, 8[r9]
+            \\ st %%r3, 12[r9]
+            \\ st %%r4, 16[r9]
+            \\ st %%r5, 20[r9]
+            \\ st %%r6, 24[r9]
+            \\ st %%r7, 28[r9]
+            \\ st %%r8, 32[r9]
+            \\ st %%r9, 36[r9]
+            \\ st %%r10, 40[r9]
+            \\ st %%r11, 44[r9]
+            \\ st %%r12, 48[r9]
+            \\ st %%r13, 52[r9]
+            \\ st %%r14, 56[r9]
+            \\ st %%r15, 60[r9]
+            \\ st %%r16, 64[r9]
+            \\ st %%r17, 68[r9]
+            \\ st %%r18, 72[r9]
+            \\ st %%r19, 76[r9]
+            \\ st %%r20, 80[r9]
+            \\ st %%r21, 84[r9]
+            \\ st %%r22, 88[r9]
+            \\ st %%r23, 92[r9]
+            \\ st %%r24, 96[r9]
+            \\ st %%r25, 100[r9]
+            \\ st %%r26, 104[r9]
+            \\ st %%r27, 108[r9]
+            \\ st %%r28, 112[r9]
+            \\ st %%r29, 116[r9]
+            \\ st %%r30, 120[r9]
+            \\ st %%r31, 124[r9]
+            :
+            : [ctx] "{r9}" (&ctx),
+            : .{ .memory = true });
+        return ctx;
+    }
+
+    pub fn dwarfRegisterBytes(ctx: *Lanai, register_num: u16) DwarfRegisterError![]u8 {
+        switch (register_num) {
+            0...31 => return @ptrCast(&ctx.s[register_num]),
+
+            else => return error.InvalidRegister,
+        }
+    }
+};
+
+/// This is an `extern struct` so that inline assembly in `current` can use field offsets.
 const LoongArch = extern struct {
     /// The numbered general-purpose registers r0 - r31. r0 must be zero.
     r: [32]Gpr,