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| author | Alex Rønne Petersen <alex@alexrp.com> | 2025-10-16 17:09:30 +0200 |
|---|---|---|
| committer | Alex Rønne Petersen <alex@alexrp.com> | 2025-10-18 00:36:52 +0200 |
| commit | ba9ab3fb6720ff5894ac07741eccaaca44122eb0 (patch) | |
| tree | b2dd557ed57b265647849588f32e22bc1167623d /lib/std/debug/cpu_context.zig | |
| parent | eb36a45ed9fbdf5ab92c3cdb650375a13eaaa648 (diff) | |
| download | zig-ba9ab3fb6720ff5894ac07741eccaaca44122eb0.tar.gz zig-ba9ab3fb6720ff5894ac07741eccaaca44122eb0.zip | |
std.debug: add CPU context and DWARF mappings for m68k
Diffstat (limited to 'lib/std/debug/cpu_context.zig')
| -rw-r--r-- | lib/std/debug/cpu_context.zig | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/lib/std/debug/cpu_context.zig b/lib/std/debug/cpu_context.zig index f4141ce33a..1278e630ff 100644 --- a/lib/std/debug/cpu_context.zig +++ b/lib/std/debug/cpu_context.zig @@ -10,6 +10,7 @@ else switch (native_arch) { .hexagon => Hexagon, .lanai => Lanai, .loongarch32, .loongarch64 => LoongArch, + .m68k => M68k, .mips, .mipsel, .mips64, .mips64el => Mips, .or1k => Or1k, .powerpc, .powerpcle, .powerpc64, .powerpc64le => Powerpc, @@ -87,6 +88,11 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native { .r = uc.mcontext.r, .pc = uc.mcontext.pc, }, + .m68k => .{ + .d = uc.mcontext.d, + .a = uc.mcontext.a, + .pc = uc.mcontext.pc, + }, .powerpc, .powerpcle, .powerpc64, .powerpc64le => .{ .r = uc.mcontext.r, .pc = uc.mcontext.pc, @@ -698,6 +704,40 @@ const LoongArch = extern struct { }; /// This is an `extern struct` so that inline assembly in `current` can use field offsets. +const M68k = extern struct { + /// The numbered data registers d0 - d7. + d: [8]u32, + /// The numbered address registers a0 - a7. + a: [8]u32, + pc: u32, + + pub inline fn current() M68k { + var ctx: M68k = undefined; + asm volatile ( + \\ movem.l %%d0 - %%a7, (%%a0) + \\ lea.l (%%pc), %%a1 + \\ move.l %%a1, (%%a0, 64) + : + : [ctx] "{a0}" (&ctx), + : .{ .a1 = true, .memory = true }); + return ctx; + } + + pub fn dwarfRegisterBytes(ctx: *M68k, register_num: u16) DwarfRegisterError![]u8 { + switch (register_num) { + 0...7 => return @ptrCast(&ctx.d[register_num]), + 8...15 => return @ptrCast(&ctx.a[register_num - 8]), + 26 => return @ptrCast(&ctx.pc), + + 16...23 => return error.UnsupportedRegister, // fp0 - fp7 + 24...25 => return error.UnsupportedRegister, // Return columns in GCC...? + + else => return error.InvalidRegister, + } + } +}; + +/// This is an `extern struct` so that inline assembly in `current` can use field offsets. const Mips = extern struct { /// The numbered general-purpose registers r0 - r31. r0 must be zero. r: [32]Gpr, |
