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authorAlex Rønne Petersen <alex@alexrp.com>2024-10-06 13:35:56 +0200
committerGitHub <noreply@github.com>2024-10-06 13:35:56 +0200
commitbe5378b03805fa95b3cf36b6727d2c364c155e64 (patch)
treee6571591425e1cf8e373a9663010de536b644148 /lib/std/atomic.zig
parent008bb1f1201a4b4987bf00de9daf46185aa9292d (diff)
parent45644b7e152e851b9f9f51095e3ce1ca7fcc8a56 (diff)
downloadzig-be5378b03805fa95b3cf36b6727d2c364c155e64.tar.gz
zig-be5378b03805fa95b3cf36b6727d2c364c155e64.zip
Merge pull request #21587 from alexrp/hexagon-porting
Some initial `hexagon-linux` port work
Diffstat (limited to 'lib/std/atomic.zig')
-rw-r--r--lib/std/atomic.zig6
1 files changed, 4 insertions, 2 deletions
diff --git a/lib/std/atomic.zig b/lib/std/atomic.zig
index 2efcefdd42..e1a6767590 100644
--- a/lib/std/atomic.zig
+++ b/lib/std/atomic.zig
@@ -433,18 +433,20 @@ pub const cache_line = switch (builtin.cpu.arch) {
.powerpc64le,
=> 128,
+ // https://github.com/llvm/llvm-project/blob/e379094328e49731a606304f7e3559d4f1fa96f9/clang/lib/Basic/Targets/Hexagon.h#L145-L151
+ .hexagon,
+ => if (std.Target.hexagon.featureSetHas(builtin.target.cpu.features, .v73)) 64 else 32,
+
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_arm.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9
// - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7
- // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/hexagon/include/asm/cache.h#L13
// - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14
.arm,
.armeb,
.thumb,
.thumbeb,
- .hexagon,
.mips,
.mipsel,
.mips64,