start adding big endian RISC-V support

The big endian RISC-V effort is mostly driven by MIPS (the company) which is
pivoting to RISC-V, and presumably needs a big endian variant to fill the niche
that big endian MIPS (the ISA) did.

GCC already supports these targets, but LLVM support will only appear in 22;
this commit just adds the necessary target knowledge and checks on our end.

2 files changed, 15 insertions, 2 deletions

diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig
index 77d60a1e9d..d7377d7e52 100644
--- a/lib/compiler/aro/aro/Compilation.zig
+++ b/lib/compiler/aro/aro/Compilation.zig
@@ -927,7 +927,7 @@ fn generateVaListType(comp: *Compilation) !Type {
             .ios, .macos, .tvos, .watchos => .char_ptr,
             else => .aarch64_va_list,
         },
-        .sparc, .wasm32, .wasm64, .bpfel, .bpfeb, .riscv32, .riscv64, .avr, .spirv32, .spirv64 => .void_ptr,
+        .sparc, .wasm32, .wasm64, .bpfel, .bpfeb, .riscv32, .riscv32be, .riscv64, .riscv64be, .avr, .spirv32, .spirv64 => .void_ptr,
         .powerpc => switch (comp.target.os.tag) {
             .ios, .macos, .tvos, .watchos, .aix => @as(Kind, .char_ptr),
             else => return Type{ .specifier = .void }, // unknown
diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 457b93e0cf..947a439705 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -15,6 +15,7 @@ pub fn intMaxType(target: std.Target) Type {
         .bpfeb,
         .loongarch64,
         .riscv64,
+        .riscv64be,
         .powerpc64,
         .powerpc64le,
         .ve,
@@ -47,6 +48,7 @@ pub fn intPtrType(target: std.Target) Type {
         .csky,
         .loongarch32,
         .riscv32,
+        .riscv32be,
         .xcore,
         .hexagon,
         .m68k,
@@ -109,6 +111,7 @@ pub fn int64Type(target: std.Target) Type {
         .loongarch64,
         .ve,
         .riscv64,
+        .riscv64be,
         .powerpc64,
         .powerpc64le,
         .bpfel,
@@ -138,7 +141,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
         .arm, .armeb => 4,
         .aarch64, .aarch64_be => 4,
         .sparc, .sparc64 => 4,
-        .riscv64 => 2,
+        .riscv64, .riscv64be => 2,
         else => 1,
     };
 }
@@ -330,7 +333,9 @@ pub const FPSemantics = enum {
             .armeb,
             .hexagon,
             .riscv32,
+            .riscv32be,
             .riscv64,
+            .riscv64be,
             .spirv32,
             .spirv64,
             => return .IEEEHalf,
@@ -429,7 +434,9 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
         .powerpc64 => "elf64ppc",
         .powerpc64le => "elf64lppc",
         .riscv32 => "elf32lriscv",
+        .riscv32be => "elf32briscv",
         .riscv64 => "elf64lriscv",
+        .riscv64be => "elf64briscv",
         .sparc => "elf32_sparc",
         .sparc64 => "elf64_sparc",
         .loongarch32 => "elf32loongarch",
@@ -477,6 +484,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpc,
         .powerpcle,
         .riscv32,
+        .riscv32be,
         .sparc,
         .thumb,
         .thumbeb,
@@ -502,6 +510,7 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .powerpc64 => copy.cpu.arch = .powerpc,
         .powerpc64le => copy.cpu.arch = .powerpcle,
         .riscv64 => copy.cpu.arch = .riscv32,
+        .riscv64be => copy.cpu.arch = .riscv32be,
         .sparc64 => copy.cpu.arch = .sparc,
         .x86_64 => copy.cpu.arch = .x86,
     }
@@ -537,6 +546,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpc64,
         .powerpc64le,
         .riscv64,
+        .riscv64be,
         .s390x,
         .sparc64,
         .ve,
@@ -552,6 +562,7 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpc => copy.cpu.arch = .powerpc64,
         .powerpcle => copy.cpu.arch = .powerpc64le,
         .riscv32 => copy.cpu.arch = .riscv64,
+        .riscv32be => copy.cpu.arch = .riscv64be,
         .sparc => copy.cpu.arch = .sparc64,
         .spirv32 => copy.cpu.arch = .spirv64,
         .thumb => copy.cpu.arch = .aarch64,
@@ -595,7 +606,9 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .powerpc64le => "powerpc64le",
         .amdgcn => "amdgcn",
         .riscv32 => "riscv32",
+        .riscv32be => "riscv32be",
         .riscv64 => "riscv64",
+        .riscv64be => "riscv64be",
         .sparc => "sparc",
         .sparc64 => "sparc64",
         .s390x => "s390x",