std.Target: Remove `spir`/`spir64` architecture tags.

These were for very old OpenCL have been long abandoned in favor of SPIR-V.

* https://github.com/KhronosGroup/SPIR
* https://github.com/KhronosGroup/SPIR-Tools

6 files changed, 2 insertions, 35 deletions

diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 8a864eb0ad..5822801036 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -53,7 +53,6 @@ pub fn intPtrType(target: std.Target) Type {
         .xcore,
         .hexagon,
         .m68k,
-        .spir,
         .spirv32,
         .arc,
         .avr,
@@ -473,7 +472,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .x86,
         .xcore,
         .nvptx,
-        .spir,
         .kalimba,
         .lanai,
         .wasm32,
@@ -487,7 +485,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .aarch64_be => copy.cpu.arch = .armeb,
         .nvptx64 => copy.cpu.arch = .nvptx,
         .wasm64 => copy.cpu.arch = .wasm32,
-        .spir64 => copy.cpu.arch = .spir,
         .spirv64 => copy.cpu.arch = .spirv32,
         .loongarch64 => copy.cpu.arch = .loongarch32,
         .mips64 => copy.cpu.arch = .mips,
@@ -526,7 +523,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .bpfel,
         .nvptx64,
         .wasm64,
-        .spir64,
         .spirv64,
         .loongarch64,
         .mips64,
@@ -550,7 +546,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .powerpcle => copy.cpu.arch = .powerpc64le,
         .riscv32 => copy.cpu.arch = .riscv64,
         .sparc => copy.cpu.arch = .sparc64,
-        .spir => copy.cpu.arch = .spir64,
         .spirv32 => copy.cpu.arch = .spirv64,
         .thumb => copy.cpu.arch = .aarch64,
         .thumbeb => copy.cpu.arch = .aarch64_be,
@@ -607,8 +602,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .spir => "spir",
-        .spir64 => "spir64",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index a69038fae4..d76eb885c0 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1027,8 +1027,6 @@ pub const Cpu = struct {
         xtensa,
         nvptx,
         nvptx64,
-        spir,
-        spir64,
         spirv,
         spirv32,
         spirv64,
@@ -1048,6 +1046,8 @@ pub const Cpu = struct {
         // - amdil64
         // - hsail
         // - hsail64
+        // - spir
+        // - spir64
         // - shave
         // - renderscript32
         // - renderscript64
@@ -1178,7 +1178,6 @@ pub const Cpu = struct {
                 .xcore => .XCORE,
                 .xtensa => .XTENSA,
                 .nvptx => .NONE,
-                .spir => .NONE,
                 .kalimba => .CSR_KALIMBA,
                 .lanai => .LANAI,
                 .wasm32 => .NONE,
@@ -1191,7 +1190,6 @@ pub const Cpu = struct {
                 .riscv64 => .RISCV,
                 .x86_64 => .X86_64,
                 .nvptx64 => .NONE,
-                .spir64 => .NONE,
                 .wasm64 => .NONE,
                 .amdgcn => .AMDGPU,
                 .bpfel => .BPF,
@@ -1231,7 +1229,6 @@ pub const Cpu = struct {
                 .xcore => .Unknown,
                 .xtensa => .Unknown,
                 .nvptx => .Unknown,
-                .spir => .Unknown,
                 .kalimba => .Unknown,
                 .lanai => .Unknown,
                 .wasm32 => .Unknown,
@@ -1244,7 +1241,6 @@ pub const Cpu = struct {
                 .riscv64 => .RISCV64,
                 .x86_64 => .X64,
                 .nvptx64 => .Unknown,
-                .spir64 => .Unknown,
                 .wasm64 => .Unknown,
                 .amdgcn => .Unknown,
                 .bpfel => .Unknown,
@@ -1289,8 +1285,6 @@ pub const Cpu = struct {
                 .wasm64,
                 .xcore,
                 .thumb,
-                .spir,
-                .spir64,
                 .ve,
                 .spu_2,
                 // GPU bitness is opaque. For now, assume little endian.
@@ -1769,8 +1763,6 @@ pub const DynamicLinker = struct {
                 .msp430,
                 .amdgcn,
                 .xcore,
-                .spir,
-                .spir64,
                 .kalimba,
                 .lanai,
                 .ve,
@@ -1868,7 +1860,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .x86,
         .xcore,
         .nvptx,
-        .spir,
         .kalimba,
         .lanai,
         .wasm32,
@@ -1887,7 +1878,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .riscv64,
         .x86_64,
         .nvptx64,
-        .spir64,
         .wasm64,
         .amdgcn,
         .bpfel,
@@ -2368,7 +2358,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .xcore,
             .dxil,
             .loongarch32,
-            .spir,
             .spirv32,
             .kalimba,
             .ve,
@@ -2391,7 +2380,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .nvptx,
             .nvptx64,
             .s390x,
-            .spir64,
             .spirv64,
             => 8,
 
@@ -2476,7 +2464,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .xcore,
             .dxil,
             .loongarch32,
-            .spir,
             .spirv32,
             .kalimba,
             .ve,
@@ -2506,7 +2493,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .nvptx,
             .nvptx64,
             .s390x,
-            .spir64,
             .spirv64,
             => 8,
 
diff --git a/src/Type.zig b/src/Type.zig
index 5bcffed6b7..22e2931019 100644
--- a/src/Type.zig
+++ b/src/Type.zig
@@ -1647,11 +1647,9 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
         .csky,
         .arc,
         .m68k,
-        .spir,
         .kalimba,
         .spirv,
         .spirv32,
-        .spir64,
         .ve,
         .spirv64,
         .dxil,
diff --git a/src/Zcu.zig b/src/Zcu.zig
index c644dcce64..bc7d2d2e49 100644
--- a/src/Zcu.zig
+++ b/src/Zcu.zig
@@ -3253,7 +3253,6 @@ pub fn atomicPtrAlignment(
         .thumbeb,
         .x86,
         .xcore,
-        .spir,
         .kalimba,
         .lanai,
         .wasm32,
@@ -3275,7 +3274,6 @@ pub fn atomicPtrAlignment(
         .riscv64,
         .sparc64,
         .s390x,
-        .spir64,
         .wasm64,
         .ve,
         .spirv64,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 23f423ab2c..fcbfa06bd2 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -79,8 +79,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .xtensa => "xtensa",
         .nvptx => "nvptx",
         .nvptx64 => "nvptx64",
-        .spir => "spir",
-        .spir64 => "spir64",
         .spirv => "spirv",
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
@@ -292,8 +290,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .xtensa => .xtensa,
         .nvptx => .nvptx,
         .nvptx64 => .nvptx64,
-        .spir => .spir,
-        .spir64 => .spir64,
         .spirv => .spirv,
         .spirv32 => .spirv32,
         .spirv64 => .spirv64,
@@ -12095,8 +12091,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
         },
 
         // LLVM backends that have no initialization functions.
-        .spir,
-        .spir64,
         .spirv,
         .spirv32,
         .spirv64,
diff --git a/src/target.zig b/src/target.zig
index ccf3ceb626..e30743f65c 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -148,8 +148,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .xtensa,
         .nvptx,
         .nvptx64,
-        .spir,
-        .spir64,
         .spirv,
         .spirv32,
         .spirv64,