diff options
Diffstat (limited to 'SOURCES/steamdeck-oled-hw-quirks.patch')
| -rw-r--r-- | SOURCES/steamdeck-oled-hw-quirks.patch | 266 |
1 files changed, 228 insertions, 38 deletions
diff --git a/SOURCES/steamdeck-oled-hw-quirks.patch b/SOURCES/steamdeck-oled-hw-quirks.patch index a2b1228..e233674 100644 --- a/SOURCES/steamdeck-oled-hw-quirks.patch +++ b/SOURCES/steamdeck-oled-hw-quirks.patch @@ -71,33 +71,6 @@ index e8b2fc4002a52..3c69d860e1c9d 100644 -- GitLab -From a32cc4f110bcd8d4595ff0812a72a521e99006ac Mon Sep 17 00:00:00 2001 -From: Keith Mikoleit <keithm@valvesoftware.com> -Date: Fri, 22 Sep 2023 17:30:44 -0700 -Subject: [PATCH] drm/amd/display: change default edp brightness check to min 1 - nit - ---- - .../amd/display/dc/link/protocols/link_edp_panel_control.c | 4 ++-- - 1 file changed, 2 insertions(+), 2 deletions(-) - -diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c -index 2039a345f23a1..e4626f2072f0f 100644 ---- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c -+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c -@@ -266,8 +266,8 @@ bool set_default_brightness_aux(struct dc_link *link) - if (link && link->dpcd_sink_ext_caps.bits.oled == 1) { - if (!read_default_bl_aux(link, &default_backlight)) - default_backlight = 150000; -- // if < 5 nits or > 5000, it might be wrong readback -- if (default_backlight < 5000 || default_backlight > 5000000) -+ // if < 1 nits or > 5000, it might be wrong readback -+ if (default_backlight < 1000 || default_backlight > 5000000) - default_backlight = 150000; // - - return edp_set_backlight_level_nits(link, true, --- -GitLab From b59fed802470f07fafe72f6a2bdda2163da5ba33 Mon Sep 17 00:00:00 2001 From: Swapnil Patel <Swapnil.Patel@amd.com> Date: Tue, 26 Sep 2023 16:24:25 -0400 @@ -155,7 +128,7 @@ index b8633df418d43..77a1bedaee98c 100644 @@ -416,8 +416,6 @@ struct drm_property *regamma_tf_property; }; - + -#define AMDGPU_MAX_BL_LEVEL 0xFF - struct amdgpu_backlight_privdata { @@ -235,16 +208,16 @@ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm index e1a77a0d66336..8e61c86819fe2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -@@ -4032,7 +4032,7 @@ +@@ -4017,7 +4017,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) return 0; } - + -#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 +#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 0 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 - -@@ -4050,11 +4050,27 @@ + +@@ -4035,11 +4035,27 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, amdgpu_acpi_get_backlight_caps(&caps); if (caps.caps_valid) { dm->backlight_caps[bl_idx].caps_valid = true; @@ -272,27 +245,27 @@ index e1a77a0d66336..8e61c86819fe2 100644 dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; dm->backlight_caps[bl_idx].max_input_signal = -@@ -4064,6 +4080,9 @@ +@@ -4049,6 +4065,9 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, if (dm->backlight_caps[bl_idx].aux_support) return; - + + printk(KERN_NOTICE"VLV Kernel built without ACPI. using backlight range defaults: %d %d\n", + AMDGPU_DM_DEFAULT_MIN_BACKLIGHT, AMDGPU_DM_DEFAULT_MAX_BACKLIGHT); + dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; #endif -@@ -4095,7 +4114,7 @@ +@@ -4080,7 +4099,7 @@ static u32 convert_brightness_from_user(const struct amdgpu_dm_backlight_caps *c if (!get_brightness_range(caps, &min, &max)) return brightness; - + - // Rescale 0..255 to min..max + // Rescale 0..AMDGPU_MAX_BL_LEVEL to min..max return min + DIV_ROUND_CLOSEST((max - min) * brightness, AMDGPU_MAX_BL_LEVEL); } -@@ -4110,7 +4129,7 @@ - +@@ -4095,7 +4114,7 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap + if (brightness < min) return 0; - // Rescale min..max to 0..255 @@ -303,6 +276,7 @@ index e1a77a0d66336..8e61c86819fe2 100644 -- GitLab + From ab7d646eacf9f1c745d284e293211569a4428573 Mon Sep 17 00:00:00 2001 From: "Pierre-Loup A. Griffais" <pgriffais@valvesoftware.com> Date: Wed, 8 Nov 2023 19:45:52 -0800 @@ -393,3 +367,219 @@ index b76ff08506181..95f33dadb2be2 100644 -- GitLab +From 32d8309584145f531b46e8c1a72c86494e72160d Mon Sep 17 00:00:00 2001 +From: Joshua Ashton <joshua@froggi.es> +Date: Wed, 6 Sep 2023 22:00:26 +0100 +Subject: [PATCH] drm/amd/display: Don't consider vblank passed if currently in + vertical front porch time + +Changing refresh rates on OLED displays works differently to typical +LCD panels in that instead of changing the clock, the vertical porch +is extended significantly for lower rates. + +This can mean that the vertical porch can be incredibly large for +non-base refresh rates eg. 60Hz on a 90Hz display. + +This isn't an issue for X11/typical compositors as their present slop +is 1/2th of the refresh interval so the issue never manifests. + +However in Gamescope, the present slop very small and tuned to be +optimal in real-time to try and reduce display latency significantly. +This results in us queueing up the atomic commit inside the vertical +porch region which, due to legacy X11/sync control reasons, means that +AMDGPU must target the next vblank. + +This patch changes that behaviour to make FRR displays match what occurs +on VRR/Freesync displays where the vertical porch time is not included +in determining what vblank to target and solves the issue. + +This means that smarter compositors can get large input latency +reductions when using OLED displays at lower than base refresh rates. + +For upstreaming this patch, it will need to be considered what the best +solution is to enable this behaviour from the userspace side. +Obviously the X11/legacy stuff probably cannot change here -- so we +either need to enable this new behaviour globally for all DRM atomic +clients (ie. basically Wayland compositors) or have a +new DRM_MODE_ATOMIC flag. + +Signed-off-by: Joshua Ashton <joshua@froggi.es> +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index b87797bc5874..28e6fa8d7860 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -434,7 +434,7 @@ static void dm_pflip_high_irq(void *interrupt_params) + + WARN_ON(!e); + +- vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); ++ vrr_active = true;//amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); + + /* Fixed refresh rate, or VRR scanout position outside front-porch? */ + if (!vrr_active || +@@ -531,11 +531,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) + * page-flip completion events that have been queued to us + * if a pageflip happened inside front-porch. + */ +- if (vrr_active) { ++ if (true) { + amdgpu_dm_crtc_handle_vblank(acrtc); + + /* BTR processing for pre-DCE12 ASICs */ +- if (acrtc->dm_irq_params.stream && ++ if (vrr_active && acrtc->dm_irq_params.stream && + adev->family < AMDGPU_FAMILY_AI) { + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + mod_freesync_handle_v_update( +@@ -8098,7 +8098,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, + int planes_count = 0, vpos, hpos; + unsigned long flags; + u32 target_vblank, last_flip_vblank; +- bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); ++ bool vrr_active = true;//amdgpu_dm_crtc_vrr_active(acrtc_state); + bool cursor_update = false; + bool pflip_present = false; + bool dirty_rects_changed = false; +-- +GitLab + +From 2bfd05863fff384619dea44bafa98ba0e6a5cdf4 Mon Sep 17 00:00:00 2001 +From: Joshua Ashton <joshua@froggi.es> +Date: Sun, 3 Dec 2023 11:35:06 +0000 +Subject: [PATCH] drm/amd/display: Revert some of the vrr always on hack + +Fixes frame timings on some non)-VRR external displays going all whacky. + +This makes us not use the late vblank irq handler (backporch line 0) and instead send the vblank event immediately on page flip when we know where the vblank is going to be. + +Should also improve latency/stutter on internal display potentially too. +--- + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +index 715f442a0e3b..06dcd463f841 100644 +--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c ++++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +@@ -434,7 +434,7 @@ static void dm_pflip_high_irq(void *interrupt_params) + + WARN_ON(!e); + +- vrr_active = true;//amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); ++ vrr_active = amdgpu_dm_crtc_vrr_active_irq(amdgpu_crtc); + + /* Fixed refresh rate, or VRR scanout position outside front-porch? */ + if (!vrr_active || +@@ -531,11 +531,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) + * page-flip completion events that have been queued to us + * if a pageflip happened inside front-porch. + */ +- if (true) { ++ if (vrr_active) { + amdgpu_dm_crtc_handle_vblank(acrtc); + + /* BTR processing for pre-DCE12 ASICs */ +- if (vrr_active && acrtc->dm_irq_params.stream && ++ if (acrtc->dm_irq_params.stream && + adev->family < AMDGPU_FAMILY_AI) { + spin_lock_irqsave(&adev_to_drm(adev)->event_lock, flags); + mod_freesync_handle_v_update( +-- +GitLab + +From d426d1ad3f92605c95bdf58bbc19129a128f5590 Mon Sep 17 00:00:00 2001 +From: Friedrich Vock <friedrich.vock@gmx.de> +Date: Fri, 1 Dec 2023 15:15:58 +0100 +Subject: [PATCH] drm/amdgpu: Enable tunneling on high-priority compute queues + +This improves latency if the GPU is already busy with other work. +This is useful for VR compositors that submit highly latency-sensitive +compositing work on high-priority compute queues while the GPU is busy +rendering the next frame. + +Userspace merge request: +https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26462 + +Signed-off-by: Friedrich Vock <friedrich.vock@gmx.de> +--- + drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + + drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 10 ++++++---- + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 3 ++- + drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 ++- + 4 files changed, 11 insertions(+), 6 deletions(-) + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +index df59a6919d878..04686b816fa11 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h +@@ -768,6 +768,7 @@ struct amdgpu_mqd_prop { + uint64_t eop_gpu_addr; + uint32_t hqd_pipe_priority; + uint32_t hqd_queue_priority; ++ bool allow_tunneling; + bool hqd_active; + }; + +diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +index 72085a3ef53c0..5d1a6e95b02e8 100644 +--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c ++++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +@@ -637,6 +637,10 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, + struct amdgpu_mqd_prop *prop) + { + struct amdgpu_device *adev = ring->adev; ++ bool is_high_prio_compute = ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && ++ amdgpu_gfx_is_high_priority_compute_queue(adev, ring); ++ bool is_high_prio_gfx = ring->funcs->type == AMDGPU_RING_TYPE_GFX && ++ amdgpu_gfx_is_high_priority_graphics_queue(adev, ring); + + memset(prop, 0, sizeof(*prop)); + +@@ -654,10 +658,8 @@ static void amdgpu_ring_to_mqd_prop(struct amdgpu_ring *ring, + */ + prop->hqd_active = ring->funcs->type == AMDGPU_RING_TYPE_KIQ; + +- if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE && +- amdgpu_gfx_is_high_priority_compute_queue(adev, ring)) || +- (ring->funcs->type == AMDGPU_RING_TYPE_GFX && +- amdgpu_gfx_is_high_priority_graphics_queue(adev, ring))) { ++ prop->allow_tunneling = is_high_prio_compute; ++ if (is_high_prio_compute || is_high_prio_gfx) { + prop->hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH; + prop->hqd_queue_priority = AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM; + } +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +index 8256f80d468dd..fc58924e8a5e0 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +@@ -6572,7 +6572,8 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m, + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1); + #endif + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); +- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); ++ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, ++ prop->allow_tunneling); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + mqd->cp_hqd_pq_control = tmp; +diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +index da21bf868080e..6d4dbb3f0e381 100644 +--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c ++++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +@@ -3795,7 +3795,8 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m, + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, + (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); +- tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); ++ tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, ++ prop->allow_tunneling); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); + mqd->cp_hqd_pq_control = tmp; +-- +GitLab + |