diff options
Diffstat (limited to 'SOURCES/0001-amd-hdr.patch')
| -rw-r--r-- | SOURCES/0001-amd-hdr.patch | 657 |
1 files changed, 346 insertions, 311 deletions
diff --git a/SOURCES/0001-amd-hdr.patch b/SOURCES/0001-amd-hdr.patch index c6fc3af..acc6afb 100644 --- a/SOURCES/0001-amd-hdr.patch +++ b/SOURCES/0001-amd-hdr.patch @@ -1,30 +1,33 @@ -From a890fe8f821eab96408c2263320e1106d5263f10 Mon Sep 17 00:00:00 2001 -From: Thomas Crider <gloriouseggroll@gmail.com> -Date: Wed, 6 Dec 2023 17:09:52 -0500 -Subject: [PATCH] hdr +From 272e1aeab63b855ed4b42f2a135497a83af72996 Mon Sep 17 00:00:00 2001 +From: Peter Jung <admin@ptr1337.dev> +Date: Fri, 22 Dec 2023 17:52:44 +0100 +Subject: [PATCH 1/8] amd-hdr +Signed-off-by: Peter Jung <admin@ptr1337.dev> --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 71 ++ drivers/gpu/drm/amd/display/Kconfig | 7 + - .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 35 +- - .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 100 +++ - .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 812 ++++++++++++++++-- - .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 72 ++ - .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 234 ++++- - .../amd/display/dc/dcn10/dcn10_cm_common.c | 95 +- - .../amd/display/dc/dcn10/dcn10_hw_sequencer.c | 14 +- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 69 +- + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 94 +++ + .../amd/display/amdgpu_dm/amdgpu_dm_color.c | 718 ++++++++++++++++-- + .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 73 +- + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 228 +++++- + .../amd/display/dc/dcn10/dcn10_cm_common.c | 95 ++- + .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 14 +- .../gpu/drm/amd/display/include/fixed31_32.h | 12 + drivers/gpu/drm/arm/malidp_crtc.c | 2 +- drivers/gpu/drm/drm_atomic.c | 1 + drivers/gpu/drm/drm_atomic_state_helper.c | 1 + + drivers/gpu/drm/drm_atomic_uapi.c | 52 +- drivers/gpu/drm/drm_property.c | 49 ++ include/drm/drm_mode_object.h | 2 +- include/drm/drm_plane.h | 7 + include/drm/drm_property.h | 6 + include/uapi/drm/drm_mode.h | 8 + + 19 files changed, 1364 insertions(+), 145 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h -index 32fe05c81..84bf501b0 100644 +index 32fe05c810c6..60440a31142a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -343,6 +343,77 @@ struct amdgpu_mode_info { @@ -34,8 +37,13 @@ index 32fe05c81..84bf501b0 100644 + + /* Driver-private color mgmt props */ + ++ /* @regamma_tf_property: Transfer function for CRTC regamma ++ * (post-blending). Possible values are defined by `enum ++ * amdgpu_transfer_function`. ++ */ ++ struct drm_property *regamma_tf_property; + /* @plane_degamma_lut_property: Plane property to set a degamma LUT to -+ * convert input space before blending. ++ * convert color space before blending. + */ + struct drm_property *plane_degamma_lut_property; + /* @plane_degamma_lut_size_property: Plane property to define the max @@ -43,8 +51,8 @@ index 32fe05c81..84bf501b0 100644 + */ + struct drm_property *plane_degamma_lut_size_property; + /** -+ * @plane_degamma_tf_property: Plane pre-defined transfer function to -+ * to go from scanout/encoded values to linear values. ++ * @plane_degamma_tf_property: Predefined transfer function to ++ * linearize content with or without LUT. + */ + struct drm_property *plane_degamma_tf_property; + /** @@ -97,16 +105,11 @@ index 32fe05c81..84bf501b0 100644 + * with or without LUT. + */ + struct drm_property *plane_blend_tf_property; -+ /* @regamma_tf_property: Transfer function for CRTC regamma -+ * (post-blending). Possible values are defined by `enum -+ * amdgpu_transfer_function`. -+ */ -+ struct drm_property *regamma_tf_property; }; #define AMDGPU_MAX_BL_LEVEL 0xFF diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig -index 901d1961b..49523fa82 100644 +index 901d1961b739..49523fa82f92 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -51,4 +51,11 @@ config DRM_AMD_SECURE_DISPLAY @@ -122,10 +125,10 @@ index 901d1961b..49523fa82 100644 + endmenu diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -index deedcd997..ccd99545b 100644 +index 4e82ee4d74ac..751929d9a63b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c -@@ -2963,6 +2963,7 @@ static int dm_resume(void *handle) +@@ -2969,6 +2969,7 @@ static int dm_resume(void *handle) dc_stream_release(dm_new_crtc_state->stream); dm_new_crtc_state->stream = NULL; } @@ -133,7 +136,7 @@ index deedcd997..ccd99545b 100644 } for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) { -@@ -4022,6 +4023,11 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) +@@ -4029,6 +4030,11 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) return r; } @@ -145,7 +148,7 @@ index deedcd997..ccd99545b 100644 r = amdgpu_dm_audio_init(adev); if (r) { dc_release_state(state->context); -@@ -5094,7 +5100,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, +@@ -5106,7 +5112,9 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ @@ -156,7 +159,16 @@ index deedcd997..ccd99545b 100644 if (ret) return ret; -@@ -8117,6 +8125,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, +@@ -8113,7 +8121,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, + int planes_count = 0, vpos, hpos; + unsigned long flags; + u32 target_vblank, last_flip_vblank; +- bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state); ++ bool vrr_active = true;//amdgpu_dm_crtc_vrr_active(acrtc_state); + bool cursor_update = false; + bool pflip_present = false; + bool dirty_rects_changed = false; +@@ -8175,6 +8183,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->surface_updates[planes_count].gamma = dc_plane->gamma_correction; bundle->surface_updates[planes_count].in_transfer_func = dc_plane->in_transfer_func; bundle->surface_updates[planes_count].gamut_remap_matrix = &dc_plane->gamut_remap_matrix; @@ -167,7 +179,7 @@ index deedcd997..ccd99545b 100644 } amdgpu_dm_plane_fill_dc_scaling_info(dm->adev, new_plane_state, -@@ -8328,6 +8340,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, +@@ -8386,6 +8398,10 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, &acrtc_state->stream->csc_color_matrix; bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; @@ -178,7 +190,7 @@ index deedcd997..ccd99545b 100644 } acrtc_state->stream->abm_level = acrtc_state->abm_level; -@@ -9516,6 +9532,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, +@@ -9587,6 +9603,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, * when a modeset is needed, to ensure it gets reprogrammed. */ if (dm_new_crtc_state->base.color_mgmt_changed || @@ -186,7 +198,7 @@ index deedcd997..ccd99545b 100644 drm_atomic_crtc_needs_modeset(new_crtc_state)) { ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); if (ret) -@@ -9583,6 +9600,10 @@ static bool should_reset_plane(struct drm_atomic_state *state, +@@ -9654,6 +9671,10 @@ static bool should_reset_plane(struct drm_atomic_state *state, */ for_each_oldnew_plane_in_state(state, other, old_other_state, new_other_state, i) { struct amdgpu_framebuffer *old_afb, *new_afb; @@ -197,7 +209,7 @@ index deedcd997..ccd99545b 100644 if (other->type == DRM_PLANE_TYPE_CURSOR) continue; -@@ -9619,6 +9640,18 @@ static bool should_reset_plane(struct drm_atomic_state *state, +@@ -9690,6 +9711,18 @@ static bool should_reset_plane(struct drm_atomic_state *state, old_other_state->color_encoding != new_other_state->color_encoding) return true; @@ -216,40 +228,80 @@ index deedcd997..ccd99545b 100644 /* Framebuffer checks fall at the end. */ if (!old_other_state->fb || !new_other_state->fb) continue; +@@ -10183,6 +10216,21 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, + } + } + } ++ ++ /* Propogate CM reset state */ ++ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { ++ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); ++ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); ++ ++ if (dm_old_crtc_state->cm_needs_reset || dm_new_crtc_state->cm_needs_reset) ++ { ++ dm_old_crtc_state->cm_needs_reset = false; ++ dm_new_crtc_state->cm_needs_reset = false; ++ ++ dm_new_crtc_state->base.color_mgmt_changed = true; ++ } ++ } ++ + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { + dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); + +@@ -10544,6 +10592,23 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, + return ret; + + fail: ++ for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { ++ /* ++ * If we failed our commit, if our new crtc was dirty color-wise, make sure we forward that ++ * dirty bit on our old state now so we don't forget to revert the work we did before ++ * we failed this commit on the next commit. ++ * ++ * Store it on old and new state so we don't lose track of it for this CRTC. ++ */ ++ dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); ++ dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); ++ ++ if (new_crtc_state->color_mgmt_changed) { ++ dm_old_crtc_state->cm_needs_reset = true; ++ dm_new_crtc_state->cm_needs_reset = true; ++ } ++ } ++ + if (ret == -EDEADLK) + DRM_DEBUG_DRIVER("Atomic check stopped to avoid deadlock.\n"); + else if (ret == -EINTR || ret == -EAGAIN || ret == -ERESTARTSYS) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h -index 9e4cc5eed..24c87f425 100644 +index 3d480be802cb..71936638d820 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h -@@ -33,6 +33,8 @@ - #include <drm/drm_plane.h> - #include "link_service_types.h" - +@@ -54,6 +54,7 @@ + #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A + #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 + #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_VERSION_3 0x3 +#define AMDGPU_HDR_MULT_DEFAULT (0x100000000LL) -+ /* - * This file contains the definition for amdgpu_display_manager - * and its API for amdgpu driver's use. -@@ -716,9 +718,91 @@ static inline void amdgpu_dm_set_mst_status(uint8_t *status, + #include "include/amdgpu_dal_power_if.h" + #include "amdgpu_dm_irq.h" +@@ -716,9 +717,85 @@ static inline void amdgpu_dm_set_mst_status(uint8_t *status, extern const struct amdgpu_ip_block_version dm_ip_block; +enum amdgpu_transfer_function { + AMDGPU_TRANSFER_FUNCTION_DEFAULT, -+ AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_BT709_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_PQ_EOTF, ++ AMDGPU_TRANSFER_FUNCTION_SRGB, ++ AMDGPU_TRANSFER_FUNCTION_BT709, ++ AMDGPU_TRANSFER_FUNCTION_PQ, + AMDGPU_TRANSFER_FUNCTION_LINEAR, + AMDGPU_TRANSFER_FUNCTION_UNITY, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF, -+ AMDGPU_TRANSFER_FUNCTION_COUNT ++ AMDGPU_TRANSFER_FUNCTION_HLG, ++ AMDGPU_TRANSFER_FUNCTION_GAMMA22, ++ AMDGPU_TRANSFER_FUNCTION_GAMMA24, ++ AMDGPU_TRANSFER_FUNCTION_GAMMA26, ++ AMDGPU_TRANSFER_FUNCTION_MAX, +}; + struct dm_plane_state { @@ -260,8 +312,7 @@ index 9e4cc5eed..24c87f425 100644 + /** + * @degamma_lut: + * -+ * 1D LUT for mapping framebuffer/plane pixel data before sampling or -+ * blending operations. It's usually applied to linearize input space. ++ * LUT for converting plane pixel data before going into plane merger. + * The blob (if not NULL) is an array of &struct drm_color_lut. + */ + struct drm_property_blob *degamma_lut; @@ -321,10 +372,11 @@ index 9e4cc5eed..24c87f425 100644 }; struct dm_crtc_state { -@@ -743,6 +827,14 @@ struct dm_crtc_state { +@@ -743,6 +820,15 @@ struct dm_crtc_state { struct dc_info_packet vrr_infopacket; int abm_level; ++ bool cm_needs_reset; + + /** + * @regamma_tf: @@ -336,7 +388,7 @@ index 9e4cc5eed..24c87f425 100644 }; #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) -@@ -804,14 +896,22 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, +@@ -804,14 +890,22 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, void amdgpu_dm_trigger_timing_sync(struct drm_device *dev); @@ -360,7 +412,7 @@ index 9e4cc5eed..24c87f425 100644 void amdgpu_dm_update_connector_after_detect( diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c -index a4cb23d05..10fef576c 100644 +index a4cb23d059bd..86a2d449cf07 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -72,6 +72,7 @@ @@ -371,116 +423,38 @@ index a4cb23d05..10fef576c 100644 /** * amdgpu_dm_init_color_mod - Initialize the color module. -@@ -84,6 +85,213 @@ void amdgpu_dm_init_color_mod(void) +@@ -84,6 +85,134 @@ void amdgpu_dm_init_color_mod(void) setup_x_points_distribution(); } +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK -+/* Pre-defined Transfer Functions (TF) -+ * -+ * AMD driver supports pre-defined mathematical functions for transferring -+ * between encoded values and optical/linear space. Depending on HW color caps, -+ * ROMs and curves built by the AMD color module support these transforms. -+ * -+ * The driver-specific color implementation exposes properties for pre-blending -+ * degamma TF, shaper TF (before 3D LUT), and blend(dpp.ogam) TF and -+ * post-blending regamma (mpc.ogam) TF. However, only pre-blending degamma -+ * supports ROM curves. AMD color module uses pre-defined coefficients to build -+ * curves for the other blocks. What can be done by each color block is -+ * described by struct dpp_color_capsand struct mpc_color_caps. -+ * -+ * AMD driver-specific color API exposes the following pre-defined transfer -+ * functions: -+ * -+ * - Linear/Unity: linear/identity relationship between pixel value and -+ * luminance value; -+ * - Gamma 2.2, Gamma 2.4, Gamma 2.6: pure gamma functions; -+ * - sRGB: 2.4 gamma with small initial linear section as standardized by IEC -+ * 61966-2-1:1999; -+ * - BT.709 (BT.1886): 2.4 gamma with differences in the dark end of the scale. -+ * Used in HD-TV and standardized by ITU-R BT.1886; -+ * - PQ (Perceptual Quantizer): used for HDR display, allows luminance range -+ * capability of 0 to 10,000 nits; standardized by SMPTE ST 2084. -+ * -+ * In the driver-specific API, color block names attached to TF properties -+ * suggest the intention regarding non-linear encoding pixel's luminance -+ * values. As some newer encodings don't use gamma curve, we make encoding and -+ * decoding explicit by defining an enum list of transfer functions supported -+ * in terms of EOTF and inverse EOTF, where: -+ * -+ * - EOTF (electro-optical transfer function): is the transfer function to go -+ * from the encoded value to an optical (linear) value. De-gamma functions -+ * traditionally do this. -+ * - Inverse EOTF (simply the inverse of the EOTF): is usually intended to go -+ * from an optical/linear space (which might have been used for blending) -+ * back to the encoded values. Gamma functions traditionally do this. -+ */ -+static const char * const -+amdgpu_transfer_function_names[] = { -+ [AMDGPU_TRANSFER_FUNCTION_DEFAULT] = "Default", -+ [AMDGPU_TRANSFER_FUNCTION_LINEAR] = "Linear", -+ [AMDGPU_TRANSFER_FUNCTION_UNITY] = "Unity", -+ [AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF] = "sRGB EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_BT709_EOTF] = "BT.709 EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_PQ_EOTF] = "PQ EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF] = "Gamma 2.2 EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF] = "Gamma 2.4 EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF] = "Gamma 2.6 EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF] = "sRGB inv_EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF] = "BT.709 inv_EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF] = "PQ inv_EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF] = "Gamma 2.2 inv_EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF] = "Gamma 2.4 inv_EOTF", -+ [AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF] = "Gamma 2.6 inv_EOTF", ++static const struct drm_prop_enum_list amdgpu_transfer_function_enum_list[] = { ++ { AMDGPU_TRANSFER_FUNCTION_DEFAULT, "Default" }, ++ { AMDGPU_TRANSFER_FUNCTION_SRGB, "sRGB" }, ++ { AMDGPU_TRANSFER_FUNCTION_BT709, "BT.709" }, ++ { AMDGPU_TRANSFER_FUNCTION_PQ, "PQ (Perceptual Quantizer)" }, ++ { AMDGPU_TRANSFER_FUNCTION_LINEAR, "Linear" }, ++ { AMDGPU_TRANSFER_FUNCTION_UNITY, "Unity" }, ++ { AMDGPU_TRANSFER_FUNCTION_HLG, "HLG (Hybrid Log Gamma)" }, ++ { AMDGPU_TRANSFER_FUNCTION_GAMMA22, "Gamma 2.2" }, ++ { AMDGPU_TRANSFER_FUNCTION_GAMMA24, "Gamma 2.4" }, ++ { AMDGPU_TRANSFER_FUNCTION_GAMMA26, "Gamma 2.6" }, +}; + -+static const u32 amdgpu_eotf = -+ BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_BT709_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_PQ_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF); -+ -+static const u32 amdgpu_inv_eotf = -+ BIT(AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF); -+ -+static struct drm_property * -+amdgpu_create_tf_property(struct drm_device *dev, -+ const char *name, -+ u32 supported_tf) -+{ -+ u32 transfer_functions = supported_tf | -+ BIT(AMDGPU_TRANSFER_FUNCTION_DEFAULT) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_LINEAR) | -+ BIT(AMDGPU_TRANSFER_FUNCTION_UNITY); -+ struct drm_prop_enum_list enum_list[AMDGPU_TRANSFER_FUNCTION_COUNT]; -+ int i, len; -+ -+ len = 0; -+ for (i = 0; i < AMDGPU_TRANSFER_FUNCTION_COUNT; i++) { -+ if ((transfer_functions & BIT(i)) == 0) -+ continue; -+ -+ enum_list[len].type = i; -+ enum_list[len].name = amdgpu_transfer_function_names[i]; -+ len++; -+ } -+ -+ return drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, -+ name, enum_list, len); -+} -+ +int +amdgpu_dm_create_color_properties(struct amdgpu_device *adev) +{ + struct drm_property *prop; + ++ prop = drm_property_create_enum(adev_to_drm(adev), ++ DRM_MODE_PROP_ENUM, ++ "VALVE1_CRTC_REGAMMA_TF", ++ amdgpu_transfer_function_enum_list, ++ ARRAY_SIZE(amdgpu_transfer_function_enum_list)); ++ if (!prop) ++ return -ENOMEM; ++ adev->mode_info.regamma_tf_property = prop; ++ + prop = drm_property_create(adev_to_drm(adev), + DRM_MODE_PROP_BLOB, + "VALVE1_PLANE_DEGAMMA_LUT", 0); @@ -495,9 +469,11 @@ index a4cb23d05..10fef576c 100644 + return -ENOMEM; + adev->mode_info.plane_degamma_lut_size_property = prop; + -+ prop = amdgpu_create_tf_property(adev_to_drm(adev), -+ "VALVE1_PLANE_DEGAMMA_TF", -+ amdgpu_eotf); ++ prop = drm_property_create_enum(adev_to_drm(adev), ++ DRM_MODE_PROP_ENUM, ++ "VALVE1_PLANE_DEGAMMA_TF", ++ amdgpu_transfer_function_enum_list, ++ ARRAY_SIZE(amdgpu_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_degamma_tf_property = prop; @@ -529,9 +505,11 @@ index a4cb23d05..10fef576c 100644 + return -ENOMEM; + adev->mode_info.plane_shaper_lut_size_property = prop; + -+ prop = amdgpu_create_tf_property(adev_to_drm(adev), -+ "VALVE1_PLANE_SHAPER_TF", -+ amdgpu_inv_eotf); ++ prop = drm_property_create_enum(adev_to_drm(adev), ++ DRM_MODE_PROP_ENUM, ++ "VALVE1_PLANE_SHAPER_TF", ++ amdgpu_transfer_function_enum_list, ++ ARRAY_SIZE(amdgpu_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_shaper_tf_property = prop; @@ -564,20 +542,15 @@ index a4cb23d05..10fef576c 100644 + return -ENOMEM; + adev->mode_info.plane_blend_lut_size_property = prop; + -+ prop = amdgpu_create_tf_property(adev_to_drm(adev), -+ "VALVE1_PLANE_BLEND_TF", -+ amdgpu_eotf); ++ prop = drm_property_create_enum(adev_to_drm(adev), ++ DRM_MODE_PROP_ENUM, ++ "VALVE1_PLANE_BLEND_TF", ++ amdgpu_transfer_function_enum_list, ++ ARRAY_SIZE(amdgpu_transfer_function_enum_list)); + if (!prop) + return -ENOMEM; + adev->mode_info.plane_blend_tf_property = prop; + -+ prop = amdgpu_create_tf_property(adev_to_drm(adev), -+ "VALVE1_CRTC_REGAMMA_TF", -+ amdgpu_inv_eotf); -+ if (!prop) -+ return -ENOMEM; -+ adev->mode_info.regamma_tf_property = prop; -+ + return 0; +} +#endif @@ -585,7 +558,7 @@ index a4cb23d05..10fef576c 100644 /** * __extract_blob_lut - Extracts the DRM lut and lut size from a blob. * @blob: DRM color mgmt property blob -@@ -182,7 +390,6 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, +@@ -182,7 +311,6 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, struct fixed31_32 *matrix) { @@ -593,7 +566,7 @@ index a4cb23d05..10fef576c 100644 int i; /* -@@ -201,12 +408,33 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, +@@ -201,12 +329,33 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, } /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */ @@ -604,7 +577,8 @@ index a4cb23d05..10fef576c 100644 + matrix[i] = dc_fixpt_from_s3132(ctm->matrix[i - (i / 4)]); + } +} -+ + +- matrix[i].value = val; +/** + * __drm_ctm2_to_dc_matrix - converts a DRM CTM2 to a DC CSC float matrix + * @ctm: DRM color transformation matrix @@ -616,8 +590,7 @@ index a4cb23d05..10fef576c 100644 + struct fixed31_32 *matrix) +{ + int i; - -- matrix[i].value = val; ++ + /* + * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating + * with homogeneous coordinates, augment the matrix with 0's. @@ -632,7 +605,7 @@ index a4cb23d05..10fef576c 100644 } } -@@ -268,16 +496,18 @@ static int __set_output_tf(struct dc_transfer_func *func, +@@ -268,16 +417,18 @@ static int __set_output_tf(struct dc_transfer_func *func, struct calculate_buffer cal_buffer = {0}; bool res; @@ -658,7 +631,7 @@ index a4cb23d05..10fef576c 100644 if (func->tf == TRANSFER_FUNCTION_LINEAR) { /* -@@ -285,27 +515,63 @@ static int __set_output_tf(struct dc_transfer_func *func, +@@ -285,27 +436,63 @@ static int __set_output_tf(struct dc_transfer_func *func, * on top of a linear input. But degamma params can be used * instead to simulate this. */ @@ -727,7 +700,7 @@ index a4cb23d05..10fef576c 100644 * @func: transfer function * @lut: lookup table that defines the color space * @lut_size: size of respective lut. -@@ -313,27 +579,249 @@ static int __set_output_tf(struct dc_transfer_func *func, +@@ -313,27 +500,235 @@ static int __set_output_tf(struct dc_transfer_func *func, * Returns: * 0 in case of success. -ENOMEM if fails. */ @@ -750,50 +723,36 @@ index a4cb23d05..10fef576c 100644 - gamma->num_entries = lut_size; + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; -+ -+ __drm_lut_to_dc_gamma(lut, gamma, false); -+ } - __drm_lut_to_dc_gamma(lut, gamma, false); -+ res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL); ++ __drm_lut_to_dc_gamma(lut, gamma, false); ++ } - res = mod_color_calculate_degamma_params(NULL, func, gamma, true); - dc_gamma_release(&gamma); ++ res = mod_color_calculate_degamma_params(caps, func, gamma, gamma != NULL); ++ + if (gamma) + dc_gamma_release(&gamma); return res ? 0 : -ENOMEM; } -+static enum dc_transfer_func_predefined -+amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) ++static enum dc_transfer_func_predefined amdgpu_tf_to_dc_tf(enum amdgpu_transfer_function tf) +{ + switch (tf) + { + default: -+ case AMDGPU_TRANSFER_FUNCTION_DEFAULT: -+ case AMDGPU_TRANSFER_FUNCTION_LINEAR: -+ return TRANSFER_FUNCTION_LINEAR; -+ case AMDGPU_TRANSFER_FUNCTION_SRGB_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_SRGB_INV_EOTF: -+ return TRANSFER_FUNCTION_SRGB; -+ case AMDGPU_TRANSFER_FUNCTION_BT709_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_BT709_INV_EOTF: -+ return TRANSFER_FUNCTION_BT709; -+ case AMDGPU_TRANSFER_FUNCTION_PQ_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_PQ_INV_EOTF: -+ return TRANSFER_FUNCTION_PQ; -+ case AMDGPU_TRANSFER_FUNCTION_UNITY: -+ return TRANSFER_FUNCTION_UNITY; -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA22_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA22_INV_EOTF: -+ return TRANSFER_FUNCTION_GAMMA22; -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA24_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA24_INV_EOTF: -+ return TRANSFER_FUNCTION_GAMMA24; -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA26_EOTF: -+ case AMDGPU_TRANSFER_FUNCTION_GAMMA26_INV_EOTF: -+ return TRANSFER_FUNCTION_GAMMA26; ++ case AMDGPU_TRANSFER_FUNCTION_DEFAULT: return TRANSFER_FUNCTION_LINEAR; ++ case AMDGPU_TRANSFER_FUNCTION_SRGB: return TRANSFER_FUNCTION_SRGB; ++ case AMDGPU_TRANSFER_FUNCTION_BT709: return TRANSFER_FUNCTION_BT709; ++ case AMDGPU_TRANSFER_FUNCTION_PQ: return TRANSFER_FUNCTION_PQ; ++ case AMDGPU_TRANSFER_FUNCTION_LINEAR: return TRANSFER_FUNCTION_LINEAR; ++ case AMDGPU_TRANSFER_FUNCTION_UNITY: return TRANSFER_FUNCTION_UNITY; ++ case AMDGPU_TRANSFER_FUNCTION_HLG: return TRANSFER_FUNCTION_HLG; ++ case AMDGPU_TRANSFER_FUNCTION_GAMMA22: return TRANSFER_FUNCTION_GAMMA22; ++ case AMDGPU_TRANSFER_FUNCTION_GAMMA24: return TRANSFER_FUNCTION_GAMMA24; ++ case AMDGPU_TRANSFER_FUNCTION_GAMMA26: return TRANSFER_FUNCTION_GAMMA26; + } +} + @@ -986,7 +945,7 @@ index a4cb23d05..10fef576c 100644 /** * amdgpu_dm_verify_lut_sizes - verifies if DRM luts match the hw supported sizes * @crtc_state: the DRM CRTC state -@@ -401,9 +889,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +@@ -401,9 +796,12 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) const struct drm_color_lut *degamma_lut, *regamma_lut; uint32_t degamma_size, regamma_size; bool has_regamma, has_degamma; @@ -999,7 +958,7 @@ index a4cb23d05..10fef576c 100644 r = amdgpu_dm_verify_lut_sizes(&crtc->base); if (r) return r; -@@ -440,26 +931,22 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +@@ -440,26 +838,22 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; @@ -1036,7 +995,7 @@ index a4cb23d05..10fef576c 100644 } /* -@@ -495,20 +982,10 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +@@ -495,20 +889,10 @@ int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) return 0; } @@ -1061,7 +1020,7 @@ index a4cb23d05..10fef576c 100644 { const struct drm_color_lut *degamma_lut; enum dc_transfer_func_predefined tf = TRANSFER_FUNCTION_SRGB; -@@ -531,8 +1008,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, +@@ -531,8 +915,7 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, °amma_size); ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); @@ -1071,7 +1030,7 @@ index a4cb23d05..10fef576c 100644 /* * This case isn't fully correct, but also fairly -@@ -564,11 +1040,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, +@@ -564,11 +947,11 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; @@ -1085,7 +1044,7 @@ index a4cb23d05..10fef576c 100644 /* * For legacy gamma support we need the regamma input * in linear space. Assume that the input is sRGB. -@@ -577,14 +1053,220 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, +@@ -577,14 +960,219 @@ int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, dc_plane_state->in_transfer_func->tf = tf; if (tf != TRANSFER_FUNCTION_SRGB && @@ -1094,11 +1053,15 @@ index a4cb23d05..10fef576c 100644 + !mod_color_calculate_degamma_params(caps, + dc_plane_state->in_transfer_func, + NULL, false)) -+ return -ENOMEM; -+ } -+ -+ return 0; -+} + return -ENOMEM; +- } else { +- /* ...Otherwise we can just bypass the DGM block. */ +- dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; +- dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + return 0; + } + +static int +__set_dm_plane_degamma(struct drm_plane_state *plane_state, @@ -1144,11 +1107,7 @@ index a4cb23d05..10fef576c 100644 + + if (!mod_color_calculate_degamma_params(color_caps, + dc_plane_state->in_transfer_func, NULL, false)) - return -ENOMEM; -- } else { -- /* ...Otherwise we can just bypass the DGM block. */ -- dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; -- dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; ++ return -ENOMEM; + } + return 0; +} @@ -1193,7 +1152,6 @@ index a4cb23d05..10fef576c 100644 + drm_dbg_kms(plane_state->plane->dev, + "setting plane %d shaper LUT failed.\n", + plane_state->plane->index); -+ + return ret; + } + @@ -1210,10 +1168,10 @@ index a4cb23d05..10fef576c 100644 + plane_state->plane->index); + + return ret; - } - - return 0; - } ++ } ++ ++ return 0; ++} + +/** + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. @@ -1313,18 +1271,29 @@ index a4cb23d05..10fef576c 100644 + dc_plane_state, color_caps); +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c -index 97b7a0b8a..f1707c774 100644 +index cb0b48bb2a7d..b131f9465761 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c -@@ -260,6 +260,7 @@ static struct drm_crtc_state *dm_crtc_duplicate_state(struct drm_crtc *crtc) +@@ -226,7 +226,6 @@ static void amdgpu_dm_crtc_destroy_state(struct drm_crtc *crtc, + if (cur->stream) + dc_stream_release(cur->stream); + +- + __drm_atomic_helper_crtc_destroy_state(state); + + +@@ -260,8 +259,10 @@ static struct drm_crtc_state *amdgpu_dm_crtc_duplicate_state(struct drm_crtc *cr state->freesync_config = cur->freesync_config; state->cm_has_degamma = cur->cm_has_degamma; state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; + state->regamma_tf = cur->regamma_tf; state->crc_skip_count = cur->crc_skip_count; state->mpo_requested = cur->mpo_requested; ++ state->cm_needs_reset = cur->cm_needs_reset; /* TODO Duplicate dc_stream after objects are stream object is flattened */ -@@ -296,6 +296,70 @@ + + return &state->base; +@@ -296,6 +297,69 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) } #endif @@ -1333,10 +1302,9 @@ index 97b7a0b8a..f1707c774 100644 + * drm_crtc_additional_color_mgmt - enable additional color properties + * @crtc: DRM CRTC + * -+ * This function lets the driver enable post-blending CRTC regamma transfer -+ * function property in addition to DRM CRTC gamma LUT. Default value means -+ * linear transfer function, which is the default CRTC gamma LUT behaviour -+ * without this property. ++ * This function lets the driver enable the 3D LUT color correction property ++ * on a CRTC. This includes shaper LUT, 3D LUT and regamma TF. The shaper ++ * LUT and 3D LUT property is only attached if its size is not 0. + */ +static void +dm_crtc_additional_color_mgmt(struct drm_crtc *crtc) @@ -1395,7 +1363,7 @@ index 97b7a0b8a..f1707c774 100644 /* Implemented only the options currently available for the driver */ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = amdgpu_dm_crtc_reset_state, -@@ -314,6 +379,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { +@@ -314,6 +378,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif @@ -1406,7 +1374,7 @@ index 97b7a0b8a..f1707c774 100644 }; static void amdgpu_dm_crtc_helper_disable(struct drm_crtc *crtc) -@@ -489,6 +558,9 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, +@@ -489,6 +557,9 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES); @@ -1417,10 +1385,10 @@ index 97b7a0b8a..f1707c774 100644 fail: diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -index cc74dd69a..2ed20e6e4 100644 +index 116121e647ca..35d78447452f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -@@ -1337,8 +1337,14 @@ +@@ -1337,8 +1337,14 @@ static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL); WARN_ON(amdgpu_state == NULL); @@ -1437,7 +1405,7 @@ index cc74dd69a..2ed20e6e4 100644 } static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct drm_plane *plane) -@@ -1354,6 +1360,32 @@ dm_drm_plane_duplicate_state(struct drm_plane *plane) +@@ -1357,6 +1363,32 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct dc_plane_state_retain(dm_plane_state->dc_state); } @@ -1470,7 +1438,7 @@ index cc74dd69a..2ed20e6e4 100644 return &dm_plane_state->base; } -@@ -1421,12 +1453,203 @@ static void dm_drm_plane_destroy_state(struct drm_plane *plane, +@@ -1424,12 +1456,197 @@ static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, { struct dm_plane_state *dm_plane_state = to_dm_plane_state(state); @@ -1493,18 +1461,14 @@ index cc74dd69a..2ed20e6e4 100644 +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK +static void -+amdgpu_dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, ++dm_atomic_plane_attach_color_mgmt_properties(struct amdgpu_display_manager *dm, + struct drm_plane *plane) +{ -+ struct amdgpu_mode_info mode_info = dm->adev->mode_info; -+ struct dpp_color_caps dpp_color_caps = dm->dc->caps.color.dpp; -+ -+ /* Check HW color pipeline capabilities for DPP (pre-blending) before expose*/ -+ if (dpp_color_caps.dgam_ram || dpp_color_caps.gamma_corr) { ++ if (dm->dc->caps.color.dpp.dgam_ram || dm->dc->caps.color.dpp.gamma_corr ) { + drm_object_attach_property(&plane->base, -+ mode_info.plane_degamma_lut_property, 0); ++ dm->adev->mode_info.plane_degamma_lut_property, 0); + drm_object_attach_property(&plane->base, -+ mode_info.plane_degamma_lut_size_property, ++ dm->adev->mode_info.plane_degamma_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, + dm->adev->mode_info.plane_degamma_tf_property, @@ -1515,41 +1479,39 @@ index cc74dd69a..2ed20e6e4 100644 + dm->adev->mode_info.plane_hdr_mult_property, + AMDGPU_HDR_MULT_DEFAULT); + -+ /* Only enable plane CTM if both DPP and MPC gamut remap is available. */ -+ if (dm->dc->caps.color.mpc.gamut_remap) -+ drm_object_attach_property(&plane->base, -+ dm->adev->mode_info.plane_ctm_property, 0); ++ drm_object_attach_property(&plane->base, ++ dm->adev->mode_info.plane_ctm_property, 0); + -+ if (dpp_color_caps.hw_3d_lut) { ++ if (dm->dc->caps.color.dpp.hw_3d_lut) { + drm_object_attach_property(&plane->base, -+ mode_info.plane_shaper_lut_property, 0); ++ dm->adev->mode_info.plane_shaper_lut_property, 0); + drm_object_attach_property(&plane->base, -+ mode_info.plane_shaper_lut_size_property, ++ dm->adev->mode_info.plane_shaper_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, -+ mode_info.plane_shaper_tf_property, ++ dm->adev->mode_info.plane_shaper_tf_property, + AMDGPU_TRANSFER_FUNCTION_DEFAULT); + drm_object_attach_property(&plane->base, -+ mode_info.plane_lut3d_property, 0); ++ dm->adev->mode_info.plane_lut3d_property, 0); + drm_object_attach_property(&plane->base, -+ mode_info.plane_lut3d_size_property, ++ dm->adev->mode_info.plane_lut3d_size_property, + MAX_COLOR_3DLUT_ENTRIES); + } + -+ if (dpp_color_caps.ogam_ram) { ++ if (dm->dc->caps.color.dpp.ogam_ram) { + drm_object_attach_property(&plane->base, -+ mode_info.plane_blend_lut_property, 0); ++ dm->adev->mode_info.plane_blend_lut_property, 0); + drm_object_attach_property(&plane->base, -+ mode_info.plane_blend_lut_size_property, ++ dm->adev->mode_info.plane_blend_lut_size_property, + MAX_COLOR_LUT_ENTRIES); + drm_object_attach_property(&plane->base, -+ mode_info.plane_blend_tf_property, ++ dm->adev->mode_info.plane_blend_tf_property, + AMDGPU_TRANSFER_FUNCTION_DEFAULT); + } +} + +static int -+amdgpu_dm_atomic_plane_set_property(struct drm_plane *plane, ++dm_atomic_plane_set_property(struct drm_plane *plane, + struct drm_plane_state *state, + struct drm_property *property, + uint64_t val) @@ -1631,7 +1593,7 @@ index cc74dd69a..2ed20e6e4 100644 +} + +static int -+amdgpu_dm_atomic_plane_get_property(struct drm_plane *plane, ++dm_atomic_plane_get_property(struct drm_plane *plane, + const struct drm_plane_state *state, + struct drm_property *property, + uint64_t *val) @@ -1674,29 +1636,29 @@ index cc74dd69a..2ed20e6e4 100644 static const struct drm_plane_funcs dm_plane_funcs = { .update_plane = drm_atomic_helper_update_plane, .disable_plane = drm_atomic_helper_disable_plane, -@@ -1658,6 +1881,10 @@ static const struct drm_plane_funcs dm_plane_funcs = { +@@ -1438,6 +1655,10 @@ static const struct drm_plane_funcs dm_plane_funcs = { .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK -+ .atomic_set_property = amdgpu_dm_atomic_plane_set_property, -+ .atomic_get_property = amdgpu_dm_atomic_plane_get_property, ++ .atomic_set_property = dm_atomic_plane_set_property, ++ .atomic_get_property = dm_atomic_plane_get_property, +#endif }; - + int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, -@@ -1514,6 +1741,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, +@@ -1517,6 +1738,9 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, drm_plane_helper_add(plane, &dm_plane_helper_funcs); +#ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK -+ amdgpu_dm_atomic_plane_attach_color_mgmt_properties(dm, plane); ++ dm_atomic_plane_attach_color_mgmt_properties(dm, plane); +#endif /* Create (reset) the plane state */ if (plane->funcs->reset) plane->funcs->reset(plane); diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c -index 3538973bd..04b2e04b6 100644 +index 3538973bd0c6..04b2e04b68f3 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -349,20 +349,37 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, @@ -1814,10 +1776,10 @@ index 3538973bd..04b2e04b6 100644 } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c -index 79befa17b..4daf8621b 100644 +index cdb903116eb7..eb45c178fe59 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c -@@ -2486,17 +2486,17 @@ void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) +@@ -2498,17 +2498,17 @@ void dcn10_program_gamut_remap(struct pipe_ctx *pipe_ctx) adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; @@ -1840,7 +1802,7 @@ index 79befa17b..4daf8621b 100644 } pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust); -@@ -2942,8 +2942,8 @@ void dcn10_program_pipe( +@@ -2954,8 +2954,8 @@ void dcn10_program_pipe( hws->funcs.set_hdr_multiplier(pipe_ctx); if (pipe_ctx->plane_state->update_flags.bits.full_update || @@ -1852,7 +1814,7 @@ index 79befa17b..4daf8621b 100644 /* dcn10_translate_regamma_to_hw_format takes 750us to finish diff --git a/drivers/gpu/drm/amd/display/include/fixed31_32.h b/drivers/gpu/drm/amd/display/include/fixed31_32.h -index d4cf7ead1..84da1dd34 100644 +index d4cf7ead1d87..84da1dd34efd 100644 --- a/drivers/gpu/drm/amd/display/include/fixed31_32.h +++ b/drivers/gpu/drm/amd/display/include/fixed31_32.h @@ -69,6 +69,18 @@ static const struct fixed31_32 dc_fixpt_epsilon = { 1LL }; @@ -1875,7 +1837,7 @@ index d4cf7ead1..84da1dd34 100644 * @brief * Initialization routines diff --git a/drivers/gpu/drm/arm/malidp_crtc.c b/drivers/gpu/drm/arm/malidp_crtc.c -index dc01c43f6..d72c22dcf 100644 +index dc01c43f6193..d72c22dcf685 100644 --- a/drivers/gpu/drm/arm/malidp_crtc.c +++ b/drivers/gpu/drm/arm/malidp_crtc.c @@ -221,7 +221,7 @@ static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc, @@ -1888,7 +1850,7 @@ index dc01c43f6..d72c22dcf 100644 ctm = (struct drm_color_ctm *)state->ctm->data; for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) { diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c -index c277b198f..c3df45f90 100644 +index f1a503aafe5a..e2bbdcb64389 100644 --- a/drivers/gpu/drm/drm_atomic.c +++ b/drivers/gpu/drm/drm_atomic.c @@ -733,6 +733,7 @@ static void drm_atomic_plane_print_state(struct drm_printer *p, @@ -1900,7 +1862,7 @@ index c277b198f..c3df45f90 100644 if (plane->funcs->atomic_print_state) plane->funcs->atomic_print_state(p, state); diff --git a/drivers/gpu/drm/drm_atomic_state_helper.c b/drivers/gpu/drm/drm_atomic_state_helper.c -index 784e63d70..25bb0859f 100644 +index 784e63d70a42..25bb0859fda7 100644 --- a/drivers/gpu/drm/drm_atomic_state_helper.c +++ b/drivers/gpu/drm/drm_atomic_state_helper.c @@ -338,6 +338,7 @@ void __drm_atomic_helper_plane_duplicate_state(struct drm_plane *plane, @@ -1911,8 +1873,106 @@ index 784e63d70..25bb0859f 100644 } EXPORT_SYMBOL(__drm_atomic_helper_plane_duplicate_state); +diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c +index 98d3b10c08ae..37caa6c33e22 100644 +--- a/drivers/gpu/drm/drm_atomic_uapi.c ++++ b/drivers/gpu/drm/drm_atomic_uapi.c +@@ -362,48 +362,6 @@ static s32 __user *get_out_fence_for_connector(struct drm_atomic_state *state, + return fence_ptr; + } + +-static int +-drm_atomic_replace_property_blob_from_id(struct drm_device *dev, +- struct drm_property_blob **blob, +- uint64_t blob_id, +- ssize_t expected_size, +- ssize_t expected_elem_size, +- bool *replaced) +-{ +- struct drm_property_blob *new_blob = NULL; +- +- if (blob_id != 0) { +- new_blob = drm_property_lookup_blob(dev, blob_id); +- if (new_blob == NULL) { +- drm_dbg_atomic(dev, +- "cannot find blob ID %llu\n", blob_id); +- return -EINVAL; +- } +- +- if (expected_size > 0 && +- new_blob->length != expected_size) { +- drm_dbg_atomic(dev, +- "[BLOB:%d] length %zu different from expected %zu\n", +- new_blob->base.id, new_blob->length, expected_size); +- drm_property_blob_put(new_blob); +- return -EINVAL; +- } +- if (expected_elem_size > 0 && +- new_blob->length % expected_elem_size != 0) { +- drm_dbg_atomic(dev, +- "[BLOB:%d] length %zu not divisible by element size %zu\n", +- new_blob->base.id, new_blob->length, expected_elem_size); +- drm_property_blob_put(new_blob); +- return -EINVAL; +- } +- } +- +- *replaced |= drm_property_replace_blob(blob, new_blob); +- drm_property_blob_put(new_blob); +- +- return 0; +-} +- + static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, + struct drm_crtc_state *state, struct drm_property *property, + uint64_t val) +@@ -424,7 +382,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, + } else if (property == config->prop_vrr_enabled) { + state->vrr_enabled = val; + } else if (property == config->degamma_lut_property) { +- ret = drm_atomic_replace_property_blob_from_id(dev, ++ ret = drm_property_replace_blob_from_id(dev, + &state->degamma_lut, + val, + -1, sizeof(struct drm_color_lut), +@@ -432,7 +390,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, + state->color_mgmt_changed |= replaced; + return ret; + } else if (property == config->ctm_property) { +- ret = drm_atomic_replace_property_blob_from_id(dev, ++ ret = drm_property_replace_blob_from_id(dev, + &state->ctm, + val, + sizeof(struct drm_color_ctm), -1, +@@ -440,7 +398,7 @@ static int drm_atomic_crtc_set_property(struct drm_crtc *crtc, + state->color_mgmt_changed |= replaced; + return ret; + } else if (property == config->gamma_lut_property) { +- ret = drm_atomic_replace_property_blob_from_id(dev, ++ ret = drm_property_replace_blob_from_id(dev, + &state->gamma_lut, + val, + -1, sizeof(struct drm_color_lut), +@@ -581,7 +539,7 @@ static int drm_atomic_plane_set_property(struct drm_plane *plane, + } else if (property == plane->color_range_property) { + state->color_range = val; + } else if (property == config->prop_fb_damage_clips) { +- ret = drm_atomic_replace_property_blob_from_id(dev, ++ ret = drm_property_replace_blob_from_id(dev, + &state->fb_damage_clips, + val, + -1, +@@ -758,7 +716,7 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector, + if (state->link_status != DRM_LINK_STATUS_GOOD) + state->link_status = val; + } else if (property == config->hdr_output_metadata_property) { +- ret = drm_atomic_replace_property_blob_from_id(dev, ++ ret = drm_property_replace_blob_from_id(dev, + &state->hdr_output_metadata, + val, + sizeof(struct hdr_output_metadata), -1, diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c -index dfec47983..f72ef6493 100644 +index dfec479830e4..f72ef6493340 100644 --- a/drivers/gpu/drm/drm_property.c +++ b/drivers/gpu/drm/drm_property.c @@ -751,6 +751,55 @@ bool drm_property_replace_blob(struct drm_property_blob **blob, @@ -1972,7 +2032,7 @@ index dfec47983..f72ef6493 100644 void *data, struct drm_file *file_priv) { diff --git a/include/drm/drm_mode_object.h b/include/drm/drm_mode_object.h -index 912f1e415..08d7a7f01 100644 +index 912f1e415685..08d7a7f0188f 100644 --- a/include/drm/drm_mode_object.h +++ b/include/drm/drm_mode_object.h @@ -60,7 +60,7 @@ struct drm_mode_object { @@ -1985,7 +2045,7 @@ index 912f1e415..08d7a7f01 100644 * struct drm_object_properties - property tracking for &drm_mode_object */ diff --git a/include/drm/drm_plane.h b/include/drm/drm_plane.h -index 79d62856d..4f87803b3 100644 +index 79d62856defb..4f87803b3ea1 100644 --- a/include/drm/drm_plane.h +++ b/include/drm/drm_plane.h @@ -237,6 +237,13 @@ struct drm_plane_state { @@ -2003,7 +2063,7 @@ index 79d62856d..4f87803b3 100644 static inline struct drm_rect diff --git a/include/drm/drm_property.h b/include/drm/drm_property.h -index 65bc9710a..082f29156 100644 +index 65bc9710a470..082f29156b3e 100644 --- a/include/drm/drm_property.h +++ b/include/drm/drm_property.h @@ -279,6 +279,12 @@ struct drm_property_blob *drm_property_create_blob(struct drm_device *dev, @@ -2020,7 +2080,7 @@ index 65bc9710a..082f29156 100644 struct drm_property_blob **replace, size_t length, diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h -index ea1b639bc..cea5653e4 100644 +index 128d09138ceb..75d2757517d8 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -846,6 +846,14 @@ struct drm_color_ctm { @@ -2041,28 +2101,3 @@ index ea1b639bc..cea5653e4 100644 -- 2.43.0 -From b938468f07222b4faab5ae5cf5391eccd9532bb0 Mon Sep 17 00:00:00 2001 -From: Bouke Sybren Haarsma <boukehaarsma23@gmail.com> -Date: Fri, 15 Dec 2023 11:14:58 +0100 -Subject: [PATCH] Don't create color_mgmt_properties on asics < SIENNA_CICHLID - ---- - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 ++- - 1 file changed, 2 insertions(+), 1 deletion(-) - -diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -index 2ed20e6e439bb5..65ee8745e96540 100644 ---- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c -@@ -1742,7 +1742,8 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, - drm_plane_helper_add(plane, &dm_plane_helper_funcs); - - #ifdef CONFIG_DRM_AMD_COLOR_STEAMDECK -- amdgpu_dm_atomic_plane_attach_color_mgmt_properties(dm, plane); -+ if (dm->adev->asic_type >= CHIP_SIENNA_CICHLID) -+ amdgpu_dm_atomic_plane_attach_color_mgmt_properties(dm, plane); - #endif - /* Create (reset) the plane state */ - if (plane->funcs->reset) --- -2.43.0 |