diff options
Diffstat (limited to 'SOURCES/0001-Revert-drm-i915-mtl-Add-fake-PCH-for-Meteor-Lake.patch')
| -rw-r--r-- | SOURCES/0001-Revert-drm-i915-mtl-Add-fake-PCH-for-Meteor-Lake.patch | 221 |
1 files changed, 221 insertions, 0 deletions
diff --git a/SOURCES/0001-Revert-drm-i915-mtl-Add-fake-PCH-for-Meteor-Lake.patch b/SOURCES/0001-Revert-drm-i915-mtl-Add-fake-PCH-for-Meteor-Lake.patch new file mode 100644 index 0000000..c01e878 --- /dev/null +++ b/SOURCES/0001-Revert-drm-i915-mtl-Add-fake-PCH-for-Meteor-Lake.patch @@ -0,0 +1,221 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Jan200101 <sentrycraft123@gmail.com> +Date: Tue, 9 Jul 2024 19:51:54 +0200 +Subject: [PATCH] Revert "drm/i915/mtl: Add fake PCH for Meteor Lake" + +This reverts commit 93cbc1accbcec2740231755774420934658e2b18. + +Signed-off-by: Jan200101 <sentrycraft123@gmail.com> +--- + drivers/gpu/drm/i915/display/intel_backlight.c | 2 +- + drivers/gpu/drm/i915/display/intel_bios.c | 3 ++- + drivers/gpu/drm/i915/display/intel_cdclk.c | 6 +++--- + drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- + drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++- + drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 6 ++++-- + drivers/gpu/drm/i915/display/intel_pps.c | 2 +- + drivers/gpu/drm/i915/soc/intel_pch.c | 16 ++++++++-------- + drivers/gpu/drm/i915/soc/intel_pch.h | 6 +++++- + 9 files changed, 29 insertions(+), 19 deletions(-) + +diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c +index 1946d7fb3c2e..3f3cd944a1c5 100644 +--- a/drivers/gpu/drm/i915/display/intel_backlight.c ++++ b/drivers/gpu/drm/i915/display/intel_backlight.c +@@ -1465,7 +1465,7 @@ static bool cnp_backlight_controller_is_valid(struct drm_i915_private *i915, int + + if (controller == 1 && + INTEL_PCH_TYPE(i915) >= PCH_ICP && +- INTEL_PCH_TYPE(i915) <= PCH_ADP) ++ INTEL_PCH_TYPE(i915) < PCH_MTP) + return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; + + return true; +diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c +index 7d1e443f97b9..02ec8e52dd7d 100644 +--- a/drivers/gpu/drm/i915/display/intel_bios.c ++++ b/drivers/gpu/drm/i915/display/intel_bios.c +@@ -2228,7 +2228,8 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) + if (IS_DGFX(i915)) + return vbt_pin; + +- if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { ++ if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) || ++ IS_ALDERLAKE_P(i915)) { + ddc_pin_map = adlp_ddc_pin_map; + n_entries = ARRAY_SIZE(adlp_ddc_pin_map); + } else if (IS_ALDERLAKE_S(i915)) { +diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c +index f672bfd70d45..789b3a379363 100644 +--- a/drivers/gpu/drm/i915/display/intel_cdclk.c ++++ b/drivers/gpu/drm/i915/display/intel_cdclk.c +@@ -3509,15 +3509,15 @@ u32 intel_read_rawclk(struct drm_i915_private *dev_priv) + { + u32 freq; + +- if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) ++ if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) ++ freq = dg1_rawclk(dev_priv); ++ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) + /* + * MTL always uses a 38.4 MHz rawclk. The bspec tells us + * "RAWCLK_FREQ defaults to the values for 38.4 and does + * not need to be programmed." + */ + freq = 38400; +- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) +- freq = dg1_rawclk(dev_priv); + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) + freq = cnp_rawclk(dev_priv); + else if (HAS_PCH_SPLIT(dev_priv)) +diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c +index f846c5b108b5..f950a87392cf 100644 +--- a/drivers/gpu/drm/i915/display/intel_display_irq.c ++++ b/drivers/gpu/drm/i915/display/intel_display_irq.c +@@ -986,7 +986,7 @@ static void gen8_read_and_ack_pch_irqs(struct drm_i915_private *i915, u32 *pch_i + * their flags both in the PICA and SDE IIR. + */ + if (*pch_iir & SDE_PICAINTERRUPT) { +- drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTL); ++ drm_WARN_ON(&i915->drm, INTEL_PCH_TYPE(i915) < PCH_MTP); + + pica_ier = intel_de_rmw(i915, PICAINTERRUPT_IER, ~0, 0); + *pica_iir = intel_de_read(i915, PICAINTERRUPT_IIR); +diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c +index d3e03ed5b79c..e9e4dcf345f9 100644 +--- a/drivers/gpu/drm/i915/display/intel_gmbus.c ++++ b/drivers/gpu/drm/i915/display/intel_gmbus.c +@@ -155,7 +155,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, + const struct gmbus_pin *pins; + size_t size; + +- if (INTEL_PCH_TYPE(i915) >= PCH_MTL) { ++ if (INTEL_PCH_TYPE(i915) >= PCH_LNL) { + pins = gmbus_pins_mtp; + size = ARRAY_SIZE(gmbus_pins_mtp); + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) { +@@ -164,6 +164,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915, + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + pins = gmbus_pins_dg1; + size = ARRAY_SIZE(gmbus_pins_dg1); ++ } else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) { ++ pins = gmbus_pins_mtp; ++ size = ARRAY_SIZE(gmbus_pins_mtp); + } else if (INTEL_PCH_TYPE(i915) >= PCH_ICP) { + pins = gmbus_pins_icp; + size = ARRAY_SIZE(gmbus_pins_icp); +diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +index 76076509f771..04f62f27ad74 100644 +--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c ++++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +@@ -163,10 +163,12 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv) + (!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv))) + return; + +- if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTL) ++ if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL) + hpd->pch_hpd = hpd_mtp; + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1) + hpd->pch_hpd = hpd_sde_dg1; ++ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP) ++ hpd->pch_hpd = hpd_mtp; + else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) + hpd->pch_hpd = hpd_icp; + else if (HAS_PCH_CNP(dev_priv) || HAS_PCH_SPT(dev_priv)) +@@ -1137,7 +1139,7 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915) + + if (INTEL_PCH_TYPE(i915) >= PCH_LNL) + xe2lpd_sde_hpd_irq_setup(i915); +- else if (INTEL_PCH_TYPE(i915) >= PCH_MTL) ++ else if (INTEL_PCH_TYPE(i915) >= PCH_MTP) + mtp_hpd_irq_setup(i915); + } + +diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c +index 2d65a538f83e..a8fa3a20990e 100644 +--- a/drivers/gpu/drm/i915/display/intel_pps.c ++++ b/drivers/gpu/drm/i915/display/intel_pps.c +@@ -366,7 +366,7 @@ static bool intel_pps_is_valid(struct intel_dp *intel_dp) + + if (intel_dp->pps.pps_idx == 1 && + INTEL_PCH_TYPE(i915) >= PCH_ICP && +- INTEL_PCH_TYPE(i915) <= PCH_ADP) ++ INTEL_PCH_TYPE(i915) < PCH_MTP) + return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; + + return true; +diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c +index 3cad6dac06b0..240beafb38ed 100644 +--- a/drivers/gpu/drm/i915/soc/intel_pch.c ++++ b/drivers/gpu/drm/i915/soc/intel_pch.c +@@ -140,6 +140,11 @@ intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id) + drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) && + !IS_ALDERLAKE_P(dev_priv)); + return PCH_ADP; ++ case INTEL_PCH_MTP_DEVICE_ID_TYPE: ++ case INTEL_PCH_MTP2_DEVICE_ID_TYPE: ++ drm_dbg_kms(&dev_priv->drm, "Found Meteor Lake PCH\n"); ++ drm_WARN_ON(&dev_priv->drm, !IS_METEORLAKE(dev_priv)); ++ return PCH_MTP; + default: + return PCH_NONE; + } +@@ -168,7 +173,9 @@ intel_virt_detect_pch(const struct drm_i915_private *dev_priv, + * make an educated guess as to which PCH is really there. + */ + +- if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) ++ if (IS_METEORLAKE(dev_priv)) ++ id = INTEL_PCH_MTP_DEVICE_ID_TYPE; ++ else if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) + id = INTEL_PCH_ADP_DEVICE_ID_TYPE; + else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv)) + id = INTEL_PCH_TGP_DEVICE_ID_TYPE; +@@ -218,13 +225,6 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) + if (DISPLAY_VER(dev_priv) >= 20) { + dev_priv->pch_type = PCH_LNL; + return; +- } else if (IS_METEORLAKE(dev_priv)) { +- /* +- * Both north display and south display are on the SoC die. +- * The real PCH is uninvolved in display. +- */ +- dev_priv->pch_type = PCH_MTL; +- return; + } else if (IS_DG2(dev_priv)) { + dev_priv->pch_type = PCH_DG2; + return; +diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h +index 89e89ede265d..1b03ea60a7a8 100644 +--- a/drivers/gpu/drm/i915/soc/intel_pch.h ++++ b/drivers/gpu/drm/i915/soc/intel_pch.h +@@ -25,11 +25,11 @@ enum intel_pch { + PCH_ICP, /* Ice Lake/Jasper Lake PCH */ + PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */ + PCH_ADP, /* Alder Lake PCH */ ++ PCH_MTP, /* Meteor Lake PCH */ + + /* Fake PCHs, functionality handled on the same PCI dev */ + PCH_DG1 = 1024, + PCH_DG2, +- PCH_MTL, + PCH_LNL, + }; + +@@ -59,12 +59,16 @@ enum intel_pch { + #define INTEL_PCH_ADP2_DEVICE_ID_TYPE 0x5180 + #define INTEL_PCH_ADP3_DEVICE_ID_TYPE 0x7A00 + #define INTEL_PCH_ADP4_DEVICE_ID_TYPE 0x5480 ++#define INTEL_PCH_MTP_DEVICE_ID_TYPE 0x7E00 ++#define INTEL_PCH_MTP2_DEVICE_ID_TYPE 0xAE00 + #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 + #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 + #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ + + #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) + #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) ++#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL) ++#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP) + #define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2) + #define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP) + #define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1) |