kernel 5.10.20

3 files changed, 0 insertions, 226 deletions

diff --git a/SOURCES/0001-Revert-drm-amd-display-Update-NV1x-SR-latency-values.patch b/SOURCES/0001-Revert-drm-amd-display-Update-NV1x-SR-latency-values.patch
deleted file mode 100644
index 36855bd..0000000
--- a/SOURCES/0001-Revert-drm-amd-display-Update-NV1x-SR-latency-values.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 910f1601addae3e430fc7d3cd589d7622c5df693 Mon Sep 17 00:00:00 2001
-From: Alex Deucher <alexander.deucher@amd.com>
-Date: Wed, 3 Feb 2021 14:03:50 -0500
-Subject: [PATCH] Revert "drm/amd/display: Update NV1x SR latency values"
-
-This reverts commit 4a3dea8932d3b1199680d2056dd91d31d94d70b7.
-
-This causes blank screens for some users.
-
-Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1388
-Cc: Alvin Lee <alvin.lee2@amd.com>
-Cc: Jun Lei <Jun.Lei@amd.com>
-Cc: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
-Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-Cc: stable@vger.kernel.org
----
- drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-index a0a4ab47a1c0..a2cbafab663c 100644
---- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
-@@ -297,8 +297,8 @@ static struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
- 			},
- 		},
- 	.num_states = 5,
--	.sr_exit_time_us = 11.6,
--	.sr_enter_plus_exit_time_us = 13.9,
-+	.sr_exit_time_us = 8.6,
-+	.sr_enter_plus_exit_time_us = 10.9,
- 	.urgent_latency_us = 4.0,
- 	.urgent_latency_pixel_data_only_us = 4.0,
- 	.urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
--- 
-2.29.2
-
diff --git a/SOURCES/0001-drm-nouveau-kms-handle-mDP-connectors.patch b/SOURCES/0001-drm-nouveau-kms-handle-mDP-connectors.patch
deleted file mode 100644
index 44c150f..0000000
--- a/SOURCES/0001-drm-nouveau-kms-handle-mDP-connectors.patch
+++ /dev/null
@@ -1,54 +0,0 @@
-From 54a080fdc2e65b38aea4dd59dde357d6c340fa25 Mon Sep 17 00:00:00 2001
-From: Karol Herbst <kherbst@redhat.com>
-Date: Thu, 26 Nov 2020 14:47:50 +0100
-Subject: [PATCH] drm/nouveau/kms: handle mDP connectors
-
-In some cases we have the handle those explicitly as the fallback
-connector type detection fails and marks those as eDP connectors.
-
-Attempting to use such a connector with mutter leads to a crash of mutter
-as it ends up with two eDP displays.
-
-Information is taken from the official DCB documentation.
-
-Upstream Nouveau commit: 95adf381b74e86a8a34b93c3fab73c15dd2f3f5c
-
-Cc: stable@vger.kernel.org
-Cc: dri-devel@lists.freedesktop.org
-Cc: Ben Skeggs <bskeggs@redhat.com>
-Reported-by: Mark Pearson <markpearson@lenovo.com>
-Tested-by: Mark Pearson <markpearson@lenovo.com>
-Signed-off-by: Karol Herbst <kherbst@redhat.com>
-Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
----
- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h | 1 +
- drivers/gpu/drm/nouveau/nouveau_connector.c             | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
-index f5f59261ea81..d1beaad0c82b 100644
---- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
-+++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/conn.h
-@@ -14,6 +14,7 @@ enum dcb_connector_type {
- 	DCB_CONNECTOR_LVDS_SPWG = 0x41,
- 	DCB_CONNECTOR_DP = 0x46,
- 	DCB_CONNECTOR_eDP = 0x47,
-+	DCB_CONNECTOR_mDP = 0x48,
- 	DCB_CONNECTOR_HDMI_0 = 0x60,
- 	DCB_CONNECTOR_HDMI_1 = 0x61,
- 	DCB_CONNECTOR_HDMI_C = 0x63,
-diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
-index 8b4b3688c7ae..4c992fd5bd68 100644
---- a/drivers/gpu/drm/nouveau/nouveau_connector.c
-+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
-@@ -1210,6 +1210,7 @@ drm_conntype_from_dcb(enum dcb_connector_type dcb)
- 	case DCB_CONNECTOR_DMS59_DP0:
- 	case DCB_CONNECTOR_DMS59_DP1:
- 	case DCB_CONNECTOR_DP       :
-+	case DCB_CONNECTOR_mDP      :
- 	case DCB_CONNECTOR_USB_C    : return DRM_MODE_CONNECTOR_DisplayPort;
- 	case DCB_CONNECTOR_eDP      : return DRM_MODE_CONNECTOR_eDP;
- 	case DCB_CONNECTOR_HDMI_0   :
--- 
-2.29.2
-
diff --git a/SOURCES/i915-fixes.patch b/SOURCES/i915-fixes.patch
deleted file mode 100644
index fab7711..0000000
--- a/SOURCES/i915-fixes.patch
+++ /dev/null
@@ -1,134 +0,0 @@
-From 660fd7a8af42f8715dc6784a2d1d2fe42dc5a72f Mon Sep 17 00:00:00 2001

-From: Chris Wilson <chris@chris-wilson.co.uk>

-Date: Tue, 19 Jan 2021 11:07:57 +0000

-Subject: [PATCH 1/3] drm/i915/gt: One more flush for Baytrail clear residuals

-

-CI reports that Baytail requires one more invalidate after CACHE_MODE

-for it to be happy.

-

-Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")

-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

-Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

-Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Reviewed-by: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

-Link: https://patchwork.freedesktop.org/patch/msgid/20210119110802.22228-1-chris@chris-wilson.co.uk

----

- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 9 ++++++---

- 1 file changed, 6 insertions(+), 3 deletions(-)

-

-diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-index e961ad6a3129..c50b18dd67be 100644

---- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-@@ -353,19 +353,21 @@ static void gen7_emit_pipeline_flush(struct batch_chunk *batch)

- 

- static void gen7_emit_pipeline_invalidate(struct batch_chunk *batch)

- {

--	u32 *cs = batch_alloc_items(batch, 0, 8);

-+	u32 *cs = batch_alloc_items(batch, 0, 10);

- 

- 	/* ivb: Stall before STATE_CACHE_INVALIDATE */

--	*cs++ = GFX_OP_PIPE_CONTROL(4);

-+	*cs++ = GFX_OP_PIPE_CONTROL(5);

- 	*cs++ = PIPE_CONTROL_STALL_AT_SCOREBOARD |

- 		PIPE_CONTROL_CS_STALL;

- 	*cs++ = 0;

- 	*cs++ = 0;

-+	*cs++ = 0;

- 

--	*cs++ = GFX_OP_PIPE_CONTROL(4);

-+	*cs++ = GFX_OP_PIPE_CONTROL(5);

- 	*cs++ = PIPE_CONTROL_STATE_CACHE_INVALIDATE;

- 	*cs++ = 0;

- 	*cs++ = 0;

-+	*cs++ = 0;

- 

- 	batch_advance(batch, cs);

- }

-@@ -397,6 +399,7 @@ static void emit_batch(struct i915_vma * const vma,

- 	batch_add(&cmds, 0xffff0000);

- 	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_1));

- 	batch_add(&cmds, 0xffff0000 | PIXEL_SUBSPAN_COLLECT_OPT_DISABLE);

-+	gen7_emit_pipeline_invalidate(&cmds);

- 	gen7_emit_pipeline_flush(&cmds);

- 

- 	/* Switch to the media pipeline and our base address */

--- 

-2.30.1

-

-From b3d131f8d2b9055052b6e072b57fa390b7275443 Mon Sep 17 00:00:00 2001

-From: Chris Wilson <chris@chris-wilson.co.uk>

-Date: Mon, 25 Jan 2021 22:02:47 +0000

-Subject: [PATCH 2/3] drm/i915/gt: Flush before changing register state

-

-Flush; invalidate; change registers; invalidate; flush.

-

-Will this finally work on every device? Or will Baytrail complain again?

-

-On the positive side, we immediately see the benefit of having hsw-gt1 in

-CI.

-

-Fixes: ace44e13e577 ("drm/i915/gt: Clear CACHE_MODE prior to clearing residuals")

-Testcase: igt/gem_render_tiled_blits # hsw-gt1

-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

-Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

-Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Link: https://patchwork.freedesktop.org/patch/msgid/20210125220247.31701-1-chris@chris-wilson.co.uk

----

- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 1 +

- 1 file changed, 1 insertion(+)

-

-diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-index c50b18dd67be..e53b409012c0 100644

---- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-@@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma,

- 						     desc_count);

- 

- 	/* Reset inherited context registers */

-+	gen7_emit_pipeline_flush(&cmds);

- 	gen7_emit_pipeline_invalidate(&cmds);

- 	batch_add(&cmds, MI_LOAD_REGISTER_IMM(2));

- 	batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7));

--- 

-2.30.1

-

-From 28f4f465f21f9dc267ce08833b8e79356cbc05f3 Mon Sep 17 00:00:00 2001

-From: Chris Wilson <chris@chris-wilson.co.uk>

-Date: Wed, 10 Feb 2021 12:27:28 +0000

-Subject: [PATCH 3/3] drm/i915/gt: Correct surface base address for renderclear

-

-The surface_state_base is an offset into the batch, so we need to pass

-the correct batch address for STATE_BASE_ADDRESS.

-

-Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")

-Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

-Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>

-Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>

-Cc: Hans de Goede <hdegoede@redhat.com>

-Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

-Cc: <stable@vger.kernel.org> # v5.7+

-Link: https://patchwork.freedesktop.org/patch/msgid/20210210122728.20097-1-chris@chris-wilson.co.uk

----

- drivers/gpu/drm/i915/gt/gen7_renderclear.c | 2 +-

- 1 file changed, 1 insertion(+), 1 deletion(-)

-

-diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-index e53b409012c0..4adbc2bba97f 100644

---- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-+++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c

-@@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch,

- 	/* general */

- 	*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

- 	/* surface */

--	*cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY;

-+	*cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY;

- 	/* dynamic */

- 	*cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY;

- 	/* indirect */

--- 

-2.30.1

-